BIOS Tutorial and codes

BIOS Tutorial
Definitions
• BIOS
• CMOS
• Chipset
• Setup
BIOS
Basic Input Output System. All computer hardware has to work with software
through an interface. The BIOS gives the computer a little builtin starter kit to
run the rest of softwares from flopp! disks "#$$% and hard disks "&$$%. The
BIOS is responsible for booting the computer b! providing a basic set of
instructions. It performs all the tasks that need to be done at startup time' (OST
"(owerOn Self Test) booting an operating s!stem from #$$ or &$$%.
#urthermore) it provides an interface to the underl!ing hardware for the operating
s!stem in the form of a librar! of interrupt handlers. #or instance) each time a ke!
is pressed) the C(* "Central (rocessing *nit% perform an interrupt to read that
ke!. This is similar for other input+output devices "Serial and parallel ports) video
cards) sound cards) hard disk controllers) etc...%. Some older (C,s cannot co
operate with all the modern hardware because their BIOS doesn,t support that
hardware. The operating s!stem cannot call a BIOS routine to use it- this problem
can be solved b! replacing !our BIOS with an newer one) that does support !our
new hardware) or b! installing a device driver for the hardware.
CMOS
Complementary Metal Oxide Semiconductor. To perform its tasks) the BIOS
need to know various parameters "hardware configuration%. These are
permanentl! saved in a little piece "./ b!tes% of CMOS 0AM "short' CMOS%.
The CMOS power is supplied b! a little batter!) so its contents will not be lost
after the (C is turned off. Therefore) there is a batter! and a small 0AM memor!
on board) which never "should...% loses its information. The memor! was in
earlier times a part of the clock chip) now it,s part of such a highl! Integrated
Circuit "IC%. CMOS is the name of a technolog! which needs ver! low power so
the computer,s batter! is not too much in use.
Actuall!) there is not a batter! on new boards) but an accumulator "1i2Cad in
most cases%. It is recharged ever! time the computer is turned on. If !our CMOS
is powered b! e3ternal batteries) be sure that the! are in good operating condition.
Also) be sure that the! do not leak. That ma! damage the motherboard.
Otherwise) !our CMOS ma! suddenl! 4forget4 its configuration and !ou ma! be
looking for a problem elsewhere. In the monolithic (C and (C+5T) this
information is supplied b! setting the $I( "$ualInline (ackage% switches at the
motherboard or peripheral cards. Some new motherboards have a technolog!
named the $allas 1ov0am. It eliminates having an onboard batter!' There is a
67 !ear lithium cell epo3!ed into the chip.
Chipset
A (C consists of different functional parts installed on its motherboard' ISA
"Industr! Standard Architecture%) 8ISA "8nhanced Industr! Standard
Architecture% 98SA "9ideo 8nhanced Standards Association% and (CI
"(eripheral Component Interface% slots) memor!) cache memor!) ke!board plug
etc... 1ot all of these are present on ever! motherboard. The chipset enables a set
of instructions so the C(* can work "communicate% with other parts of the
motherboard. 1owada!s most of the discrete chips- (IC "(rogrammable Interrupt
Controller%) $MA "$irect Memor! Access%) MM* "Memor! Management *nit%)
cache) etc... are packed together on one) two or three chips- the chipset. Since
chipsets of a different brand are not the same) for ever! chipset there is a BIOS
version. 1ow we have fewer and fewer chipsets which do the :ob. Some chipsets
have more features) some less. O(Ti is such a commonl! used chipset. In some
well integrated motherboards) the onl! components present are the C(*) the two
BIOS chips "BIOS and ;e!board BIOS%) one chipset IC) cache memor!
"$0AMs) $!namic 0andom Access Memor!%) memor! "SIMMs) Single Inline
Memor! Module) most of the time% and a clock chip.
Setup
Setup is the set of procedures enabling the configure a computer according to its
hardware caracteristics. It allows !ou to change the parameters with which the
BIOS configures !our chipset. The original IBM (C was configured b! means of
$I( switches buried on the motherboard. Setting (C and 5T $I( switches
properl! was something of an arcane art. $I( switches+:umpers are still used for
memor! configuration and clock speed selection. <hen the (CAT was
introduced) it included a batter! powered CMOS memor! which contained
configuration information. CMOS was originall! set b! a program on the
$iagnostic $isk) however later clones incorporated routines in the BIOS which
allowed the CMOS to be "re%configured if certain magic ke!strokes were used.
*nfortunatel! as the chipsets controlling modern C(*s have become more
comple3) the variet! of parameters specifiable in S8T*( has grown. Moreover)
there has been little standardi=ation of terminolog! between the half do=en BIOS
vendors) three do=en chipset makers and large number of motherboard vendors.
Complaints about poor motherboard documentation of S8T*( parameters are
ver! common.
To e3acerbate matters) some parameters are defined b! BIOS vendors) others
b!chipset designers) others b! motherboard designers) and others b! various
combinations of the above. (arameters intended for use in $esign and
$evelopment) are intermi3ed with parameters intended to be ad:usted b!
technicians who are fre>uentl! :ust as baffled b! this stuff as ever!one else is.
1o one person or organi=ation seems to understand all the parameters available
for an! given S8T*(.
Hardware Performance
• S!stem Timing
• The ?ear @77 problem
• The Motherboard
• The Central (rocessor
Although computers ma! have basic similarities "the! all look the same on a
shelf%) performance will differ markedl! between them) :ust the same as it does
with cars. The (C contains several processes running at the same time) often at
different speeds) so a fair amount of coordination is re>uired to ensure that the!
don,t work against each other.
Most performance problems arise from bottlenecs between components that are
not necessaril! the best for a particular :ob) but a result of compromise between
price and performance. *suall!) price wins out and !ou have to work around the
problems this creates.
The trick to getting the most out of an! machine is to make sure that each
component is giving of its best) then eliminate potential bottlenecks between
them. ?ou can get a bottleneck simpl! b! having an old piece of e>uipment that is
not designed to work at modern high speed a computer is only as fast as its
slowest component) but bottlenecks can also be due to badl! written software.
System Timin!
The clock is responsible for the speed at which numbers are crunched and
instructions e3ecuted. It results in an electrical signal that switches constantl!
between high and low voltage several millions times a second.
The System Cloc) or CA;I1) is the fre>uenc! used b! the processor- on @B.s
and CB.s) this will be half the speed of the main cr!stal on the motherboard "the
C(* devides it b! two%) which is often called CA;@I1. /B. processors run at the
same speed) because the! use both edges of the timing signal. A clock generator
chip "B@@B/ or similar% is used to s!nchroni=e timing signals around the
computer) and the data bus would be run at slower speed s!nchronousl! with the
C(*) e.g. CA;I1+/ for an ISA bus with a CC M&= C(*.
ATCA; is a separate clock for the bus) when it,s run as!nchronousl!) or not
derived from CA;@I1. There is also a 6/.6CB M&= cr!stal which was used for all
s!stem timing on 5Ts. 1ow it,s onl! used for the colour fre>uenc! of the video
controller ".B/D%.
The "ear #$$$ problem
As far as the (C hardware is concerned) the problem lies with the Real Time
Clock) or 0TC) and its relation to the internal $OS clock device driver
"CAOC;E%) which is actuall! a counter and not a real clock at all. ?ou can verif!
if !our s!stem has this problem b! setting the date :ust before midnight 6FFF and
leaving the machine running to see what happen when it reaches @777. $OS
copes with the problem >uite easil!. &owever) if !ou turn the power off and
reboot) !ou might see a s!stem date starting somewhere in 6FB7 "do not log on to
the network) if it is the case) otherwise !ou might get the server time%. The date
76+76+6FB7 is usuall! set if !our CMOS contents are lost) and 76+7/+6FB7 if an
outofrange date is encountered.
The reason for this discrepanc! is the interaction between the two clocks
mentioned above. The 0TC lives inside the CMOS chip that keeps the BIOS
settings and is kept alive b! the batter!. Some of these cannot keep track of the
centuries b! themselves) so a b!te is used in the CMOS to do the :ob instead.
Also) the! are trimmed at the factor! to a certain tolerance) t!picall! plus or
minus @7 seconds a month) which will onl! be kept to if the desired operating
environment is kept "temprerature) humidit!) etc.%.
The $OS device driver "CAOC;E%) on the other hand) onl! interrogates the 0TC
"via the BIOS% when the machine starts) then proceeds to ignore it as long as the
(C is running. This is to save going as far as the 0TC for the time) which is a
slower process. The date supplied is converted to the number of da!s since
Ganuar! 6st 6FB7) and the number of seconds since midnight of the current da!.
The latter is stored in the counter b! the BIOS) and when $OS needs to read the
clock) the BIOS is called to read the counter and the number of ticks is converted
back to seconds. If the counter goes past midnight) it is reset to =ero b! the BIOS)
and the first caller after that is told that the da! has advanced. As a result) if more
thant @/ hours has elapsed between calls) there is no wa! that $OS can tell which
da! it is.
This is wh! there is often a time difference between !our watch and !our (C at
the end of the da!- the s!stem clock has to compete for attention with other
devices) and is often reprogrammed b! games) etc) who use it for their own
timing purposes) mostl! to do with running the video faster. In short) being
interrupt dri%en) its accurac! depends on s!stem activit!.
As $OS operates between 6FB7 and @7FF) it can figure out that 77 e>uates to
@777) although it ma! have problems if the 0TC specificall! hands it a date of
6F77) or an! other incompatible date. In practice) the BIOS converts it as well-
some correct the time automaticall! at boot and some will suppl! $OS with @777
instead of a hardware date of 6F77. Others cannot produce a date later than 6FFF
an!wa!- Award BIOS /.DH prior to 1ovember 6FFD can onl! accept dates
between 6FF/ and 6FFF. A good wa! to solve the @777 problem "for the BIOS
aspect of it at least% is the chan!e your motherboard. &ave a look at
[email protected] or www.sbhs.com/y2k.
The Motherboard
This is a large circuit board to which are fi3ed the Central Processor "C(*%) the
data bus) memor! and various support chips) such as those that control speed and
timing the ke!board) etc. The C(* does all the thinking) and is told what to do b!
instructions contained in memor!) so there will be a direct twowa! connection
between them. The data bus is actuall! a part of the C(*) although it,s treated
separatel!.
83tra circuitr! in the form of expansion cards is placed into expansion slots on
the data bus) so the basic setup of the computer can be changed easil! "for
e3ample) !ou can connect more disk drives or a modem there%.
A math coprocessor is fre>uentl! fitted alongside the main processor) which is
speciall! built to cope with noninteger arithmetic "e.g. decimal points%. The main
processor has to convert decimals and fractions to whole numbers before
calculating them) and then has to convert them back again.
The Central Processor
The chip that was the brains of the original IBM (C was called the B7BB)
manufactured b! Intel. In the da!s Intel developed the B7BB) microprocessors
were classified b! their e3ternal databus. Intel has thus officiall! classified their
B7BB as an Bbit &MOS microprocessor. Although it was internall! classified as
being 6.bit) it spoke to the data bus and memor! with B bits in order to keep the
costs down and keep in line with the capabilities of the support chips. Then when
it wanted to send two characters to the screen over the data bus) it had to send
them one at a time) rather than both together) so there was an idle state where
nothing was done ever! time the data was sent.
In addition) it could onl! talk to 6 Mb of memor! at an! time- there were @7
ph!sical connections between it and the C(*. On a binar! s!stem this represents
@
@7
) or 6)7/B)DI..
The &$#&'
The B7@B. was introduced in response to competition from manufacturers who
were cloning the IMB (C. The connections between the various parts of the
motherboard became 6.bit throughout) thus increasing efficienc! / times. It also
has @/ memor! address lines) so it could talk to 6.Mb of ph!sical memor!.
&owever) $OS could not use it since it had to be addressed in protected mode.
$OS can onl! run in real mode) which is restricted to the 6 Mb that can be seen
b! the B7BB. Therefore) a (entium running $OS is :ust a fast 5T. Gust as the
B7BB) the B7@B. C(* is limitted to 6MB "J ./;B% when running in real mode.
The B7@B. C(* has to run in protected mode to access e3tended memor!. On a
B7@B. s!stem) $OS, e3tended memor! manager "himem.s!s% uses BIOS service
I1T 6Dh+A&KBIh to move data from+to e3tended memor!. I1T 6Dh enters and
leaves protected mode.
The &$(&'
Compa> was the first compan! to use the B7CB. "the $5 version) as opposed to
the S5see below%) which uses C@ bits between itself and memor!) but 6. towards
the data bus) which has not reall! been developed in tandem wit the rest of the
machine. This is partl! to ensure backwards compatibilit! and partl! due to the
plumbing arrangements of running a fast C(* with faster memor! and a slow bus
"B M&=%.
The CB. can run multiple copies of real mode "that is) it can create several virtual
B7BBs%. It uses paging to remap memor! so that these machines are brought to the
attention of the C(* when the programs in them re>uire it- this is done on a
timeslice basis) around .7 times a second) which is how we get multitasking in
<indows of OS+@ "in FD the slice is ever! @7 ns%.
The CB. can also switch out of protected mode on the fl!) or at least in a more
elegant wa! that the @B.- in order to get the hard disk and other parts of the
computer) protectedmode software hat to get $OS to perform real mode services)
so the C(* has to switch in and out of protected mode continuall!. The goal is
therefore to use real mode as little as possible and to run in protected mode.
<indows does this b! using C@bit instructions. Because of C@bit addressing) the
B7CB. and above C(*,s are not limitted to 6MB when running in real mode.
Because the address bus is also C@bit) an! address can be reached using
7777'LC@bit offsetM. Also) $OS segments larger than ./;B can be handled as a
whole instead using chunks of ./;B) or b! using normali=ed "huge% pointers. On
B7CB.J s!stems) $OS, e3tended memor! manager simpl! uses a C@bit block
move instruction to move data from+to e3tended memor!.
The CB. uses pipelining to help streamline memor! accessthe idea is that the!
are done independentl! of each other "at the same time% while other units get on
with their :obs- a form of primitive parallel processing. The CB. also has a pre
fetch unit for instructions) that tries to speed things up b! guessing which ones the
processor will use ne3t.
Although the CB. is C@bit and has certain benefits) like the abilit! to manipulate
memor! and switch in and out of protected mode more readil!) replacing a @B.
with a CB. does not automaticall! give !ou performance benefits it !ou are
running 6.bit B7@B. code "most $OS programs%.
The &$(&'S)
The B7CB.S3 is a C@bit chip internall!) but 6.bit e3ternall! to both memor! and
the data bus) so !ou get bottlenecking. It is a cutdown version of the B7CB.$5)
created to both cut costs and give the impression the @B. was obsolete "true%)
because at the time other manufacturers could make the @B. under license.
Although it can run BC.specific software) it looks like a @B. to the machine it is
in) so e3isting @B. motherboards could be used to plug in CB.S5 C(*s. At the
same clock speed) a CB.S5 is around @DN slower than a CB.$5.
The &$*&'
To nontechnical people) the B7/B. is a fast B7CB.$5 with an onboard math co
processor and B; of cache memor!. It is not reall! a newer technolog! as such
"onl! second generation%) but better use is made of its facilities. #or e3ample) it
takes fewer instruction c!cles to do the same :ob) and is optimi=ed to keep as
man! operations inside the chip as possible. The CB. prefetch unit was replaced
b! B; of S0AM cache) and pipelining was replaced b! burst mode) which works
on the theor! that most of the time spent getting data concerns its address. Burst
allows a device to send large amounts of data in a short time without interruption.
(ipelining on the CB. re>uires @ clocks per transfer- onl! one is needed with /B.
Burst Mode. Memor! parit! checks also take their own path at the same time as
the data the! relate to. The /B. has an onboard clock) and both edges of the
s>uare wave signal are used to calculate the clock signal) so the motherboard runs
at the same speed as the C(*. In addition) the bus s!stem uses a single pulse
c!cle. Henerall! speaking) at the same clock speed) a /B. will deliver between @
C times the performance of a CB..
The &$*&'S)
The /B.S5 is as above) but with the math coprocessor facilit! disabled)
therefore !ou should find no significant difference between it and a CB.- a CB.+/7
is broadl! e>uivalent to a /B.+@D.
Cloc Doublin!
The $5+4 chip runs at double speed of the original) but it is not the same as
having a proper high speed motherboard because the bus will still be running at
the normal speed. *nfortunatel!) high speed motherboards are more e3pensive
because of having to design out 0# emissions) and the like.
Actual performance depends on how man! accesses are satisfied from the chip,s
cache) which is how the C(* is kept bus!) rather than waiting for the rest of the
machine. If the C(* has to go outside the cache) effective speed is the same as
the motherboard or) more properl!) the relevant bus "memor! or data%) so best
performance is obtained when all the C(*,s needs are satisfied from inside itself.
&owever) performance is still good if it has to use cache) as the hit rate is around
F7N. The $5/ has a larger cache "6.;% to cope with the higher speed.
The Pentium
8ssentiall! two /B.s in parallel "or rather an S5 and a $5%) so more instructions
are processed at the same time- t!picall! two at once. This) however) depends on
whether software can take advantage of it) and get the timing of the binar! code
:ust right. It has separate B; caches) for instructions and data) split into banks
which can be accessed alternatel!. It has a ./bit bus) to cope with @ C@bit chips.
The Pentium Pro
This is a 0ISC chip with a /B. hardware emulator on it) running at @77 M&= of
below. Several techni>ues are used b! this chip to produce more performance
than its predecessors- speed is achieved b! dividing processing into more stages)
and more work is done within each clock c!cle- three instructions can be decoded
in each one) as opposed to two for the (entium.
In additions) instruction decoding and e3ecution are decoupled) which means that
instructions can still be e3ecuted if one pipeline stops "such as when one
instruction is waiting for data from memor!- the (entium would stop all
processing at this point%. Instructions are sometimes e3ecuted out of order) that is)
not necessaril! as written down in the program) but rather when information is
available) although the! won,t be much out of se>uence- :ust enough to make
things run smoother.
It has a B; cache for programs and data) but it will be a two chip set) with the
processor and a @D.; A@ cache in the same package. It is optimi=ed for C@bit
code) so will run 6.bit code no faster than a (entium.
Cyrix
The .3B. is a (entiumt!pe chip with (entium (ro characteristics) as it can
e3ecute faster instructions out of se>uence. The! use a P-Rating to determine
performance relative to the (entium) so a .3B.6.. is e>uivalent to a (entium
6..) even if running at 6CC M&=.
Summin! up
In principle) the faster the C(* the better) but onl! if !our applications do a lot of
logical operations and calculation "where the work is centered around the chip%
rather than writing to disk. #or e3ample) when a t!pical word processing task)
replacing a 6. M&= CB. with a CC M&= one "doubling the speed% will onl! get
!ou something like a D67N increase in practical performance) regardless of what
the benchmarks might sa!. It is often a better idea to spend money on a faster
hard dis.
Also) with onl! B Mb 0AM in !our computer) !ou won,t see much performance
increase from a $5@+.. until !ou get a (entium F7 "none at all between a
$5/+677 and a (entium ID%. <ith <indows) this is because the hard disk is used
a lot for virtual memor! "swap files%) which means more activit! over the data
bus. Since motherboards below the F7 run at CCMh= "onl! the chips run faster%)
the bottleneck is the disk I+O) running at much the same speed on them all. This is
especiall! true if !ou use (rogrammed I+O "(IO%) where the C(* must scrutini=e
ever! bit to and from the hard drive "although Multisector I+O or 8I$8 will
improve things%. As the (entium F7,s motherboard runs faster ".7 M&=%) the I+O
can proceed at a much faster pace) and performance will more than double "a
more sophisticated chipset helps%.
<ith 6. Mb) on the other hand) performance will be almost double an!wa!)
regardless of the processor) because the need to go to the hard disk is so much
reduced) and the processor can make a contribution to performance. The biggest
:ump is from a $5@+.. to a $5+/) with the curve flattening out progressivel! up
to the (entium F7.
Processo
r
MB
Speed
Cloc
)
Bus
Speed
(.7 .7 6 C7
(.. .. 6 CC
(ID D7 6.D @D
(F7 .7 6.D C7
(677 .. 6.D CC
(6@7 .7 @ C7
(6CC .. @ CC
(6D7 .7 @.D C7
(6.. .. @.D CC
(@77 .. C CC
.3B.
6@7
D7 @ @D
.3B.
6CC
DD @ O
.3B.
6D7
.7 @ C7
.3B.
6..
.. @ CC
Memory
• Memor! T!pes
• Memor! Access
• <ait States
• Shadow 0AM
• Base Memor!
• *pper Memor!
• 83tended Memor!
• &igh Memor!
• 83panded Memor!
• 9irtual Memor!
Memory Types
*nlike the good old da!s of mainframe computers when there were onl! two
t!pes of memor! to deal with) the (C uses five) again for historical reasons. The
memor! contains the instructions that tell the Central (rocessor what to do) as
well as the data created b! its activities. Since the computer works with the binar!
s!stem) memor! chips work b! keeping electronic switches in one state or the
other for however long the! are re>uired. Actuall!) the! consist of a capacitor and
a transistor- the capacitor stores a charge "data%) which represents a 6) and the
transistor acts as a switch that turns the charge on or off. <here these states can
be changed at will) it is called +andom ,ccess Memory) or 0AM. The term
derives from when magnetic tapes were used for data storage) and the information
could onl! be accessed se>uentiall!. A 0OM) on the other hand) is a memor! chip
with its electronic switches permanentl! on of off) so the! can,t be changed)
hence +ead Only Memory.
• Static +,M "S0AM% is the fastest available) with a t!pical access time of @D
nanoseconds. Static 0AM is e3pensive and can onl! store a >uarter of the data
that $0AM is able to in the same given area) although it does retain it for as
long as the chip is powered. The transistors are connected so that onl! one is
either in or out at an! time- whichever one is in stands for a 6 bit. S!nchronous
S0AM allows a faster data stream to pass through it- which is needed when
used for cacheing on F7 and 677 M&= (entium.
• Dynamic +,M "$0AM% uses internal capacitors to store data "a single
transistor turns it on of off% which lose their charge over time) so the! need
constant refreshing to retain information) otherwise 6s will turn to 7s. The end
result is that between ever! memor! access is sent an electrical charge that
refreshes the chip,s capacitors to keep data in a fit state) which cannot be
reached whilst recharging is going on. 0eading a $0AM discharges its
contents) so the! have to be written back to immediatel! to keep the sane
information.
• -nhanced D+,M "8$0AM% replaces standard $0AM and the S0AM in the
level @ cache on the motherboard) t!picall! combining @D. b!tes of 6Dns
S0AM inside CDns $0AM. Since the S0AM can take a whole @D. b!te page
of memor! at once) it gives an effective 6Dns access speed when !ou get a hit
"CDns otherwise%. The level @ cache is replaced with an SIC chip to sort out
chipset vs. memor! re>uirements. S!stem performance is increased b! around
/7N. 8$0AM has a separate write path that accepts and completes re>uests
without the rest of the chip.
• .+,M "<indows 0AM%) created b! Samsung) is dual ported) but costs about
@7N less than 90AM and is D7N faster. It runs at D7 M&= and is optimi=ed
for acceleration and can transfer blocks and supports te3t and pattern fills.
Mostl! used for video cards.
• Synchronous D+,M "S$0AM% takes memor! access awa! from the C(*,s
control- internal registers in the chips accept the re>uest) and let the C(* do
something else while the data re>uested is assembled for the ne3t time the
C(* talks to the memor!. As the! work on their own clock) the rest of the
s!stem can be clocked faster. There is a version optimi=ed for video cards.
• -DO "83tended $ata Output% is an advanced version of fast page mode "often
called &!per (age Mode%) which can be up to C7N better and onl! cost DN
more. Singlec!cle 8$O will carr! out a complete memor! transaction in 6
clock c!cle- otherwise) each se>uential 0AM access inside the same page
takes @ clock c!cles instead of C) once the page has been selected. As it
replaces level @ cache and doesn,t need a separate controller) space on the
motherboard is saved) which is good for notebooks. It also saves batter!
power. In short) 8$O gives and increased bandwidth due to shortening of the
page mode c!cle) but it doesn,t appear to be that much faster in practice.
Memory ,ccess
The cycle time is the time it takes to read from and write to a memor! cell) and it
consists of two stages- precharge and access. Prechar!e is where the capacitor in
the memor! cell is able to recover from a previous access and stabili=e. ,ccess is
where a data bit is actuall! moved between memor! and the bus or the C(*.
Total access time includes the finding of data) data flow and recharge) and parts
of the access time can be eliminated or overlapped to improve performance. The
combination of precharge and access e>uals c!cle time) which is what !ou should
use to calculate wait states from.
There are wa!s of making refreshes happen so that the C(* doesn,t notice "i.e.
Concurrent and &idden%) which is helped b! the /B. being able to use its on
board cache and not needing to use memor! so often an!wa!. In addition) !ou can
affect the +ow ,ccess Strobe "0AS%) or have Column ,ccess Strobe "CAS%
before 0AS "see Advanced Chipset Setup%.
The fastest $0AM commonl! available is rated at .7ns. As these chips need
alternate refresh c!cles) under normal circumstances data will actuall! be
obtained ever! 6@7ns) giving !ou and effective speed of around B M&= for the
whole computer) regardless of the C(* speed) assuming no action is taken to
compensate. Memor! chips therefore need to be operating at something like @7ns
to keep up) assuming that the C(* needs onl! one clock c!cle for each one from
the memor! bus- one internal c!cle for each e3ternal one. Intel processors mostl!
use two for one) so the CC M&= C(* is actuall! read! to use memor! ever! .7ns)
but !ou need to allow a little more for overheads) such as data assembl! and the
like. One wa! of matching the capacities of components with different speeds
includes the use of wait states.
Cloc Speed
/MH01
Cycle Time
/ns1
6 6777
D @77
B 6@D
6@ BC
6. .C
@7 D7
@D /7
CC C7
/7 @D
.ait States
A wait state indicates how man! ticks of the s!stem clock the C(* has to wait for
memor! to catch upit will generall! be 7 or 6) but can be up to C if !ou,re using
slower memor! chips. <a!s of avoiding wait states include'
• Pa!e2mode memory. This will cutdown address c!cles to retrieve
information form one general area) based on the fact that the second access to a
memor! location on the same page takes around half the time as the first-
addresses are normall! in two halves) with high bits "for row% and low bits "for
column% being multiple3ed onto one set of address pins. The page address of
data is noted) and if the ne3t data is in the same area) a second address c!cle is
eliminated as a whole row of memor! cells can be read in one go- that is) once
a row access has been made) !ou can get to subse>uent column addresses in
that row in the time available "!ou should therefore increase row access time
for best performance%. Otherwise data is retrieved normall!) which will take
twice as long. 3ast Pa!e Mode is a >uicker version of the same thing- the
$0AMs concerned have a faster CAS access speed. Memor! capable of
running in page mode is different from normal bitb!bit t!pe) and the two
don,t mi3. It,s unlikel! that low capacit! SIMMs are so capable.
• Interlea%ed memory) which divides memor! into two or four portions that
process data alternatel!- that is) the C(* sends information to one section
while another goes through a refresh c!cle- a t!pical installation will have odd
addresses on one side and even on the other "!ou can have word or block
interleave%. If memor! accesses are se>uential) the precharge of one will
overlap the access time of the other. To put interleaved memor! to best use) fill
ever! socket !ou,ve got "that is) eight 6 Mb SIMMs are better than two / Mb
ones%. The SIMM t!pes must be the same. As an e3ample) a machine in non
interleaved mode "sa! a CB.S5+@7% ma! need .7ns or faster $0AM for 7ws
access) where B7ns chip could do if interleaving were enabled.
• A processor +,M cache) which is a bridge between the C(* and slower main
memor!- it consists of an!where between C@D6@; of "fast% Static 0AM chips
and is designed to retain the most fre>uentl! accessed code and data from main
memor!. It can make 6 wait state 0AM look like that with 7 wait states)
without ph!sical ad:ustments) assuming that the data the C(* wants is in the
cache when re>uired "known as a cache hit%. To minimi=e the penalt! of a
cache miss) cache and memor! access are often in parallel) with one being
terminated when not re>uired. On a /B.) how much cache !ou need reall!
depends on the amount of memor!- $ell sa! that :umping from 6@B; to @D.;
onl! increases the hit rate b! around DN and 9iglen sa! !ou onl! need more
than @D.; if !ou have more than C@ Mb 0AM. A cache should be fast and
capable of holding the contents of several different parts of main memor!.
Software pla!s a part as well) since cache operation is based on the assumption
that programs access memor! where the! have done so alread!) or are likel! to
ne3t) ma!be through looping "where code is reused% or code is organi=ed to be
ne3t to other relevant parts. A basic cache design will look up an address for
the C(* and return the data inside one clock c!cle) or @7ns at D7 M&=.
Asynchronous S0AM will be used for this. As the round trip from the C(* to
cache and back again takes up a certain amount of time) onl! the remainder is
available to retrieve data) which gets smaller as the motherboard speed is
increased. Synchronous S0AM uses a buffer to keep the whole routine inside
one clock c!cle) even though it ma! use two "or more% clock c!cles the first
time round. The address from the C(* is stored) and while the ne3t is coming
in to the buffer) the data for the first is retrieved) and the c!cle continues.
(ipeline S0AM uses more clock c!cles) t!picall! three) the first time round)
and Burst S0AM will deliver / words "blocks of data% over for consecutive
c!cles if the re>uest from the C(* is for the first- there will be no waiting for
the C(* to re>uest each one individuall!. 1ote the level @ cache can be
unreliable) so be prepared to disable it in the interests of reliabilit!. #or
ma3imum efficienc!) or minimum access time) a cache ma! be subdivided into
smaller blocks that can be separatel! loaded) so the chances of a different part
of memor! being re>uested and the time needed to replace a wrong section are
minimi=ed. There are three mapping schemes that assist with this'
• 3ully ,ssociati%e) where the whole address is kept with each block of
data in the cache "in tag 0AM%) needed because it is assumed there is no
relationships between the blocks. This can be inefficient) as an address
comparison needs to be made with ever! entr! each time the C(*
presents the address for its ne3t instruction.
• Direct Mapped) where ever! block can onl! be in one place in the
cache) so onl! one address comparison is needed to see if the data
re>uired is there. Although simple) the cache controller must go to main
memor! more fre>uentl! if program code needs to :ump between
locations with the sane inde3) which defeats the ob:ect somewhat) as
alternate references to the same cache cell mean cache misses for other
processes. The 4inde34 comes form the lower order addresses presented
b! the C(*.
• Set ,ssociati%e) a compromise between the above two. &ere) an inde3
can select several entries) so in a 2 Way Set Associative cache) @ entries
can have the same inde3) so two comparisons are needed to see if the
data re>uired is in the cache. Also) the tag field is correspondingl! wider
and needs larger S0AMs to store address information. As there are two
locations for each inde3) the cache controller has to decide which one to
update or overwrite) as the case ma! be. The most common methods used
to make these decisions are Random Replacement) First In First ut
"#I#O% and !east Recently "sed "A0*%. The latter is the most efficient. It
the cache is large enough "e.g. ./;%) performance from this over direct
mapping ma! not be much. A Write Thru Cache means that ever! write
access is immediatel! passed on to memor!- although it means that cache
contents are alwa!s identical to main memor!) it is slow) as the C(* then
has to wait for $0AMs. Buffers can be used to provide a variation on
this) where data is written into a temporar! buffer so the C(* is released
>uickl! before main memor! is updated. A Write #ack Cache) on the
other hand) e3ists where changed data is temporaril! stored in the cache
and written to memor! when the s!stem is >uiet) or when absolutel!
necessar!. This will give better performance when main memor! is
slower than the cache) or when several writes are made in a ver! short
space of time) but is more e3pensive. A 4dirt! bit4 is used as a mental
note that the cache and main memor! contents are different) and that the
cache contains the most up to date data. This bit will be checked if the
cache needs to be written to) and main memor! updated first if this bit is
set. Some motherboards don,t have the re>uired S0AM for the dirt! bit)
but it,s still faster than <rite Thru.
Shadow +,M
0OMs are used b! components that need their own instructions to work properl!)
such as video card of cacheing disk controller. 0OMs are Bbit devices) so onl!
one b!te is accessed at a time- also) the! t!picall! run between 6D7/77ns) so
using them will be slow relative to C@bit memor! at .7B7ns) which is capable of
making four accesses at once.
Shado$ RA% is the process of cop!ing the contents of a 0OM directl! into
e3tended memor! which is given the same address as the 0OM) from where it
will run much faster. The original 0OM is then disabled) and the new location
write protected. If !our applications e3ecute 0OM routines often enough)
enabling Shadow 0AM will make a difference in performance of around BN)
assuming a program spends about 67N of its time using instructions from 0OM)
but theoreticall! as high as C77N. The drawback is that the 0AM set aside for
shadowing cannot be used for an!thing else) and !ou will lose a corresponding
amount of e3tended memor!) The remainder of *pper Memor!) however) can
usuall! be remapped to the end of e3tended memor! and used there.
<ith some 9HA cards) if video shadow is disabled) !ou might get $MA errors)
because of timing when code is fetched from the 9HA BIOS) when the C(*
cannot accept $MA re>uests. Some programs don,t make use of the video 0OM)
preferring to directl! address the card,s registers) so !ou ma! want to use
e3tended memor! for something else. If !ou machine hangs during the startup
se>uence for no apparent reason) check that !ou haven,t shadowed an area of
upper memor! containing a 0OM that doesn,t like itparticularl! one on a hard
disk controller) or that !ou haven,t got two in the same 6@B; segment.
Base Memory
The first ./7; available) which traditionall! contains $OS) device drivers) TS0s
and an! programs to be run) plus their data) so the less room $OS takes up) the
more there is for the rest. $ifferent versions of $OS were better or worse in this
respect. In fact) under normal circumstances) !ou can e3pect the first F7; or so to
consist of'
• An Interrupt &ector Ta'le) which is 6; in si=e) including the name and address
of the program providing the interrupt service. Interrupt vectors point to
routines in the BIOS or $OS that programs can use to perform low level
hardware access. $OS uses io4sys and msdos4sys for the BIOS and $OS)
respectivel!.
• 0OM BIOS tables) which are used b! s!stem 0OMs to keep track of what,s
going on. This will include I+O addresses and possibl! userdefined hard disk
data.
• $OS itself) plus an! associated data files it needs to operate with "e.g. buffers)
etc.%.
$OS was written to run applications inside the bottom ./7; block simpl!
because the designers of the original IBM (C decided to. Memor! at the time was
e3pensive) and most C(+M machines onl! used ./; an!wa! "the (C with 6@B;
was E67)777P%. Other machines of the same era used more- the Sirius allowed
BF.; for programs. Contrar! to popular belief) <indows C.6 uses memor! below
6Mb) for administration purposes- although it pools all memor! above and below
6 Mb "and calls it the (lo'al )eap%) certain essential <indows C.6 structures
must live below 6 Mb) such as the Task *ata#ase "T$B% which is necessar! for
starting new tasks.
8ver! <indows C.6 application needs D6@ b!tes of memor! below 6 Mb to load)
but some will take much more if the! can) even all that,s available) thus
preventing others from loading) which is one source of 4Out of Memor!4
messages. There are programs that will purposel! fragment base memor! so it
can,t be hogged b! an! one program.
0ather than starting at 7 and counting upwards) memor! addressing on the (C
uses a twostep se!ment5offset addressing scheme. The segment specifies a 6.
b!te paragraph of 0AM- the o++set identifies a specific b!te within it. The C(*
finds a particular b!te in memor! b! using two registers. One contains the
starting segment value and the other the offset. The ma3imum that can be stored
in one is .D)DCD "#### in he3%. The C(* calculates a ph!sical address b! taking
the contents of the segment register) shifting it one character to the left) and
adding the two together "see &igh Memor!%.
Sometimes) !ou will see both values separated b! a colon) as with ####'777#)
meaning the si3teenth b!te in memor! segment ####- this can also be
represented as the effective address 7#####h. <hen referring onl! to 6.b!te
paragraph ranges) the offset value is often left out. The 67@D;B of $OS memor!
is divided into 6. segments of ./;Beach. Conventional memor! contains the ten
segments from 7777h to F###h "b!tes 7 to .DDD)6.I%) and *pper memor!
contains the si3 segments ranging from A777h to ####h.
6pper Memory
The ne3t CB/; is reserved for private use b! the computer) so that an! e3pansion
cards with their own memor! or 0OMs can operate safel! there without
interfering with programs in base memor!) and vice versa, T!pical e3amples
include network interface cards or graphics adapters. There is no memory in it-
the space is simpl! reserved. This is wh! the memor! count on older machines
with onl! 6 Mb was ./7 J CB/; of e-tended memory- the CB/; was remapped
above 6 Mb so it could be used. <hen upper memor! blocks are needed) that
memor! is remapped back again) so !ou lose a bit of e3tended memor!.
This area is split into regions) A#) which in turn are split into areas numbered
from 7777 to #### he3adecimall! "./; each%. <ith the right software) this area
can be converted in "pper %emory for use b! TS0 "memor!resident programs%
to make more room downstairs. The amount of upper memor! available varies
between computers) and depends on the amount of space taken up b! the S!stem
BIOS and whether !ou have a separate 9HA BIOS "on board video sometimes
has its BIOS integrated in the s!stem BIOS%. It also depends on the number of
addin cards !ou have) e.g. disk controllers) that normall! take up around 6.;.
Some chipsets will alwa!s reserve this CB/; area for shadowing) so it will not
appear in the initial memor! count on powerup) the s!stem configuration screen)
or when using M8M. Other chipsets have a %emory Relocation option which will
readdress it above 6 Mb as e3tended memor!. Occasionall!) some 0OM space is
not needed once the machine has booted) and !ou might be able to use it. A good
e3ample is the first C@; of the S!stem BIOS) at #777 in ISA machines. It,s onl!
used in the initial stages of booting up) that is) before $OS gets to set up device
drivers) so this area is often useable.
-xtended Memory
Memor! above 6 Mb is known as extended memory) and is not normall! useable
under $OS) e3cept to provide 0AM disks or caches) because $OS runs in real
mode) and it can,t access e3tended memor! in protected mode which OS+@ and
<indows FD do. Some programs are able to switch the C(* from one to the other
b! using the *S Protected %ode Inter+ace "$(MI%. Although e3tended memor!
first appeared on the @B.) and some software was written to take advantage of it)
the @B. was used mostl! as a fast 5T) because $OS wasn,t rewritten. It wasn,t
until the CB.) with its memor! paging capabilit!) that e3tended memor! came to
be used properl!.
Hi!h Memory
The first ./; "less 6. b!tes% of e3tended memor!) which is useable onl! b! @B.)
CB. or /B. based computers that have more than 6Mb of memor!. It is the result
of having more than @7 address linees that can be e3ploited b! $OS to use that
portion of e3tended memor! as if it were below 6Mb) leaving !et more available
for programs in base memor!. In other words) it is e3tended memor! that can be
accessed in real mode. It is activated with himem4sys.
&MA access is possible because of the se!ment5offset addressing scheme of the
(C. Memor! addresses on a (C are @7 bits long) and are calculated b! shifting the
contents of a 6.bit register / bits to the left) and adding it to a 6.bit offset. The
B7BB) with onl! @7 address lines) cannot handle the address carr! bit) so the
processor simpl! wraps around to address 7777'7777 after ####'777#- in other
words) the upper / bits are discarded.
On a @B. or later) the is a @6st memor! address line that was left open b! accident
and which can be operated b! software) which gives !ou a dirt! bit. If the s!stem
activates this bit while in B7BB "real% mode) the wraparound doesn,t happen) and
the high memor! area becomes available. IBM has lead the A@7 line through a
switch in the ke!board controller to "de%activate this address line.
-xpanded Memory
This is the most confusing one of all) because it sounds so much like e3pansion
memor!) which is what e3tended memor! is sometimes called. Once the (C was
on the market) it wasn,t long before ./7; wasn,t enough) particularl! for people
using Aotus) the topselling application of the time) who were creating large
spreadsheets and not having enough memor! to load them) especiall! when
version @ needed .7; more memor! than the original. It wasn,t entirel! their
fault- Aotus itself in its earl! da!s was ver! inefficient in its use of memor!
an!wa!.
*sers got onto Aotus) Intel and Microsoft for a workaround) and the! came up
with AIM memor!) also known as -xpanded. It,s a s!stem of ph!sical bank
switching) were several e3tra banks of memor! can be allocated to a program) but
onl! one will be in the address space of the C(* at an! time) as that bank
switched) or pa!ed) as re>uired. In other words) the program code sta!s in the
ph!sical cells) but the electronic address of those cells is changed) either b!
software or circuitr!.
In effect) AIM "/.7% directl! swaps the contents of an! 6.; block of e3panded
memor! with a similar one inside upper memor!- no swapping takes place) but
the pages have their address changed to look as if it does. Once the page frame is
mapped to a page on the card) the data of that page can be seen b! the C(*.
(oints to note about AIM'
• It,s normall! onl! available for data "no program code%.
• (rograms need to be speciall! written to use it.
In theor!) AIM / doesn,t need a page frame) the programs !ou run ma! well
e3pect to see one. In addition) there could be up to ./ pages) so !ou could bank
switch up to a megab!te at a time) effectivel! doubling the address space of the
C(*) and enabling program code to be run and multitasking. This was called
large-+rame .%S) but it still used onl! four pages in upper memor!- the idea was
to remove most of the memor! on the motherboard. The memor! card 'ack+illed
conventional memor! and used the e3tra pages for banking.
On an B7B. or @B.based machine) e3panded memor! is usuall! provided b!
circuitr! on an e3pansion card) but there are some software solutions. CB. "and
/B.% based machines have memor! management built in to the central processor)
so all that,s needed is the relevant software to emulate AIM /emm(&'4exe or
similar%.
7irtual Memory
49irtual4 in the computer industr! is a word meaning that something is other than
what it appears to be. Man! people have difficulties to understand what virtual
memor! actuall! means. 9irtual memor! is memor! that does not e3ist. Several
contradictor! definitions about virtual memor! e3ist. #or some) virtual memor! is
not disk space. $isk "swap% space is used for backing allocated "committed%
memor! "global data) heap and stack% when the OS ran out of s!stem memor!
"0AM%. 83ample' ?ou create a program and define a stack of ./;B. Because
!our program reall! doesn,t re>uire ./;B "onl! @;B%) the OS will allocate onl!
one page "/;% during runtime. The other ./;B /;B K .7;B is virtual
memor!- memor! that does not e3ist) not in s!stem memor!) not on disk. Onl!
when !our program runs out of stack) another page will be allocated unless a total
of ./;B is used alread!.
#rom another point of view) 9irtual Memor! isn,t memor! at all) but hard disk
space made to look like it- the opposite of a 0AM disk. <indows "and S!stem I%
uses virtual memor! for s$ap +iles) used when ph!sical memor! runs out "!ou
need protected mode on a (C to do that%. Aike disk cacheing) 9M was used on
mainframes for some time before migrating to the (C- 9MS) the OS used on
$8C 9A5es) actuall! stands for &irtual %emory System. There is a speed
penalt!) of course) as !ou have to access the hard disk to use it) but 9irtual
Memor! is a good stopgap when !ou,re running short.
Bus Types
The purpose of an e3pansion bus is to provide a wa! for users to add hardware
de%ices "slotin cards% to a (C using standardised connectors. The advances of
technolog!) especiall! advancements in developing e3tremel! fast micro
processors) has given birth to more computer bus options than ever before. The
blame for not attaining high throughput levels no lon!er lies with the processor)
but rather with Input8Output de%ices such as hard disks) AA1 cards and video
cards. It is for this reason that manufacturers are devising better and more
efficient wa!s of interfacing the e3pansion slots to the processor itself.
The e3pansion bus "where e3pansion cards go% is an e3tension of the Central
(rocessor) so when adding cards to it) !ou are e3tending the capabilities of the
C(* itself. The relevance of this regard to the BIOS is that older cards are less
able to cope with modern buses running at higher speeds than the original design
of B or so M&=. Also) when the bus is accessed) the whole computer slows down
to the bus speed) so it,s often worth altering the speed of the bus or the wait states
between it and the C(* to speed things up. The (C actuall! has four buses- the
processor bus connects the C(* to its support chips) the memory bus connects
it to its memor!) the address bus is part of both of them) and the I8O /or
expansion1 bus is what concerns us here.
• Background
• ISA
• 8ISA
• MCA
• 9ABus
• (CI
Bac!round
Before the da!s of the original IBM (C) there were no standards. The first agreed
upon bus specification which was drawn up was called the S677. Steven Gobs
and Steven <osniak) the originators of Apple computers) are generall! credited as
been the first to implement e3pansion slots to allow the possibilit! of adding slot
in cards. This caught the attention of IBM and produced the first IBM (C with
e3pansion slots using the B7BB 6. bit C(*. The B7BB had an e3ternal bus of B bits
running at /.II M&=. The e3pansion slots were connected directl! to the C(*
and could therefore run at the full C(* clock speed of /.II M&=.
IBM then produced the AT computer which had an e3ternal 6. bit bus with a bus
speed of . M&= and later B M&=. The e3pansion slots were made to cope with
the 6. bit bus. In order to maintain compatibilit! with e3isting B bit cards) the 6.
bit slot was made to be backwards compatible. IBM clone manufacturers then
started pushing the C(* speeds up and kept the e3pansion slots at the same speed
as the C(*. At a bus speed of 6@ M&=) it was found that e3pansion cards no
longer functioned correctl!. Consensus was reached within the industr! to keep
e3pansion slots at a speed of B M&= irrespective of the C(* speed the Industr!
Standard Architecture "ISA% was born. It was at this time when e3pansion slots
were no longer directl! connected to the C(*.
The industr! was at peace until Intel produced the B7CB. processor with a C@ bit
bus. IBM also announced its Micro Channel Architecture for C@ bit bus data
transfer running at 67 M&=. In response to clone manufacturers) the 83tended
Industr! Standard Architecture "8ISA% was born in 6FBB with a bus speed of B.CC
M&=. 8ISA and MCA was considered too e3pensive for the average user so ISA
still remained as an alternative.
The world is now sitting with C@ bit architecture with video graphics cards and
hard disk controller cards plugged into ISA e3pansion slots tr!ing to transfer
man! megab!tes of data per second down a 6. bit bus running at B M&=. This
can be compared to a four lane high speed highwa! suddenl! coming down to
two lanes and still tr!ing to cater for the same high volume of traffic.
IS,
Industry Standard ,rchitecture. The Bbit version cane on the original (C and
the AT) but the latter uses an e3tension to make it 6.bit. It has a ma-imum data
transfer rate of about B megabits per second on an AT) which is actuall! well
above the capabilit! of disk drives) or most network and video cards. The
average data throughput is around a >uarter of that. Its design makes it difficult to
mi3 B and 6.bit 0AM or 0OM within the same 6@B; block of upper memor!-
an Bbit 9HA card could force all other cards in the same "C777$###% range to
use B bits as well) which was a common source of ine3plicable crashes where 6.
bit network card were involved.
System ,ttributes PC or )T ,T Classic Bus
Processor B7BB+B7B. @B. and higher
CP6 Modes 0eal 0eal+(rotected
-xpansion Slot B bit 6. bit
Slot Type ISA ISA
Interrupts B J 1MI 6. J 1MI
DM, Channels / B
Maximum +,M 6 MB 6. MB
3loppy Controller C.7;+I@7; 6.@M+6.//M
-IS,
-xtended Industry Standard ,rchitecture. An evolution of ISA and
"theoreticall!% backward compatible with it) including the speed "B M&=%) so the
increased data throughput is mainl! due to the bus doubling in si=ebut !ou must
use 8ISA e3pansion cards. It has its own $MA arrangements) which can use the
complete address space. On advantage of 8ISA "and Micro Channel% is the ease
of setting up e3pansion cardsplus them in and run the configuration software
which will automaticall! detect their settings.
System ,ttributes -IS, IS,
Memory Capacity / HB 6. MB
Data bus width C@ bit 6. bit
DM, +an!e / HB 6. MB
DM, data path B+6.+C@ B+6.
Maximum DM, Transfer CC MB+sec @ MB+sec
Bus ,rbitration . Bus Masters Single
Bus Master data path 6.+C@ 6.
Synchronous cloc rate B.CC M&= B.CC M&=
MC,
Micro Channel ,rchitecture. A proprietar! standard established b! IBM in 6FBI
to take over from ISA) and therefore incompatible with an!thing else. It comes in
two versions) 6. and C@bit and) in practical terms) is capable of transferring
around @7 MBps.
It was found that poorl! designed ISA bus machines did have fairl! high radio
fre>uenc! emissions. Hood ISA bus designs complied with the basic #CC Class A
regulations. MCA) with its ver! strict #CC Class B certification) has a distinct
advantage over ISA and 8ISA as C(* clock speeds go higher and higher. MCA is
ver! well shielded which makes it immune to electrical noise.
MCA is designed to eliminate the hassle associated with setting :umpers and $I(
switches on adapter boards. The adapter card booklet describing all possible
settings gets invariabl! lost) making the card unusable if the card,s environment
changes. IBM,s answer is called (rogrammable Option Selection "(OS% which is
built into MCA computers. The (OS uses a special file called an Adapter
$escription #ile "A$#% which is supplied with each adapter board. This A$#
contains all the possible setting and configurations for the specific card. The (OS
will also take care of an! conflicting settings.
MCA also corrects an! potential timing problems which ma! e3ist between
adapter boards or even memor!. 8ach e3pansion slot is supposed to carr! the
same signals as an! other slot but this might not alwa!s happen. 8ffects on the
bus) such as capacitance and signal propagation dela!s) can cause timing
windows to appear differentl! in different slots. These effects cause une3plained
problems to occur mostl! in a random fashion. MCA has the abilit! to wait for a
response "automatic wait states% until the adapter is read! to continue. This can
slow the process down but is considered more important than the 4ghost4
s!mptoms found on ISA.
79 Bus
The 9ideo 8lectronics Standards Association "98SA% formed a committee in
Gune 6FF@ to stud! e3isting and certainl! emerging) local bus video s!stems in
terms of connector la!out) signal and data structures. In September 6FF@ the!
finalised the 98SA Aocal Bus connector which connects devices directl! to the
local+host bus. There,s also an ,Opti local bus connector,. This connector e3tends
the 8ISA bus where the 9AB connector e3tends the ISA bus. The local bus is one
more directl! suited to the C(*- it,s ne3t door "hence local%) has the same
bandwidth and runs at the same speed) so the bottleneck is less "ISA was local in
the earl! da!s%. $ata is therefore moved along the bus at processor speeds. 792
B6S) a C@bit bus which allows bus mastering) and uses two c!cles to transfers a
C@bit word) peaking at .. Mb+sec. It also supports burst mode) where a single
address c!cle precedes four data c!cles) meaning that / C@bit words can move in
onl! D c!cles) as opposed to B) giving 67D Mb+sec at CC M&=. The speed is
mainl! obtained b! allowing 9ABus adapter cards first choice at intercepting
C(* c!cles. It,s not designed to cope with more than a certain number of cards at
particular speeds- e.g. C at CC) @ at /7 and onl! 6 at D7 M&=) and even that often
needs a wait state inserted. 9ABus @ is ./bit) !ielding C@7 Mb+sec at D7 M&=.
There are two t!pes of slot- Master and Slave. Master boards "e.g. SCSI
controllers% have their own C(*s which can do their own things- slaves "i.e.
video cards% don,t. A slave board will work on a master slot) but not vice versa.
PCI
PCI) which is a me==anine bus) divorced from the C(*) giving it some
independence and the abilit! to cope with more devices) so it,s more suited to
crossplatform work. It is time multiple3ed) meaning that address and data lines
share connections. It has its own burst mode that allows 6 address c!cle to be
followed b! as man! data c!cles as s!stem overheads allow. At nearl! 6 word per
c!cle) the potential is @./ Mb+sec. It can operate up to CC M&=) or .. M&= with
(CI @.6 and can transfer data at C@ bits per clock c!cle so !ou can get up to 6C@
Mb!tes+sec "@./ with @.6%. The (CI @.6 specs include a ./bit ..M&= (CI bus.
8ach (CI card can perform up to B functions) and !ou can have more than one
busmastering card on the bus. It should be noted) though) that man! functions are
not available with (CI) such as sound. 1ot !et) an!wa!. It is part of the plug and
play standard) assuming !our operating s!stem and BIOS agree) so it is auto
configuring "although some cards use :umpers instead of storing information in a
chip%- it will also share interrupts under the same circumstances. The (CI chipset
handles transactions between cards and the rest of the s!stem) and allows other
buses to be bridged to it "t!picall! and ISA bus to allow older cards to be used%.
1ot all of them are e>ual) though- certain features) such as 'yte merging) ma! be
absent. The connector ma! var! according to the voltage the card uses "C.C or Dv-
some cards can cope with both%
Basic Optimi0ation Trics
This section is intended for users who have a limited knowledge of BIOS setup to
safel! alter their settings. It provides a set of fundamental procedures that ma!
help improve the performance of !our s!stem. Also) have a look at the important
BIOS settings section.
• Make sure that all standard settin!s correspond to the installed components of
!our s!stem. #or instance) !ou should verif! the date) the time) available
memor!) hard disks and flopp! disks. #or more information) go to the Standard
CMOS Setup section.
• Make sure that !our cache memory "internal and e3ternal% is enabled. Of
course !ou must have internal "A6% and e3ternal "A@% cache memor! present
which is alwa!s the case for recent s!stems "less than five !ears old%. #or more
information) go to the Advanced CMOS Setup section. 0ecentl!) some
motherboards were found having fae cache memory. Some unscrupulous
manufacturers are using solid plastics chips containing no memor! to lure
vendors and customers and then gain e3tra profits in an highl! competitive
semiconductors market. BewareP #or more information about this scam
"mostl! occurring in 8ngland%) please consult this <eb site'
http'++www.dfw.net+Qsdw+bios.html.
• Make sure that !our .ait States values are at the minimum possible. ?ou
must however be careful because if values are too low) !our s!stem ma! free=e
"hang up%. #or more information "notabl!) to value to choose depending on
!our memor! speed% go to the Advanced Chipset Setup section.
• Make sure to shadow !our 9ideo and S!stem 0OM. On older s!stems) this
ma! improve performance significantl!) while on newer it ma! not make much
difference. #or more information) go to the Advanced CMOS Setup section.
• Make sure to use a coherent power mana!ement strateg!. Choosing the right
timing ma! increase the life e3pectanc! of !our hard disk. See the (ower
Management section.
• Hard dis speed is the ma:or bottlenec for a s!stem performance) notabl!
for those with 6. MB of memor! and more. ?ou ma! have the fastest C(*)
lots of memor! and a confortable cache) but if !ou have a crumm! hard disk)
!ou ma! not see improvement in performances.
Important BIOS Settin!s
This is a short list of settings important for the appropriate configuration of !our
s!stem. A long list is available in the inde3 section. DO ;OT mess with these
settings unless !ou have read carefully their implications. Also) please have a
look at the basic optimi=ation tricks on how to coordinate some of these settings.
Standard CMOS Setup
• $ate and Time
• (rimar! $ispla!
• ;e!board
• &ard $isk C T!pe
• #lopp! $rive A
,d%anced CMOS Setup
• Above 6 MB Memor! Test
• Memor! parit! error check
• 1umeric (rocessor Test
• S!stem Boot Se>uence
• 83ternal Cache Memor!
• Internal Cache Memor!
• (assword Checking Option
• 9ideo 0OM Shadow C777)6.;
• S!stem 0OM Shadow #777)./;
,d%anced Chipset Setup
• AT B*S Clock Selection
• Memor! 0ead <ait State
• Memor! <rite <ait State
• Cache 0ead Option
• I$8 Multi Block Mode
Plu! and Play8PCI
• Aatenc! Timer "(CI Clocks%
• Slot 5 *sing I1TR
• 5th Available I0S
• (CI I$8 I0S Map to
• AT bus clock fre>uenc!
• (CI Clock #re>uenc!
• ISA Bus Clock #re>uenc!
Standard CMOS Setup
+emember youn! <edi=
?ou should have !our current setup options written down O; P,P-+
somewhere) preferabl! taped to the inside or the outside of the case. CMOS
memor! has a tendenc! to get erased as the batter! gets old) or become
inaccessible if !ou forget the password. 8speciall! remember the hard dis
settin!s- the! are the most important.
If !ou have warmbooted the computer "via CT0AAAT$8A% to go into the
CMOS setup) the BIOS routine to handle the 4(rint Screen4 ke! will probabl! be
installed. ?ou can displa! each screen of the CMOS setup and press S&I#T
(0I1T SC0881 to get a printed cop! directl!. There are several good CMOS
saver programs out on the market) including the (CTools and 1orton recover!
programs. The! allow a user to save a cop! of the CMOS registers to a file in
case the batter! dies) or if the! messed around with the settings) etc.
• Date /mn8date8year1 and Time' To change the date and time of the s!stem
clock. $o not e3pect !our computer to keep tract of time as accuratel! as an
atomic clock) or even a wrist watchP $epending of the >ualit! of the
motherboard e3pect to loose "or gain% several seconds per month. On rare
occasion !ou will need to setup the clock in BIOS Setting as all operating
s!stems allow to change these settings within their environments. See also the
?ear @777 (roblem.
• Dayli!ht Sa%in!' Allows the clock to automaticall! adapt to the da!light
saving scheme which is removing one hour on the last Sunda! of October and
adding one hour on the last Sunda! of April. Onl! related to 1orth American
and <indows FD and 1T automaticall! use it.
• Hard dis C type' The number of !our primar! "master% hard drive. Most of
the time this number is /I) which means that !ou must specif! the drive specs
according to !our hard drive manual.
• Cyln' The number of c!linders on !our hard disk.
• Head' The number of heads.
• .Pcom' <rite (recompensation. Older hard drives have the same
number of sectors per track at the innermost tracks as at the outermost
tracks. This means that the data densit! at the innermost tracks is higher
and thus the bits are l!ing closer together. Starting with this C!lR until
the end of C!lRs the writing starts earlier on the disk. In modern &$s
such as SCSI "Small Computer S!stems Interface% this entr! is useless.
Set it either to 6 or ma3 C!ln "a common value is .DDCD%. #or I$8
"Integrated $evice 8lectronics% hard drives it is not necessar! to enter a
<( c!linder. The I$8 &$$ will i!nore it for it has its own parameters
inboard.
• 9>one' The address of the landing =one. Same as <(com. *sed in old
&$s without an autoparking feature "M#M) Modified #re>uenc!
Modulated) or 0AA) 0un Aength Aimited%. Set it to 7 or ma3 C!lR.
• Sect' The number of sectors per track. It is often 6I for M#M and @. for
0AA &$$. On other t!pes of drives) it will var!.
• Si0e ' This is automaticall! calculated according the number of c!linders)
heads and sectors. It is in megab!tes and applies this formula' "&ds T C!l
T Sect T D6@% + 67/B.
-ID- specifications. <ith the growing capacit! of hard disks on desktop
computers) a redefinition of I$8 specifications was necessar!. The old I$8
specification onl! supported drives up to D@B megab!tes) which is the ;ormal
partition setting. In 6FF/) the 8I$8 "8nhanced I$8% protocol was designed and
now all new motherboards support it. This new protocol uses the 9B, "Aogic
Block Addressing% s!stem which considers logic blocks instead of heads)
c!linders and sectors. It can support drive up to B./ HB. If !our BIOS does not
support ABA) several hard disk manufacturers provide drivers to trick the BIOS.
?ou will also find a 9ar!e partition setting that can accommodate drives up to
67@/ c!linders) but do not support ABA. *nfortunatel!) man! large
implementations don,t work correctl! for drives of over 6HB "there,s no good
reason wh! it wouldn,t work for much larger drives though%. 1ote that 67@/
c!linders native is D@BMB. The D@BMB limit is the 67@/ c!l + 6. head + .C sector
limit. #or more information about 8I$8) please have a look at the 8I$8 #AS.
• Hard dis D type' The number of !our secondar! "slave% hard drive. Same
procedure than above. <umpers must be set for an hard dri%e to perform as
sla%e as well as master. (lease refer to !our hard drive manual for appopriate
:umpers settings "these settings are also shown on the hard disk itself%. ?ou
might also want to refer to the hard disk data file fre>uentl! posted to
comp.s!s.ibm.pc.hardware.storage.
Several of the (CI motherboards can now accommodate up to four I$8 drives'
(rimar! Master) (rimar! Slave) Secondar! Master and Secondar! Slave.
• 3loppy dri%e ,' The t!pe of flopp! drive installed for drive A. #re>uent
configurations are 6.// MB "C 6+@ inches%) or 6.@ MB "D 6+/%. 1ewer s!stems
have also a @.BB MB "C 6+@% setting.
• 3loppy dri%e B' The t!pe of flopp! drive installed for drive B.
• Primary display' The t!pe of displa!ing standard !ou are using) and in case of
s!stems with two video adapters the primar! one. The most fre>uent is
9HA+(HA+8HA. Modern computers have 9HA "9ideo Hraphics Arra!%. If
!ou have an older black+white displa! select Mono or &ercules) if !our 9ideo
adapter card is te3t onl!) select M$A.
• ?eyboard' Installed recommended. If 4not installed4 this option sets the BIOS
to pass the ke!board test in the (OST) allowing to reset a (C without a
ke!board "file server) printer server) etc.%) without the BIOS producing a
ke!board error. As a s!stem administrator) !ou can uninstall the ke!board as a
supplementar! securit! procedure to prevent people messing up with the
server.
,d%anced CMOS Setup
+emember=
Ma! var! according to !our s!stem) BIOS version and brand. Some functions
ma! not be present or the order and name may be different "particularl! for
different BIOS brand%. ;now -),CT9" what !ou are doing. Some
configurations ma! keep !our computer off from bootin!. If that,s the case'
Switch the power off. Turn !our computer on .HI9- keeping the D-9 ke!
pressed. This is supposed to erase the BIOS memor!. If it still doesn,t boot)
consult !our motherboard manual. Aook for a 4forget CMOS 0AM4 :umper. Set
it. Tr! it again. If it still doesn,t boot) ask a friend or post to a computer hardware
newsgroup. ?ou are permitted to panic.
• Typematic +ate Pro!rammin!' $isabled recommended. It enables the
t!pematic rate programming of the ke!board. 1ot all ke!boards support thisP
The following two entries specif! how the ke!board is programmed if enabled.
• Typematic +ate Delay /msec1' D77 ns recommended. The initial dela! before
ke! autorepeat starts) that is how long !ou,ve got to press a ke! before it starts
repeating.
• Typematic +ate /Chars8Sec1' 6D. It is the fre>uenc! of the autorepeat i.e.
how fast a ke! repeats.
• ,bo%e @ MB Memory Test' If !ou want the s!stem to check the memor!
above 6 MB for errors. Disabled recommended for faster boot se>uence. The
&IM8M.S?S driver for $OS ..@ verifies the 5MS "83tended Memor!
Specification%) so this test is redundant. It is thus preferable to use the 5MS
test provided b! &IM8M.S?S since it is operating in the real environment
"where user wait states and other are operational%.
• Memory Test Tic Sound' 8nabled recommended. It gives an audio record
that the boot se>uence is working properl!. (lus) it is an aural confirmation of
!our C(* clock speed+Turbo switch setting. An e3perimented user can hear if
something is wrong with the s!stem :ust be the memor! test tick sound. Since
s!stems have now much more memor! than before) this setting is not common
an!more.
• Memory Parity -rror Chec' -nabled recommended. Additional feature to
test bit errors in the memor!. All "or almost all% (Cs are checking their
memor! during operation.8ver! b!te in memor! has another ninth bit) that
with ever! write access is set in such wa! that the parit! of all b!tes is odd.
<ith ever! read access the parit! of a b!te is checked for this odd parit!. If a
parit! error occurs) the 1MI "1on Maskable Interrupt%) an interrupt !ou mostl!
cannot switch off) so the computer stops his work and displa!s a 0AM failure%
becomes active and forces the C(* to enter an interrupt handler) mostl!
writing something like this on the screen' (A0IT? 800O0 AT 7ABD'77B8
S?ST8M &AAT8$. On some motherboards !ou can disable parit! checking
with standard memor!. 8nabled to be sure data from memor! are correct.
$isable onl! if !ou have Bbit 0AM) which some vendors use because it is
67N cheaper. Also) this setting is no longer necessar! on recent computers
since the >ualit! and reliance of memor! chips has greatl! been improved.
,bout different memory speeds' Be sure to have memor! chips of the same
speed installed. It is not uncommon to have s!stem crashes simpl! because
memor! SIMMS are of different speed. #aster memor! ma! not adapt itself to the
speed of slower memor!. .7 ns and B7 ns SIMMS will surel! make !our s!stem
crash and !ourself wonder what is the problem "I know%.
• Hard Dis Type *A +,M ,rea' The BIOS has to place the &$ t!pe /I data
somewhere in memor!. ?ou can choose between $OS memor! or (C BIOS
"or peripheral card% memor! area 7'C77. $OS memor! is valuable) !ou onl!
have ./7;B of it. So !ou should tr! to use 7'C77 memor! area instead. There
ma! be some peripheral card which needs this area too "sound card) network
card) whatever%. So if there are some fanc! cards in !our (C) check the
manuals if the!,re using the 7'C77 area. But in most cases this will work
without checking. This is redundant if BIOS is shadowed "ma!be not in ver!
old BIOSes%. The 0AM area can be verified b! checking address of int/6h and
int/.h. These are fi3ed disk parameters blocks. If the! point to the BIOS area)
BIOS made modification of parameters before mapping 0AM there.
• If An! 8rror4.ait for B3@C If ,ny -rror' <hen the boot se>uence encounter
an error it asks !ou to press #6. Onl! at ,nonfatal, errors. If disabled) the
s!stem prints a warning and continues to boot without waiting for !ou to press
an! ke!s. 8nabled recommended. $isabled if !ou want the s!stem to operate
as a server without a ke!board.
• System Boot 6p ;um 9oc' Specif! if !ou want the 1um Aock ke! to be
activated at boot up. Some like it) some do not. MS$OS "starting with ..7)
ma!be earlier% allows a 41*MAOC;K4 directive in config.s!s) too- if
someone turns the BIOS flag off but has 1*MAOC;KO1 in their
configuration file) the! ma! be a bit perturbed.
• ;umeric Processor Test' 8nabled if !ou have a math coprocessor "built in for
the /B.$5) /B.$5@) /B.$5C and (entium DB. famil!%. $isabled if !ou
don,t "CB.S5) CB.$5) /B.S5) /B.SAC and /B.$AC%. If disabled) !our #(*
"#loating (oint *nit) if present% isn,t recogni=ed as present b! the s!stem and
will therefore significantl! decrease the performance of !our s!stem.
• .eite Coprocessor' If !ou have <eitek #(*) enable. If !ou have not)
disable. This high performance #(* has @C times the performance of the Intel
#(*. <eitek uses some 0AM address space) so memor! from this region must
be remapped somewhere else. This setting is normall! found on CB.
motherboards.
• 3loppy Dri%e See at Boot' (ower up !our A' flopp! drive at boot. Disabled
recommended for faster boot seDuence and for reduced dama!e to heads.
$isabling the flopp! drive) changing the s!stem boot se>uence and setting a
BIOS password are good techni>ues for adding some securit! to a (C.
• System Boot SeDuence' <hat drive the s!stem checks first for an operating
s!stem. C5E ,5 recommended for faster boot seDuence) or to not allow an!
user to enter !our s!stem b! booting from the #$$ if !our autoe3ec.bat starts
with a login procedure. A') C' if the person who uses the computer is someone
who don,t knows how to setup CMOS. Because if something fails and a boot
flopp! won,t work) man! users won,t know what to do ne3t. &owever) be
careful. ?ou had better know this setting is turned on and be prepared to turn it
off if !our hard disk boot track becomes corrupted) but not obviousl! absent)
since !ou otherwise won,t be able to boot from flopp!. Also) it,s eas! to fool
!ourself into thinking !ou booted from a known virusfree flopp! when it
actuall! booted from the "virusinfested% hard drive.
• System Boot 6p CP6 speed' Specif! at what processor speed the s!stem will
boot from. *sual settings are &IH& and AO<. HIFH recommended. If !ou
encounter booting problems) !ou ma! tr! AO<. ?ou ma! also change the C(*
speed with CtrlAlt J.
• -xternal Cache Memory' 8nabled if !ou have e3ternal cache memor!
"better nown as 9# cache memory%. This is a fre>uent error in CMOS setup
as if $isabled when !ou have cache memor!) the s!stem performance
decreases significantl!. Most s!stems have from ./; to D6@; of e3ternal
cache. It is a cache between the C(* and the s!stem bus. $ifferent operating
s!stems ma! address different levels of cache memor!. #or instance) $OS and
<indows can address up to ./; at one time while <indows FD) OS+@ and
<indows 1T can address larger memor! spaces. So) don,t bu! @D.; of cache
is !ou are using a $OS environment with less than BMB of memor!. It will not
improve much the performance of !our s!stem. If 8nabled when the s!stem
does not have cache memor!) the s!stem will free0e most of the time.
• Internal Cache Memory' 8nable or disable the internal cache memor! of the
C(* "better nown as 9@ cache memory%. $isabled for CB. and 8nabled for
/B. "6 to B;B of internal C(* cache%. If the C(* does not have internal
cache) the s!stem ma! free=e if enabled.
In man! AMI and A<A0$ BIOSes) the two previous options are implemented
either as separate Internal and 83ternal 8nable+$isable options) or as a single
option "Cache Memory 5 Disabled8Internal8Both%.
• CP6 Internal Cache5 same as above.
• 3ast Fate ,#$ Option' 8nabled recommended. A@7 refers to the first ./;B
of e3tended memor! "A7 to A6F% known as the 4high memor! area4. This
option uses the fast gate A@7 line) supported in some chipsets) to access
memor! above 6 MB. 1ormall! all 0AM access above 6 MB is handled
through the ke!board controller chip "B7/@ or BI/@%. *sing this option will
make the access faster than the normal method. This option is ver! useful in
networking and multitasking operating s!stems.
• Turbo Switch 3unction' 8nables or disables the turbo switch. $isabled
recommended. This setting is now removed since there are no need to switch
from normal to turbo modes.
• Shadow Memory Cacheable' ?ou increase speed b! cop!ing 0OM to 0AM.
$o !ou want to increase it b! cacheing itO ?es or no see 9ideo BIOS Area
cacheable. ?es recommended for MS$OS and OS+@. Ainu3 and other *ni3
like operating s!stems will not use the cached 0OMs and will benefit from the
additional available memor! if the! are not cached.
• Password Checin! Option' Setup password to have access to the s!stem and
+ or to the setup menu. Hood if the computer is to be shared with several
persons and !ou don,t want an!one "friends) sister) etc.% to mess up with the
BIOS. $efault password' AMI "if !ou have AMI BIOS%. Award' BIOSTA0 or
A<A0$2S< for newer versions "1ote' I even know a computer store that
kept standard A<A0$ BIOS configuration with their s!stems because the!
didn,t know what the default password wasP%.
• 7ideo +OM Shadow C$$$E (#?' Memor! hidden under the 4I+O hole4 from
737A7777 to 737##### ma! be used to 4shadow4 0OM "0eadOnl!
Memor!%. $oing so) the contents of the 0OM are copied into the 0AM and the
0AM is used instead) which is obviousl! faster. 9ideo BIOS is stored in slow
8(0OM "8rasable (rogrammable 0eadOnl! Memor!% chips "6@7 to 6D7ns of
access time%. Also) 0OM is B or 6. bit while 0AM C@ bit wide access. <ith
Shadow on) the 8(0OM content is copied to 0AM ".7 to B7ns of access time
with C@ bit wide access%. Therefore performance increases significantl!. Onl!
sensible on 8HA+9HA s!stems. -nabled recommended. If !ou have flash
BIOS "88(0OM%) !ou can disable it. #lash BIOS enables access at speeds
similar to memor! access so !ou can use the memor! elsewhere. &owever)
flash BIOS is still onl! accessing it at the speed of the bus "ISA) 8ISA or
9AB%. On s!stems where the BIOS automaticall! steals CB/; of 0AM
an!wa!) it shouldn,t hurt to enable shadowing even on flash 0OM. One side
effect is that !ou will not be able to modif! the contents of flash 0OM when
the chip is shadowed. If !ou reconfigure an adapter which !ou think might
have flash 0OM) and !our changes are ignored) or of course if it gives !ou an
error message when !ou tr! to change them) !ou,ll need to temporaril! disable
shadowing that adapter. On "S%9HA !ou should enable both video shadows.
Some video cards ma!be using different addresses than C777 and C/77. If it is
the case) !ou should use supplied utilities that will shadow the video BIOS) in
which case !ou should disable this setting in the CMOS. 9ideo BIOS
shadowing can cause software like 5#reeB. "the free 5 <indow S!stem% to
hang. The! should be probabl! be disabled if !ou run an! of the CB. uni3es.
Some cards map BIOS or other memor! not onl! in the usual a7777fffff address
range) but also :ust below the 6.MB border or at other places. The BIOS "for (CI
buses onl!O% now allows to create a hole in the address range where the card sits.
The hole ma! be enabled b! giving an address) then a si=e is re>uested in power
of @) ./k 6MB.
• ,daptor +OM Shadow C&$$E@'?' $isabled. Those addresses "CB77 to
8C77% are for special cards) e.g. network and controllers. 8nable onl! if !ou,ve
got an adapter card with 0OM in one of these areas. It is a BA$ idea to use
shadow 0AM for memor! areas that aren,t reall! 0OM) e.g. network card
buffers and other memor!mapped devices. This ma! interfere with the card,s
operation. To intelligentl! set these options !ou need to know what cards use
what addresses. Most secondar! displa! cards "like M$A and &ercules% use
the 0OM CB77 address. Since the! are slow) shadowing this address would
improve their performance. An advanced tip' in some setups it is possible to
enable shadow 0AM without writeprotecting it- with a small driver "*MM% it
is then possible to use this ,shadow 0AM, as *MB "*pper Memor! Block%
space. This has speed advantages over *MB space provided b! 8MMCB..
Some BIOSes have three options per 6.;B+C@;B+./;B block- e.g. disable
shadow 0OM shadow 0AM or disable shadow+<( shadow "<( K write
protect% the third option is for upper memor!.
• ,daptor +OM Shadow CC$$E@'?' $isabled. Some hard drive adapters use
that address.
• ,daptor +OM Shadow D$$$E@'?' $isabled. $777 is the default Address for
most 1etwork Interface Cards.
• ,daptor +OM Shadow D*$$E@'?' $isabled. Some special controllers for
four flopp! drives have a BIOS 0OM at $/77..$I##.
• ,daptor +OM Shadow D&$$E@'?' $isabled
• ,daptor +OM Shadow DC$$E@'?' $isabled
• ,daptor +OM Shadow -$$$E@'?' $isabled. 8777 is a good 4out of the wa!4
place to put the 8MS page frame. If necessar!.
• ,daptor +OM Shadow -*$$E@'?' $isabled
• ,daptor +OM Shadow -&$$E@'?' $isabled
• ,daptor +OM Shadow -C$$E@'?' $isabled. SCSI controller cards with
their own BIOS could be accelerated b! using Shadow 0AM. Some SCSI
controllers do have some 0AM areas too) so it depends on the brand.
Some SCSI adapters do not use I+OAddresses. The BIOS address range contains
writable addresses) which in fact are the I+Oports. This means this address must
not be shadowed and even not be cached.
• System +OM Shadow 3$$$E '*?' Same thing as 9ideo shadow) but
according to the s!stem BIOS "main computer BIOS%. -nabled
recommended for impro%ed performance. S!stem BIOS shadowing and
caching should be disabled to run an!thing but $OS "<indows%.
On older BIOS versions the shadow choices are in /77"he3%b!te increments. #or
instance) instead of one 9ideo 0OM Shadow segment of C@;) !ou will have two
6.; segments "C/77 and CB77%. Same thing for Adaptor 0OM Shadow
segments.
• BootSector 7irus Protection' It is not e3actl! a %irus protection. All it does
is whenever !our boot sector is accessed for writing) it gives a warning to the
screen allowing !ou to disable the access or to continue. 83tremel! anno!ing if
!ou use something like OS+@ Boot Manager that needs to write to it. It is
completel! useless for SCSI or 8S$I "8nhanced Small $evice Interface%
drives as the! use their own BIOS on the controller. Disabled recommended.
If !ou want virus protection) use a TS0 "Terminate and Sta! 0esident% virus
detection "1orton) Central (oint) etc...%. 9iruscan b! Macfee is also a good
idea since it is a shareware.
,d%anced Chipset Setup
+emember=
Confi!urations may %ary according to !our s!stem) BIOS version and brand.
So) some settings ma! be present on !our computer) some ma! not or have a
different name. Be sure of what !ou are doingP If !ou find a configuration having
a different name) please let us know.
• +efresh
• Data Bus
• Cachein!
• Memory
• ,utomatic Confi!uration' Allows the BIOS to set automaticall! several
important settings "e.g. Clock divider) wait states) etc.%. 9er! useful for
newbies. Disabled recommended if you want to play around with the
settin!s. If !ou have some special adapter cards) !ou will also have to disable
this option.
• ?eyboard +eset Control' 8nable CtrlAlt$el warm reboot. 8nabled
recommended for more control over !our s!stem.
+efresh
• Hidden +efresh' Allows the 0AM refresh memor! c!cles to take place in
memor! banks not used b! !our C(* at this time) instead or together with the
normal refresh c!cles) which are e3ecuted ever! time a certain interrupt
"$0S7 ever! 6D ms% is called b! a certain timer "O*T6%. 8ver! time it takes @
to / ms for the refresh. One refresh c!cle ever! Q6. us refreshes @D. rows in Q
/ms. 8ach refresh c!cle onl! takes the e>uivalent of one memor! read or less)
as CAS "Column Address Strobe% is not needed for a refresh c!cle. Some
0AM can do it) some not. Tr!. If the computer fails) turn it off. 8nabled
recommended. There are t!picall! C t!pes of refresh schemes' c!cle steal)
c!cle stretch) or hidden refresh. C!cle steal actuall! steals a clock c!cle from
the C(* to do the refresh. C!cle stretch actuall! dela!s a c!cle from the
processor to do the refresh. Since it onl! occurs ever! sa! /ms or so) it,s an
improvement from c!cle steal. <e,re not reall! stealing a c!cle) onl! stretching
one. &idden refresh t!picall! doesn,t stretch or steal an!thing. It,s usuall! tied
to $TAC; "$ata acknowledge% or AA8 "Address Aatch 8nable% or some other
signal relating to memor! access. Since memor! is accessed AAA of the time it
is eas! to s!nchroni=e the refresh on the falling edge of this event. Of course)
the s!stem performance is at its optimum efficienc!) refresh wise since we,re
not taking clock c!cles awa! from the C(*.
• Slow +efresh' Causes 0AM refresh to happen less often than usual) around
four times. This increases the performance slightl! due to the reduced
contention between the C(* and refresh circuitr!) but not all $0AM
memories necessaril! support these reduced refresh rates "in which case !ou
will get parit! errors and crashes%. It also saves power) a good opportunit! for
laptop computers. -nabled recommended
• Concurrent +efresh' Both the processor and the refresh hardware have access
to the memor! at the same time. If !ou switch this off) the processor has to
wait until the refresh hardware has finished "it,s a lot slower%. -nabled
recommended.
• Burst +efresh5 (erforms several refresh c!cles at once. Increase the s!stem
performance.
• D+,M Burst at * +efresh5 0efresh is occurring at Bursts of four) increasing
the s!stem performance.
• Hi2speed +efresh5 0efreshes are occurring at an higher fre>uenc!) which is
improving the s!stem performance. Of course) not all t!pes of memor! can
support it and Slow 0efresh is preferred.
• Sta!!ered +efresh5 0efresh is performed on memor! banks se>uentiall!. The
advantages are related to less power consumption and less interference
between memor! banks.
• Slow Memory +efresh Di%ider5 The AT refresh c!cle occurs normall! ever!
6. ns) straining the C(*. If !ou can select an higher value) such as ./ ns) !ou
will increase the performance of !our s!stem.
• Decoupled +efresh Option5 8nables the ISA bus and the 0AM to refresh
separatel!. Because refreshing the ISA bus is more slow) this causes less strain
on the C(*.
• +efresh 7alue' The lower this value is) the best the performance.
• +efresh +,S ,cti%e Time' The amount of active time needed for 0ow
Address Strobe during refresh. The lower the better.
Data Bus
• Sin!le ,9- -nable' Address Aatch 8nable "AA8% is an ISA Bus Signal "(in
B@B% that indicates that a valid address is posted on the bus. The bus is used to
communicate with B and 6. bit peripheral cards. Some chipsets have the
capabilit! to support an enhanced mode in which multiple AA8 assertions ma!
be made during a single Bus C!cle. Single AA8 8nable apparentl! enables or
disables that capabilit!. Ma! slow the video bus speed if enabled. $isabled
"1o% recommended.
• ,T B6S Cloc Selection /or ,T Bus Cloc Source1' Hives a division of the
C(* clock "or S!stem Clock% so it can reach the ISA 8ISA bus clock. An
improper setting ma! cause significant decrease in performance. The settings
are in terms of CA;+3) "or CA;I1+3 and CA;@+3% where 3 ma! have values
like @) C) /) D) etc. CA; represents !our processor speed) with the e3ception
that clockmultiple processors need to use the 85T801AA clock rate) so a
/B.$5CC) /B.$5@+..) and /B.$5C+FF all count as CC and should have a
divider value of /. #or @B. and CB. processors) CA; is half the speed of the
C(*. ?ou should try to reach &4(( Mh0 "that,s the old bus clock of IBM AT-
there ma! be cards which could do higher) but it,s not highl! recommended%.
On some motherboards) the AT bus speed is I.6D Mh=. On new BIOS versions)
there is an A*TO setting that will look at the clock fre>uenc! and determine
the proper divider. &ere are some appropriate settings'
CA;
+C
S5+$56.) $5@7) $5@D) $5@+D7)
$5/+677
CA;
+/
S5+$5CC) $5@+..) $5C+FF
CA;
+D
$5/7) $5@+B7
CA;
+.
$5D7) $5@+677
Selectin! the ri!ht cloc di%ider. ?ou can tr! other clock settings to increase
performance. If !ou choose a too small di%ider "CA;+@ for a $5CC% your
system may han!. #or a too bi! di%ider "CA;+D for a $5CC% the performance
of IS, cards will decrease. This setting is for data e3change with ISA cards)
;OT 79 bus and PCI cards which run at C(* bus clock speeds' @DMh=)
CCMh= and higher. If !our ISA cards are fast enough to keep up) it is possible to
run the bus at 6@ Mh=. 1ote that if !ou switch cr!stals to overclock !our C(*)
!ou are also overclocking the ISA bus unless !ou change settings to compensate.
Gust because !ou can overclock the C(* doesn,t mean !ou can get awa! with
overclocking the ISA bus. It might :ust be one card that causes trouble) but one is
enough. It might cause trouble even if !ou aren,t using it b! responding when it
shouldn,t.
• IS, Bus Speed' As above) but related to (CI.
• Bus Mode' It can be set in s!nchronous and as!nchronous modes. In
s!nchronous mode) the C(* clock is used) while in as!nchronous mode the
ATCA; is used.
• ,T Cycle .ait State' <henever an operation is performed with the AT bus) it
indicates the number of wait states inserted. ?ou ma! need some wait states if
old ISA cards are used) notabl! if the! are in operation with fast adapter cards.
• @'2bit MemoryE I8O .ait State5 The number of wait states before 6.bit
memor! and I+O operations.
• &2bit MemoryE I8O .ait State' As above) e3cept this setting is for Bbit
operations.
• @'2bit I8O +eco%ery Time' The additional dela! time inserted after ever! 6.
bit operations. This value is added to the minimum dela! inserted after ever!
AT c!cles.
• 3ast ,T Cycle' If enabled) ma! speed up transfer rates with ISA cards) notabl!
video.
• IS, I+G' Inform the (CI cards of the I0Ss used b! ISA cards) so the! be
discarded.
• DM, .ait States' The number of wait states inserted before direct memor!
access "$MA%. The lower the better.
• DM, Cloc Source' The source of the $MA clock for which some peripheral
controllers) like flopp!) tape) network and SCSI adapters use to address
memor!) which is D M&= ma3imum.
• -$$$$ +OM belon!s to ,TB6S' Tells if the 87777 area "upper memor!%
belongs to the MB $0AM or to the AT bus. ?es recommended.
• Memory +emappin!' 0emaps the memor! used b! the BIOS "A7777 to
#### CB/ k% above the 6 Mb limit. If enabled !ou cannot shadow 9ideo and
S!stem BIOS. $isabled recommended.
• 3ast Decode -nable' 8nabled recommended. 0efers to some hardware that
monitors the commands sent to the ke!board controller chip. The original AT
used special codes not processed b! the ke!board itself to control the
switching of the @B. processor back from protected mode to real mode. The
@B. had no hardware to do this) so the! actuall! have to reset the C(* to
switch back. This was not a speed! operation in the original AT) since IBM
never e3pected that an OS might need to :ump back and forth between real and
protected modes. Clone makers added a few (A$ chips to monitor the
commands sent to the ke!board controller chip) and when the 4reset C(*4
code was seen) the (A$ chips did an immediate reset) rather than waiting for
the ke!board controller chip to poll its input) recogni=e the reset code) and then
shut down the C(* for a short period. This 4fast decode4 of the ke!board reset
command allowed OS+@ and <indows to switch between real and protected
mode faster) and gave much better performance. "earl! @B. clones with
(hoeni3 @B. BIOS had this setting to enable+disable the fast decode logic.% On
CB. and newer processors) the fast decode is probabl! not used) since these
C(*s have hardware instructions for switching between modes. There is
another possible definition of the 4#ast $ecode 8nable4 command. The design
of the original AT bus made it ver! difficult to mi3 Bbit and 6.bit 0AM or
0OM within the same 6@B; block of high address space. Thus) an Bbit BIOS
0OM on a 9HA card forced all other peripherals using the C777$fff range to
also use B bits. B! doing an 4earl! decode4 of the high address lines along with
the B+6. bit select flag) the I+O bus could then use mi3ed B and 6. bit
peripherals. It is possible that on later s!stems) this BIOS flag controls the
4fast decode4 on these address lines.
• -xtended I8O Decode' The normal range of I+O addresses is 773Cff- 67 bits
of I+O address space. 83tended I+Odecode enables wider I+Oaddress bus. The
C(* support a ./; I+O space) 6. address lines. Most motherboards or I+O
adapters can be decoded onl! b! 67 address bits.
• I8O +eco%ery Time' I+O recover! time is the number of wait states to be
inserted between two consecutive I+O operations. It is generall! specified as a
two number pair e.g. D+C. The first number is the number of wait states to
insert on an B bit operation) the second the number of waits on a 6. bit
operation. A few BIOSes specif! an I+O Setup time "AT Bus "I+O% Command
$ela!%. It is specified similarl! to IO 0ecover! Time) but is a dela! before
STA0TI1H an I+O operation rather than a dela! B8T<881 I+O operations.
D+C has been recommended as a value which will often !ield a good
combination of performance and reliabilit!. <hen enabled) more I+O wait
states are inserted. A transfer from I$8 hard drive to memor! happens without
an! handshaking) meaning the data has to be present "in the cache of the hard
disk% when the C(* wants to read them from an I+O (ort. This is called PIO
"(rogrammed I+O% and works with a 08( I1S< assembler instruction. 1ow
I+O 0ecover! Time enabled adds some wait states to this instruction. <hen
disabled) the hard drive is a lot faster. 1ote that there is a connection between
I+O 0ecover! Time and AT B*S Clock Selection. #or e3ample) if the AT B*S
Clock is set to B M&= and !ou have a normal hard disk) I+O 0ecover! Time
can be turned off) resulting in a higher transfer rate from hard disk.
• ID- Multi Bloc Mode' 8nable I$8 drives to transfer several sectors per
interrupt. According to the hard drive cache si=e) si3 modes are possible. Mode
$ "standard mode transferring a single sector at a time%) Mode @ "no
interrupts%) Mode @ "Sectors are transferred in a single burst%) Mode ( "C@bit
instructions with speeds up to 66.6 Mb+sec.In BIOSes usuall! abbreviated as
4C@bit mode4. 1ot to be confused with C@bit protected modeinstructions"P% or
<indows, C@bit disk access.%) Mode * "up to 6.)I Mb+sec.% and Mode H "up to
@7 Mb+sec.%. The socalled 4(IO mode D4 is completel! bogus. It was launched
b! some controller manufacturers but was never accepted) never absorbed into
the standards and !ou will not find an! disk drives supporting it. 1or will !ou
find an! such drives in the future. The relevant parameter for block mode is the
number of sectors per interrupt. The ma3imum number of sectors per interrupt
is often "but not alwa!s% related to the drive,s buffer si=e. If this setting is not
set properl!) communication with COM ports ma! not work properl!. If the
block si=e "sectors+interrupt% is set to too large a value) !ou ma! e3perience
serial port overruns and C0C errors. To fi3 this) decrease the block si=e
"preferred% or disable block mode altogether.#or more info) please have a look
at The 8I$8 #ASATA harddisks.
• ID- DM, Transfer Mode' Settings are $isabled) T!pe B "for 8ISA% and
Standard "for (CI%. Standard is the fastest but ma! cause problems with I$8
C$ 0OMs. The standard t!pe is t!pe #. 1ote that both are socalled 4third
part! $MA4 and should not be confused with firstpart! "busmastering% $MA
offered b! man! modern boards.
• ID- Multiple Sector Mode' <hen I$8 $MA Transfer Mode is enabled) this
sets the number of sectors per burst) with a ma3imum of ./. (roblems ma!
occur with COM ports.
• ID- Bloc Mode' 8nables multisectors transfers. Also known as ID- HDD
Bloc Mode.
.arnin!4 This setting is known to cause crashes in <inFD. $isabled
recommended. 83tremel! anno!ing.
• ID- (#2bit Transfer' <hen enabled) the read + write rate of the hard disk is
faster. <hen disabled onl! 6.bit data transfers is possible. The read+write rate
of the harddisk sta!s the same) but the transfers over the host bus are maybe
faster. So) don,t e3pect an!thing reall! dramatic. Actuall!) !ou should
ordinaril! e3pect no difference at all) since even with 6.bit transfers) the local
bus is fast enough to accomodate :ust about an! disk drive. &owever) some
interface hardware uses faster timing on the ATA "I$8% bus when C@bit
transfers are used. In those cases !ou ma! notice a speedup. 1ote that ATA
"I$8% is a 6.bit bus. The C@bit transfers referred to here are strictl! the
transfers between C(* and interface chip.
• -xtended DM, +e!isters' <ithin a AT) $MA occurs for 6. Mb. <hen
enabled) $MA covers the whole / Hb of a C@bit processor.
Cachein!
• Cache +ead Option' Often referred as S+,M +ead wait state or Cache
+ead Hit Burst "S0AM' Static 0andom Access Memor!%. A specification of
the number of clocks needed to load four C@bit words into a C(* internal
cache. T!picall! specified as clocks per word. @666 indicates D clocks to
load the four words and is the theoretical minimum for current high end C(*s
"/B.$5) /B.S5) /B.$5@) /B.$5/) (entium%. Conceptuall!) the mnnn
notation is narrowl! limited to C(*s supporting burst mode and with caches
organi=ed as / word 4lines4. &owever it would not be a surprise to see it
e3tended to other C(* architectures. It takes simple integer values) such as @
666) C666 or C@@@. This determines the number of wait states for the
cache 0AM in normal and burst transfers "the latter for /B. onl!%. The lower
!ou computer can support) the better. /666 is usuall! recommended.
• Cache .rite Option' Same thing as memor! wait states) but according to
cache ram.
• 3ast Cache +ead8.rite' 8nable if !ou have two banks of cache) ./; or
@D.;.
• Cache .ait State5 Aike conventional memor!) the lower wait states for !our
cache) the better. 7 will give the optimal performance) but 6 wait state ma! be
re>uired for bus speed higher than CC M&=.
• Ta! +am Includes Dirty' 8nabling will cause an increase in performance)
because the cache is not replaced during c!cles) simpl! written over. It will
usuall! cut the ma3imum cachable range in half) as one bit is taken off the
address tag in order to be used as a dirt! tag bit. So) if !ou have a lot of
memor!) !ou might be better off without dirt! tag bit.
• ;on2Cacheable Bloc2@ Si0e' $isabled. The 1onCacheable region is
intended for a memor!mapped I+O device that isn,t supposed to be cached.
#or e3ample) some video cards can present all video memor! at 6D Mb 6.
Mb so software doesn,t have to bankswitch. If the noncacheable region
covers actual 0AM memor! !ou are using) e3pect a significant performance
decrease for accesses to that area. If the noncacheable region covers onl! non
e3istent memor! addresses) don,t worr! about it. If !ou don,t want to cache
some memor! !ou can e3clude @ regions of memor!. There are good reasons
not to cache some memor! areas. #or e3ample) if the memor! area
corresponds to some kind of buffer memor! on a card so that the card ma!
alter the contents of this buffer without warning the cache to invalidate the
corresponding cache lines. Some BIOSes take more options than enabled
+disabled) namel! 1onlocal +1oncache +$isabled "9AB onl!O%.
• ;on2Cacheable Bloc2@ Base' 7;B. 8nter the base address of the area !ou
don,t want to cache. It must be a multiple of the 1onCacheable Block6 Si=e
selected.
• ;on2Cacheable Bloc2# Si0e' $isabled.
• ;on2Cacheable Bloc2# Base' 7;B.
• Cacheable +,M ,ddress +an!e' *suall! chipsets allow memor! to be
cached :ust up to 6. or C@ MB. This is to limit the number of bits of a memor!
address that need to be saved in the cache together with its contents. If !ou
onl! have /MB of 0AM) select /MB here. The lower the better) don,t enter
6.MB if !ou onl! have BMB installedP
• 7ideo BIOS ,rea Cacheable' To cache or not to cache video BIOS) a good
>uestion. ?ou should tr! what is better video access is faster with ,enabled,)
but cache has its si=e. <ith an 4accelerated4 video card it ma! be necessar! to
make the video 0AM region noncacheable so the C(* can see an! changes
the drawing engine makes in the frame buffer.
Memory
• Memory +ead .ait State' "often referred as D+,M .ait States% 8ach wait
states adds C7 ns of 0AM access speed. The C(* is often much faster than the
memor! access time. On a /B.) 6 or more wait states are often re>uired for
0AM with B7ns or higher access time. And) depending on the processor and
motherboard) also for lower than B7ns access time. The less wait states) the
better. Consult !our manual. If wait states are too low) a parit! error will occur.
#or CB. or /B. nonburst memor! access c!cle takes @ clock ticks. A rou!h
indication of 0AM speed necessar! for 7 wait states is @777+ClockUM&=V 67
UnsV. #or a CCMh= processor) this would give D7ns of access time re>uired) so
if !ou do not have D7ns memories) wait state is re>uired. The number of wait
states necessar! is approximately "0amSpeedUnsV J67% T ClockUM&=V +6777
@. #or I7ns 0AM and a CCMh= processor "ver! standard configuration%) this
would give roughl! 6 wait state. But this reall! is dependent on chipset)
motherboard and cache design) C(* t!pe and whether we talk about reads or
writes. Take these formulas with a large grain of salt. ?ou can find out the
access time of !our 0AM chips b! looking at their product numbers. Mostl! at
the end there is a I7) B7) F7) or even .7. If 67 stands there) it means 677 ns.
Some 0AM chips also have an e3plicitl! written speed in ns. The 0AM !ou
bu! these da!s mostl! have I7ns or .7ns.
• Memory .rite .ait State' Same as above e3cept for writting "self evident%.
In some BIOSes) these two options are combined as D+,M .ait State. In that
case) the number of read and write wait states is necessaril! e>ual.
• D+,M C,S Timin! Delay' The default is no CAS dela!. $0AM is
organi=ed b! rows and columns and accessed through strobes. Then a memor!
read+write is performed) the C(* activates 0AS "0ow Access Strobe% to find
the row containing the re>uired data. Afterwards) a CAS "Column Access
Strobe% specifies the column. 0AS and CAS are used to identif! a location in a
$0AM chip. 0AS access is the speed of the chip while CAS is half the speed.
<hen !ou have slow $0AM) !ou should use 6 state dela!.
• D+,M +efresh Method' Selects the timing pulse width of 0AS from 0AS
Onl! or CAS before 0AS "which one is betterO%.
• +,S Prechar!e Time' Technicall!) this is the duration of the time interval
during which the 0ow Address Strobe signal to a $0AM is held low during
normal 0ead and <rite C!cles. This is the minimum interval between
completing one read or write and starting another from the same "nonpage
mode% $0AM. Techni>ues such as memor! interleaving) or use of (age Mode
$0AM are often used to avoid this dela!. Some chipsets re>uire this parameter
in order to set up the memor! configuration properl!. The 0AS (recharge
value is t!picall! about the same as the 0AM Access "data read+write% time.
The latter can be used as an estimate if the actual value is unavailable. At least
one BIOS describes the precharge and access times as 0AS AO< and 0AS
&IH& Times. #or a CC M&= C(*) / is a good choice) while lower values
should be selected for slower speeds.
• +,S ,cti%e Time' The amount of time a 0AS can be kept open for multiple
accesses. &igh figures will improve performance.
• +,S to C,S Delay Time' Amount of time a CAS is performed after a 0AS.
The lower the better) but some $0AM will not support low figures.
• C,S Before +,S' 0educes refresh c!cles and power consumption.
• C,S .idth in +ead Cycle' The number of wait states for the C(* to read
$0AM. The lower the better.
• Interlea%e Mode' Controls how the C(* access different $0AM banks.
• 3ast Pa!e Mode D+,M' This speeds up memor! access for $0AM capable
of handling it "most do%. <hen access occurs in the same memor! area) 0AS
and CAS are not necessar!.
Plu! and Play8PCI
A s!stem intended to make fitting of e3pansion cards easier "!es) reall!P%. In this
conte3t) ISA cards are known as Aegac! Cards) and are switched as normal to
make them fit in. &ave as few of these as possible) as accesses to them are slow.
<ith Concurrent (CI) The T II "or /C7&5+95% chipset,s Multi Transaction Timer
allows multiple transfers in one (CI re>uest) b! reducing rearbitration when
several (CI processes can take place at once. (assive 0elease allows the (CI bus
to continue working when it,s receiving data from ISA devices) which would
normall! hog the bus. $ela!ed Transaction allows (CI bus masters to work b!
dela!ing transmissions to ISA cards. <rite merging combines b!te) word and
$word c!cles into a single write to memor!.
The idea is that plug and pla! cards get interrogated b! the s!stem the! are
plugged into) and their re>uirements checked against those of the cards alread! in
there. The BIOS will feed the data as re>uired to the Operating S!stem) t!picall!
<indows ,FD. &ere !ou will be able to assign I0Ss) etc to (CI slots and map (CI
I1TRs to them. Although <indows ,FD or a (n( BIOS can do a lot b! themselves)
!ou reall! need the lot) e.g.a (lug and (la! BIOS) with compatible devices and an
Operating S!stem for the best performance. Be aware that not all (CI "@.7% cards
are (n(. (C "(CMCIA% cards are also 4(lug and (la!4) but are not considered
here.
(n( itself was originall! devised b! Compa>) Intel and (hoeni3. ?our chipset
settings ma! allow !ou to choose of two methods of operation'
• All (n( devices are configured and activated.
• All (n( ISA cards are isolated and checked) but onl! those needed to boot the
machine are activated. The ISA s!stem cannot produce specific information
about a card) so the BIOS has to isolate each one and give it a temporar!
handle so its re>uirements can be read. 0esources can be allocated once all
cards have been dealt with "recommended for <indows ,FD) as it can use the
0egistr! and its own procedures to use the same information ever! time !ou
boot%.
8SC$ "83tended S!stem Configuration $ata%) a s!stem which is part of (n(
"actuall! a superset of 8ISA%) that can store data on (n( or non(n( 8ISA) ISA or
(CI cards to perform the same function as the <indows ,FD 0egistr! above) that
is) provide consistenc! between sessions. It occupies part of *pper Memor!
"87778$##%) which is not available to memor! managers. The default length is
/;) and problems have been reported with 8MS buffer addressing when this area
has been used.
PCI Slot Confi!uration
Although an unlimited number of (CI slots is allowed) in practice / is the
ma3imum) due to loading considerations.(CI cards and slots use an internal
interrupt s!stem) with each slot being able to activate up to /) labelled either
I1TRAI1TR$) or I1TR6I1TR/. These are nothing to do with I0Ss) although
the! can be mapped to them if the card concerned needs it. T!picall! I0Ss F and
67 are reserved for this) but an! available ones can be used.
• 9atency Timer /PCI Clocs1. Controls the length of time an agent on the (CI
bus can hold the bus when another has re>uested it) so ever!thing gets its fair
share.Since the (CI bus runs faster than the ISA bus) the (CI bus must be
slowed during interactions with it. This setting allows !ou to define how long
the (CI bus will dela! for a transaction between the given (CI slot and the ISA
bus. This number is dependent on the (CI master device in use and varies from
7 to @DD. AMI defaults to ..) but /7 clocks is a good place to start at CCM&=
"(hoeni3%. The shorter the value) the more rapid access to the bus a device
gets) with better response times) but the lower becomes the effective
bandwidth and hence data throughput. 1ormall!) leave this alone) but !ou
could set it to a lower value if !ou have latenc! sensitive cards "e.g. audio
cards and+or network cards with small buffers%. Increase slightl! if I+O
sensitive applications are being run.
• *sing I0S. Affected b! the Trigger method. <ith (CI) !ou assign I0Ss)
etc to a slot) rather than ad:usting the card) but onl! if the card needs an
I0S. There are two methods of I0S usage) Aevel or 8dge triggered "see
83pansion Cards%. Most (CI cards use the former) and ISA the latter.
• (CI Slot 3 I1T3. Assigns (CI I1TRs to slots 6+@+C "or whatever%. See
Slot 5 using I1TR) overleaf.
• 8dge+Aevel Select. (rograms (CI I0Ss to singleedge or logic
level. Aevel or 8dge sensitivit! is programmed per controller.
Select 8dge for (CI I$8.
• (CI $evice) Slot 6+@+C. 8nables I+O and memor! c!cle decoding.
• 8nable. As slave
• 8n Master. 8nables (CI device as bus master.
• *se $efault Aatenc! Timer 9alue. If !es) !ou don,t need Aatenc!
Timer "above%.
• Slot ) 6sin! I;TI. Selects an I1TR channel for a (CI Slot) and there are four
"A) B) C W $% for each one) that is) each (CI bus slot supports interrupts A) B)
C and $. RA is allocated automaticall!) and !ou would onl! use RB) RC) etc if
the card needs to use more than one "(CI% interrupt service. #or e3ample)
select R$ if !our card needs four. *sing Auto is simplest. Most graphics cards
don,t need this.
• )th ,%ailable I+G. Selects "or maps% an I0S for one of the available I1TRs
above. There are ten selections "C) /) D) .) I) F) 67) 66) 6@) 6/) 6D%. 6st available
I0S means the BIOS will assign this I0S to the first (CI slots "order is 6) @) C)
/%. 1A means the I0S has been assigned to the ISA bus and is therefore not
available to a (CI slot.
• @st2'th ,%ailable I+G. As above.
• PCI I+G ,cti%ated by. The method b! which the (CI bus recognises an I0S
re>uest- Aevel or 8dge "see 83pansion Cards%. *se the default unless advised
otherwise b! !our manufacturer or if !ou have a (CI device which onl!
recogni=es one of them.
• Confi!uration Mode. Sets the method b! which information about legac!
cards is conve!ed to the s!stem.
• *se IC*the BIOS depends on information provided b! (lug and (la!
software "e.g. Configuration Manager or ISA Configuration *tilit!%.
Onl! set this if !ou have the utilities concerned.
• *se Setup *tilit!. The BIOS depends on information provided b! !ou in
the following settings. $on,t use the above utilities.
• IS, Shared Memory Si0e. Sets a block of s!stem memor! which will not be
shadowed. Should be disabled) unless !ou have an ISA card that uses the upper
memor! area. If !ou use this setting !ou will also get the following'
• ISA Shared Memor! Base Address. If !ou choose ./;) !ou can onl!
choose $777 or below.
• I+G (2I+G @H. *sed to indicate what I0Ss are in use b! ISA Aegac! cards. If
not used) set to Available. Otherwise) set *sed b! ISA Card) which means that
nothing else can use it.
• PCI ID- Prefetch Buffers. $isables a set of prefetch buffers in the (CI I$8
controller. ?ou ma! need to do this with an operating s!stem "like 1T% that
doesn,t use the BIOS to access the hard disk and doesn,t disable interrupts
when completing a programmed I+O operation. $isabling also prevents errors
with fault! (CII$8 interface chips that can corrupt data on the hard disk "with
true C@bit operating s!stems%. Check if !ou,ve got a (CTech 0X6777 or a
CM$ (CIO ./7) but disabling is done automaticall! with later boards.
• PCI ID- #nd Channel. $isable this if !ou,re not using the @nd channel on the
(CI I$8 card) or !ou will lose I0S 6D on the ISA slots.
• PCI ID- I+G Map to. Allows !ou to configure !our s!stem to the t!pe of
I$8 disk controller- an ISA device is assumed. The more apparent difference is
the t!pe of slot being used. &owever) if !ou have a (CI I$8 controller) this
setting allows !ou to specif! which slot has the controller and which (CI I1TR
"A) B)C or $% is associated with the connected hard drives. 1ote that this refers
to the hard disk rather than individual partitions. Since each I$8 controller
supports two drives) !ou can select the I1TR for each. 1ote also that the
primar! has a lower interrupt than the secondar!) as described in Slot 3 *sing
I1TR.
• (CIAuto. If the I$8 is detected b! the BIOS on one of the (CI slots)
then the apropriate I1TR channel will be assigned to I0S 6/.
• (CISlot 5. If the I$8 is not detected) !oun can manuall! select the slot.
• (rimar! I$8 I1TR) Secondar! I$8 I1TR. Assigns @ I1T channels for
primar! and secondar! channels) if supported.
• ISA. Assigns no I0Ss to (CI slots. *se for (CI I$8 cards that connect
I0Ss 6/ and 6D directl! from an ISA slot using a table from a legac!
paddleboard.
• PCI Bus Parin!. Sort of bus mastering- a device parking on the (CI Bus has
full control of the bus for a short time. Improves performance when that device
is being used) but e3cludes others. Tr! with 1ICs and &ard $isk Controllers.
• ID- Buffer for DOS J .in. #or I$8 read ahead and posted write buffers) so
!ou can increase throughput to and from I$8 devices b! buffering reads and
writes. Slower I$8 devices could end up slower) though.
• ID- Master /Sla%e1 PIO Mode. Changes I$8 data transfer speed- Mode 7/)
or Auto. (IO means (rogrammed Input+Output. 0ather than have the BIOS
issue commands to effect transfers to or from the disk drive) (IO allows the
BIOS to tell the controller what it wants) and then lets the controller and the
C(* perform the complete task b! themselves. Modes 6/ are available.
• HC9? PCIC9?. &ost CA; vs (CI CA; divider- A*TO) 66) 66.D.
• PCI2IS, BC9? Di%ider. (CI Bus CA; vs ISA Bus CA; divider- A*TO)
(CICA;6+C) (CICA;6+@) (CICA;6+/.
• CP6 to PCI Byte Mer!e. See B!te Merging for e3planation "below%.
• PCI .rite2byte2Mer!e. <hen enabled) this allows data sent from the C(* to
the (CI bus to be held in a buffer. The chipset will then write the data in the
buffer to the (CI bus when appropriate.
• CP62to2PCI +ead Buffer. <hen enabled) up to four $words can be read
from the (CI bus without interrupting the C(*. <hen disabled) a write buffer
is not used and the C(* read c!cle will not be completed until the (CI bus
signals that it is read! to receive the data. The former is best for performance.
• PCI2to2CP6 .rite Buffer. See above.
• CP62to2PCI +ead29ine. <hen On) more time will be allocated for data setup
with faster C(*s. This ma! onl! be re>uired if !ou add an Intel Over$rive
processor to !our s!stem.
• CP62to2PCI +ead2Burst. <hen enabled) the (CI bus will interpret C(* read
c!cles as the (CI burst protocol) meaning that backtoback se>uential C(*
memor! read c!cles addressed to the (CI will be translated into fast (CI burst
memor! c!cles. (erformance is improved) but some nonstandard (CI adapters
"e.g. 9HA% ma! have problems.
• PCI to D+,M Buffer. Improves (CI to $0AM performance b! allowing
data to be stored if a destination is bus!.Buffers are needed because the (CI
bus is divorced from the C(*.
• 9atency for CP6 to PCI write. $ela! time before C(* writes data to the (CI
bus.
• PCI Cycle Cache Hit .S. Similar to above. <ith the latter) the C(* has less
to do) so performance is better.
• 1ormalCache refresh during normal (CI c!cles.
• #astCache refresh without (CI c!cle for CAS.
• 6se Default 9atency Timer 7alue. <hether or not the default value for the
Aatenc! Timer will be loaded) or the succeeding Aatenc! Timer 9alue will be
used. If ?es is selected "default%) no further programming is needed in the
Aatenc! Timer 9alue option "below%.
• 9atency Timer 7alue. The ma3imum number of (CI bus clocks that the
master ma! burst. A longer latenc! time gives the C(* more of a chance to
control the bus. See also Aatenc! Timer "(CI Clocks%.
• 9atency from ,DSI status. This allows !ou to configure how long the C(*
waits for the Address $ata Status "A$S%. It determines the C(* to (CI (ost
write speed. <hen set to CT) this is DT for each double word. <ith @T
"default%) it is /T per double word. #or a Sword (CI memor! write) the rate is
IT "@T% or BT "CT%. The default should be O;) but if !ou add a faster C(* to
!our s!stem) !ou ma! find it necessar! to increase it. The choices are'
• CTThree C(* clocks
• @TTwo C(* clocks "$efault%
• PCI Master 9atency. If !our (CI Master cards control the bus for too long)
there is less time for the C(* to control it. A longer latenc! time gives the
C(* more of a chance. $on,t use =ero.
• Max burstable ran!e. The ma3imum bursting length for each #0AM8R
asserting. #0AM8R is an electrical signal. $unno what it does) !et.
• CP6 to PCI burst memory write. If enabled) backtoback se>uential C(*
memor! write c!cles to (CI are translated to (CI burst memor! write c!cles.
Otherwise) each single write to (CI will have an associated #0AM8R
se>uence. 8nabled is best for performance) but some nonstandard (CI cards
"e.g. 9HA% ma! have problems.
• 3ast Bac To Bac. (ossibl! as above) but working on itP
• CP6 to PCI post memory write. 8nabling allows up to / $words of data to
be posted to (CI. Otherwise) not onl! is buffering disabled) completion of
C(* writes is limited "e.g. C(* write does not complete until the (CI
transaction completes%. 8nabled is best for performance.
• CP6 to PCI .rite Buffer. As above. Buffers are needed because the (CI bus
is divorced from the C(*- the! improve overall s!stem performance b!
allowing the processor "or bus master% to do what it needs without writing data
to its final destination- the data is temporaril! stored in fast buffers.
• PCI to IS, .rite Buffer. <hen enabled) the s!stem will temporaril! write
data to a buffer so the C(* is not interrupted. <hen disabled) the memor!
write c!cle for the (CI bus will be direct to the slower ISA bus. The former is
best for performance.
• DM, 9ine Buffer. Allows $MA data to be stored in a buffer so (CI bus
operations are not interrupted. $isabled means that the line buffer for $MA is
in single transaction mode. 8nabled allows it to operate in an Bb!te
transaction mode for greater efficienc!.
• IS, Master 9ine Buffer. ISA master buffers are designed to isolate the slower
ISA I+O operations from the (CI bus for better performance. $isabled means
the buffer for ISA master transaction is in single mode. 8nabled means it is in
Bb!te mode) increasing the ISA master,s performance.
• CP68PCI Post .rite Delay. $ela! time before the C(* writes data into the
(CI bus.
• Post .rite C,S ,cti%e. (ulse width of CASR when the (CI master writes to
$0AM.
• PCI master accesses shadow +,M. 8nables the shadowing of a 0OM on a
(CI master for better performance.
• -nable Master. 8nables the selected device as a (CI bus master and checks
whether the card is so capable.
• ,T bus cloc freDuency. AT bus speed in a (CI s!stem. Choose whatever
divisor gives !ou a speed of .B.CC M&=) depending on the speed of the (CI
bus.
• IS, Bus Cloc 3reDuency. As above.
• Base I8O ,ddress. The base of the I+O address range from which the (CI
device resource re>uests are satisfied.
• Base Memory ,ddress. The base of the C@bit memor! address range from
which the (CI device resource re>uests are satisfied.
• Parity. Allows parit! checking of (CI devices.
• IS, 9inear 3rame Buffer. Set to the appropriate si=e if !ou use an ISA card
that features a linear frame buffer "e.g. a second video card for ACA$%. The
address will be set automaticall!.
• IS, 7F, 3rame Buffer Si0e. This is to help !ou use a 9HA frame buffer and
6. Mb of 0AM at the same time- the s!stem will allow access to the graphics
card through a hole in its own memor! map- in other words) accesses made to
addresses within this hole will be directed to the ISA bus instead of main
memor!. Should be set to $isabled) unless !ou are using an ISA card with
more than ./; of memor! that needs to be accessed b! the C(*) and !ou are
not using the (lug and (la! utilities. If !ou have less than B Mb memor!) or
use MS$OS) this will be ignored.
• +esidence of 7F, Card. <hether on (CI or 9A Bus.
• IS, 93B Si0e. A#BKAinear #rame Buffer. See above.
• Memory Map HoleK Memory Map Hole Start8-nd ,ddress. See ISA 9HA
#rame Buffer Si=e. <here the hole starts depends on ISA A#B Si=e.
Sometimes this is informative onl!. If !ou can change it) base address should
be 6.Mb) less buffer si=e.
• Memory Hole Si0e. Options include 6 Mb) @ Mb) / Mb) B Mb) $isabled.
These are the amounts below 6 Mb assigned to the AT Bus) and reserved for
ISA cards.
• Memory Hole Start ,ddress. To improve performance) certain parts of
memor! are reserved for ISA cards) which must be mapped into the memor!
space below 6. MB for $MA reasons. The selections are from 66D with each
number in Mb. This is irrelevant if the memor! hole is disabled "see above%.
• Memory Hole at @H2@'M. See above.
• 9ocal Memory @H2@'M. To increase performance) !ou can map slower device
memor! "e.g. on the ISA bus% into much faster local bus memor!. Aocal
memor! is set aside and the start point transferred from the device memor! to
local memor!. The default is enabled.
• @H2@'M Memory 9ocation. The area in the memor! map allocated for ISA
option 0OMs. Choices are Aocal "default% or 1onlocal.
• Byte Mer!in!. This e3ists where writes to se>uential memor! addresses are
merged into one (CItomemor! operation) which increases performance for
older applications that write to video memor! in b!tes rather than wordsnot
supported on all (CI video cards. 8nable unless !ou get bad graphics. See also
ne3t for a variation.
• Byte Mer!e Support. B or 6.bit data en route from the C(* to the (CI bus
is held in a buffer where it is accumulated) or merged) into C@bit data) giving
faster performance. In this case) enabling means that C(*(CI writes are
buffered "Award%.
• Multimedia Mode. 8nables or disables palette snooping for multimedia cards.
• 7ideo Palette Snoop. Controls how a (CI graphics card can 4snoop4 write
c!cles to an ISA video card,s colour palette registers. Snooping essentiall!
means interfereing with a device.Onl! set to $isabled if'
• An ISA card connects to a (CI graphics card through a 98SA connector
• The ISA card connects to a colour monitor) and
• The ISA card uses the 0AM$AC on the (CI card) and
• (alette Snooping "0AM$AC shadowing% not operative on (CI card.
• PCI87F, Palette Snoop. Alters the 9HA palette setting while graphic signals
pass through the feature connector of (CI 9HA card and are processed b!
M(8H card. 8nable if !ou have M(8H connections through the 9HA feature
connector- this means !ou can ad:ust (CI+9HA palettes. 9HA snooping is
used b! multimedia video devices "e.g. video capture boards% to look ahead at
the video controller "9HA device% to see what color palette is currentl! in use.
It is onl! in e3ceptional circumstances that !ou might ever need to enable this)
so disable for ordinar! s!stems. "Award BIOS%.
• Snoop 3ilter. Saves the need for multiple en>uiries to the same line if it was
in>uired previousl!. <hen enabled) cache snoop filters ensure data integrit!
"cache coherenc!% while reducing the snoop fre>uenc! to a minimum.
• -&$$$ (#? ,ccessible. The ./; 8 area of upper memor! is used for BIOS
purposes on (S+@s) C@ bit operating s!stems and (lug and (la!. This setting
allows the second C@; page to be used for other purposes when not needed) in
the same wa! that the first C@; page of the # range is useable after boot up has
finished.
• PH Piped ,ddress. $efault is $isabled
• PCI ,rbiter Mode. $evices gain access to the (CI bus through arbitration.
There are two modes) 6 "the default% and @. The idea is to minimi=e the time it
takes to gain control of the bus and move data. Henerall!) Mode 6 should be
sufficient) but tr! mode @ if !ou get problems.
• Stop CP6 .hen 3lush ,ssert. See below.
• Stop CP6 when PCI 3lush. <hen enabled) the C(* will be stopped when
the (CI bus is being flushed of data. $isabling "default% allows the C(* to
continue processing) giving greater efficienc!.
• Stop CP6 at PCI Master. <hen enabled) the C(* will be stopped when the
(CI bus master is operating on the bus. $isabling "default% allows the C(* to
carr! on) giving greater efficienc!.
• I8O Cycle +eco%ery. <hen enabled) the (CI will be allowed a recover! period
for backtoback I+O) which slows backtoback data transfers- it,s like adding
wait states) so disable "default% for best performance.
• I8O +eco%ery Period. Sets the length of time of the recover! c!cle used
above. The range is from 76.ID microseconds in 7.@D microsecond intervals.
• ,ction .hen .LBuffer 3ull. Sets the behaviour of the s!stem when the write
buffer is full. B! default the s!stem will immediatel! retr!) rather than wait for
it to be emptied.
• 3ast Bac2to2Bac. <hen enabled) the (CI bus will interpret C(* read c!cles
as the (CI burst protocol) meaning that backtoback se>uential C(* memor!
read c!cles addressed to the (CI will be translated into the fast (CI burst
memor! c!cles. $efault is enabled.
• CP6 Pipelined 3unction. This allows the s!stem controller to signal the C(*
for a new memor! address) even before all data transfers for the current c!cle
are complete) resulting in increased throughput. The default is $isabled) that
is) pipelining off.
• Primary 3rame Buffer. <hen enabled) this allows the s!stem to use
unreserved memor! as a primar! frame buffer. *nlike the 9HA frame buffer)
this would reduce overall available 0AM for applications.
• M@**H+D"< to CP6+D"<. <hether the (CI 0ead! signal is to be
s!nchroni=ed b! the C(* clock,s read! signal or b!passed "default%.
• 7-S, Master Cycle ,DS<. Allows !ou to increase the length of time the
98SA Master has to decode bus commands. Choices are 1ormal "default% and
Aong.
• 9D-7< Chec Point Delay. This allows !ou to select how much time is
allocated for checking bus c!cle comands. These commands must be decoded
to determine whether a local bus device access signal "A$89G% is being sent)
or an ISA device is being addressed. Increasing the dela! increases stabilit!)
especiall! the 98SA subs!stem while ver! slightl! degrading the
performance of the ISA subs!stem. Settings are in terms of the feedback clock
rate "#BCA;@% used in the cache+memor! control interface.
1 FBCLK2=One clock
2 FBCLK2=Two clocks (Default)
3 FBCLK2=Three clocks
• CP6 Dynamic23ast2Cycle. Hives !ou faster access to the ISA bus. <hen the
C(* issues a bus c!cle) the (CI bus e3amines the command to determine if a
(CI agent claims it. If not) then an ISA bus c!cle is initiated. The $!namic
#astAccess then allows for faster access to the ISA bus b! decreasing the
latenc! "or dela!% between the original C(* command and the beginning of
the ISA c!cle.
• CP6 Memory sample point. This allows !ou to select the c!cle check point)
which is where memor! decoding and cache hit+miss checking takes place.
8ach selection indicates that the check takes place at the end of a C(* c!cle)
with one wait state indicating more time for checking to take place than =ero
wait states. A longer check time allows for greater stabilit! at the e3pense of
some speed.
• 9D-7I Chec point. The 98SA local device "A$89R% check point is where
the 9Abus device decodes the bus commands and error checks) within the bus
c!cle itself.
0 Bus cycle o!nt T1 (Default)
1 Dur!n" the f!rst T2
2 Dur!n" secon# T2
3 Dur!n" th!r# T2
• 9ocal memory chec point. Allows !ou to select between two techni>ues for
decoding and error checking local bus writes to $0AM during a memor!
c!cle.
• SlowK83tra wait state- better checking "default%.
• #astK1o e3tra wait state used.
• 3+,M-< !eneration. <hen the (CI9A bus bridge is acting as a (CI Master
and receiving data from the C(*) a fast C(*to(CI buffer will be enabled if
this selection is also enabled. *sing the buffer allows the C(* to complete a
write even though the data has not been delivered to the (CI bus. This reduces
the number of C(* c!cles involved and speeds overall processing.
• 1ormal Buffering not emplo!ed "$efault%
• #ast Buffer used for C(*to(CI writes.
• PCI to CP6 .rite Pendin!. Sets the behaviour of the s!stem when the write
buffer is full. B! default) the s!stem will immediatel! retr!) but !ou can set it
to wait for the buffer to be emptied before retr!ing.
• Delay for SCSI8HDD /Secs1. The length of time in seconds the BIOS will
wait for the SCSI hard disk to be read! for operation. If the hard drive is not
read!) the (CI SCSI BIOS might not detect the hard drive correctl!. The range
is from 7.7 seconds.
• Master IOCH+D". 8nabled) allows the s!stem to monitor for a 98SA
master re>uest to generate an I+O channel read! "IOC&0$?% signal.
• 7F, Type. This data is used when the video bios is being shadowed. The
BIOS uses this information to determine which bus to use. Choices are
Standard "default%) (CI) ISA+98SA.
• PCI Mstr Timin! Mode. This s!stem supports two timing modes) 7 "default%
and 6.
• PCI ,rbit4 +otate Priority. T!picall!) the s!stem manages or arbitrates access
to the (CI bus on a firstcomefirstserved basis. <hen priorit! is rotated) once
a device gains control of the bus it is assigned the lowest priorit! and ever!
other device is moved up one in the priorit! >ueue.
• I8O Cycle Post2.rite. <hen 8nabled "default%) data being written during an
I+O c!cle will be buffered for faster performance.
• PCI Post2.rite 3ast. As in the above I+O C!cle (ost<rite) enabling this will
allow the s!stem to use a fast memor! buffer for writes to the (CI bus.
• CP6 Mstr Post2.+ Buffer. <hen the C(* operates as a bus master for
either memor! access or I+O) this item controls its use of a high speed posted
write buffer. Choices are 1A) 6) @ and / "default%.
• CP6 Mstr Post2.+ Burst Mode. <hen the C(* operates as a bus master for
either memor! access or I+O) this item controls its abilit! to use a high speed
burst mode for posted writes to a buffer.
• CP6 Mstr 3ast Interface. This enables+disables what is known as a fast back
toback interface when the C(* operates as a bus master. <hen enabled)
consecutive reads+writes are interpreted as the C(* highperformance burst
mode.
• PCI Mstr Post2.+ Buffer. <hen a (CI device operates as a bus master for
either memor! access or I+O) this item controls its use of a high speed posted
write buffer. Choices are 1A) 6) @ and / "default%.
• PCI Mstr Burst Mode. <hen a (CI device operates as a bus master for either
memor! access or I+O) this item controls its abilit! to use a high speed burst
mode for posted writes to a buffer.
• PCI Mstr 3ast Interface. This enables+disables what is known as a fast back
toback interface when a (CI device operates as a bus master. <hen enabled)
consecutive reads+writes are interpreted as the (CI highperformance burst
mode.
• CP6 Mstr D-7S-9I Time2out. <hen the C(* initiates a master c!cle using
an address "target% which has not been mapped to (CI+98SA or ISA space) the
s!stem will monitor the $89S8A "device select% pin for a period of time to see
if an! device claims the c!cle. This item allows !ou to determine how long the
s!stem will wait before timingout. Choices are C (CICA;) / (CICA;) D
(CICA; and . (CICA; "default%.
• PCI Mstr D-7S-9I Time2out. <hen a (CI device initiates a master c!cle
using an address "target% which has not been mapped to (CI+98SA or ISA
space) the s!stem will monitor the $89S8A "device select% pin for a period of
time to see if an! device claims the c!cle. This item allows !ou to determine
how long the s!stem will wait before timingout. Choices are C (CICA;) /
(CICA; "default%) D (CICA; and . (CICA;.
• I+G 9ine. If !ou have installed a device re>uiring an I0S service into the
given (CI slot) use this item to inform the (CI bus which I0S it should
initiate. Choices range from I0S C through I0S 6D.
• 3ast Bac2to2Bac Cycle. <hen enabled) the (CI bus will interpret C(* read
or write c!cles as (CI burst protocol) meaning that backtoback se>uential
C(* memor! read+write c!cles addressed to the (CI will be translated into fast
(CI burst memor! c!cles.
• State Machines. The chipset uses four state machines to manage specific C(*
and+or (CI operations. 8ach can be thought of as a highl! optimi=ed process
center designed to handle specific operations. Henerall!) each operation
involves a master device and the bus it wishes to emplo!. The four state
machines are'
C$% &aster to C$% 'us (CC)
C$% &aster to $C( 'us (C$)
$C( &aster to $C( 'us ($$)
$C( &aster to C$% 'us ($C)
• 8ach have the following settings'
• Address 7 <S. This refers to the length of time the s!stem will dela!
while the transaction address is decoded. 8nabledKno dela!.
• $ata <rite 7 <S. The length of time the s!stem will dela! while data is
being written to the target address. <hen 8nabled) there will be no dela!.
• $ata 0ead 7 <S. The length of time the s!stem will dela! while data is
being read from the target address. <hen 8nabled) there will be no dela!.
• On Board PCI8SCSI BIOS. ?ou would enable this if !our s!stem
motherboard had a builtin SCSI controller attached to the (CI bus) and !ou
wanted to boot from it.
• PCI I8O Start ,ddress. I+O devices make themselves accessible b! occup!ing
an address space. This allows !ou to make additional room for older ISA
devices b! defining the I+O start address for the (CI devices.
• Memory Start ,ddress. This is for devices with their own memor! which use
part of the C(*,s memor! address space) allowing !ou to determine the
starting point in memor! where (CI device memor! will be mapped.
• 7F, @#& +an!e ,ttribute. <hen enabled) this allows the chipset to appl!
features like C(*TO(CI B!te Merge) C(*TO(CI (refetch to be applied to
9HA memor! range A7777&B####&.
• 8nabledK9HA receives C(*TO(CI functions.
• $isabledK0etain standard 9HA interface.
• CP62To2PCI .rite Postin!. The Orion chipset maintains its own internal
read and write buffers which are used to help compensate for the speed
differences between the C(* and the (CI bus. <hen this is 8nabled) writes
from the C(* to the (CI bus will be buffered. <hen $isabled "default%) the
writes will not be buffered and the C(* will be forced to wait until the write is
completed.
• CP6 +ead Multiple Prefetch. A prefetch occurs during a process "e.g.
reading from the (CI or memor!% when the chipset peeks at the ne3t
instruction and actuall! begins the ne3t read. The Orion chipset has four read
lines. A multiple prefetch means the chipset can initiate more than one prefetch
during a process. $efault is $isabled.
• CP6 9ine +ead Multiple. A line read means that the C(* is reading a full
cache line. <hen a cache line is full it holds C@ b!tes "eight $<O0$S% of
data. Because the line is full) the s!stem knows e3actl! how much data it will
be reading and doesn,t need to wait for an endofdata signal) freeing it to do
other things. <hen this is enabled) the s!stem is allowed to read more than one
full cache line at a time. The default is disabled.
• CP6 9ine +ead Prefetch. See above. <hen this is enabled) the s!stem is
allowed to prefetch the ne3t read instruction and initiate the ne3t process.
• CP6 9ine +ead. This 8nables or $isables "default% full C(* line reads.
• CP6 Burst .rite ,ssembly. The "Orion% chipset maintains four posted write
buffers. <hen this is enabled) the chipset can assemble long (CI bursts from
the data held in them. $efault is $isabled.
• 7F, Performance Mode. If enabled) the 9HA memor! range of A 7777B
7777 will use a special set of performance features. This has little or no effect
using video modes be!ond the standard 9HA most commonl! used for
<indows) OS+@) *1I5) etc) but this memor! range is heavil! used b! games
such as $OOM.
• Snoop ,head. This is onl! applicable if the cache is enabled. <hen enabled)
(CI bus masters can monitor the 9HA palette registers for direct writes and
translate them into (CI burst protocol for greater speed) to enhance the
performance of multimedia video.
• DM, 9ine Buffer Mode. This allows $MA data to be stored in a buffer so as
not to interrupt the (CI bus. <hen Standard is selected) the line buffer is in
single transaction mode. 8nhanced allows it to operate in Bb!te transaction
mode.
• Master ,rbitration Protocol. This is the method b! which the (CI bus
determines which bus master device gains access to it.
• PCI Cloc 3reDuency. Allows !ou to set the clock rate for the (CI bus) which
can operate between 7CC Mh=. C(*CA;+C means the (CI bus was operating
at 66 Mh= "CC+C K 66%.
C$%CLK)1*+ C$% see# ) 1*+ (Default)
C$%CLK)3 C$% see#)3
1, -h. 1, -h.
C$%CLK)2 C$% see#)2
• MaxE Burstable +an!e. Sets the si=e of the ma3imum range of contiguous
memor! which can be addressed b! a burst from the (CI bus) a half or one ;.
• IS, Bus Cloc 3reDuency. Allows !ou to set the speed of the ISA bus in
fractions of the (CI bus speed) so if the (CI bus is operating at its theoretical
ma3imum) CC Mh=) (CICA;+C would !ield an ISA speed of 66 Mh=.
/*1+0 -h. (#efault)
$C(CLK), 1 2uarter see# of the $C( 'us
$C(CLK)3 One th!r# see# of the $C( 'us
• & Bit I8O +eco%ery Time. The recover! time is the length of time) measured
in C(* clocks) which the s!stem will dela! after the completion of an
input+output re>uest to the ISA bus) needed because the C(* is running faster
than the bus) and needs to be slowed down. Clock c!cles are added to a
minimum dela! "usuall! D% between (CIoriginated I+O c!cles to the ISA bus.
Choices are from 6 to I or B C(* clocks. 6 is the default.
• @' Bit I8O +eco%ery Time. As above) for 6. bit I+O. Choices are from 6 to /
C(* clocks. 6 is the default.
• I8O +eco%ery Time. A programmed dela! which allows the (CI bus to
e3change data with the slower ISA bus without data errors. Settings are in
fractions of the (CI BCA'
2 BCLK=Two BCLK3 (#efault)
, BCLK=Four BCLK3
4 BCLK=5!"ht BCLK3
12 BCLK=Twel6e BCLK3
• PCI Concurrency. 8nabled "default% means that more than one (CI device
can be active at a time "Award%. <ith Intel Chipsets) it allocates memor! bus
c!cles to a (CI controller while an ISA operation) such as bus mastered $MA)
is taking place) which normall! re>uires constant attention. This involves
turning on additional read and write buffering in the chipset. The (CI bus can
also obtain access c!cles for small data transfers without the dela!s caused b!
renegotiatiating bus access for each part of the transfer) so is meant to improve
performance and consistenc!.
• PCI Streamin!. $ata is t!picall! moved to and from memor! and between
devices in discrete chunks of limited si=es) because the C(* is involved. On
the (CI bus) data can be streamed) that is) much larger chunks can be moved
without the C(* being bothered. 8nable for best performance.
• PCI Burstin!. Consecutive writes from C(* will be regarded as a (CI Burst
c!cle. 8nable K best performance- some cards might not like it.
• PCI /ID-1 Burstin!. As above) but this one enables burst mode access to
video memor! over the (CI bus. The C(* provides the first address) and
consecutive data is transferred at one word per clock. The device must support
burst mode.
• Burst Copy2Bac Option. <hen enabled) if a cache miss occurs) the chipset
will initiate a second) burst cache line fill from main memor! to the cache) the
ob:ect being to maintain the status of the cache.
• Preempt PCI Master Option. <hen enabled) (CI bus operations can be
preempted b! certain s!stem operations) such as $0AM refresh) etc.
Otherwise) the! can take place concurrentl!.
• IBC D-7S-9I Decodin!. Allows !ou to set the t!pe of decoding used b! the
ISA Bridge Controller "IBC% to determine which device to select. The longer
the decoding c!cle) the better chance the IBC has to correctl! decode the
commands. Choices are #ast) Medium and Slow "default%.
• ?eyboard Controller Cloc. Sets the speed of the ke!board controller
"(CICA;I K (CI bus speed%.
/*17 -h. Default
$C(CLK()2 1)2 $C(CLK(
$C(CLK()3 1)3 $C(CLK(
$C(CLK(), 1), $C(CLK(
• CP6 Pipeline 3unction. This allows the s!stem controller to signal the C(*
for a new memor! address even before all data transfers for the current c!cle
are complete) resulting in increased throughput. 8nabled means that address
pipelining is active.
• PCI Dynamic Decodin!. <hen enabled) this setting allows the s!stem to
remember the (CI command which has :ust been re>uested. If subse>uent
commands fall within the same address space) the c!cle will be automaticall!
interpreted as a (CI command.
• Master +etry Timer. This sets how long the C(* master will attempt a (CI
c!cle before the c!cle is unmasked "terminated%. The choices are measured in
(CICA;s which the (CI timer. 9alues are 67 "default%) 6B) C/ or .. (CICA;s.
• PCI Pre2Snoop. (resnooping is a techni>ue b! which a (CI master can
continue to burst to the local memor! until a /; page boundar! is reached
rather than :ust a line boundar!.
• CP68PCI .rite Phase. $etermines the turnaround between the address and
data phases of the C(* master to (CI slave writes. Choices are 6 ACA;
"default% or 7 ACA;.
• PCI Preempt Timer. This item sets the length of time before one (CI master
preempts another when a service re>uest has been pending.
D!sa'le# 8o ree&t!on (#efault)*
270 LCLKs $ree&t after 270 LCLKs
132 LCLKs $ree&t after 132 LCLKs
74 LCLKs $ree&t after 74 LCLKs
37 LCLKs $ree&t after 37 LCLKs
20 LCLKs $ree&t after 20 LCLKs
12 LCLKs $ree&t after 12 LCLKs
+ LCLKs $ree&t after + LCLKs
• CP6 to PCI POST8B6+ST. $ata from the C(* to the (CI bus can be posted
"buffered b! the controller% and+or burst. This sets the methods.
• (OST+CO1.B*0ST. (osting and bursting supported "default%.
• 1O18+1O18. 1either supported.
• (OST+1O18. (osting but not bursting supported.
• PCI C9?. <hether the (CI clock is tightl! s!nchroni=ed with the C(* clock)
or is as!nchronous. If !our C(*) motherboard and (CI bus are running at
multiple speeds of each other) e.g. (entium 6@7) .7 M&= m+b and C7 M&= (CI
bus) choose s!nchronise.
• I+G @H +outin! Selection. MISAKMultiple3ed ISA for as!nchronousl!
interrupting the C(*. I0S 6D is usuall! used for Secondar! I$8 channels or
C$0OMs.
• CP6 cycle cache hit same point. <orking on this.
• PCI cycle cache hit sam point. As above.
• ,rbiter timer timeout /PCI C9?1 # x (#. <orking on this.
POST and -nterin! Setup
• A t!pical BIOS (OST se>uence
• AMI BIOS (OST errors
• Other AMI BIOS (OST codes
• BIOS error messages
<hen the s!stem is powered on) the BIOS will perform diagnostics and initiali=e
s!stem components) including the video s!stem. "This is selfevident when the
screen first flicks before the 9ideo Card header is displa!ed%. This is commonl!
referred as (OST "Power2On Self Test%. Afterwards) the computer will proceed
its final bootup stage b! calling the operating s!stem. Gust before that) the user
ma! interrupt to have access to S8T*(.
To allow the user to alter the CMOS settings) the BIOS provides a little program)
S-T6P. *suall!) setup can be entered b! pressing a special ke! combination
"D-9) -SC) CT+92-SCE or C+T92,9T2-SC% at boot time "Some BIOSes
allow !ou to enter setup at an! time b! pressing CT+92,9T2-SC%. The AMI
BIOS is mostl! entered b! pressing the D-9 ke! after resetting "CT0AAAT
$8A% or powering up the computer. ?ou can b!pass the e3tended CMOS settings
b! holding the BI;SC ke! down during bootup. This is reall! helpful) especiall!
if !ou bend the CMOS settings right out of shape and the computer won,t boot
properl! an!more. This is also a hand! tip for people who pla! with the older
AMI BIOSes with the 5CMOS setup. It allows changes directl! to the chip
registers with ver! little technical e3planation.
, Typical BIOS POST SeDuence
Most BIOS (OST se>uences occur along four stages "five if !ou have a (CI bus%'
6. $ispla! some basic information about the video card like its brand) video
BIOS version and video memor! available. Since the s!stem,s BIOS takes over
the (OST right after the video card BIOS) !ou will not have enough time to
read the displa!ed information.
@. $ispla! the BIOS version and cop!right notice in upper middle screen. ?ou
will see a large se>uence of numbers at the bottom of the screen. This
se>uence is the BIOS identification line.
C. $ispla! memor! count. ?ou will also hear tick sounds if !ou have enabled it
"see Memor! Test Tick Sound section%.
/. If !ou have a (CI bus) the s!stem will attempt an initialisation of the cards and
will displa! the card,s name.
D. Once the (OST have succeeded and the BIOS is read! to call the operating
s!stem "$OS) OS+@) 1T) <I1FD) etc.% !ou will see a basic table of the
s!stem,s configurations'
• Main Processor' The t!pe of C(* identified b! the BIOS. *suall! C3CB.$5)
C3/B.$5) (6@7) etc..
• ;umeric Processor' (resent if !ou have a #(* or 1one on the contrar!. If
!ou have a #(* and the BIOS does not recogni=e it) see section 1umeric
(rocessor Test in Advanced CMOS Setup.
• 3loppy Dri%e ,' The drive A t!pe. See section #lopp! drive A in Standard
CMOS Setup to alter this setting.
• 3loppy Dri%e B' Idem.
• Display Type' See section (rimar! displa! in Standard CMOS Setup.
• ,MI or ,ward BIOS Date' The revision date of !our BIOS. *seful to
mention when !ou have compatibilit! problems with adaptor cards "notabl!
fanc! ones%.
• Base Memory Si0e' The number of ;B of base memor!. *suall! ./7.
• -xt4 Memory Si0e' The number of ;B of e3tended memor!.
In the ma:orit! of cases) the summation of base memor! and e3tended memor!
does not eDual the total s!stem memor!. #or instance in a /7F. ;B "/MB%
s!stem) !ou will have ./7;B of base memor! and C7I@;B of e3tended memor!)
a total of CI6@;B. The missing CB/;B is reserved b! the BIOS) mainl! as
shadow memor! "see Advanced CMOS Setup%.
• Hard Dis C5 Type' The master &$$ number. See &ard disk C' t!pe section
in Standard CMOS Setup.
• Hard Dis D5 Type' The slave &$$ number. See &ard disk $' t!pe section in
Standard CMOS Setup.
• Serial Port/s1' The he3 numbers of !our COM ports. C#B and @#B for COM6
and COM@.
• Parallel Port/s1' The he3 number of !our AT( ports. CIB for A(T6.
• Cache memory information' 0ight under the table) BIOS usuall! displa!s the
si=e of cache memor!. Common si=es are ./;B) 6@B;B or @D.;B. See
83ternal Cache Memor! section in Advanced CMOS Setup.
• PCI cards information. If !our s!stem supports (CI cards) !ou will see a
table containing a list of !our (CI cards) as well as its (CI port number "7 to C
or A to $% and the manufacturer,s number.
,MI BIOS POST -rrors
$uring the POST routines) which are performed each time the s!stem is
powered on) errors ma! occur. ;on2fatal errors are those which) in most cases)
allow the s!stem to continue the boot up process. The error messages normall!
appear on the screen. 3atal errors are those which will not allow the s!stem to
continue the bootup procedure. If a fatal error occurs) !ou should consult with
!our s!stem manufacturer or dealer for possible repairs. These errors are usuall!
communicated through a series of audible beeps. The numbers on the fatal error
list correspond to the number of beeps for the corresponding error. All errors
listed) with the e3ception of RB) are fatal errors. All errors found b! the BIOS will
be forwarded to the I+O port B7h.
• @ beep' $0AM refresh failure. The memor! refresh circuitr! on the
motherboard is fault!.
• # beeps' (arit! Circuit failure. A parit! error was detected in the base memor!
"first ./k Block% of the s!stem.
• ( beeps' Base ./; 0AM failure. A memor! failure occurred within the first
./k of memor!.
• * beeps' S!stem Timer failure. Timer R6 on the s!stem board has failed to
function properl!.
• H beeps' (rocessor failure. The C(* on the s!stem board has generated an
error.
• ' beeps' ;e!board Controller B7/@Hate A@7 error. The ke!board controller
"B7/@% contains the gate A@7 switch which allows the computer to operate in
virtual mode. This error message means that the BIOS is not able to switch the
C(* into protected mode.
• A beeps' 9irtual Mode "processor% 83ception error. The C(* on the
motherboard has generated an Interrupt #ailure e3ception interrupt.
• & beeps' $ispla! Memor! 0+< Test failure. The s!stem video adapter is either
missing or 0ead+<rite 8rror its memor! is fault!. This is not a fatal error.
• M beeps' 0OMBIOS Checksum failure. The 0OM checksum value does not
match the value encoded in the BIOS. This is good indication that the BIOS
0OMs went bad.
• @$ beeps' CMOS Shutdown 0egister. The shutdown register for the CMOS
memor! 0ead+<rite 8rror has failed.
• @@ beeps' Cache 8rror + 83ternal Cache Bad. The e3ternal cache is fault!.
Other ,MI BIOS POST Codes
• # short beeps' (OST failed. This is caused b! a failure of one of the hardware
testing procedures.
• @ lon! J # short beeps' 9ideo failure. This is caused b! one of two possible
hardware faults. 6% 9ideo BIOS 0OM failure) checksum error encountered. @%
The video adapter installed has a hori=ontal retrace failure.
• @ lon! J ( short beeps' 9ideo failure. This is caused b! one of three possible
hardware problems. 6% The video $AC has failed. @% the monitor detection
process has failed. C% The video 0AM has failed.
• @ lon! beep' POST successful. This indicates that all hardware tests were
completed without encountering errors.
If !ou have access to a (OST Card reader) "Gameco) etc.% !ou can watch the
s!stem perform each test b! the value that,s displa!ed. If+when the s!stem hangs
"if there,s a problem% the last value displa!ed will give !ou a good idea where and
what went wrong) or what,s bad on the s!stem board. Of course) having a
description of those codes would be helpful) and different BIOSes have different
meanings for the codes. "could someone point out #T( sites where we could have
access to a complete list of error codes for different versions of AMI and Award
BIOSesO%.
BIOS -rror Messa!es
This is a short list of most fre>uent onscreen BIOS error messages. ?our s!stem
ma! show them in a different manner. <hen !ou see an! of these) !ou are in
trouble $ohP "$oes someone has an! additions or correctionsO%
• N&$*# Fate 2 ,#$ -rrorN' Hate A@7 on the ke!board controller "B7/@% is not
working.
• N,ddress 9ine ShortON' 8rror in the address decoding circuitr!.
• NCache Memory BadE Do ;ot -nable CacheON' Cache memor! is defective.
• NCH2# Timer -rrorN' There is an error in timer @. Several s!stems have two
timers.
• NCMOS Battery State 9owN ' The batter! power is getting low. It would be a
good idea to replace the batter!.
• NCMOS Checsum 3ailureN ' After CMOS 0AM values are saved) a
checksum value is generated for error checking. The previous value is different
from the current value.
• NCMOS System Options ;ot SetN' The values stored in CMOS 0AM are
either corrupt or none3istent.
• NCMOS Display Type MismatchN' The video t!pe in CMOS 0AM is not the
one detected b! the BIOS.
• NCMOS Memory Si0e MismatchN' The ph!sical amount of memor! on the
motherboard is different than the amount in CMOS 0AM.
• NCMOS Time and Date ;ot SetN' Self evident.
• NDisette Boot 3ailureN' The boot disk in flopp! drive A' is corrupted
"virusO%. Is an operating s!stem presentO
• NDisplay Switch ;ot ProperN' A video switch on the motherboard must be
set to either color or monochrome.
• NDM, -rrorN' 8rror in the $MA "$irect Memor! Access% controller.
• NDM, I@ -rrorN' 8rror in the first $MA channel.
• NDM, I# -rrorN' 8rror in the second $MA channel.
• N3DD Controller 3ailureN' The BIOS cannot communicate with the flopp!
disk drive controller.
• NHDD Controller 3ailureN' The BIOS cannot communicate with the hard
disk drive controller.
• NI;T+ I@ -rrorN' Interrupt channel 6 failed (OST.
• NI;T+ I# -rrorN' Interrupt channel @ failed (OST.
• N?eyboard -rrorN' There is a timing problem with the ke!board.
• N?B8Interface -rrorN' There is an error in the ke!board connector.
• NParity -rror PPPPN' (arit! error in s!stem memor! at an unknown address.
• NMemory Parity -rror at xxxxxN' Memor! failed at the 33333 address.
• NI8O Card Parity -rror at xxxxxN' An e3pansion card failed at the 33333
address.
• NDM, Bus Time2outN' A device has used the bus signal for more than
allocated time "around B microseconds%.
If !ou encounter an! (OST error) there is a good chance that it is an
&A0$<A08 related problem. ?ou should at least verif! if adaptor cards or other
removable components "simms) drams etc...% are properl! inserted before calling
for help. One common attribute in human nature is to rel! on others before
investigating the problem !ourself. (lease don,t be a politician "Aidetoi et le ciel
t,aidera%.
BIOS Identification 9ine
There ma! be up to three identification lines in the BIOS startup screen.
• #irst identification line
• Second identification line
• Third identification line
3irst Identification 9ine
/@1 Processor Type
• O B7BB or B7B.
• O B7@B.
• O B7CB.
• 5 B7CB.S5
• / B7/B.
• D (entium
/#1 Si0e of BIOS
• 7 ./;
• 6 6@B;
/*2H1 Ma:or 7ersion ;umber
/'2A1 Minor 7ersion ;umber
/M2@*1 +eference ;umber
/@'1 Halt on POST -rror
• 7 Off
• 6 On
/@A1 Initiali0e CMOS in e%ery boot
• 7 Off
• 6 On
/@&1 Bloc pins ## and #( of the eyboard controller
• 7 Off
• 6 On
/@M1 Mouse support in BIOS8eyboard controller
• 7 Off
• 6 On
/#$1 .ait for B3@C if error found
• 7 Off
• 6 On
/#@1 Display floppy error durin! POST
• 7 Off
• 6 On
/##1 Display %ideo error durin! POST
• 7 Off
• 6 On
/#(1 Display eyboard error durin! POST
• 7 Off
• 6 On
/#H2#'1 BIOS Date Month
/#A2#&1 BIOS Date Day
/#M2($1 BIOS Date "ear
/(#2(M1 Chipset Identification 8 BIOS ;ame
/*@1 ?eyboard controller %ersion number
Second Identification 9ine
/@2#1 Pin number for cloc switchin! throu!h eyboard controller
/(1 Indicates hi!h si!nal on pin switches cloc speed to hi!h or low
• & &igh
• A Aow
/H1 Cloc switchin! throu!h chipset re!isters
• 7 Off
• 6 On
/A2@$1 Port address to switch cloc hi!h
/@#2@(1 Data %alue to switch cloc hi!h
/@H2@'1 Mas %alue to switch cloc hi!h
/@&2#@1 Port address to switch cloc low
/#(2#*1 Data %alue to switch cloc low
/#'2#A1 Mas %alue to switch cloc low
/#M2(@1 Pin number for turbo switch
Third Identification 9ine
/@2#1 ?eyboard Controller Pin for cache control
/(1 Indicates whether hi!h si!nal on cache control pin enables or disables cache
• & 8nable
• A $isable
/H1 Indicates if the hi!h si!nal if used on the eyboard controller pin
• 7 #alse
• 6 True
/A2M1 Cache control throu!h chipset re!isters
• 7 Cache control off
• 6 Cache control on
/@@2@#1 Port address to enable cache throu!h special port
/@*2@H1 Data %alue to enable cache throu!h special port
/@A2#$1 Mas %alue to enable cache throu!h special port
/##2#(1 Port address to disable cache throu!h special port
/#H2#'1 Data %alue to disable cache throu!h special port
/#&2#M1 Mas %alue to disable cache throu!h special port
/(@1 Pin number for resettin! the &#((H memory controller
/((1 BIOS modified fla! /Incremented each time BIOS is modified1
Chan!in! "our Password
8nable !ou to change the active password. The default is no password.
+emember your passwordOOO .rite it down somewhereOOO Ask !ourself' $o I
reall! need to set a password to access m! s!stem and+or the BIOSO "is !our
brother + sister + kid + emplo!ee + colleague that dangerousO% If securit! is of some
minor concern to !ou) disabled recommended. <h! not onl! password protect
"or encr!pt% some critical files "personal finances things the I0S should not see)
:uic! love letters) pornographic images "the thing that Internet is most used for%)
customer information databases) etc...%O If !ou lose your password) !ou will
have to erase your CMOS memory "see the #AS%. Some s!stems allow !ou to
choose when the password is needed to change the CMOS settings) to boot the
machine) etc.
,uto Confi!uration
All recent motherboards have now an autoconfiguration setting leaving much of
BIOS setup problems out of the user,s hands) such as Bus Clock Speed and <ait
States. On the ma:orit! of cases it will do :ust fine. But !ou must remember) it is
not an optimi0ation of !our s!stem,s performances) but a set of efficient settin!s
that will insure a good result. ?ou will have to Disable this setting if !ou want to
alter the BIOS !ourself) otherwise !our settings will be i!nored. On some
s!stems) !ou ma! get supplementary performances b! improving over auto
configuration settings) but on others auto configuration is all you will e%er need.
,uto Confi!uration with BIOS Defaults
The BIOS defaults ma! not be tuned for !our motherboard+chipset) but give a
reasonable chance of getting into (OST. *suall! these settings are a !ood start
to fine tune !our s!stem. If !ou did somethin! wron! and don,t know what)
select this. It will replace !our BIOS settings b! default values. ?ou will have to
start all over again. Be sure to know !our s!stem,s configuration. This option
does ;OT alter the dateE hard dis and floppy dis confi!urations in the
Standard CMOS setup) so in general !ou can e3pect !our s!stem to boot without
problems after selecting this.
,uto Confi!uration with Power2on Defaults
<hen powering on) the BIOS puts the s!stem in the most conser%ati%e state !ou
can think of. Turbo off) all caches disabled) all wait states to ma3imum) etc... This
is to make sure that !ou can alwa!s enter BIOS setup. *seful if the settings
obtained b! selecting A*TO CO1#IH*0ATIO1 <IT& BIOS $8#A*ATS fail.
If the s!stem does not wor with these values) itQs time to panic' the problem
ma! be hardwarerelated "$I( switches) cards not inserted properl! or worst)
something broken%.
-xitin! BIOS
There are two wa!s to e3it BIOS settings.
• .rite to CMOS and -xit' Save the changes !ou made in the CMOS. ?ou
must do that to permanentl! keep !our configuration. Several users sa! the!
changed the CMOS setup but forgot to e3it with this oneP A common source of
error.
• Do ;ot .rite to CMOS and -xit' If !ou are not sure of the changes !ou
made in the CMOS settings) use this option to e3it safel!.
,d%anced CMOS Setup
+emember=
Ma! var! according to !our s!stem) BIOS version and brand. Some functions
ma! not be present or the order and name may be different "particularl! for
different BIOS brand%. ;now -),CT9" what !ou are doing. Some
configurations ma! keep !our computer off from bootin!. If that,s the case'
Switch the power off. Turn !our computer on .HI9- keeping the D-9 ke!
pressed. This is supposed to erase the BIOS memor!. If it still doesn,t boot)
consult !our motherboard manual. Aook for a 4forget CMOS 0AM4 :umper. Set
it. Tr! it again. If it still doesn,t boot) ask a friend or post to a computer hardware
newsgroup. ?ou are permitted to panic.
• Typematic +ate Pro!rammin!' $isabled recommended. It enables the
t!pematic rate programming of the ke!board. 1ot all ke!boards support thisP
The following two entries specif! how the ke!board is programmed if enabled.
• Typematic +ate Delay /msec1' D77 ns recommended. The initial dela! before
ke! autorepeat starts) that is how long !ou,ve got to press a ke! before it starts
repeating.
• Typematic +ate /Chars8Sec1' 6D. It is the fre>uenc! of the autorepeat i.e.
how fast a ke! repeats.
• ,bo%e @ MB Memory Test' If !ou want the s!stem to check the memor!
above 6 MB for errors. Disabled recommended for faster boot se>uence. The
&IM8M.S?S driver for $OS ..@ verifies the 5MS "83tended Memor!
Specification%) so this test is redundant. It is thus preferable to use the 5MS
test provided b! &IM8M.S?S since it is operating in the real environment
"where user wait states and other are operational%.
• Memory Test Tic Sound' 8nabled recommended. It gives an audio record
that the boot se>uence is working properl!. (lus) it is an aural confirmation of
!our C(* clock speed+Turbo switch setting. An e3perimented user can hear if
something is wrong with the s!stem :ust be the memor! test tick sound. Since
s!stems have now much more memor! than before) this setting is not common
an!more.
• Memory Parity -rror Chec' -nabled recommended. Additional feature to
test bit errors in the memor!. All "or almost all% (Cs are checking their
memor! during operation.8ver! b!te in memor! has another ninth bit) that
with ever! write access is set in such wa! that the parit! of all b!tes is odd.
<ith ever! read access the parit! of a b!te is checked for this odd parit!. If a
parit! error occurs) the 1MI "1on Maskable Interrupt%) an interrupt !ou mostl!
cannot switch off) so the computer stops his work and displa!s a 0AM failure%
becomes active and forces the C(* to enter an interrupt handler) mostl!
writing something like this on the screen' (A0IT? 800O0 AT 7ABD'77B8
S?ST8M &AAT8$. On some motherboards !ou can disable parit! checking
with standard memor!. 8nabled to be sure data from memor! are correct.
$isable onl! if !ou have Bbit 0AM) which some vendors use because it is
67N cheaper. Also) this setting is no longer necessar! on recent computers
since the >ualit! and reliance of memor! chips has greatl! been improved.
,bout different memory speeds' Be sure to have memor! chips of the same
speed installed. It is not uncommon to have s!stem crashes simpl! because
memor! SIMMS are of different speed. #aster memor! ma! not adapt itself to the
speed of slower memor!. .7 ns and B7 ns SIMMS will surel! make !our s!stem
crash and !ourself wonder what is the problem "I know%.
• Hard Dis Type *A +,M ,rea' The BIOS has to place the &$ t!pe /I data
somewhere in memor!. ?ou can choose between $OS memor! or (C BIOS
"or peripheral card% memor! area 7'C77. $OS memor! is valuable) !ou onl!
have ./7;B of it. So !ou should tr! to use 7'C77 memor! area instead. There
ma! be some peripheral card which needs this area too "sound card) network
card) whatever%. So if there are some fanc! cards in !our (C) check the
manuals if the!,re using the 7'C77 area. But in most cases this will work
without checking. This is redundant if BIOS is shadowed "ma!be not in ver!
old BIOSes%. The 0AM area can be verified b! checking address of int/6h and
int/.h. These are fi3ed disk parameters blocks. If the! point to the BIOS area)
BIOS made modification of parameters before mapping 0AM there.
• If An! 8rror4.ait for B3@C If ,ny -rror' <hen the boot se>uence encounter
an error it asks !ou to press #6. Onl! at ,nonfatal, errors. If disabled) the
s!stem prints a warning and continues to boot without waiting for !ou to press
an! ke!s. 8nabled recommended. $isabled if !ou want the s!stem to operate
as a server without a ke!board.
• System Boot 6p ;um 9oc' Specif! if !ou want the 1um Aock ke! to be
activated at boot up. Some like it) some do not. MS$OS "starting with ..7)
ma!be earlier% allows a 41*MAOC;K4 directive in config.s!s) too- if
someone turns the BIOS flag off but has 1*MAOC;KO1 in their
configuration file) the! ma! be a bit perturbed.
• ;umeric Processor Test' 8nabled if !ou have a math coprocessor "built in for
the /B.$5) /B.$5@) /B.$5C and (entium DB. famil!%. $isabled if !ou
don,t "CB.S5) CB.$5) /B.S5) /B.SAC and /B.$AC%. If disabled) !our #(*
"#loating (oint *nit) if present% isn,t recogni=ed as present b! the s!stem and
will therefore significantl! decrease the performance of !our s!stem.
• .eite Coprocessor' If !ou have <eitek #(*) enable. If !ou have not)
disable. This high performance #(* has @C times the performance of the Intel
#(*. <eitek uses some 0AM address space) so memor! from this region must
be remapped somewhere else. This setting is normall! found on CB.
motherboards.
• 3loppy Dri%e See at Boot' (ower up !our A' flopp! drive at boot. Disabled
recommended for faster boot seDuence and for reduced dama!e to heads.
$isabling the flopp! drive) changing the s!stem boot se>uence and setting a
BIOS password are good techni>ues for adding some securit! to a (C.
• System Boot SeDuence' <hat drive the s!stem checks first for an operating
s!stem. C5E ,5 recommended for faster boot seDuence) or to not allow an!
user to enter !our s!stem b! booting from the #$$ if !our autoe3ec.bat starts
with a login procedure. A') C' if the person who uses the computer is someone
who don,t knows how to setup CMOS. Because if something fails and a boot
flopp! won,t work) man! users won,t know what to do ne3t. &owever) be
careful. ?ou had better know this setting is turned on and be prepared to turn it
off if !our hard disk boot track becomes corrupted) but not obviousl! absent)
since !ou otherwise won,t be able to boot from flopp!. Also) it,s eas! to fool
!ourself into thinking !ou booted from a known virusfree flopp! when it
actuall! booted from the "virusinfested% hard drive.
• System Boot 6p CP6 speed' Specif! at what processor speed the s!stem will
boot from. *sual settings are &IH& and AO<. HIFH recommended. If !ou
encounter booting problems) !ou ma! tr! AO<. ?ou ma! also change the C(*
speed with CtrlAlt J.
• -xternal Cache Memory' 8nabled if !ou have e3ternal cache memor!
"better nown as 9# cache memory%. This is a fre>uent error in CMOS setup
as if $isabled when !ou have cache memor!) the s!stem performance
decreases significantl!. Most s!stems have from ./; to D6@; of e3ternal
cache. It is a cache between the C(* and the s!stem bus. $ifferent operating
s!stems ma! address different levels of cache memor!. #or instance) $OS and
<indows can address up to ./; at one time while <indows FD) OS+@ and
<indows 1T can address larger memor! spaces. So) don,t bu! @D.; of cache
is !ou are using a $OS environment with less than BMB of memor!. It will not
improve much the performance of !our s!stem. If 8nabled when the s!stem
does not have cache memor!) the s!stem will free0e most of the time.
• Internal Cache Memory' 8nable or disable the internal cache memor! of the
C(* "better nown as 9@ cache memory%. $isabled for CB. and 8nabled for
/B. "6 to B;B of internal C(* cache%. If the C(* does not have internal
cache) the s!stem ma! free=e if enabled.
In man! AMI and A<A0$ BIOSes) the two previous options are implemented
either as separate Internal and 83ternal 8nable+$isable options) or as a single
option "Cache Memory 5 Disabled8Internal8Both%.
• CP6 Internal Cache5 same as above.
• 3ast Fate ,#$ Option' 8nabled recommended. A@7 refers to the first ./;B
of e3tended memor! "A7 to A6F% known as the 4high memor! area4. This
option uses the fast gate A@7 line) supported in some chipsets) to access
memor! above 6 MB. 1ormall! all 0AM access above 6 MB is handled
through the ke!board controller chip "B7/@ or BI/@%. *sing this option will
make the access faster than the normal method. This option is ver! useful in
networking and multitasking operating s!stems.
• Turbo Switch 3unction' 8nables or disables the turbo switch. $isabled
recommended. This setting is now removed since there are no need to switch
from normal to turbo modes.
• Shadow Memory Cacheable' ?ou increase speed b! cop!ing 0OM to 0AM.
$o !ou want to increase it b! cacheing itO ?es or no see 9ideo BIOS Area
cacheable. ?es recommended for MS$OS and OS+@. Ainu3 and other *ni3
like operating s!stems will not use the cached 0OMs and will benefit from the
additional available memor! if the! are not cached.
• Password Checin! Option' Setup password to have access to the s!stem and
+ or to the setup menu. Hood if the computer is to be shared with several
persons and !ou don,t want an!one "friends) sister) etc.% to mess up with the
BIOS. $efault password' AMI "if !ou have AMI BIOS%. Award' BIOSTA0 or
A<A0$2S< for newer versions "1ote' I even know a computer store that
kept standard A<A0$ BIOS configuration with their s!stems because the!
didn,t know what the default password wasP%.
• 7ideo +OM Shadow C$$$E (#?' Memor! hidden under the 4I+O hole4 from
737A7777 to 737##### ma! be used to 4shadow4 0OM "0eadOnl!
Memor!%. $oing so) the contents of the 0OM are copied into the 0AM and the
0AM is used instead) which is obviousl! faster. 9ideo BIOS is stored in slow
8(0OM "8rasable (rogrammable 0eadOnl! Memor!% chips "6@7 to 6D7ns of
access time%. Also) 0OM is B or 6. bit while 0AM C@ bit wide access. <ith
Shadow on) the 8(0OM content is copied to 0AM ".7 to B7ns of access time
with C@ bit wide access%. Therefore performance increases significantl!. Onl!
sensible on 8HA+9HA s!stems. -nabled recommended. If !ou have flash
BIOS "88(0OM%) !ou can disable it. #lash BIOS enables access at speeds
similar to memor! access so !ou can use the memor! elsewhere. &owever)
flash BIOS is still onl! accessing it at the speed of the bus "ISA) 8ISA or
9AB%. On s!stems where the BIOS automaticall! steals CB/; of 0AM
an!wa!) it shouldn,t hurt to enable shadowing even on flash 0OM. One side
effect is that !ou will not be able to modif! the contents of flash 0OM when
the chip is shadowed. If !ou reconfigure an adapter which !ou think might
have flash 0OM) and !our changes are ignored) or of course if it gives !ou an
error message when !ou tr! to change them) !ou,ll need to temporaril! disable
shadowing that adapter. On "S%9HA !ou should enable both video shadows.
Some video cards ma!be using different addresses than C777 and C/77. If it is
the case) !ou should use supplied utilities that will shadow the video BIOS) in
which case !ou should disable this setting in the CMOS. 9ideo BIOS
shadowing can cause software like 5#reeB. "the free 5 <indow S!stem% to
hang. The! should be probabl! be disabled if !ou run an! of the CB. uni3es.
Some cards map BIOS or other memor! not onl! in the usual a7777fffff address
range) but also :ust below the 6.MB border or at other places. The BIOS "for (CI
buses onl!O% now allows to create a hole in the address range where the card sits.
The hole ma! be enabled b! giving an address) then a si=e is re>uested in power
of @) ./k 6MB.
• ,daptor +OM Shadow C&$$E@'?' $isabled. Those addresses "CB77 to
8C77% are for special cards) e.g. network and controllers. 8nable onl! if !ou,ve
got an adapter card with 0OM in one of these areas. It is a BA$ idea to use
shadow 0AM for memor! areas that aren,t reall! 0OM) e.g. network card
buffers and other memor!mapped devices. This ma! interfere with the card,s
operation. To intelligentl! set these options !ou need to know what cards use
what addresses. Most secondar! displa! cards "like M$A and &ercules% use
the 0OM CB77 address. Since the! are slow) shadowing this address would
improve their performance. An advanced tip' in some setups it is possible to
enable shadow 0AM without writeprotecting it- with a small driver "*MM% it
is then possible to use this ,shadow 0AM, as *MB "*pper Memor! Block%
space. This has speed advantages over *MB space provided b! 8MMCB..
Some BIOSes have three options per 6.;B+C@;B+./;B block- e.g. disable
shadow 0OM shadow 0AM or disable shadow+<( shadow "<( K write
protect% the third option is for upper memor!.
• ,daptor +OM Shadow CC$$E@'?' $isabled. Some hard drive adapters use
that address.
• ,daptor +OM Shadow D$$$E@'?' $isabled. $777 is the default Address for
most 1etwork Interface Cards.
• ,daptor +OM Shadow D*$$E@'?' $isabled. Some special controllers for
four flopp! drives have a BIOS 0OM at $/77..$I##.
• ,daptor +OM Shadow D&$$E@'?' $isabled
• ,daptor +OM Shadow DC$$E@'?' $isabled
• ,daptor +OM Shadow -$$$E@'?' $isabled. 8777 is a good 4out of the wa!4
place to put the 8MS page frame. If necessar!.
• ,daptor +OM Shadow -*$$E@'?' $isabled
• ,daptor +OM Shadow -&$$E@'?' $isabled
• ,daptor +OM Shadow -C$$E@'?' $isabled. SCSI controller cards with
their own BIOS could be accelerated b! using Shadow 0AM. Some SCSI
controllers do have some 0AM areas too) so it depends on the brand.
Some SCSI adapters do not use I+OAddresses. The BIOS address range contains
writable addresses) which in fact are the I+Oports. This means this address must
not be shadowed and even not be cached.
• System +OM Shadow 3$$$E '*?' Same thing as 9ideo shadow) but
according to the s!stem BIOS "main computer BIOS%. -nabled
recommended for impro%ed performance. S!stem BIOS shadowing and
caching should be disabled to run an!thing but $OS "<indows%.
On older BIOS versions the shadow choices are in /77"he3%b!te increments. #or
instance) instead of one 9ideo 0OM Shadow segment of C@;) !ou will have two
6.; segments "C/77 and CB77%. Same thing for Adaptor 0OM Shadow
segments.
• BootSector 7irus Protection' It is not e3actl! a %irus protection. All it does
is whenever !our boot sector is accessed for writing) it gives a warning to the
screen allowing !ou to disable the access or to continue. 83tremel! anno!ing if
!ou use something like OS+@ Boot Manager that needs to write to it. It is
completel! useless for SCSI or 8S$I "8nhanced Small $evice Interface%
drives as the! use their own BIOS on the controller. Disabled recommended.
If !ou want virus protection) use a TS0 "Terminate and Sta! 0esident% virus
detection "1orton) Central (oint) etc...%. 9iruscan b! Macfee is also a good
idea since it is a shareware.
,d%anced Chipset Setup
+emember=
Confi!urations may %ary according to !our s!stem) BIOS version and brand.
So) some settings ma! be present on !our computer) some ma! not or have a
different name. Be sure of what !ou are doingP If !ou find a configuration having
a different name) please let us know.
• +efresh
• Data Bus
• Cachein!
• Memory
• ,utomatic Confi!uration' Allows the BIOS to set automaticall! several
important settings "e.g. Clock divider) wait states) etc.%. 9er! useful for
newbies. Disabled recommended if you want to play around with the
settin!s. If !ou have some special adapter cards) !ou will also have to disable
this option.
• ?eyboard +eset Control' 8nable CtrlAlt$el warm reboot. 8nabled
recommended for more control over !our s!stem.
+efresh
• Hidden +efresh' Allows the 0AM refresh memor! c!cles to take place in
memor! banks not used b! !our C(* at this time) instead or together with the
normal refresh c!cles) which are e3ecuted ever! time a certain interrupt
"$0S7 ever! 6D ms% is called b! a certain timer "O*T6%. 8ver! time it takes @
to / ms for the refresh. One refresh c!cle ever! Q6. us refreshes @D. rows in Q
/ms. 8ach refresh c!cle onl! takes the e>uivalent of one memor! read or less)
as CAS "Column Address Strobe% is not needed for a refresh c!cle. Some
0AM can do it) some not. Tr!. If the computer fails) turn it off. 8nabled
recommended. There are t!picall! C t!pes of refresh schemes' c!cle steal)
c!cle stretch) or hidden refresh. C!cle steal actuall! steals a clock c!cle from
the C(* to do the refresh. C!cle stretch actuall! dela!s a c!cle from the
processor to do the refresh. Since it onl! occurs ever! sa! /ms or so) it,s an
improvement from c!cle steal. <e,re not reall! stealing a c!cle) onl! stretching
one. &idden refresh t!picall! doesn,t stretch or steal an!thing. It,s usuall! tied
to $TAC; "$ata acknowledge% or AA8 "Address Aatch 8nable% or some other
signal relating to memor! access. Since memor! is accessed AAA of the time it
is eas! to s!nchroni=e the refresh on the falling edge of this event. Of course)
the s!stem performance is at its optimum efficienc!) refresh wise since we,re
not taking clock c!cles awa! from the C(*.
• Slow +efresh' Causes 0AM refresh to happen less often than usual) around
four times. This increases the performance slightl! due to the reduced
contention between the C(* and refresh circuitr!) but not all $0AM
memories necessaril! support these reduced refresh rates "in which case !ou
will get parit! errors and crashes%. It also saves power) a good opportunit! for
laptop computers. -nabled recommended
• Concurrent +efresh' Both the processor and the refresh hardware have access
to the memor! at the same time. If !ou switch this off) the processor has to
wait until the refresh hardware has finished "it,s a lot slower%. -nabled
recommended.
• Burst +efresh5 (erforms several refresh c!cles at once. Increase the s!stem
performance.
• D+,M Burst at * +efresh5 0efresh is occurring at Bursts of four) increasing
the s!stem performance.
• Hi2speed +efresh5 0efreshes are occurring at an higher fre>uenc!) which is
improving the s!stem performance. Of course) not all t!pes of memor! can
support it and Slow 0efresh is preferred.
• Sta!!ered +efresh5 0efresh is performed on memor! banks se>uentiall!. The
advantages are related to less power consumption and less interference
between memor! banks.
• Slow Memory +efresh Di%ider5 The AT refresh c!cle occurs normall! ever!
6. ns) straining the C(*. If !ou can select an higher value) such as ./ ns) !ou
will increase the performance of !our s!stem.
• Decoupled +efresh Option5 8nables the ISA bus and the 0AM to refresh
separatel!. Because refreshing the ISA bus is more slow) this causes less strain
on the C(*.
• +efresh 7alue' The lower this value is) the best the performance.
• +efresh +,S ,cti%e Time' The amount of active time needed for 0ow
Address Strobe during refresh. The lower the better.
Data Bus
• Sin!le ,9- -nable' Address Aatch 8nable "AA8% is an ISA Bus Signal "(in
B@B% that indicates that a valid address is posted on the bus. The bus is used to
communicate with B and 6. bit peripheral cards. Some chipsets have the
capabilit! to support an enhanced mode in which multiple AA8 assertions ma!
be made during a single Bus C!cle. Single AA8 8nable apparentl! enables or
disables that capabilit!. Ma! slow the video bus speed if enabled. $isabled
"1o% recommended.
• ,T B6S Cloc Selection /or ,T Bus Cloc Source1' Hives a division of the
C(* clock "or S!stem Clock% so it can reach the ISA 8ISA bus clock. An
improper setting ma! cause significant decrease in performance. The settings
are in terms of CA;+3) "or CA;I1+3 and CA;@+3% where 3 ma! have values
like @) C) /) D) etc. CA; represents !our processor speed) with the e3ception
that clockmultiple processors need to use the 85T801AA clock rate) so a
/B.$5CC) /B.$5@+..) and /B.$5C+FF all count as CC and should have a
divider value of /. #or @B. and CB. processors) CA; is half the speed of the
C(*. ?ou should try to reach &4(( Mh0 "that,s the old bus clock of IBM AT-
there ma! be cards which could do higher) but it,s not highl! recommended%.
On some motherboards) the AT bus speed is I.6D Mh=. On new BIOS versions)
there is an A*TO setting that will look at the clock fre>uenc! and determine
the proper divider. &ere are some appropriate settings'
CA;
+C
S5+$56.) $5@7) $5@D) $5@+D7)
$5/+677
CA;
+/
S5+$5CC) $5@+..) $5C+FF
CA;
+D
$5/7) $5@+B7
CA;
+.
$5D7) $5@+677
Selectin! the ri!ht cloc di%ider. ?ou can tr! other clock settings to increase
performance. If !ou choose a too small di%ider "CA;+@ for a $5CC% your
system may han!. #or a too bi! di%ider "CA;+D for a $5CC% the performance
of IS, cards will decrease. This setting is for data e3change with ISA cards)
;OT 79 bus and PCI cards which run at C(* bus clock speeds' @DMh=)
CCMh= and higher. If !our ISA cards are fast enough to keep up) it is possible to
run the bus at 6@ Mh=. 1ote that if !ou switch cr!stals to overclock !our C(*)
!ou are also overclocking the ISA bus unless !ou change settings to compensate.
Gust because !ou can overclock the C(* doesn,t mean !ou can get awa! with
overclocking the ISA bus. It might :ust be one card that causes trouble) but one is
enough. It might cause trouble even if !ou aren,t using it b! responding when it
shouldn,t.
• IS, Bus Speed' As above) but related to (CI.
• Bus Mode' It can be set in s!nchronous and as!nchronous modes. In
s!nchronous mode) the C(* clock is used) while in as!nchronous mode the
ATCA; is used.
• ,T Cycle .ait State' <henever an operation is performed with the AT bus) it
indicates the number of wait states inserted. ?ou ma! need some wait states if
old ISA cards are used) notabl! if the! are in operation with fast adapter cards.
• @'2bit MemoryE I8O .ait State5 The number of wait states before 6.bit
memor! and I+O operations.
• &2bit MemoryE I8O .ait State' As above) e3cept this setting is for Bbit
operations.
• @'2bit I8O +eco%ery Time' The additional dela! time inserted after ever! 6.
bit operations. This value is added to the minimum dela! inserted after ever!
AT c!cles.
• 3ast ,T Cycle' If enabled) ma! speed up transfer rates with ISA cards) notabl!
video.
• IS, I+G' Inform the (CI cards of the I0Ss used b! ISA cards) so the! be
discarded.
• DM, .ait States' The number of wait states inserted before direct memor!
access "$MA%. The lower the better.
• DM, Cloc Source' The source of the $MA clock for which some peripheral
controllers) like flopp!) tape) network and SCSI adapters use to address
memor!) which is D M&= ma3imum.
• -$$$$ +OM belon!s to ,TB6S' Tells if the 87777 area "upper memor!%
belongs to the MB $0AM or to the AT bus. ?es recommended.
• Memory +emappin!' 0emaps the memor! used b! the BIOS "A7777 to
#### CB/ k% above the 6 Mb limit. If enabled !ou cannot shadow 9ideo and
S!stem BIOS. $isabled recommended.
• 3ast Decode -nable' 8nabled recommended. 0efers to some hardware that
monitors the commands sent to the ke!board controller chip. The original AT
used special codes not processed b! the ke!board itself to control the
switching of the @B. processor back from protected mode to real mode. The
@B. had no hardware to do this) so the! actuall! have to reset the C(* to
switch back. This was not a speed! operation in the original AT) since IBM
never e3pected that an OS might need to :ump back and forth between real and
protected modes. Clone makers added a few (A$ chips to monitor the
commands sent to the ke!board controller chip) and when the 4reset C(*4
code was seen) the (A$ chips did an immediate reset) rather than waiting for
the ke!board controller chip to poll its input) recogni=e the reset code) and then
shut down the C(* for a short period. This 4fast decode4 of the ke!board reset
command allowed OS+@ and <indows to switch between real and protected
mode faster) and gave much better performance. "earl! @B. clones with
(hoeni3 @B. BIOS had this setting to enable+disable the fast decode logic.% On
CB. and newer processors) the fast decode is probabl! not used) since these
C(*s have hardware instructions for switching between modes. There is
another possible definition of the 4#ast $ecode 8nable4 command. The design
of the original AT bus made it ver! difficult to mi3 Bbit and 6.bit 0AM or
0OM within the same 6@B; block of high address space. Thus) an Bbit BIOS
0OM on a 9HA card forced all other peripherals using the C777$fff range to
also use B bits. B! doing an 4earl! decode4 of the high address lines along with
the B+6. bit select flag) the I+O bus could then use mi3ed B and 6. bit
peripherals. It is possible that on later s!stems) this BIOS flag controls the
4fast decode4 on these address lines.
• -xtended I8O Decode' The normal range of I+O addresses is 773Cff- 67 bits
of I+O address space. 83tended I+Odecode enables wider I+Oaddress bus. The
C(* support a ./; I+O space) 6. address lines. Most motherboards or I+O
adapters can be decoded onl! b! 67 address bits.
• I8O +eco%ery Time' I+O recover! time is the number of wait states to be
inserted between two consecutive I+O operations. It is generall! specified as a
two number pair e.g. D+C. The first number is the number of wait states to
insert on an B bit operation) the second the number of waits on a 6. bit
operation. A few BIOSes specif! an I+O Setup time "AT Bus "I+O% Command
$ela!%. It is specified similarl! to IO 0ecover! Time) but is a dela! before
STA0TI1H an I+O operation rather than a dela! B8T<881 I+O operations.
D+C has been recommended as a value which will often !ield a good
combination of performance and reliabilit!. <hen enabled) more I+O wait
states are inserted. A transfer from I$8 hard drive to memor! happens without
an! handshaking) meaning the data has to be present "in the cache of the hard
disk% when the C(* wants to read them from an I+O (ort. This is called PIO
"(rogrammed I+O% and works with a 08( I1S< assembler instruction. 1ow
I+O 0ecover! Time enabled adds some wait states to this instruction. <hen
disabled) the hard drive is a lot faster. 1ote that there is a connection between
I+O 0ecover! Time and AT B*S Clock Selection. #or e3ample) if the AT B*S
Clock is set to B M&= and !ou have a normal hard disk) I+O 0ecover! Time
can be turned off) resulting in a higher transfer rate from hard disk.
• ID- Multi Bloc Mode' 8nable I$8 drives to transfer several sectors per
interrupt. According to the hard drive cache si=e) si3 modes are possible. Mode
$ "standard mode transferring a single sector at a time%) Mode @ "no
interrupts%) Mode @ "Sectors are transferred in a single burst%) Mode ( "C@bit
instructions with speeds up to 66.6 Mb+sec.In BIOSes usuall! abbreviated as
4C@bit mode4. 1ot to be confused with C@bit protected modeinstructions"P% or
<indows, C@bit disk access.%) Mode * "up to 6.)I Mb+sec.% and Mode H "up to
@7 Mb+sec.%. The socalled 4(IO mode D4 is completel! bogus. It was launched
b! some controller manufacturers but was never accepted) never absorbed into
the standards and !ou will not find an! disk drives supporting it. 1or will !ou
find an! such drives in the future. The relevant parameter for block mode is the
number of sectors per interrupt. The ma3imum number of sectors per interrupt
is often "but not alwa!s% related to the drive,s buffer si=e. If this setting is not
set properl!) communication with COM ports ma! not work properl!. If the
block si=e "sectors+interrupt% is set to too large a value) !ou ma! e3perience
serial port overruns and C0C errors. To fi3 this) decrease the block si=e
"preferred% or disable block mode altogether.#or more info) please have a look
at The 8I$8 #ASATA harddisks.
• ID- DM, Transfer Mode' Settings are $isabled) T!pe B "for 8ISA% and
Standard "for (CI%. Standard is the fastest but ma! cause problems with I$8
C$ 0OMs. The standard t!pe is t!pe #. 1ote that both are socalled 4third
part! $MA4 and should not be confused with firstpart! "busmastering% $MA
offered b! man! modern boards.
• ID- Multiple Sector Mode' <hen I$8 $MA Transfer Mode is enabled) this
sets the number of sectors per burst) with a ma3imum of ./. (roblems ma!
occur with COM ports.
• ID- Bloc Mode' 8nables multisectors transfers. Also known as ID- HDD
Bloc Mode.
.arnin!4 This setting is known to cause crashes in <inFD. $isabled
recommended. 83tremel! anno!ing.
• ID- (#2bit Transfer' <hen enabled) the read + write rate of the hard disk is
faster. <hen disabled onl! 6.bit data transfers is possible. The read+write rate
of the harddisk sta!s the same) but the transfers over the host bus are maybe
faster. So) don,t e3pect an!thing reall! dramatic. Actuall!) !ou should
ordinaril! e3pect no difference at all) since even with 6.bit transfers) the local
bus is fast enough to accomodate :ust about an! disk drive. &owever) some
interface hardware uses faster timing on the ATA "I$8% bus when C@bit
transfers are used. In those cases !ou ma! notice a speedup. 1ote that ATA
"I$8% is a 6.bit bus. The C@bit transfers referred to here are strictl! the
transfers between C(* and interface chip.
• -xtended DM, +e!isters' <ithin a AT) $MA occurs for 6. Mb. <hen
enabled) $MA covers the whole / Hb of a C@bit processor.
Cachein!
• Cache +ead Option' Often referred as S+,M +ead wait state or Cache
+ead Hit Burst "S0AM' Static 0andom Access Memor!%. A specification of
the number of clocks needed to load four C@bit words into a C(* internal
cache. T!picall! specified as clocks per word. @666 indicates D clocks to
load the four words and is the theoretical minimum for current high end C(*s
"/B.$5) /B.S5) /B.$5@) /B.$5/) (entium%. Conceptuall!) the mnnn
notation is narrowl! limited to C(*s supporting burst mode and with caches
organi=ed as / word 4lines4. &owever it would not be a surprise to see it
e3tended to other C(* architectures. It takes simple integer values) such as @
666) C666 or C@@@. This determines the number of wait states for the
cache 0AM in normal and burst transfers "the latter for /B. onl!%. The lower
!ou computer can support) the better. /666 is usuall! recommended.
• Cache .rite Option' Same thing as memor! wait states) but according to
cache ram.
• 3ast Cache +ead8.rite' 8nable if !ou have two banks of cache) ./; or
@D.;.
• Cache .ait State5 Aike conventional memor!) the lower wait states for !our
cache) the better. 7 will give the optimal performance) but 6 wait state ma! be
re>uired for bus speed higher than CC M&=.
• Ta! +am Includes Dirty' 8nabling will cause an increase in performance)
because the cache is not replaced during c!cles) simpl! written over. It will
usuall! cut the ma3imum cachable range in half) as one bit is taken off the
address tag in order to be used as a dirt! tag bit. So) if !ou have a lot of
memor!) !ou might be better off without dirt! tag bit.
• ;on2Cacheable Bloc2@ Si0e' $isabled. The 1onCacheable region is
intended for a memor!mapped I+O device that isn,t supposed to be cached.
#or e3ample) some video cards can present all video memor! at 6D Mb 6.
Mb so software doesn,t have to bankswitch. If the noncacheable region
covers actual 0AM memor! !ou are using) e3pect a significant performance
decrease for accesses to that area. If the noncacheable region covers onl! non
e3istent memor! addresses) don,t worr! about it. If !ou don,t want to cache
some memor! !ou can e3clude @ regions of memor!. There are good reasons
not to cache some memor! areas. #or e3ample) if the memor! area
corresponds to some kind of buffer memor! on a card so that the card ma!
alter the contents of this buffer without warning the cache to invalidate the
corresponding cache lines. Some BIOSes take more options than enabled
+disabled) namel! 1onlocal +1oncache +$isabled "9AB onl!O%.
• ;on2Cacheable Bloc2@ Base' 7;B. 8nter the base address of the area !ou
don,t want to cache. It must be a multiple of the 1onCacheable Block6 Si=e
selected.
• ;on2Cacheable Bloc2# Si0e' $isabled.
• ;on2Cacheable Bloc2# Base' 7;B.
• Cacheable +,M ,ddress +an!e' *suall! chipsets allow memor! to be
cached :ust up to 6. or C@ MB. This is to limit the number of bits of a memor!
address that need to be saved in the cache together with its contents. If !ou
onl! have /MB of 0AM) select /MB here. The lower the better) don,t enter
6.MB if !ou onl! have BMB installedP
• 7ideo BIOS ,rea Cacheable' To cache or not to cache video BIOS) a good
>uestion. ?ou should tr! what is better video access is faster with ,enabled,)
but cache has its si=e. <ith an 4accelerated4 video card it ma! be necessar! to
make the video 0AM region noncacheable so the C(* can see an! changes
the drawing engine makes in the frame buffer.
Memory
• Memory +ead .ait State' "often referred as D+,M .ait States% 8ach wait
states adds C7 ns of 0AM access speed. The C(* is often much faster than the
memor! access time. On a /B.) 6 or more wait states are often re>uired for
0AM with B7ns or higher access time. And) depending on the processor and
motherboard) also for lower than B7ns access time. The less wait states) the
better. Consult !our manual. If wait states are too low) a parit! error will occur.
#or CB. or /B. nonburst memor! access c!cle takes @ clock ticks. A rou!h
indication of 0AM speed necessar! for 7 wait states is @777+ClockUM&=V 67
UnsV. #or a CCMh= processor) this would give D7ns of access time re>uired) so
if !ou do not have D7ns memories) wait state is re>uired. The number of wait
states necessar! is approximately "0amSpeedUnsV J67% T ClockUM&=V +6777
@. #or I7ns 0AM and a CCMh= processor "ver! standard configuration%) this
would give roughl! 6 wait state. But this reall! is dependent on chipset)
motherboard and cache design) C(* t!pe and whether we talk about reads or
writes. Take these formulas with a large grain of salt. ?ou can find out the
access time of !our 0AM chips b! looking at their product numbers. Mostl! at
the end there is a I7) B7) F7) or even .7. If 67 stands there) it means 677 ns.
Some 0AM chips also have an e3plicitl! written speed in ns. The 0AM !ou
bu! these da!s mostl! have I7ns or .7ns.
• Memory .rite .ait State' Same as above e3cept for writting "self evident%.
In some BIOSes) these two options are combined as D+,M .ait State. In that
case) the number of read and write wait states is necessaril! e>ual.
• D+,M C,S Timin! Delay' The default is no CAS dela!. $0AM is
organi=ed b! rows and columns and accessed through strobes. Then a memor!
read+write is performed) the C(* activates 0AS "0ow Access Strobe% to find
the row containing the re>uired data. Afterwards) a CAS "Column Access
Strobe% specifies the column. 0AS and CAS are used to identif! a location in a
$0AM chip. 0AS access is the speed of the chip while CAS is half the speed.
<hen !ou have slow $0AM) !ou should use 6 state dela!.
• D+,M +efresh Method' Selects the timing pulse width of 0AS from 0AS
Onl! or CAS before 0AS "which one is betterO%.
• +,S Prechar!e Time' Technicall!) this is the duration of the time interval
during which the 0ow Address Strobe signal to a $0AM is held low during
normal 0ead and <rite C!cles. This is the minimum interval between
completing one read or write and starting another from the same "nonpage
mode% $0AM. Techni>ues such as memor! interleaving) or use of (age Mode
$0AM are often used to avoid this dela!. Some chipsets re>uire this parameter
in order to set up the memor! configuration properl!. The 0AS (recharge
value is t!picall! about the same as the 0AM Access "data read+write% time.
The latter can be used as an estimate if the actual value is unavailable. At least
one BIOS describes the precharge and access times as 0AS AO< and 0AS
&IH& Times. #or a CC M&= C(*) / is a good choice) while lower values
should be selected for slower speeds.
• +,S ,cti%e Time' The amount of time a 0AS can be kept open for multiple
accesses. &igh figures will improve performance.
• +,S to C,S Delay Time' Amount of time a CAS is performed after a 0AS.
The lower the better) but some $0AM will not support low figures.
• C,S Before +,S' 0educes refresh c!cles and power consumption.
• C,S .idth in +ead Cycle' The number of wait states for the C(* to read
$0AM. The lower the better.
• Interlea%e Mode' Controls how the C(* access different $0AM banks.
• 3ast Pa!e Mode D+,M' This speeds up memor! access for $0AM capable
of handling it "most do%. <hen access occurs in the same memor! area) 0AS
and CAS are not necessar!.
Plu! and Play8PCI
A s!stem intended to make fitting of e3pansion cards easier "!es) reall!P%. In this
conte3t) ISA cards are known as Aegac! Cards) and are switched as normal to
make them fit in. &ave as few of these as possible) as accesses to them are slow.
<ith Concurrent (CI) The T II "or /C7&5+95% chipset,s Multi Transaction Timer
allows multiple transfers in one (CI re>uest) b! reducing rearbitration when
several (CI processes can take place at once. (assive 0elease allows the (CI bus
to continue working when it,s receiving data from ISA devices) which would
normall! hog the bus. $ela!ed Transaction allows (CI bus masters to work b!
dela!ing transmissions to ISA cards. <rite merging combines b!te) word and
$word c!cles into a single write to memor!.
The idea is that plug and pla! cards get interrogated b! the s!stem the! are
plugged into) and their re>uirements checked against those of the cards alread! in
there. The BIOS will feed the data as re>uired to the Operating S!stem) t!picall!
<indows ,FD. &ere !ou will be able to assign I0Ss) etc to (CI slots and map (CI
I1TRs to them. Although <indows ,FD or a (n( BIOS can do a lot b! themselves)
!ou reall! need the lot) e.g.a (lug and (la! BIOS) with compatible devices and an
Operating S!stem for the best performance. Be aware that not all (CI "@.7% cards
are (n(. (C "(CMCIA% cards are also 4(lug and (la!4) but are not considered
here.
(n( itself was originall! devised b! Compa>) Intel and (hoeni3. ?our chipset
settings ma! allow !ou to choose of two methods of operation'
• All (n( devices are configured and activated.
• All (n( ISA cards are isolated and checked) but onl! those needed to boot the
machine are activated. The ISA s!stem cannot produce specific information
about a card) so the BIOS has to isolate each one and give it a temporar!
handle so its re>uirements can be read. 0esources can be allocated once all
cards have been dealt with "recommended for <indows ,FD) as it can use the
0egistr! and its own procedures to use the same information ever! time !ou
boot%.
8SC$ "83tended S!stem Configuration $ata%) a s!stem which is part of (n(
"actuall! a superset of 8ISA%) that can store data on (n( or non(n( 8ISA) ISA or
(CI cards to perform the same function as the <indows ,FD 0egistr! above) that
is) provide consistenc! between sessions. It occupies part of *pper Memor!
"87778$##%) which is not available to memor! managers. The default length is
/;) and problems have been reported with 8MS buffer addressing when this area
has been used.
PCI Slot Confi!uration
Although an unlimited number of (CI slots is allowed) in practice / is the
ma3imum) due to loading considerations.(CI cards and slots use an internal
interrupt s!stem) with each slot being able to activate up to /) labelled either
I1TRAI1TR$) or I1TR6I1TR/. These are nothing to do with I0Ss) although
the! can be mapped to them if the card concerned needs it. T!picall! I0Ss F and
67 are reserved for this) but an! available ones can be used.
• 9atency Timer /PCI Clocs1. Controls the length of time an agent on the (CI
bus can hold the bus when another has re>uested it) so ever!thing gets its fair
share.Since the (CI bus runs faster than the ISA bus) the (CI bus must be
slowed during interactions with it. This setting allows !ou to define how long
the (CI bus will dela! for a transaction between the given (CI slot and the ISA
bus. This number is dependent on the (CI master device in use and varies from
7 to @DD. AMI defaults to ..) but /7 clocks is a good place to start at CCM&=
"(hoeni3%. The shorter the value) the more rapid access to the bus a device
gets) with better response times) but the lower becomes the effective
bandwidth and hence data throughput. 1ormall!) leave this alone) but !ou
could set it to a lower value if !ou have latenc! sensitive cards "e.g. audio
cards and+or network cards with small buffers%. Increase slightl! if I+O
sensitive applications are being run.
• *sing I0S. Affected b! the Trigger method. <ith (CI) !ou assign I0Ss)
etc to a slot) rather than ad:usting the card) but onl! if the card needs an
I0S. There are two methods of I0S usage) Aevel or 8dge triggered "see
83pansion Cards%. Most (CI cards use the former) and ISA the latter.
• (CI Slot 3 I1T3. Assigns (CI I1TRs to slots 6+@+C "or whatever%. See
Slot 5 using I1TR) overleaf.
• 8dge+Aevel Select. (rograms (CI I0Ss to singleedge or logic
level. Aevel or 8dge sensitivit! is programmed per controller.
Select 8dge for (CI I$8.
• (CI $evice) Slot 6+@+C. 8nables I+O and memor! c!cle decoding.
• 8nable. As slave
• 8n Master. 8nables (CI device as bus master.
• *se $efault Aatenc! Timer 9alue. If !es) !ou don,t need Aatenc!
Timer "above%.
• Slot ) 6sin! I;TI. Selects an I1TR channel for a (CI Slot) and there are four
"A) B) C W $% for each one) that is) each (CI bus slot supports interrupts A) B)
C and $. RA is allocated automaticall!) and !ou would onl! use RB) RC) etc if
the card needs to use more than one "(CI% interrupt service. #or e3ample)
select R$ if !our card needs four. *sing Auto is simplest. Most graphics cards
don,t need this.
• )th ,%ailable I+G. Selects "or maps% an I0S for one of the available I1TRs
above. There are ten selections "C) /) D) .) I) F) 67) 66) 6@) 6/) 6D%. 6st available
I0S means the BIOS will assign this I0S to the first (CI slots "order is 6) @) C)
/%. 1A means the I0S has been assigned to the ISA bus and is therefore not
available to a (CI slot.
• @st2'th ,%ailable I+G. As above.
• PCI I+G ,cti%ated by. The method b! which the (CI bus recognises an I0S
re>uest- Aevel or 8dge "see 83pansion Cards%. *se the default unless advised
otherwise b! !our manufacturer or if !ou have a (CI device which onl!
recogni=es one of them.
• Confi!uration Mode. Sets the method b! which information about legac!
cards is conve!ed to the s!stem.
• *se IC*the BIOS depends on information provided b! (lug and (la!
software "e.g. Configuration Manager or ISA Configuration *tilit!%.
Onl! set this if !ou have the utilities concerned.
• *se Setup *tilit!. The BIOS depends on information provided b! !ou in
the following settings. $on,t use the above utilities.
• IS, Shared Memory Si0e. Sets a block of s!stem memor! which will not be
shadowed. Should be disabled) unless !ou have an ISA card that uses the upper
memor! area. If !ou use this setting !ou will also get the following'
• ISA Shared Memor! Base Address. If !ou choose ./;) !ou can onl!
choose $777 or below.
• I+G (2I+G @H. *sed to indicate what I0Ss are in use b! ISA Aegac! cards. If
not used) set to Available. Otherwise) set *sed b! ISA Card) which means that
nothing else can use it.
• PCI ID- Prefetch Buffers. $isables a set of prefetch buffers in the (CI I$8
controller. ?ou ma! need to do this with an operating s!stem "like 1T% that
doesn,t use the BIOS to access the hard disk and doesn,t disable interrupts
when completing a programmed I+O operation. $isabling also prevents errors
with fault! (CII$8 interface chips that can corrupt data on the hard disk "with
true C@bit operating s!stems%. Check if !ou,ve got a (CTech 0X6777 or a
CM$ (CIO ./7) but disabling is done automaticall! with later boards.
• PCI ID- #nd Channel. $isable this if !ou,re not using the @nd channel on the
(CI I$8 card) or !ou will lose I0S 6D on the ISA slots.
• PCI ID- I+G Map to. Allows !ou to configure !our s!stem to the t!pe of
I$8 disk controller- an ISA device is assumed. The more apparent difference is
the t!pe of slot being used. &owever) if !ou have a (CI I$8 controller) this
setting allows !ou to specif! which slot has the controller and which (CI I1TR
"A) B)C or $% is associated with the connected hard drives. 1ote that this refers
to the hard disk rather than individual partitions. Since each I$8 controller
supports two drives) !ou can select the I1TR for each. 1ote also that the
primar! has a lower interrupt than the secondar!) as described in Slot 3 *sing
I1TR.
• (CIAuto. If the I$8 is detected b! the BIOS on one of the (CI slots)
then the apropriate I1TR channel will be assigned to I0S 6/.
• (CISlot 5. If the I$8 is not detected) !oun can manuall! select the slot.
• (rimar! I$8 I1TR) Secondar! I$8 I1TR. Assigns @ I1T channels for
primar! and secondar! channels) if supported.
• ISA. Assigns no I0Ss to (CI slots. *se for (CI I$8 cards that connect
I0Ss 6/ and 6D directl! from an ISA slot using a table from a legac!
paddleboard.
• PCI Bus Parin!. Sort of bus mastering- a device parking on the (CI Bus has
full control of the bus for a short time. Improves performance when that device
is being used) but e3cludes others. Tr! with 1ICs and &ard $isk Controllers.
• ID- Buffer for DOS J .in. #or I$8 read ahead and posted write buffers) so
!ou can increase throughput to and from I$8 devices b! buffering reads and
writes. Slower I$8 devices could end up slower) though.
• ID- Master /Sla%e1 PIO Mode. Changes I$8 data transfer speed- Mode 7/)
or Auto. (IO means (rogrammed Input+Output. 0ather than have the BIOS
issue commands to effect transfers to or from the disk drive) (IO allows the
BIOS to tell the controller what it wants) and then lets the controller and the
C(* perform the complete task b! themselves. Modes 6/ are available.
• HC9? PCIC9?. &ost CA; vs (CI CA; divider- A*TO) 66) 66.D.
• PCI2IS, BC9? Di%ider. (CI Bus CA; vs ISA Bus CA; divider- A*TO)
(CICA;6+C) (CICA;6+@) (CICA;6+/.
• CP6 to PCI Byte Mer!e. See B!te Merging for e3planation "below%.
• PCI .rite2byte2Mer!e. <hen enabled) this allows data sent from the C(* to
the (CI bus to be held in a buffer. The chipset will then write the data in the
buffer to the (CI bus when appropriate.
• CP62to2PCI +ead Buffer. <hen enabled) up to four $words can be read
from the (CI bus without interrupting the C(*. <hen disabled) a write buffer
is not used and the C(* read c!cle will not be completed until the (CI bus
signals that it is read! to receive the data. The former is best for performance.
• PCI2to2CP6 .rite Buffer. See above.
• CP62to2PCI +ead29ine. <hen On) more time will be allocated for data setup
with faster C(*s. This ma! onl! be re>uired if !ou add an Intel Over$rive
processor to !our s!stem.
• CP62to2PCI +ead2Burst. <hen enabled) the (CI bus will interpret C(* read
c!cles as the (CI burst protocol) meaning that backtoback se>uential C(*
memor! read c!cles addressed to the (CI will be translated into fast (CI burst
memor! c!cles. (erformance is improved) but some nonstandard (CI adapters
"e.g. 9HA% ma! have problems.
• PCI to D+,M Buffer. Improves (CI to $0AM performance b! allowing
data to be stored if a destination is bus!.Buffers are needed because the (CI
bus is divorced from the C(*.
• 9atency for CP6 to PCI write. $ela! time before C(* writes data to the (CI
bus.
• PCI Cycle Cache Hit .S. Similar to above. <ith the latter) the C(* has less
to do) so performance is better.
• 1ormalCache refresh during normal (CI c!cles.
• #astCache refresh without (CI c!cle for CAS.
• 6se Default 9atency Timer 7alue. <hether or not the default value for the
Aatenc! Timer will be loaded) or the succeeding Aatenc! Timer 9alue will be
used. If ?es is selected "default%) no further programming is needed in the
Aatenc! Timer 9alue option "below%.
• 9atency Timer 7alue. The ma3imum number of (CI bus clocks that the
master ma! burst. A longer latenc! time gives the C(* more of a chance to
control the bus. See also Aatenc! Timer "(CI Clocks%.
• 9atency from ,DSI status. This allows !ou to configure how long the C(*
waits for the Address $ata Status "A$S%. It determines the C(* to (CI (ost
write speed. <hen set to CT) this is DT for each double word. <ith @T
"default%) it is /T per double word. #or a Sword (CI memor! write) the rate is
IT "@T% or BT "CT%. The default should be O;) but if !ou add a faster C(* to
!our s!stem) !ou ma! find it necessar! to increase it. The choices are'
• CTThree C(* clocks
• @TTwo C(* clocks "$efault%
• PCI Master 9atency. If !our (CI Master cards control the bus for too long)
there is less time for the C(* to control it. A longer latenc! time gives the
C(* more of a chance. $on,t use =ero.
• Max burstable ran!e. The ma3imum bursting length for each #0AM8R
asserting. #0AM8R is an electrical signal. $unno what it does) !et.
• CP6 to PCI burst memory write. If enabled) backtoback se>uential C(*
memor! write c!cles to (CI are translated to (CI burst memor! write c!cles.
Otherwise) each single write to (CI will have an associated #0AM8R
se>uence. 8nabled is best for performance) but some nonstandard (CI cards
"e.g. 9HA% ma! have problems.
• 3ast Bac To Bac. (ossibl! as above) but working on itP
• CP6 to PCI post memory write. 8nabling allows up to / $words of data to
be posted to (CI. Otherwise) not onl! is buffering disabled) completion of
C(* writes is limited "e.g. C(* write does not complete until the (CI
transaction completes%. 8nabled is best for performance.
• CP6 to PCI .rite Buffer. As above. Buffers are needed because the (CI bus
is divorced from the C(*- the! improve overall s!stem performance b!
allowing the processor "or bus master% to do what it needs without writing data
to its final destination- the data is temporaril! stored in fast buffers.
• PCI to IS, .rite Buffer. <hen enabled) the s!stem will temporaril! write
data to a buffer so the C(* is not interrupted. <hen disabled) the memor!
write c!cle for the (CI bus will be direct to the slower ISA bus. The former is
best for performance.
• DM, 9ine Buffer. Allows $MA data to be stored in a buffer so (CI bus
operations are not interrupted. $isabled means that the line buffer for $MA is
in single transaction mode. 8nabled allows it to operate in an Bb!te
transaction mode for greater efficienc!.
• IS, Master 9ine Buffer. ISA master buffers are designed to isolate the slower
ISA I+O operations from the (CI bus for better performance. $isabled means
the buffer for ISA master transaction is in single mode. 8nabled means it is in
Bb!te mode) increasing the ISA master,s performance.
• CP68PCI Post .rite Delay. $ela! time before the C(* writes data into the
(CI bus.
• Post .rite C,S ,cti%e. (ulse width of CASR when the (CI master writes to
$0AM.
• PCI master accesses shadow +,M. 8nables the shadowing of a 0OM on a
(CI master for better performance.
• -nable Master. 8nables the selected device as a (CI bus master and checks
whether the card is so capable.
• ,T bus cloc freDuency. AT bus speed in a (CI s!stem. Choose whatever
divisor gives !ou a speed of .B.CC M&=) depending on the speed of the (CI
bus.
• IS, Bus Cloc 3reDuency. As above.
• Base I8O ,ddress. The base of the I+O address range from which the (CI
device resource re>uests are satisfied.
• Base Memory ,ddress. The base of the C@bit memor! address range from
which the (CI device resource re>uests are satisfied.
• Parity. Allows parit! checking of (CI devices.
• IS, 9inear 3rame Buffer. Set to the appropriate si=e if !ou use an ISA card
that features a linear frame buffer "e.g. a second video card for ACA$%. The
address will be set automaticall!.
• IS, 7F, 3rame Buffer Si0e. This is to help !ou use a 9HA frame buffer and
6. Mb of 0AM at the same time- the s!stem will allow access to the graphics
card through a hole in its own memor! map- in other words) accesses made to
addresses within this hole will be directed to the ISA bus instead of main
memor!. Should be set to $isabled) unless !ou are using an ISA card with
more than ./; of memor! that needs to be accessed b! the C(*) and !ou are
not using the (lug and (la! utilities. If !ou have less than B Mb memor!) or
use MS$OS) this will be ignored.
• +esidence of 7F, Card. <hether on (CI or 9A Bus.
• IS, 93B Si0e. A#BKAinear #rame Buffer. See above.
• Memory Map HoleK Memory Map Hole Start8-nd ,ddress. See ISA 9HA
#rame Buffer Si=e. <here the hole starts depends on ISA A#B Si=e.
Sometimes this is informative onl!. If !ou can change it) base address should
be 6.Mb) less buffer si=e.
• Memory Hole Si0e. Options include 6 Mb) @ Mb) / Mb) B Mb) $isabled.
These are the amounts below 6 Mb assigned to the AT Bus) and reserved for
ISA cards.
• Memory Hole Start ,ddress. To improve performance) certain parts of
memor! are reserved for ISA cards) which must be mapped into the memor!
space below 6. MB for $MA reasons. The selections are from 66D with each
number in Mb. This is irrelevant if the memor! hole is disabled "see above%.
• Memory Hole at @H2@'M. See above.
• 9ocal Memory @H2@'M. To increase performance) !ou can map slower device
memor! "e.g. on the ISA bus% into much faster local bus memor!. Aocal
memor! is set aside and the start point transferred from the device memor! to
local memor!. The default is enabled.
• @H2@'M Memory 9ocation. The area in the memor! map allocated for ISA
option 0OMs. Choices are Aocal "default% or 1onlocal.
• Byte Mer!in!. This e3ists where writes to se>uential memor! addresses are
merged into one (CItomemor! operation) which increases performance for
older applications that write to video memor! in b!tes rather than wordsnot
supported on all (CI video cards. 8nable unless !ou get bad graphics. See also
ne3t for a variation.
• Byte Mer!e Support. B or 6.bit data en route from the C(* to the (CI bus
is held in a buffer where it is accumulated) or merged) into C@bit data) giving
faster performance. In this case) enabling means that C(*(CI writes are
buffered "Award%.
• Multimedia Mode. 8nables or disables palette snooping for multimedia cards.
• 7ideo Palette Snoop. Controls how a (CI graphics card can 4snoop4 write
c!cles to an ISA video card,s colour palette registers. Snooping essentiall!
means interfereing with a device.Onl! set to $isabled if'
• An ISA card connects to a (CI graphics card through a 98SA connector
• The ISA card connects to a colour monitor) and
• The ISA card uses the 0AM$AC on the (CI card) and
• (alette Snooping "0AM$AC shadowing% not operative on (CI card.
• PCI87F, Palette Snoop. Alters the 9HA palette setting while graphic signals
pass through the feature connector of (CI 9HA card and are processed b!
M(8H card. 8nable if !ou have M(8H connections through the 9HA feature
connector- this means !ou can ad:ust (CI+9HA palettes. 9HA snooping is
used b! multimedia video devices "e.g. video capture boards% to look ahead at
the video controller "9HA device% to see what color palette is currentl! in use.
It is onl! in e3ceptional circumstances that !ou might ever need to enable this)
so disable for ordinar! s!stems. "Award BIOS%.
• Snoop 3ilter. Saves the need for multiple en>uiries to the same line if it was
in>uired previousl!. <hen enabled) cache snoop filters ensure data integrit!
"cache coherenc!% while reducing the snoop fre>uenc! to a minimum.
• -&$$$ (#? ,ccessible. The ./; 8 area of upper memor! is used for BIOS
purposes on (S+@s) C@ bit operating s!stems and (lug and (la!. This setting
allows the second C@; page to be used for other purposes when not needed) in
the same wa! that the first C@; page of the # range is useable after boot up has
finished.
• PH Piped ,ddress. $efault is $isabled
• PCI ,rbiter Mode. $evices gain access to the (CI bus through arbitration.
There are two modes) 6 "the default% and @. The idea is to minimi=e the time it
takes to gain control of the bus and move data. Henerall!) Mode 6 should be
sufficient) but tr! mode @ if !ou get problems.
• Stop CP6 .hen 3lush ,ssert. See below.
• Stop CP6 when PCI 3lush. <hen enabled) the C(* will be stopped when
the (CI bus is being flushed of data. $isabling "default% allows the C(* to
continue processing) giving greater efficienc!.
• Stop CP6 at PCI Master. <hen enabled) the C(* will be stopped when the
(CI bus master is operating on the bus. $isabling "default% allows the C(* to
carr! on) giving greater efficienc!.
• I8O Cycle +eco%ery. <hen enabled) the (CI will be allowed a recover! period
for backtoback I+O) which slows backtoback data transfers- it,s like adding
wait states) so disable "default% for best performance.
• I8O +eco%ery Period. Sets the length of time of the recover! c!cle used
above. The range is from 76.ID microseconds in 7.@D microsecond intervals.
• ,ction .hen .LBuffer 3ull. Sets the behaviour of the s!stem when the write
buffer is full. B! default the s!stem will immediatel! retr!) rather than wait for
it to be emptied.
• 3ast Bac2to2Bac. <hen enabled) the (CI bus will interpret C(* read c!cles
as the (CI burst protocol) meaning that backtoback se>uential C(* memor!
read c!cles addressed to the (CI will be translated into the fast (CI burst
memor! c!cles. $efault is enabled.
• CP6 Pipelined 3unction. This allows the s!stem controller to signal the C(*
for a new memor! address) even before all data transfers for the current c!cle
are complete) resulting in increased throughput. The default is $isabled) that
is) pipelining off.
• Primary 3rame Buffer. <hen enabled) this allows the s!stem to use
unreserved memor! as a primar! frame buffer. *nlike the 9HA frame buffer)
this would reduce overall available 0AM for applications.
• M@**H+D"< to CP6+D"<. <hether the (CI 0ead! signal is to be
s!nchroni=ed b! the C(* clock,s read! signal or b!passed "default%.
• 7-S, Master Cycle ,DS<. Allows !ou to increase the length of time the
98SA Master has to decode bus commands. Choices are 1ormal "default% and
Aong.
• 9D-7< Chec Point Delay. This allows !ou to select how much time is
allocated for checking bus c!cle comands. These commands must be decoded
to determine whether a local bus device access signal "A$89G% is being sent)
or an ISA device is being addressed. Increasing the dela! increases stabilit!)
especiall! the 98SA subs!stem while ver! slightl! degrading the
performance of the ISA subs!stem. Settings are in terms of the feedback clock
rate "#BCA;@% used in the cache+memor! control interface.
1 FBCLK2=One clock
2 FBCLK2=Two clocks (Default)
3 FBCLK2=Three clocks
• CP6 Dynamic23ast2Cycle. Hives !ou faster access to the ISA bus. <hen the
C(* issues a bus c!cle) the (CI bus e3amines the command to determine if a
(CI agent claims it. If not) then an ISA bus c!cle is initiated. The $!namic
#astAccess then allows for faster access to the ISA bus b! decreasing the
latenc! "or dela!% between the original C(* command and the beginning of
the ISA c!cle.
• CP6 Memory sample point. This allows !ou to select the c!cle check point)
which is where memor! decoding and cache hit+miss checking takes place.
8ach selection indicates that the check takes place at the end of a C(* c!cle)
with one wait state indicating more time for checking to take place than =ero
wait states. A longer check time allows for greater stabilit! at the e3pense of
some speed.
• 9D-7I Chec point. The 98SA local device "A$89R% check point is where
the 9Abus device decodes the bus commands and error checks) within the bus
c!cle itself.
0 Bus cycle o!nt T1 (Default)
1 Dur!n" the f!rst T2
2 Dur!n" secon# T2
3 Dur!n" th!r# T2
• 9ocal memory chec point. Allows !ou to select between two techni>ues for
decoding and error checking local bus writes to $0AM during a memor!
c!cle.
• SlowK83tra wait state- better checking "default%.
• #astK1o e3tra wait state used.
• 3+,M-< !eneration. <hen the (CI9A bus bridge is acting as a (CI Master
and receiving data from the C(*) a fast C(*to(CI buffer will be enabled if
this selection is also enabled. *sing the buffer allows the C(* to complete a
write even though the data has not been delivered to the (CI bus. This reduces
the number of C(* c!cles involved and speeds overall processing.
• 1ormal Buffering not emplo!ed "$efault%
• #ast Buffer used for C(*to(CI writes.
• PCI to CP6 .rite Pendin!. Sets the behaviour of the s!stem when the write
buffer is full. B! default) the s!stem will immediatel! retr!) but !ou can set it
to wait for the buffer to be emptied before retr!ing.
• Delay for SCSI8HDD /Secs1. The length of time in seconds the BIOS will
wait for the SCSI hard disk to be read! for operation. If the hard drive is not
read!) the (CI SCSI BIOS might not detect the hard drive correctl!. The range
is from 7.7 seconds.
• Master IOCH+D". 8nabled) allows the s!stem to monitor for a 98SA
master re>uest to generate an I+O channel read! "IOC&0$?% signal.
• 7F, Type. This data is used when the video bios is being shadowed. The
BIOS uses this information to determine which bus to use. Choices are
Standard "default%) (CI) ISA+98SA.
• PCI Mstr Timin! Mode. This s!stem supports two timing modes) 7 "default%
and 6.
• PCI ,rbit4 +otate Priority. T!picall!) the s!stem manages or arbitrates access
to the (CI bus on a firstcomefirstserved basis. <hen priorit! is rotated) once
a device gains control of the bus it is assigned the lowest priorit! and ever!
other device is moved up one in the priorit! >ueue.
• I8O Cycle Post2.rite. <hen 8nabled "default%) data being written during an
I+O c!cle will be buffered for faster performance.
• PCI Post2.rite 3ast. As in the above I+O C!cle (ost<rite) enabling this will
allow the s!stem to use a fast memor! buffer for writes to the (CI bus.
• CP6 Mstr Post2.+ Buffer. <hen the C(* operates as a bus master for
either memor! access or I+O) this item controls its use of a high speed posted
write buffer. Choices are 1A) 6) @ and / "default%.
• CP6 Mstr Post2.+ Burst Mode. <hen the C(* operates as a bus master for
either memor! access or I+O) this item controls its abilit! to use a high speed
burst mode for posted writes to a buffer.
• CP6 Mstr 3ast Interface. This enables+disables what is known as a fast back
toback interface when the C(* operates as a bus master. <hen enabled)
consecutive reads+writes are interpreted as the C(* highperformance burst
mode.
• PCI Mstr Post2.+ Buffer. <hen a (CI device operates as a bus master for
either memor! access or I+O) this item controls its use of a high speed posted
write buffer. Choices are 1A) 6) @ and / "default%.
• PCI Mstr Burst Mode. <hen a (CI device operates as a bus master for either
memor! access or I+O) this item controls its abilit! to use a high speed burst
mode for posted writes to a buffer.
• PCI Mstr 3ast Interface. This enables+disables what is known as a fast back
toback interface when a (CI device operates as a bus master. <hen enabled)
consecutive reads+writes are interpreted as the (CI highperformance burst
mode.
• CP6 Mstr D-7S-9I Time2out. <hen the C(* initiates a master c!cle using
an address "target% which has not been mapped to (CI+98SA or ISA space) the
s!stem will monitor the $89S8A "device select% pin for a period of time to see
if an! device claims the c!cle. This item allows !ou to determine how long the
s!stem will wait before timingout. Choices are C (CICA;) / (CICA;) D
(CICA; and . (CICA; "default%.
• PCI Mstr D-7S-9I Time2out. <hen a (CI device initiates a master c!cle
using an address "target% which has not been mapped to (CI+98SA or ISA
space) the s!stem will monitor the $89S8A "device select% pin for a period of
time to see if an! device claims the c!cle. This item allows !ou to determine
how long the s!stem will wait before timingout. Choices are C (CICA;) /
(CICA; "default%) D (CICA; and . (CICA;.
• I+G 9ine. If !ou have installed a device re>uiring an I0S service into the
given (CI slot) use this item to inform the (CI bus which I0S it should
initiate. Choices range from I0S C through I0S 6D.
• 3ast Bac2to2Bac Cycle. <hen enabled) the (CI bus will interpret C(* read
or write c!cles as (CI burst protocol) meaning that backtoback se>uential
C(* memor! read+write c!cles addressed to the (CI will be translated into fast
(CI burst memor! c!cles.
• State Machines. The chipset uses four state machines to manage specific C(*
and+or (CI operations. 8ach can be thought of as a highl! optimi=ed process
center designed to handle specific operations. Henerall!) each operation
involves a master device and the bus it wishes to emplo!. The four state
machines are'
C$% &aster to C$% 'us (CC)
C$% &aster to $C( 'us (C$)
$C( &aster to $C( 'us ($$)
$C( &aster to C$% 'us ($C)
• 8ach have the following settings'
• Address 7 <S. This refers to the length of time the s!stem will dela!
while the transaction address is decoded. 8nabledKno dela!.
• $ata <rite 7 <S. The length of time the s!stem will dela! while data is
being written to the target address. <hen 8nabled) there will be no dela!.
• $ata 0ead 7 <S. The length of time the s!stem will dela! while data is
being read from the target address. <hen 8nabled) there will be no dela!.
• On Board PCI8SCSI BIOS. ?ou would enable this if !our s!stem
motherboard had a builtin SCSI controller attached to the (CI bus) and !ou
wanted to boot from it.
• PCI I8O Start ,ddress. I+O devices make themselves accessible b! occup!ing
an address space. This allows !ou to make additional room for older ISA
devices b! defining the I+O start address for the (CI devices.
• Memory Start ,ddress. This is for devices with their own memor! which use
part of the C(*,s memor! address space) allowing !ou to determine the
starting point in memor! where (CI device memor! will be mapped.
• 7F, @#& +an!e ,ttribute. <hen enabled) this allows the chipset to appl!
features like C(*TO(CI B!te Merge) C(*TO(CI (refetch to be applied to
9HA memor! range A7777&B####&.
• 8nabledK9HA receives C(*TO(CI functions.
• $isabledK0etain standard 9HA interface.
• CP62To2PCI .rite Postin!. The Orion chipset maintains its own internal
read and write buffers which are used to help compensate for the speed
differences between the C(* and the (CI bus. <hen this is 8nabled) writes
from the C(* to the (CI bus will be buffered. <hen $isabled "default%) the
writes will not be buffered and the C(* will be forced to wait until the write is
completed.
• CP6 +ead Multiple Prefetch. A prefetch occurs during a process "e.g.
reading from the (CI or memor!% when the chipset peeks at the ne3t
instruction and actuall! begins the ne3t read. The Orion chipset has four read
lines. A multiple prefetch means the chipset can initiate more than one prefetch
during a process. $efault is $isabled.
• CP6 9ine +ead Multiple. A line read means that the C(* is reading a full
cache line. <hen a cache line is full it holds C@ b!tes "eight $<O0$S% of
data. Because the line is full) the s!stem knows e3actl! how much data it will
be reading and doesn,t need to wait for an endofdata signal) freeing it to do
other things. <hen this is enabled) the s!stem is allowed to read more than one
full cache line at a time. The default is disabled.
• CP6 9ine +ead Prefetch. See above. <hen this is enabled) the s!stem is
allowed to prefetch the ne3t read instruction and initiate the ne3t process.
• CP6 9ine +ead. This 8nables or $isables "default% full C(* line reads.
• CP6 Burst .rite ,ssembly. The "Orion% chipset maintains four posted write
buffers. <hen this is enabled) the chipset can assemble long (CI bursts from
the data held in them. $efault is $isabled.
• 7F, Performance Mode. If enabled) the 9HA memor! range of A 7777B
7777 will use a special set of performance features. This has little or no effect
using video modes be!ond the standard 9HA most commonl! used for
<indows) OS+@) *1I5) etc) but this memor! range is heavil! used b! games
such as $OOM.
• Snoop ,head. This is onl! applicable if the cache is enabled. <hen enabled)
(CI bus masters can monitor the 9HA palette registers for direct writes and
translate them into (CI burst protocol for greater speed) to enhance the
performance of multimedia video.
• DM, 9ine Buffer Mode. This allows $MA data to be stored in a buffer so as
not to interrupt the (CI bus. <hen Standard is selected) the line buffer is in
single transaction mode. 8nhanced allows it to operate in Bb!te transaction
mode.
• Master ,rbitration Protocol. This is the method b! which the (CI bus
determines which bus master device gains access to it.
• PCI Cloc 3reDuency. Allows !ou to set the clock rate for the (CI bus) which
can operate between 7CC Mh=. C(*CA;+C means the (CI bus was operating
at 66 Mh= "CC+C K 66%.
C$%CLK)1*+ C$% see# ) 1*+ (Default)
C$%CLK)3 C$% see#)3
1, -h. 1, -h.
C$%CLK)2 C$% see#)2
• MaxE Burstable +an!e. Sets the si=e of the ma3imum range of contiguous
memor! which can be addressed b! a burst from the (CI bus) a half or one ;.
• IS, Bus Cloc 3reDuency. Allows !ou to set the speed of the ISA bus in
fractions of the (CI bus speed) so if the (CI bus is operating at its theoretical
ma3imum) CC Mh=) (CICA;+C would !ield an ISA speed of 66 Mh=.
/*1+0 -h. (#efault)
$C(CLK), 1 2uarter see# of the $C( 'us
$C(CLK)3 One th!r# see# of the $C( 'us
• & Bit I8O +eco%ery Time. The recover! time is the length of time) measured
in C(* clocks) which the s!stem will dela! after the completion of an
input+output re>uest to the ISA bus) needed because the C(* is running faster
than the bus) and needs to be slowed down. Clock c!cles are added to a
minimum dela! "usuall! D% between (CIoriginated I+O c!cles to the ISA bus.
Choices are from 6 to I or B C(* clocks. 6 is the default.
• @' Bit I8O +eco%ery Time. As above) for 6. bit I+O. Choices are from 6 to /
C(* clocks. 6 is the default.
• I8O +eco%ery Time. A programmed dela! which allows the (CI bus to
e3change data with the slower ISA bus without data errors. Settings are in
fractions of the (CI BCA'
2 BCLK=Two BCLK3 (#efault)
, BCLK=Four BCLK3
4 BCLK=5!"ht BCLK3
12 BCLK=Twel6e BCLK3
• PCI Concurrency. 8nabled "default% means that more than one (CI device
can be active at a time "Award%. <ith Intel Chipsets) it allocates memor! bus
c!cles to a (CI controller while an ISA operation) such as bus mastered $MA)
is taking place) which normall! re>uires constant attention. This involves
turning on additional read and write buffering in the chipset. The (CI bus can
also obtain access c!cles for small data transfers without the dela!s caused b!
renegotiatiating bus access for each part of the transfer) so is meant to improve
performance and consistenc!.
• PCI Streamin!. $ata is t!picall! moved to and from memor! and between
devices in discrete chunks of limited si=es) because the C(* is involved. On
the (CI bus) data can be streamed) that is) much larger chunks can be moved
without the C(* being bothered. 8nable for best performance.
• PCI Burstin!. Consecutive writes from C(* will be regarded as a (CI Burst
c!cle. 8nable K best performance- some cards might not like it.
• PCI /ID-1 Burstin!. As above) but this one enables burst mode access to
video memor! over the (CI bus. The C(* provides the first address) and
consecutive data is transferred at one word per clock. The device must support
burst mode.
• Burst Copy2Bac Option. <hen enabled) if a cache miss occurs) the chipset
will initiate a second) burst cache line fill from main memor! to the cache) the
ob:ect being to maintain the status of the cache.
• Preempt PCI Master Option. <hen enabled) (CI bus operations can be
preempted b! certain s!stem operations) such as $0AM refresh) etc.
Otherwise) the! can take place concurrentl!.
• IBC D-7S-9I Decodin!. Allows !ou to set the t!pe of decoding used b! the
ISA Bridge Controller "IBC% to determine which device to select. The longer
the decoding c!cle) the better chance the IBC has to correctl! decode the
commands. Choices are #ast) Medium and Slow "default%.
• ?eyboard Controller Cloc. Sets the speed of the ke!board controller
"(CICA;I K (CI bus speed%.
/*17 -h. Default
$C(CLK()2 1)2 $C(CLK(
$C(CLK()3 1)3 $C(CLK(
$C(CLK(), 1), $C(CLK(
• CP6 Pipeline 3unction. This allows the s!stem controller to signal the C(*
for a new memor! address even before all data transfers for the current c!cle
are complete) resulting in increased throughput. 8nabled means that address
pipelining is active.
• PCI Dynamic Decodin!. <hen enabled) this setting allows the s!stem to
remember the (CI command which has :ust been re>uested. If subse>uent
commands fall within the same address space) the c!cle will be automaticall!
interpreted as a (CI command.
• Master +etry Timer. This sets how long the C(* master will attempt a (CI
c!cle before the c!cle is unmasked "terminated%. The choices are measured in
(CICA;s which the (CI timer. 9alues are 67 "default%) 6B) C/ or .. (CICA;s.
• PCI Pre2Snoop. (resnooping is a techni>ue b! which a (CI master can
continue to burst to the local memor! until a /; page boundar! is reached
rather than :ust a line boundar!.
• CP68PCI .rite Phase. $etermines the turnaround between the address and
data phases of the C(* master to (CI slave writes. Choices are 6 ACA;
"default% or 7 ACA;.
• PCI Preempt Timer. This item sets the length of time before one (CI master
preempts another when a service re>uest has been pending.
D!sa'le# 8o ree&t!on (#efault)*
270 LCLKs $ree&t after 270 LCLKs
132 LCLKs $ree&t after 132 LCLKs
74 LCLKs $ree&t after 74 LCLKs
37 LCLKs $ree&t after 37 LCLKs
20 LCLKs $ree&t after 20 LCLKs
12 LCLKs $ree&t after 12 LCLKs
+ LCLKs $ree&t after + LCLKs
• CP6 to PCI POST8B6+ST. $ata from the C(* to the (CI bus can be posted
"buffered b! the controller% and+or burst. This sets the methods.
• (OST+CO1.B*0ST. (osting and bursting supported "default%.
• 1O18+1O18. 1either supported.
• (OST+1O18. (osting but not bursting supported.
• PCI C9?. <hether the (CI clock is tightl! s!nchroni=ed with the C(* clock)
or is as!nchronous. If !our C(*) motherboard and (CI bus are running at
multiple speeds of each other) e.g. (entium 6@7) .7 M&= m+b and C7 M&= (CI
bus) choose s!nchronise.
• I+G @H +outin! Selection. MISAKMultiple3ed ISA for as!nchronousl!
interrupting the C(*. I0S 6D is usuall! used for Secondar! I$8 channels or
C$0OMs.
• CP6 cycle cache hit same point. <orking on this.
• PCI cycle cache hit sam point. As above.
• ,rbiter timer timeout /PCI C9?1 # x (#. <orking on this.
Hard Dis 6tility
• &ard disk format
• Auto detect hard disk
• Auto interleave
• Media anal!sis
Hard Dis 3ormat
<ill format !our hard disk so it can receive new partitions.
IT .I99 SM,SH -7-+"THI;F O; "O6+ H,+D DIS?OOO 6S- .ITH
C,6TIO;4 A lot of ine3perienced users have lost their sanit! with this one.
Several computer stores have made e3tra mone! with itP There,s no need to do
this unless !ou e3perience errors or if !ou want to change the interleave. DO;QT
TO6CH THIS I3 "O6 H,7- ,; ID- D+I7-. It will perform a low level
format and probabl! SC0A( !our I$8 hard drive. I$8 is the standard drive t!pe
that nearl! ever!one has now. SCSI or 8S$I drives shouldn,t be lowlevel
formatted. The new drives actuall! don,t perform the low level format) but some
old ATBus "I$8% drives !ou can scratch with this... This entr! is onl! sensible for
old M#M or 0AA hard disksP (lease refer to !our hard disk manual to see how or
if !our hard disk can be low level formatted. $on,t tell us we did not warn !ou.
Man! manufacturers provide utilities to low level format their I$8 drives "or an!
other t!pes%. (lease refer to the comp.s!s.ibm.pc.hardware.storage #AS for more
technical information about this procedure. If normal "high level% hard disk
formatting is re>uired) !ou can use $OS #$IS; to first erase and create
partitions and then use #O0MAT. It is also a good idea when !ou hard disk
becomes inaccessible to see if it is :ust the s!stem files that are corrupted. Most of
the time) it is the case. S?S will do the :ob of replacing s!stem files. Several
packages "(CTools) 1orton) etc.% provide utilities for repairing 4damaged4 &$$
and #$$. Therefore) low level format is alwa!s of AAST 08SO0T when !ou
encounter &$$ problems.
,uto Detect Hard Dis
&and! when !ou 4forgot4 the specs of !our hard drive. The BIOS will detect the
number of c!linders) heads and sectors on !our hard disk. In some BIOS
versions) this option in the main S8T*( menu.
,uto Interlea%e
$etermines the optimum interleave factor for older hard disks. Some controllers
are faster than others) and !ou don,t want the sectors laid out so reading
consecutive sectors usuall! results in :ust missing the sector !ou wanted and
having to wait a whole disk rotation for it to come around again. On modern ones)
it,s alwa!s 6'6 "and even if it wasn,t) !ou cannot reformat an!wa!%.
Interleaving is specified in a ratio) n'6) for small positive integers n. Basicall!) it
means that the ne3t sector on the track is located n positions after the current
sector. The idea is that data on a hard drive might spin past the heads faster than
the adapter can feed it to the host. If it takes !ou more than a certain amount of
time to read a sector) b! the time !ou,re read! for the ne3t sector) the heads will
have passed it alread!. If this is the case) the interleave is said to be 4too tight4.
The converse) where the C(* spends more time than necessar! waiting for the
ne3t sector to spin under the heads) is too 4loose4 of an interleave. Clearl!) it is
better to have too loose an interleave than too tight) but the proper interleave is
better still. 8speciall! since an! controller with readahead cacheing can pull the
whole track into its buffer) no matter how slow the C(* is about fetching the data
down.
The 6'6 interleave arranges the sectors on a track as follows'
7 6 @ C / D . I B F a b c d e f g "6Isectors) using base 6I for convenience) this is
clearl! the inorder arrangement) one after another%
This is @'6 interleaving'
7 F 6 a @ b C c / d D e . f I g B
The C(* has a whole sector,s worth of time to get the a sector,s data taken care of
before the ne3t sector arrives. It shows which logical sector goes in each ph!sical
sector.
An!wa!) an n'6 interleave restricts the transfer rate to 6+n the speed of a 6'6
interleave "which is better than 6 revolution per sector if the interleave is too
tightP%. 1o modern (C should re>uire interleaving. Onl! M#M and 0AA "ma!be
also 8S$I% and flopp! drives which are capable of it "!ou could format a 6.//
meg flopp! to @6 sectors+track) which would re>uire a @'6 interleave to not
e3ceed the D77 mbps speed of the controller...but wh!O%.
Media ,nalysis
Scan the hard disk for bad blocks. It is performing a 9O. 9-7-9 3O+M,T
on the track where bad sector is encountered to mark that sector as a bad. It could
cause damage on user data) even if scanning itself is nondestructive "also on
M#M) 0AA disks%. Therefore) DO;QT 6S- this option to on ATBus "I$8%) SCSI
or 8S$I drives. These drives store the bad block data themselves) so !ou don,t
have to tell them or scan the mediaP 0ecommendation' use a media anal!sis
program provided b! an utilit! package or !our hard drive manufacturer.
Power Mana!ement
This menu appears on computers having the 4Freen PC4 specification) an
initiative of the 8(A "8nvironmental (rotection Agenc! of the *nited States% with
its 8nerg! Star program. The main purpose is to minimi=e power usage when the
s!stem sta!s inactive for a while. The standard is still not !et achieved among
manufacturers) so e3pect to see several variations. On most cases) the power
management strategies are incremental) meaning that the longer a s!stem sta!s
inactive) the more parts will close down.
There e3ists three power management schemes' ,PM "Advanced (ower
Management% proposed b! Intel and Microsoft. ,T, "AT Attachment% for I$8
drives. DPMS "$ispla! (ower Management Signaling% matches video monitors
and video cards so the! ma! simultaneousl! shut down.
• Freen Timer of Main Board' Allows to setup the time after which the C(*
of an idle s!stem will shut down. $isabled or a time interval ranging from 6 to
6D minutes are the usual options. D to 67 minutes recommended.
• Do0e Timer' Amount of time before the s!stem will reduce B7N of its activit!.
• Standby Timer' Amount of time before the s!stem will reduce F@N of its
activit!.
• Suspend Timer' Amount of time after the s!stem goes in the most inactive
state possible) which is FFN. After this state) the s!stem will re>uire a warm up
period so the C(*) hard disk and monitor ma! go online.
• HDD Standby Timer' Allows to setup the time after which the hard disk of an
&&$ idle s!stem "no &$$ access% will shut down. A terrific option if !ou
have a somewhat nois! hard drive unit. The choice of a time interval depends
on how hard disk intensive is !our operating s!stem. This ma! depends also on
the amount of memor! available. ?ou should setup a longer time interval) like
67 minutes) if !ou onl! have BMB of 0AM and running OS+@ or <indows. #or
a plain+standard $OS environments) @ to D minutes are recommended. If !ou
have a comfortable 6. MB or more) the time lapse can be shorter. There are
some reports that this option ma! cause problems with slave hard drives "AMI
BIOS onl!O%.
• System Slow Down. After the specified time interval) the C(* will slowed
down to B M&=.
3reDuently ,sed Guestions
• <hat are the best BIOS settings for m! computerO
• &ow do I clear the BIOS memor!O
• Can I upgrade m! BIOSO
.hat are the best BIOS settin!s for my computerP
See Basic optimi=ation tricks and Important settings.
How do I clear the BIOS memoryP
Three alternatives are available depending of !our t!pe of motherboard'
• 8nter BIOS Setup and change to settings to (owerOn $efaults.
• $isconnect the batter!.
• Insert appropriate :umper an wait until the BIOS memor! is cleared "see
mainboard documentation) the :umper is often located near the batter!%.
Sometimes this is possible with $I( switches on the motherboard. Sometimes "if
not%) !ou will have to remove the batter!. And sometimes "if no $I(,s and no
removable batter!) and not willing to desolder the batter!%) !ou can short the
batter! with a resistor to lower the current available for the CMOS.
This is onl! recommendable as a ver! last option. The 1iCad cells often
emplo!ed have a ver! low internal resistance) so the resistor will have to be of a
ver! low value for the voltage to drop significantl!. The corresponding current
would be >uite high) which is not ver! good for batter! life. A better option would
be to use a resistor to discharge the batter!. Obviousl!) this onl! makes sense
when !ou have a 1iCad cell "which will be recharged ever! time !ou turn the
computer on% as opposed to a lithium cell "which cannot be recharged%. In the
former case) a resistor of CF Ohm will discharge the batter! in under half an hour
relativel! safel!.
Another good wa! to discharge the 1iCad is to put a . volt lantern lamp across it)
and let it discharge completel!. 1ot onl! does it provide an effective load) it also
gives a visual indication of the charge state. It,s a good wa! to prevent 4ghost
memor!4 that,s so common to 1iCads. Metal 1ickel &!dride batteries are now
being seen in some s!stems. The! don,t have this problem and the! are more EE.
Can I up!rade my BIOSP
Most BIOSes are specificall! designed for a motherboard and its chipset.
Therefore) on rare occasions !ou can upgrade !our BIOS for a newer version. It is
often less troublesome to buy a new motherboard that comes with its own
BIOS and transfer your CP6 "memor!) cache memor! and adaptor cards...%
than start hunting around for a new BIOS chip. I know ver! few computer stores
who sell BIOS chips separatel!. &owever) it is possible to upgrade !our BIOS so
it ma! support new hardware. B! browsing in computer maga=ines "like
Computer Shopper) (C Maga=ine) etc.% !ou will find adds on companies that
speciali=e on that sort of thing. The information the! need is the Serial 1umber
for the BIOS chip. It is the lon! number that prints out when !ou boot up. It
includes the BIOS date) the chipset) etc. The price tag can var! greatl! "from E67
to EB7%) so are the BIOS upgrades offered.
The most important condition is that the mainboard should be as 4clean4 as
possible) that is' a genuine clone with not too much I+O integration or better none
at all. B@CI66 Combo I+O) (CBIC67 Super I+O and some other I+O chips are
supported in most cases. #ailures to BIOS upgrades are mainl! due to the wa! of
implementation of the ke!board controller on the mainboard or special revisions
of AMI BIOSes) such as the ;B revisions 7) M or $. Because the BIOS is put
into a #lash 8(0OM now) upgrades can be done ver! easil!. Most MB designers
have upgrades available at their <<< sites. There,s even a compan! which has
,shareware, BIOS for man! MB,s based on the intel Triton famil! of chipsets
"http'++www.mrbios.com%.
$oes an!one have supplementar! information on this) like goodbad e3periences
with BIOS upgradeO Aet me know. <e had several feedbacks) some positive)
other negative. Once again) we recommend to buy a new motherboard instead
of up!radin! BIOS.