Code No: C0502, C4002, C5802
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech I SEMESTER EXAMINATIONS, APRIL/MAY-2013
COMPUTER SYSTEM DESIGN
(COMMON TO COMPUTER SCIENCE, INFORMATION TECHNOLOGY,
COMPUTER SCIENCE AND ENGINEERING)
Time: 3hours
Max.Marks:60
Answer any five questions
All questions carry equal marks
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Q6
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1.a)
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b)
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2.a)
b)
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3.a)
b)
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4.a)
b)
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5.a)
b)
Q6
Write the features of Von-Newman architecture and differentiate with Harvard
architecture.
Explain how the control and data path is implemented in IA-32 Pentium.
Q6
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What are data hazards and instruction hazards? Explain.
Identify the RAW hazard for the following sequence of instructions where
r1, r2, r3… are registers and I1, I2 …
I1: add r1, r2, r3
(r1 = r2 + r3)
I2: sub r4, r5, r1
I3: mul r2, r6, r4
Q6
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D
L
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R
O
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Explain the Belady’s anamoly. Which page replacement algorithm leads to
Belady’s anamoly?
Describe the 2-way set associative mapping method in cache memory
organization.
Q6
W
U
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T
N
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J
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Describe the directory structure in Unix file systems.
Distinguish between the single-cycle and multi-cycle implementation in RISC
architectures.
List the functions of device drivers. Explain.
Write an assembly language instructions to perform logical and relational
Operations with examples.
7.a)
b)
Explain the concepts of content addressable memory.
Describe the inter process communication using monitors.
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8.
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Define process and thread. Write the structure and usage of thread control
block?
What are P and V operations? Explain how these operations resolves IPC
problem.