Objectives:
1.Learn How to write basic logic circuits using VHDL.
2.Using Quartus II compile and simulate the text file and then analyze the simulation for proper operation.
3.Learn how to assign pins and then how to download the program to the eSOC II board.
4. Verify that the eSOC II board behaves correctly when the output is what is expected depending on the input configuration.
Using the results of the compilation for the Design Project, what percent of the FPGA is used to implement the design.
In the compilation process, what is the difference between an error and a warning?
Use the zoom tool to measure the propagation delays, tPHL and tPLH, for the FPGA implementing the Design Project (the times between an input change of state and the subsequent output change of state in response). The zoom tool is used by expanding the time scale, right clicking on one signal and selecting “Insert Time Bar.”
What is “JTAG” and why is it used? Be sure to cite your sources.
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Content
Objectives:
1.Learn How to write basic logic circuits using VHDL.
2.Using Quartus II compile and simulate the text file and then analyze the simulation for proper operation.
3.Learn how to assign pins and then how to download the program to the eSOC II board.
4. Verify that the eSOC II board behaves correctly when the output is what is expected depending on the input configuration.
Using the results of the compilation for the Design Project, what percent of the FPGA is used to implement the design.
In the compilation process, what is the difference between an error and a warning?
Use the zoom tool to measure the propagation delays, tPHL and tPLH, for the FPGA implementing the Design Project (the times between an input change of state and the subsequent output change of state in response). The zoom tool is used by expanding the time scale, right clicking on one signal and selecting “Insert Time Bar.”
What is “JTAG” and why is it used? Be sure to cite your sources.