ECET 230 Week 3 iLab Flip-Flops in VHDL

ECET 230 Week 3 iLab Flip-Flops in VHDL Click Below Link To Purchase www.foxtutor.com/product/ecet-230-week-3-ilab-flip-flops-in-vhdl Objectives: Simulate an edge-triggered D flip-flop. Test a 74LS74 D flip-flop and compare against predictions. Describe and simulate edge-triggered D and J-K flip-flops with VHDL. Test a 74LS112 J-K flip-flop and compare against predictions. 1. Why is the condition when both and are LOW considered illegal? 2. How does the value you measured for tsetup compare with value specified in the 74LS74 data sheet? You may need to go on-line to find this value. 3. Why were the LEDs removed before making the propagation delay measurements? 4. Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that the preset (PRE) is synchronous instead of asynchronous. The clear (CLR) remains asynchronous.