Simplifying the Complexities of Multicore Processors with COTS Single Board Computer Solutions
Speaker:
Glenn Beck - Segment Marketing Manager - Single Board Computing and Aerospace & Defense Markets- Freescale Semiconductor
Haritha Treadway- Product Manager at Eurotech Inc.
Adam Auer- Marketing Manager with the Embedded Computing business of Emerson Network Power
Moderator:
Chris Ciufo, OpenSystems Media
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Simplifying the Complexities of QorIQ Multicore Processors with COTS Single Board Computer Solutions
17 February, 2011
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Freescale, the Freescale logo, AltiVec, CodeWarrior and PowerQUICC are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet, QorIQ and QUICC Engine are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2011 Freescale Semiconductor, Inc.
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Introduction QorIQ Processors from Freescale
Freescale, Glenn Beck • Roadmap • Creating High Assurance Computing
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COM Express Platform: Right Fit for QorIQ Processors
Eurotech, Haritha Treadway
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Embedded Pin-Out for COM Express Platform
Emerson, Adam Auer
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Questions and Answers
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3
Single Board Computing Market Dynamics
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OEM Dynamics
Hardware engineering resources are at 25% of OEM’s. Software and Systems engineers now make up the majority. This is at a historical low. • Complexities of processors increasing rapidly
o o
Multicore processors with memory subsystems, high-speed IO, hardware acceleration on a single device High-speed IO • Memories have moved from DDR1 to DDR3 in just a few years • PCI to PCI Express® gen 1 to gen 2. (5 GHz) • On board Gigabit Ethernet and 10G Ethernet
•
Need to get more products to the market faster with more capability at lower development cost Has the expertise to deal with high-speed design and multicore processors Module offering provides customers semicustom capability to make their products unique for a variety of markets Module standardization allows for multi-performance capability Improves the time to market and lowers the development cost
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SBC Ecosystem Dynamics
• • • •
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Power Architecture® Processor Roadmap
High Performance within Embedded Power Budget of 30W – 64-bit Cores High Performance within Embedded Power Budget of 30W
QorIQ – P5
P5020 P5010
Increase FP Perf Next Gen process Security plus
QorIQ – P4 e600 +SoC
P4080 P4040
Increasing Performance
Next Gen Core Increase FP Perf Security plus
Decreasing Power
Performance at Reasonable Power 15 W
QorIQ – P3
P3041
Increase FP Perf Next Gen process Security plus
Value Priced for Power/Performance Applications 10W Power Sensitive Applications 5W
PowerQUICC III
QorIQ – P2
P2020/P2010 P2040
Trust Architecture More cores
PowerQUICC II Pro PowerQUICC II PowerQUICC I
QorIQ – P1
P1010/P1014 P1020/P1011 P1021/P1012 P1022/P1013 P1023/P1017
Multicore Next Gen Process Trust Arch
Increasing Performance
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Power Architecture® Processor Roadmap
High Performance within Embedded Power Budget of 30W – 64-bit Cores High Performance within Embedded Power Budget of 30W
QorIQ – P5
P5020 P5010
Increase FP Perf Next Gen process Security plus
AltiVec
Next Gen Core Increase FP Perf Security plus
QorIQ – P4 e600 +Soc
P4080 P4040
Increasing Performance
Decreasing Power
AltiVec
Performance at Reasonable Power 15 W
QorIQ – P3
P3041
Increase FP Perf Next Gen process Security plus
AltiVec
Value Priced for Power/Performance Applications 10W Power Sensitive Applications 5W
PowerQUICC III
QorIQ
P2020/P2011 O2040
Trust Arch More cores AltiVec Multicore Next Gen Process Trust Arch
PowerQUICC II Pro PowerQUICC II PowerQUICC I
QorIQ – P1
P1010/P1014 P1020/P1011 P1021/P1012 P1022/P1013 P1023/P1017
Increasing Performance
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Balanced SoC Architecture
QorIQ P4080
Multicore Processor
Power Architecture® e500-mc Core
32 KB D-Cache 32 KB I-Cache
1024 KB Frontside L3 Cache 1024 KB Frontside L3 Cache 64-bit DDR-2 / 3 Memory Controller 64-bit DDR-2 / 3 Memory Controller
128 KB Backside L2 Cache
eOpenPIC PreBoot Loader Security Monitor Internal BootROM Power Mgmt SD/MMC SPI 2x DUART 4x I 2 C 2x USB 2.0/ULPI Clocks/Reset GPIO CCSR
Test Port/ SAP
Pattern Match Engine 2.0 Frame Manager Parse, Classify, Distribute
Buffer PAMU PAMU PAMU
CoreNet
Coherency Fabric
PAMU PAMU Peripheral Access Mgmt Unit
eLBC
Security
4.0
Queue Mgr.
Frame Manager Parse, Classify, Distribute
Buffer
Real Time Debug
RapidIO Message Unit (RMU) PCIe PCIe
2x DMA
Watchpoint Cross Trigger Perf CoreNet Monitor Trace
Buffer Mgr.
1GE 10GE 1GE
1GE 10GE 1GE
1GE 1GE
1GE 1GE
SRIO
PCIe SRIO Aurora
18-Lane 5GHz SerDes
•
• •
Power Architecture® technology: superscalar OOO transactions Memory Hierarchy: L1 – L2 – L3 – Main Memory High-speed IO: Gen 2 PCI Express®, RapidIO®, Gig and 10G Ethernet
• • •
Embedded IO’s: UARTs, SPI, USB, GPIO Hardware accelerators: SEC, Pattern Matching Engine, Data Path Acceleration Architecture Assured Computing: Secure Boot, Separation of Domains and threat detection
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High Assurance Platform - Security in a Connected World
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Key Capabilities of the High Assurance PlatformR – HAP
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Embedded Security Module – provides hardware-based protection of cryptographic keys, stores measurements of device state and helps to prove to a third party that the device is trustworthy. Device Hardware Security – hardware memory partition provides a secure connection to the ESM to guard against unauthorized access and separation of resources to isolate different security domains. Software Measurement - At boot time and at runtime, a HAP device measures software in a trusted manner before that software is allowed to execute. Separation of Domains - Software can be run free from interference or threat from other software running in other domains on the same device. Remote Attestation - When connecting to a network, a HAP device provides proof of its state to HAP network devices and servers, which can then make a determination about the trustworthiness of the HAP device and, based on that determination, allow access, quarantine or remediate the HAP device. Secure Central Administration - HAP devices can be administered centrally through their entire lifecycle, enabling the secure provisioning, audit, identification, authentication, management and decommissioning of the HAP devices in enterprise environments.
Source: www.nsa.gov/hap
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QorIQ Processors
Objective of the Assurance: Trust Architecture
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Protection Against:
Theft of Functionality - loss of control of the system’s functionality • Theft of Data - where a data protection policy exists, loss of data to an unauthorized party • Theft of Uniqueness - loss of product differentiation through reverse engineering, duplication and unapproved inter-operability.
•
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Relying on:
Secure Boot – start from Trusted code base or don’t start at all • Strong Partitioning of the System – isolation of cores from each other to provide redundancy and data corruption protection between critical functions • Threat detection – internal and external security event detection • Secure Debug – allows for protected on sight and remote debug
•
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Trusted Boot Process
(Embedded Security Module, Software Measurement)
Code Signing Entity System Code (Plaintext)
Plaintext Hash = (ciphertext hash)(e) mod N
Ciphertext Hash = (plaintext hash) (d) mod N E,d, and N are large integers, at least 2048b E, d, and N are mathematically chosen so that RSA works (N is the product of 2 large primes) Sign and Verify are identical operations (modular exponentiation)
Internal Secure Boot Code
If Decrypted Hash = Generated Hash, the Syst Code has not been modifi Decrypted Hash
Hash
Public Key (e) Public Modulus (N)
Generated Hash
RSA Sign
Private Key (d) Public Modulus (N)
RSA Verify
Signature System Code (Plaintext)
System NV RAM
Signature System Code (Plaintext)
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Partition 1
128 KB Backside L2 Cache
Domain Separation
Partition 2
HV MMU
Power e500-mc Core
32 KB D-Cache
Qman Portal Qman Portal
Architecture®
32 KB I-Cache 128 KB Backside L2 Cache
Power Architecture e500-mc Core
HV MMU
Shared Main Memory
32 KB D-Cache
Qman Portal Qman Portal
32 KB I-Cache
2 MB Front side L3 Cache HV Private Memory
128 KB Backside L2 Cache
Power Architecture e500-mc Core
32 KB D-Cache
HV MMU
32 KB I-Cache
128 KB Backside L2 Cache
Power Architecture e500-mc Core
32 KB D-Cache
HV MMU
Partition 1 Private Memory Partition 2 Private Memory Partition 3 Private Memory Partition 4 Private Memory Command Control Status Registers
32 KB I-Cache
Partition 3
Qman Portal Qman Portal
Partition 4
Qman Portal Qman Portal
QMan
CoreNet Coherency Fabric
PAMU PAMU PAMU PAMU PAMU
BMan
Peripheral Access Mgmt Units
Frame Manager Parse, Classify, Distribute SEC
4.0
Frame Manager Parse, Classify, Distribute
Buffer 1GE 1GE 1GE 1GE
PME 2.0
10GE
Buffer 1GE 1GE 1GE 1GE 10GE
PCIe PCIe PCIe sRIO sRIO
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Power Architecture® Technology: QorIQ Platform
Size, Weight, Power and Performance
• Answering the demands of the market
High Assurance Architecture
• User controlled line of trust
QorIQ – A balanced architecture for performance and power • High performance multicore processing • Tri-level Memory subsystem • High Speed IO – PCI Express, Rapid IO • Hardware Acceleration - Security and Networking • CoreNet - Non-blocking Fabric Control • Scalable Signal Processing
Secure Boot
• • • • Drive Linux® enhancements Drive multicore support Drive open virtualization technologies Drive open firmware, x86 emulation, HAL
Threat Protection
&
QorIQ – Scalable Performance • 600 MHz to 2.2 GHz/core • 4 to 30 Watts • Single ISA across family
Signal Processing
Trusted Architecture
• From Loss of Functionality • From Loss of Data • From Loss of Uniqueness
Strong Partitioning Tamper Detection
Ecosystem
Tools and OS Single Board Computing
- Emerson - Eurotech • Broad OS support - Green Hills - ENEA - Mentor Embedded - QNX - Wind River
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► ►
Introduction QorIQ Processors from Freescale
Freescale, Glenn Beck • Roadmap • Creating High Assurance Computing
►
COM Express Platform: Right Fit for QorIQ Processors
Eurotech, Haritha Treadway
►
Embedded Pin-Out for COM Express Platform
Emerson, Adam Auer
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Questions and Answers
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Benefits of COM Express:
Optimize Performance, Power and Size
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Delivers full performance capabilities of the QorIQ platform
• • • • • •
Multicore capabilities PCI Express® interconnects Gigabit Ethernet USB 2.0 SATA LVDS Compact form factor Six channels for data communication
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Reduces power usage for minimal consumption specs
• •
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Small footprint supports a broad range of applications
• •
Basic and compact form factor solutions Ideal for battery-operated or space-constrained devices
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Benefits of COM Express:
Reduce Cost and Time to Market
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Low cost of total ownership
• • •
Freescale 10-year product lifecycle for QorIQ platform Critical component EOL issues managed by module vendor Extends life of final solution Processor design complexities already addressed in module Enables OEMs to focus on core, application-specific designs Reduce time to market and revenue Fewer layers required on the carrier Reduced effort to manage component procurement Overall total cost reductions
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Reduce design and development costs
• • •
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Reduce manufacturing costs
• • •
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Benefits of COM Express:
Flexibility and Customization
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Scalability
•
Standard footprints and pin-outs offer migration paths to newer technologies without carrier board redesign • No need to redesign enclosures since carrier boards can remain the same
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SBC
Portability
•
COM
Design several carrier boards using one processor platform • Migrate across product line with minimal design work required
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Carrier boards
Application-specific carrier boards
•
Form, fit and function suited specifically for end application • Minimized development efforts
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Overall Comparison: COM Express Versus SBC
Product Development Phase Designing the product
COM Express Module • Board supplier optimizes module for processor capabilities • OEM focuses on application design
SBC Designs • OEM required to work with board supplier on understanding features, pop/depop requirements • Essentially introducing new product with every SBC design • High inventory because of inability to reuse existing designs and enclosures • Board EOL’ed, OEM negotiates Last Time Buy conditions
Introducing to the factory
• Opportunity to reuse existing resources • Low system assembly costs
Maintenance and manufacturing End of lifecycle costs
• Lower cost overall • Fewer components to maintain • Scale to new technology to extend product lifecycle
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Eurotech’s QorIQ Solutions:
Target Markets and Applications
Adbc7517
P4080 Up to 1.5 GHz, <35W Max, 8 cores, ECC, high speed I/O Medical Xray Industrial Automation Military/Aerospace
Performance
Adbc7520
P1021
Adbc7519
P2020 Up to 1.2 GHz, <10W Max, 2 cores, networking, graphics, ECC Transportation Semiconductor manufacturing
Up to 800 MHz, <5W Max, 2-core, QUICC Engine, networking, graphics
Security camera
Networked communications
Power Consumption
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► ►
Introduction QorIQ Processors from Freescale
Freescale, Glenn Beck • Roadmap • Creating High Assurance Computing
►
COM Express Platform: Right Fit for QorIQ Processors
Eurotech, Haritha Treadway
►
Embedded Pin-Out for COM Express Platform
Emerson, Adam Auer
►
Questions and Answers
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Emerson Network Power
Corporate Sales of $21B (2010)
Best cost design and manufacturing facilities
Widest range of embedded computing products
• Over 30 years legacy in Embedded Computing incorporating Motorola Computer Group, Force Computers, Prolog, Blue Wave Systems, Paceline, Artesyn and others • Globally recognized for our quality, reliability and long life-cycle products • Excellent pre- and post-sales support plus comprehensive services portfolio for trouble-free deployment
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COM Express Pins and Headers
•
COM Express pin-outs define which signals are taken to the end of a processing module via the 4 COM Express connectors: A,B,C,D Modules are built according to a certain type - in order to successfully mate with a carrier The types are defined by PICMG. http://www.picmg.org/ The QorIQ modules use new pinouts that are PICMG compatible, not compliant.
A B C D
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Goals of the Pin-Out
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Processor-agnostic approach
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Greater flexibility
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Removal of x86 specific pins
•
LPC, PEG, AC'97 Audio, Sleep states 3, and 4, etc.
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Addition of embedded interfaces:
•
•
• •
IEEE® 1588 Precision Time Protocol 8 Bit local bus UART interfaces Configurable SerDes lanes - enabling 10G XAUI Ethernet, SGMII, Serial RapidIO® or PCI Express® interconnects
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QorIQ P1022 Processor Compared to a Type 6
P1022
A GIGE 0 B 1588 CK i2C SATA SATA DDI x 1 C GIGE 1 D
Type 6 A
GIGE 0
B
LPC SMB i2C
C
USB 3.0 PCIE 7 DDI x 3
D
USB 3.0 PCIE 8
SATA
SATA
SATA
SATA
AC97 Audio AC97 Audio USB USB USB USB PCIE 1 PCIE 2 PCIE 3 LVDS A SPI SDIO SPI VGA SDIO UART 0 UART 1 SPI I2S Audio MDIO IRQ SPI USB USB PCIE 4 USB USB PCIE 1 PCIE 2 PCIE 3 LVDS A SPI LPC USB USB USB USB PCIE 4 PCIE 5 PCIE 6 LVDS B SPI VGA PEG
GPIO/SDIO GPIO/SDIO
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QorIQ P2020 Processor Compared to a Type 2
P2020 A
GIGE 0
Type 2
B
1588 CK i2C
C
GIGE 1
D
GIGE 2
A
GIGE 0
B
LPC SMB i2C
C
IDE
D
SATA
SATA
PCI
SATA
AC97 Audio USB USB USB
SATA
AC97 Audio USB USB USB USB PEG
USB USB PCIE 1 PCIE 2 PCIE 3 LVDS A SPI SDIO
USB USB
USB
PCIE 1
PCIE 2 PCIE 3 LVDS A SPI LPC GPIO/SDIO ExpressCard
PCIE 4
PCIE 5 PCIE 6 LVDS B SPI VGA GPIO/SDIO ExpressCard
UART 0 UART 1 SPI VGA SDIO SPI
MDIO IRQ SPI
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QorIQ P4080 Processor Compared to a Type 5
P4080 A
GIGE 0
Type 5 C D
GIGE 2
B
1588 CK i2C
A
GIGE 0
B
LPC SMB i2C
C
GIGE 1
D
GIGE 2
GIGE 1
SERDES 6 SERDES 7
SATA
SATA
SATA
SATA
PCIE 7
PCIE 9 PCIE 11 PCIE 13 PCIE 15 PCIE 17 PCIE 19 PCIE 21 PCIE 23 PCIE 25 PCIE 27 PCIE 29 PCIE 31
PCIE 8
PCIE 10 PCIE 12 PCIE 14 PCIE 16 PCIE 18 PCIE 20 PCIE 22 PCIE 24 PCIE 26 PCIE 28 PCIE 30 PCIE 32
AC97 Audio AC97 Audio USB USB USB USB USB USB USB USB SERDES 17 SERDES 17 SERDES 18 SERDES 19 USB USB USB USB PCIE 1 PCIE 2 UART 0 UART 1 SPI SDIO SPI SDIO SPI UART 2 Local Bus Tamper MDIO IRQ SPI PCIE 3 LVDS A SPI LPC USB USB USB USB PCIE 4 PCIE 5 PCIE 6 LVDS B SPI VGA
SERDES 0 SERDES 3
SERDES 1 SERDES 4 SERDES 2 SERDES 5
GPIO/SDIO GPIO/SDIO
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Results
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Dramatically increased flexibility
•
Configurable SerDes lanes allow interfaces to be configured during boot-up
100% compatible power and ground pins 100% compatible common interfaces (SATA, USB) Interchangeable with limited functionality Mechanically Identical - mounting and thermal designs can be re-used
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Pin-out Compatible modules
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QorIQ Architecture is now available on modules! For more information:
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•
COM Express please visit PICMG.org: http://www.picmg.org/ QorIQ implementation: contact Emerson Network Power, Eurotech or Freescale Semiconductor for more information.
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QorIQ Modules from Emerson Network Power
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COMX-P4080
• • •
8 Core 1.5 GHz CPU Up to 4 GB DDR3 12 configurable SerDes lanes
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COMX-P2020
• •
2 Core 1.0 GHz CPU Up to 2 GB DDR3
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COMX-P1022
• •
2 Core 800 MHz CPU Up 2 GB DDR3
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► ►
Introduction QorIQ Processors from Freescale
Freescale, Glenn Beck • Roadmap • Creating High Assurance Computing
►
COM Express Platform: Right Fit for QorIQ Processors
Eurotech, Haritha Treadway
►
Embedded Pin-Out for COM Express Platform
Emerson, Adam Auer
►
Questions and Answers
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Glenn Beck - Segment Marketing Manager - Single Board Computing and Aerospace & Defense Markets- Freescale Semiconductor Haritha Treadway- Product Manager at Eurotech Inc. Adam Auer- Marketing Manager with the Embedded Computing business of Emerson Network Power
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Thanks for joining us
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