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DESIGN OF LEAKAGE POWER REDUCTION TECHNIQUE IN SUBMICRON TECHNOLOGY MINI PROJECT
Submitted in partial fulfillment of the Requirements for the award of the Degree of

BACHELOR OF TECHNOLOGY IN ELECTRONICS AND COMMUNICATION ENGINEERING
by P. PRIYANKA U. NAGA PRAVEEN T. V. S. PRITHVI RAJ BODI SAILU 107R1A0437 107R1A0454 107R1A0453 107R1A0467

Under the esteemed guidance of SK. DILSHAD M.Tech
Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING CMR TECHNICAL CAMPUS (AFFILIATED TO JNTU, HYDERABAD) KANDLAKOYA (V), MEDCHAL, HYDERABAD - 501401

2013
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CMR TECHNICAL CAMPUS (AFFILIATED TO JNTU, HYDERABAD) KANDLAKOYA (V), MEDCHAL, HYDERABAD – 501401

CERTIFICATE
This is to certify that the project report entitled “DESIGN OF LEAKAGE POWER REDUCTION TECHNIQUE IN SUBMICRON TECHNOLOGY” that is being submitted by P. PRIYANKA, U. NAGA PRAVEEN, T. V. S. PRITHVI and BODI SAILU bearing Admn. No.’s: 107R1A0437, 107R1A0454, 107R1A0453 and 107R1A0465 in partial fulfillment for the award of the Degree of BACHELOR OF TECHNOLOGY in ELECTRONICS AND COMMUNICATION ENGINEERING to the Jawaharlal Nehru Technological University is a record of bonafide work carried out by them under my guidance and supervision. The results embodied in this report have not been submitted to any other university or institute for the award of any degree or diploma.

INTERNAL GUIDE SK. DILSHAD M.Tech
Assistant Professor

HEAD OF THE DEPARTMENT G. SRIKANTH M.Tech, (Ph.D)
Associate Professor

EXTERNAL EXAMINER Dr. A. RAJI REDDY M.Tech, Ph.D

DIRECTOR

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ACKNOWLEDGEMENT

We are expressing our sincere thanks to DR. A. RAJI REDDY, DIRECTOR CMR TECHNICAL CAMPUS
DURING OUR STUDY PERIOD .

OF

FOR HIS KIND CO- OPERATION AND VALUABLE SUGGESTIONS

We are delighted to express our acknowledgements to Dr. R. PURNACHANDRA RAO, Dean of CMR Technical Campus, for his continuous care towards our achievements. It is a great honor to express our gratitude to Mr. G. SRIKANTH, HEAD ELECTRONICS I T’S
AND OF

THE

COMMUNICATIONS ENGINEERING DEPARTMENT. MRS . SK. HER
AND

AN IMMENSE PLEASURE TO THANK OUR INTERNAL GUIDE FOR SUPPORTING US THROUGHOUT GUIDANCE , VALUABLE

DILSHAD ASST. PROF ,
INSPIRING REMARKS ,

OUR PROJECT . SUGGESTIONS

SIMULATING

INFLUENCING ENCOURAGEMENT HELPED US GREATLY IN THE COMPLETION OF OUR PROJECT .

I would like to express our deep gratitude to our Project Co-coordinator SK. DILSHAD, Asst. Prof Department of ECE. Finally, we would like to thank our parents and friends who provided us a lot of moral support and encouragement in many ways for the completion of this project work.

P. PRIYANKA U. NAGA PRAVEEN BODI SAILU

- 107R1A0437 - 107R1A0454 - 107R1A0465

T. V. S. PRITHVI RAJ - 107R1A0453

iii

ABSTRACT
The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become an increasingly important issue in processor hardware and software design. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. In this paper, we propose a new stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product when compared to the existing methods. Existing Method: While Designing of Inverters we have Techniques for leakage power reduction can be grouped into two categories: state-preserving techniques, state-destructive techniques; A state-preserving technique has an advantage over a state destructive technique in that with a state-preserving technique the circuitry can resume operation at a point much later in time without having to somehow regenerate state. All well known approach is “SLEEP” in this method we reduce leakage power. The proposed DUAL SLEEP approach we reduce more power leakage. Proposed Method: Dual sleep approach uses the advantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the dual sleep portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.

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CONTENTS
Title Certificates Acknowledgement Abstract Contents List of Figures CHAPTER 1: INTRODUCTION 1.1 CMOS 1.2 Importance Of Low Power CMOS Design 1.2.1 Dynamic Power consumption 1.2.2 Short Circuit Power 1.2.3 Leakage Power Consumption 1.2.4 Static Power Consumption CHAPTER 2: POWER LEAKAGE TECHNIQUE 2.1 Fine-grain vs. Coarse-grain sleep transistor 2.2 Sleepy keeper 2.3 Sleepy transistor i ii iii iv v vii 1 2 5 6 7 7 7 9 9 13 15

CHAPTER 3: APPROACH TO LOW LEAKAGE POWER

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CHAPTER 4: SIMULATION ENVIRONMENT 4.1 DSCH (Digital Schematic) 4.1.1 MOS as A Switch

22 22 22

4.1.2 Connecting Procedure 4.2 Micro wind 4.2.1 MOS Layout 4.2.2 Static MOS Characteristics 4.2.3 Manual Layout Design 4.2.4 Connection between Devices 4.2.5 Simulation 4.2.6 Checking The Layout

23 23 23 25 25 26 27 27

CHAPTER 5: VERILOG HDL 5.1 What Is HDL? 5.2 Verilog Overview 5.2.1 Introduction 5.2.2 Design Styles 5.2.3 Bottom-Up Design 5.2.4 Top-Down Design 5.2.5 Abstraction Levels of Verilog 5.2.6 Behavioral level 5.2.7 Register-Transfer Level 5.2.8 Gate Level 5.3 VLSI Design Flow 5.3.1 Introduction CHAPTER 6: SIMULATION RESULTS 6.1. Schematic Design For Circuit

28 28 28 28 29 29 29 29 30 30 30 30 30 32 32

6.2. Generating Verilog File 6.3. Layout In Micro wind 6.4 Analysis for Voltage Vs Time 6.5 Analysis for Voltage Vs Current 6.6 Analysis for Frequency Vs Time CHAPTER 7: APPLICATIONS AND ADVANTAGES Applications Advantages Limitations CHAPTER 8: CONCLUSION REFERENCES Appendix A : VERILOG Code for the Design

32 33 33 34 34 35 35 35 35 36 37 38 38

LIST OF FIGURES
Figure 1.1: NAND gate in CMOS Figure 1.2: NAND Physical Layout Figure 2.1: Fine-grain sleep transistor implementation in NAND gate Figure 2.2: Coarse-grain sleep transistor implementations Figure 2.3: Sleep method Figure 2.4: Sleepy stack Figure 2.5: Dual sleep Figure 2.6: Sleepy keeper approach Figure 2.7: Sleep approach Figure 2.8: Zigzag approach Figure 2.9: Stack approach Figure 2.10: Sleepy stack approach Figure 2.11: Leakage feedback approach Figure 3.1: Low Leakage Power (a chain of 4 inverter) Figure 4.1: Symbol of NMOS and PMOS Figure 4.2: Creating the Nchannel MOS transistor Figure 4.3: N-Channel MOS characteris tics

Figure 4.4: Selecting the PMOS device

14 15 16 17

3 4 10 11 12 13 13

17 18 20 22 24 25 26

Chapter 1 INTRODUCTION
Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. Two components determine the power consumption in a CMOS circuit; Static power: Includes sub-threshold leakage, drain junction leakage and gate leakage due to tunneling. Among these, sub threshold leakage is the most prominent one. Dynamic power: Includes charging and discharging power and short circuit power. When technology feature size scales down, supply voltage and threshold voltage also scale down. Sub-threshold leakage power increases exponentially as threshold voltage decreases. Furthermore, the structure of the short channel device lowers the threshold voltage even lower. So it is becoming more and more important to reduce leakage power as well as dynamic power. There are several VLSI techniques for reducing leakage power. Each technique provides an efficient way to reduce leakage power, but disadvantages of each technique limit its application. In this paper, we propose a novel dual stack technique that reduces not only leakage

power but also dynamic power. We summarized and compared the previous techniques with our new approach. Lowering supply voltage is effective for power reduction because of the quadratic relationship between supply voltage and dynamic power consumption. To compensate the performance loss due to a lower supply voltage, transistor threshold voltage has to be decreased as well, which causes exponential increase in the sub threshold leakage current. To reduce leakage power, multi threshold CMOS has been proposed with low blocks connected to ground through high transistors named as sleep transistors. The sleep transistor is turned on when the circuit is in the computational mode, and is turned off to cutoff the power supply in the standby mode for significant power reduction. In order to achieve high density and high performance, CMOS technology feature size and threshold voltage have been scaling down for decades. Because of this technology trend, transistor leakage power has increased exponentially. As the feature size becomes smaller, shorter channel lengths result in increased sub threshold leakage current through a transistor when it is off. Low threshold voltage also results in increased sub threshold leakage current because transistors cannot be turned off completely. For these reasons, static power consumption, i.e., leakage power dissipation, has become a significant portion of total power consumption for current and future silicon technologies. There are several VLSI techniques to reduce leakage power. Each technique provides an efficient way to reduce leakage power, but disadvantages of each technique limit the application of each technique. We propose a new approach, thus providing a new choice to low-leakage power VLSI designers. Previous techniques are summarized and compared with our new approach presented in this paper. 1.1 CMOS: Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. CMOS is also sometimes referred to as complementary-symmetry metal–oxide– semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the

typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips. The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor Material. Aluminum was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of high-k dielectric materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and beyond. "CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes. As of 2010, CPUs with the best performance per watt each year have been CMOS static logic since 1976. CMOS circuits use a combination of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. Although CMOS logic can be implemented with discrete devices (e.g., for instructional purposes in an introductory circuits class), typical commercial CMOS products are integrated circuits composed of millions of transistors of both types on a rectangular piece of silicon of between 10 & 400mm2. These devices are commonly called "chips", although within the industry they are also referred to as "die" (singular) or "dice", or "dies" (plural). Logic:

Figure 1.1: NAND gate in CMOS

More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modeling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modeling an OR. Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage

between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise. NAND gate in physical layout:

Figure 1.2: NAND Physical Layout

This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a P-type substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the P-type substrate. The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection. The inputs to the NAND (illustrated in green color) are in polysilicon. The CMOS transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout example matches the NAND logic circuit given in the previous example. The N device is manufactured on a P-type substrate while

the P device is manufactured in an N-type well (n-well). A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latch up. In order to achieve high density and high performance, CMOS technology feature size and threshold voltage have been scaling down for decades. Because of this technology trend, transistor leakage power has increased exponentially. 1.2 IMPORTANCE OF LOW-POWER CMOS DESIGN With advances in CMOS technology, the potential packing densities increase as the feature size of the MOS devices shrinks. These increases and decreases validate what Gordon Moore once said in the 1960s: the number of transistors that can be integrated on a single die would grow exponentially with time (Moore, 1965). The example that amazingly proved his visionary prediction is best illustrated by tracking the historical evolution of integrated circuit (IC) design in the company he founded in1972, Intel, and by using the trends in memory evolution .Such observations are evident. The trend in the IC logic complexity evolution for Intel processors in the last two decades. The components of power consumption in CMOS design The power consumption in digital CMOS circuits can be described by: Pavg = Pdynamic + Pshort -circuit + Pstatic + Pleakage (1) where Pavg is the average power consumption, Pdynamic is the dynamic power consumption due to switching of transistors, Pshort -circuit is the short-circuit current dissipation when there is direct path from the power source down to ground, Pstatic is the static power consumption, and Pleakage is the power consumption due to leakage currents. 1.2.1 Dynamic Power Consumption The dynamic power consumption, Pdynamic , is caused by the charging and discharging of parasitic capacitances in the circuit. We illustrate the computation of the dynamic consumption through the example of a CMOS inverter driving a load capacitor CL, The output

capacitor represents the cumulative effect the parasitic capacitances of the nMOS and pMOS transistors (source and drain-diffusion to bulk), the capacitance associated with the internal and external wires to inverter cell, and the input capacitance (gate to bulk) of the next driven circuits. We will explain the operation of a CMOS inverter considering that the circuit is initially in a steady state, having as input logic value ‘1’ and, obviously, output logic value ‘0’. In this situation the output capacitor is discharged. When the input waveform undergoes a falling transition, the pMOS transistor conducts (ON), while the nMOS transistor turns off, This implies that the current drawn from the power source charges the capacitance CL to the value Vdd. During this process, the energy that is drawn from the supply is CL ×Vd2d , of which half is stored in the capacitor CL whereas the second half is dissipated by the parasitic capacitors of pMOS and interconnect. When the input undergoes a rising transition, the nMOS transistor conducts while the pMOS turns off. However, there is a path from the output capacitor directly to the ground and thus, discharging current flows through this path. The stored energy 0.5C V 2 L × Vdd is dissipated to the nMOS transistor and interconnect. Therefore, the dynamic power dissipated by the CMOS inverter over a time interval [0, T] can be computed.

1.2.2 Short-Circuit Power The short circuit power, Pshort -circuit , is caused by the direct path from the power supply to ground, during the transition phase. When an input signal changes from a logic value to another value, there is a very small time interval where both nMOS and pMOS transistor are ON, and thus, there is short current between the power supply and ground. 1.2.3 Leakage Power Consumption The leakage power consumption, Pleakage, consists of two kinds of leakage currents (i the reverse-bias diode leakage at the transistor drains ii) the sub-threshold current through an turned-off transistor channel. However, these components are technologically-controlled and thus, the designer has a few things to do about their minimization. Diode leakage occurs when a transistor is turned-off, the other ON transistor charges up/down the drain with the respect to the

former’s substrate potential. there is a pMOS transistor with negative bias Vdd of gate with respect to substrate. So, the diode composed by drain diffusion and substrate is reversely-biased. 1.2.4 Static Power Consumption Ideally, in the steady state of CMOS circuits there is no static power consumption, which is the most attractive characteristic of CMOS technology. However, the actual operation of a CMOS circuit is slightly different. More specifically, the degenerated voltage levels feeding into static complementary gates and pseudo nMOS logic family. Then, we will discuss these issues. We illustrate the phenomenon of static consumption due to degenerated input signals through a certain example. An nMOS transistor drives an inverter. From basic CMOS circuit theory, the voltage value of the node A is Vdd -Vtn . Since inverter’s input is high (i.e. Vdd -Vtn ), the output should be low. However, the pMOS transistor will be weakly ON ( Vgs -Vtp at 0) conducting static current from power to ground rail. The associated consumption might be significant if the inverter has small operation frequency. A pseudo-nMOS logic gate consists of a single pMOS transistor, whose gate connector is always grounded and a complex block of nMOS transistors, which actually implements the Boolean function . It can be easily seen that there exists always a path from power to ground rail, because the pMOS transistor is always ON. Thus, during the steady state there is static power dissipation. Whether the pseudo-nMOS logic family is appropriate for low power or not depends on certain requirements, such as area savings, frequency operation, and after careful trade-off analysis.

Chapter 2 POWER LEAKAGE TECHNIQUE
Leakage power has been increasing exponentially with the technology scaling. In 90nm node, leakage power can be as much as 35% of chip power. Consequently, leakage power reduction becomes critical in low-power applications such as cell phone and handheld terminals. Power-gating is the most effective standby leakage reduction method recently developed. In the power gating, sleep transistors are used as switches to shut off power supplies to parts of a design in standby mode. Although the concept of the sleep transistor is simple, design of a correct and optimal sleep transistor is challenge because of many effects introduced by the sleep transistor on design performance, area, rout ability, overall power dissipation, and signal/power integrity. Currently, many of the effects have not been fully aware by designers. This could result in

improper sleeper transistor design that would either fail to meet power reduction target when silicon is back or cause chip malfunction due to serious power integrity problems introduced. We have carried out comprehensive investigations on various effects of sleep transistor design and implementations on chip performance, power, area and reliability. In this paper, we shall describe a number of critical considerations in the sleep transistor design and implementation including header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. A sleep transistor is referred to either a PMOS or NMOS high Vth transistor that connects permanent power supply to circuit power supply which is commonly called “virtual power supply”. The sleep transistor is controlled by a power management unit to switch on and off power supply to the circuit. The PMOS sleep transistor is used to switch VDD supply and hence is named “header switch”. The NMOS sleep transistor controls VSS supply and hence is called “footer switch”. In sub-90nm designs, either header or footer switch is only used due to the constraint of sub-1V power supply voltage. 2.1 FINE-GRAIN VS. COARSE-GRAIN SLEEP TRANSISTOR The sleep transistors can be implemented in a design in either “coarse-grain” or “finegrain” power gating styles. In the “fine grain” implementation, the sleep transistor is inserted in every standard cell which is often called MTCMOS cell. A power gating control signal is added to switch on and off power supply to the cell.

Figure 2.1: fine-grain sleep transistor implementation in NAND gate

A weak pull-up/down transistor controlled by the sleep signal is added to prevent floating output when the cell is in sleep mode. This is necessary to prevent short circuit current in those active cells connected to the sleep cell due to floating inputs. The pull-up/down transistor remains in OFF state in normal operation mode. Only one isolation state is allow which is “1” in footer switch implementations and “0” in the header switch implementations. The advantage of the fine-grain sleep transistor implementations is that the virtual power nets (VVSS or VVDD) are short and hidden in the cell. Moreover, the MTCMOS cell can be implemented by existing standard cell based synthesis and place& route tools. However, the fine-grain sleep transistor implementation adds a sleep transistor to every MTCMOS cell that results in significant area increase. Also, it is not able to use the normal standard cells provided by library vendors and ASIC foundries. Another issue is that the MTCMOS cells become more sensitive to PVT variations, because the built-in sleep transistor is subject to PVT variation which results in added IR-drop variation in the cell and hence performance variation. In the “coarse-grain” power gating designs as shown in Fig., the sleep transistors are connected together between the permanent power supply and the virtual power supply networks. The main advantage of the “coarse-grain” power gating is that sleep transistors share charge/discharge current. Consequently, it is less sensitive to PVT variation and introduces less IR-drop variations than the “fine-grain” implementations. Also, the area overhead is significantly smaller due to charge sharing among the sleep transistors. Most power-gating designs prefer the “coarse-grain” sleep transistor implementation than the “fine-grain” implementation which incurs large area penalty and higher PVT sensitivity. In this paper, we shall focus on challenges in the “coarse-grain” sleep transistor designs and implementations.

Figure 2.2: coarse-grain sleep transistor implementations

Techniques for leakage power reduction can be grouped into two categories: statepreserving techniques; where circuit state is retained and state-destructive techniques; where the current Boolean output value of the circuit might be lost. A state-preserving technique has an advantage over a state destructive technique in that with a state-preserving technique the circuitry can resume operation at a point much later in time without having to somehow regenerate state. The most well-known traditional approach is the sleep approach. In the sleep approach, a "sleep" PMOS transistor is placed between Vdd and the pull-up network of a circuit and a "sleep" NMOS transistor is placed between the pull-down network and Gnd. These sleep transistors turn off the circuit by cutting off the power rails. The sleep transistors are turned on when the circuit is active and turned off when the circuit is idle. By cutting off the power source, this technique can reduce leakage power effectively. However, output will be floating after sleep mode, so the technique results in destruction of state plus a floating output voltage. A variation of the sleep approach, the zigzag approach, reduces wake-up overhead caused by sleep transistors by placement of alternating sleep transistors assuming a particular preselected input vector. Another technique for leakage power reduction is the stack approach, which forces a stack effect by breaking down an existing transistor into two half size transistors. The divided transistors increase delay significantly and could limit the usefulness of the approach. The sleepy stack approach combines the sleep and stack approaches.

Figure 2.3: Sleep method

The sleepy stack technique divides existing transistors into two half size transistors like the stack approach. Then sleep transistors are added in parallel to one of the divided transistors. During sleep mode, sleep transistors are turned off and stacked transistors suppress leakage current while saving state. Each sleep transistor, placed in parallel to the one of the stacked transistors, reduces resistance of the path, so delay is decreased during active mode. However, area penalty is a significant matter for this approach since every transistor is replaced by three transistors and since additional wires are added for S and S’, which are sleep signals. Another technique called Dual sleep approach uses the advantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the dual sleep portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.

Figure 2.4: Sleepy stack

Figure

2.5: Dual sleep

2.2 SLEEPY KEEPER In this section, we describe our new leakage reduction technique, which we call the “sleepy keeper” approach. This section explains the structure of the sleepy keeper approach as well as how it operates. In addition, we discuss some layout issues for the sleepy keeper approach. The basic problem with traditional CMOS is that the transistors are used only in their most efficient, and naturally inverting, way: namely, PMOS transistors connect to VDD and NMOS transistors connect to GND.

It is well known that PMOS transistors are not efficient at passing GND; similarly, it is well known that NMOS transistors are not efficient at passing VDD. However, to maintain a value of ‘1’ in sleep mode, given that the ‘1’ value has already been calculated, the sleepy keeper approach uses this output value of ‘1’ and an NMOS transistor connected to VDD to maintain output value equal to ‘1’ when in sleep mode. As shown in Figure 6, an additional single NMOS transistor placed in parallel to the pull-up sleep transistor connects VDD to the pull-up network. When in sleep mode, this NMOS transistor is the only source of VDD to the pull-up network since the sleep transistor is off.

Figure 2.6: Sleepy keeper approach

Similarly, to maintain a value of ‘0’ in sleep mode, given that the ‘0’ value has already been calculated, the sleepy keeper approach uses this output value of ‘0’ and a PMOS transistor connected to GND to maintain output value equal to ‘0’ when in sleep mode. As shown in Fig, an additional single PMOS transistor placed in parallel to the pull-down sleep transistor is the only source of GND to the pull-down network which is the dual case of the output ‘1’ case explained above. For this approach to work, all that is needed is for the NMOS connected to VDD and the PMOS connected to GND to be able to maintain proper logic state. This seems likely to be possible as other researchers have described ways to use far lower VDD values to maintain logic state. For example, Flaunter et al. propose some significantly

reduced VDD values sufficient to maintain state. We wish to here emphasize that, as explained at the end of Section III, we emphatically do not use sleepy keeper transistors (the NMOS connected to VDD and the PMOS connected to GND) to dynamically change the output voltage but instead only use them to maintain an already calculated output voltage. Specifically, only a few clock cycles after entering sleep to a few clock cycles prior to exiting sleep do the sleepy keeper transistors acts as the sole connection to keep the output voltage unchanged. 2.3 SLEEPY TRANSISTOR The most well-known traditional approach is the sleep approach. In the sleep approach, both (i) an additional "sleep" PMOS transistor is placed between VDD and the pull-up network of a circuit and (ii) an additional "sleep" NMOS transistor is placed between the pull-down network and GND. These sleep transistors turn off the circuit by cutting off the power rails. Fig shows its structure. The sleep transistors are turned on when the circuit is active and turned off when the circuit is idle. By cutting off the power source, this technique can reduce leakage power effectively. However, output will be floating after sleep mode, so the technique results in destruction of state plus a floating output voltage.

Figure 2.7: Sleep approach

A variation of the sleep approach, the zigzag approach, reduces wake-up overhead caused by sleep transistors by placement of alternating sleep transistors assuming a particular preselected input vector. In Fig2.6, we assume that, in sleep mode, the input of the logic is ‘0’ and each logic stage reverses its input signal, i.e., the output is ‘1’ if the input is ‘0,’ and the output is

‘0’ is the input is ‘1.’ If the output is ‘1,’ then a sleep transistor is added to the pull down network; if the output is ‘0’, then a sleep transistor is added to the pull-up network. Thus, the zigzag approach uses fewer sleep transistors than the original sleep approach. Furthermore, this approach still results in destruction of state (i.e., state is set to the particular pre-selected input vector), although the problem of floating output voltage is eliminated.

Figure 2.8: Zigzag approach

Another technique for leakage power reduction is the stack approach, which forces a stack effect by breaking down an existing transistor into two half size transistors. Fig shows its structure. When the two transistors are turned off together, induced reverse bias between the two transistors results in sub threshold leakage current reduction. However, divided transistors increase delay significantly and could limit the usefulness of the approach. The sleepy stack approach combines the sleep and stack approaches. The sleepy stack technique divides existing transistors into two half size transistors like the stack approach. Then sleep transistors are added in parallel to one of the divided transistors. Fig shows its structure. During sleep mode, sleep transistors are turned off and stacked transistors suppress leakage

current while saving state. Each sleep transistor, placed in parallel to the one of the stacked transistors, reduces resistance of the path, so delay is decreased during active mode. However, area penalty is a significant matter for this approach since every transistor is replaced by three transistors and since additional wires are added for S and S’, which are sleep signals.

Figure 2.9: Stack approach

Figure 2.10: Sleepy stack approach

The leakage feedback approach is based on the sleep approach. However, the leakage feedback approach uses two additional transistors to maintain logic state during sleep mode, and the two transistors are driven by the output of an inverter which is driven by output of the circuit implemented utilizing leakage feedback .A PMOS transistor is placed in parallel to the sleep transistor (S) and a NMOS transistor is placed in parallel to the sleep transistor (S'). The two transistors are driven by the output of the inverter which is driven by the output of the circuit.

During sleep mode, sleep transistors are turned off and one of the transistors in parallel to the sleep transistors keep the connection with the appropriate power rail.

Figure 2.11: Leakage feedback approach

For the sleep, zigzag, sleepy stack and leakage feedback approaches, dual Vth technology can be applied to obtain greater leakage power reduction. Since high-Vth results in less leakage but lowers performance, high-Vth is applied only to leakage reduction transistors, which are sleep transistors, and any transistors in parallel to the sleep transistors; on the other hand, lowVth is applied to the remaining transistors to Maintain logic performance. Currently, sub threshold leakage seems to be the dominant contributor to overall leakage power. Another possible contributor to leakage power is gate-oxide leakage. A possible solution widely reported is the potential use of high-k (high dielectric constant) gate insulators. In any case, this papers targets reduction of the sub threshold leakage component of static power consumption; other approaches (most likely orthogonal to what we propose here in this paper)

should be considered for reduction of gate oxide leakage. Do please note, however, that all results reported in this paper include all sources of leakage power (to the extent that the HSPICE models we use accurately model sources of leakage) With application of dual threshold voltage (Vth) techniques, the sleep, zigzag and sleepy stack approaches result in orders of magnitude sub threshold leakage power Reduction. The major advantage of the sleepy stack approach (see previous section) over the sleep and zigzag approaches is that the sleepy stack approach saves exact logic state. However, the sleepy stack approach carries a nontrivial penalty: each transistor in the original, base case, traditional CMOS design results in three transistors in the sleepy stack equivalent. The goal of our new approach is to achieve the benefit of the sleepy stack approach without the large associated penalties due to the tripled transistor count. One final comment about motivation is that we assume proper logic design and timing for transition to sleep mode for sleepy keeper VLSI circuits. In particular, we assume that there is a small delay (perhaps a few clock cycles) between the final computation in active mode and the transition to sleep mode. This allows the transition to sleep mode to only require that an existing logic state be maintained. Finally, we further assume that transition from sleep mode back to active mode also has a few clock cycles of delay between turning sleep transistors back on and beginning to actively calculate new logic values (i.e., beginning to change state again).

Chapter 3 APPROACH TO LOW LEAKAGE POWER
In this section, the structure and operation of our novel low-leakage-power design is described. It is also compared with well-known previous approaches, i.e., the sleepy stack, dual sleep and sleep transistor methods. First we explain the circuit operation for a chain of 4 inverters in sleep mode. In sleep mode, the sleep transistors are off, i.e. transistor N5 and P5 are off. We do so by making S=0 and hence S’=1. Now we see that the other 4 transistors P6, P7 and N6, N7 connect the main circuit with power rail. Here we use 2 pmos in the pull-down network and 2 nmos in the pull-up network. Block Diagram:

Figure 3.1: Low Leakage Power (a chain of 4 inverter)

So, the pass transistors decreases the voltage applied across the main circuit. As we know that static power is proportional to the voltage applied, with the reduced voltage the power decreases but we get the advantage of state retention. Another advantage is got during off mode if we increase the threshold voltage of N6, N7 and P6, P7. The transistors are held in reverse body bias. As a result their threshold voltage is high. High threshold voltage causes low leakage current and hence low leakage power. If we use minimum size transistors, i.e. aspect ratio of 1, we again get low leakage power due to low leakage current. As a result of stacking, P6 and N6 have less drain voltage. So, the DIBL effect is less for them and they cause high barrier for leakage current. While in active mode i.e. S=1 and S=0, both the sleep transistors (N5 and P5) and the parallel transistors (N6, N7 and P6, P7) are on. They work as transmission gate and the power connection is again established in uncorrupted way. Further they decrease the dynamic power. The sleep transistor efficiency is defined by a ratio of drain current in ON and OFF states. It is desirable to maximize the efficiency to achieve high drive in normal operation and low leakage in sleep mode. A high temperature is set on ON sleep transistor to model high chip temperature in operating mode and a low temperature is set on OFF sleep transistor to reflect the cool situation when the design is in sleep mode. The sleep transistor efficiency varies with gate length, width and body bias. The sleep transistor efficiency also depends on body bias because reversed body bias increases Vth and hence smaller sub-threshold leakage and higher efficiency.

Chapter 4 SIMULATION ENVIRONMENT
The simulation parameters have been analyzed with the help of the Micro wind tool and DSCH for the schematic verification. 4.1. DSCH (DIGITAL SCHEMATIC) DSCH is software for logic design. Based on primitives, a hierarchical circuit can be built and simulated. It also includes delay and power consumption evaluation. Silicon is for 3D display of the atomic structure of silicon, with emphasis on the silicon lattice, the dopants, and the silicon dioxide. 4.1.1 MOS as a switch The MOS transistor is basically a switch. When used in logic cell design, it can be on or off. When on, a current can flow between drain and source. When off, no current flow between drain and source. The MOS is turned on or off depending on the gate voltage. In CMOS technology, both n-channel (and nMOS) and p-channel MOS (or pMOS) devices exist. The nMOS and pMOS symbols are reported below.

Figure 4.1: Symbol of NMOS and PMOS

The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In contrary, the p-channel MOS device requires a logic value 0 to be on. When the MSO device is

on, the link between the source and drain is equivalent to a resistance. The order of range of this ‘on’ resistance is 100Ω-5KΩ. The ‘off’ resistance is considered infinite at first order, as its value is several MΩ. 4.1.2 Connecting Procedure Instantiate NMOS or PMOS transistors from the symbol library and place them in the editor window. Connect Vdd and GND to the schematic. Connect input button and output LED. The simulation output can be observed as a waveform after the application of the inputs as above. Click on the timing diagram icon in the icon menu to see the timing diagram of the input and output waveforms. The Verilog, Hierarchy and Netlist window appears. This window shows the Verilog representation of NORgate. Click OK to save the Verilog as a .txt file. 4.2. MICROWIND Micro wind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator. The Microwind program allows designing and simulating an integrated circuit at physical description level. The package contains a library of common logic and analog ICs to view and simulate. Microwind includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, Verilog compiler, tutorial on MOS devices). You can gain access to Circuit Simulation by pressing one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately. 4.2.1 MOS Layout Microwind is used to draw the MOS layout and simulate its behavior. The Microwind display window includes four main windows: • • The main menu The layout display window

• •

The icon menu The layer palette. The layout window features a grid, scaled in lambda (λ) units. The lambda unit is fixed to

half of the minimum available lithography of the technology. The default technology is a CMOS 6-metal layers 0.12µm technology, consequently lambda is 0.06µm (60nm). The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. By using the following procedure, you can create a manual design of the n-channel MOS. • Fix the first corner of the box with the mouse. While keeping the mouse button pressed, move the mouse to the opposite corner of the box. Release the button. This creates a box in polysilicon layer. The box width should not be inferior to 2 λ, which is the minimum width of the polysilicon box. • Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button. Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 2-3. N-diffusion boxes are represented in green. The intersection between diffusion and polysilicon creates the channel of the nMOS device.

Figure.4.2: Creating the N-channel MOS transistor

4.2.2 Static Mos Characteristics The MOS size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the value of the current. In Figure, the MOS width is 1.74µm and the length is 0.12µm. A high gate voltage (Vg =1.2V) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. You may change the voltage values of Vd, Vg, Vs by using the voltage cursors situated on the right side of the window. A maximum current around 1.5mA is obtained for Vg=1.2V, Vd=1.2V, with Vs=0.0. The MOS parameters correspond to SPICE Level 3.

Figure 4.3: Channel

NMOS

characteristics.

4.2.3 Manual Layout Design Click the icon MOS generator on the palette. The following window appears. By default the proposed length is the minimum length available in the technology (2 lambda), and the width is 10 lambda. In 0.12µm technology, where lambda is 0.06µm, the corresponding size is 0.12µm for the length and 0.6µm for the width. Simply click Generate Device, and click on the middle of the screen to fix the MOS device. Click again the icon MOS generator on the palette. Change the

type of device by a tick on p-channel, and click Generate Device. Click on the top of the NMOS to fix the PMOS device.

Figure 4.4: Selecting the PMOS device

4.2.4 Connection Between Devices (A) Metal To Poly As polysilicon is a poor conductor, metal is preferred to interconnect signals and supplies. Consequently, the input connection of the inverter is made with metal. Metal and polysilicon are separated by an oxide which prevents electrical connections. Therefore, a box of metal drawn across a box of polysilicon does not allow an electrical connection. To build an electrical connection, a physical contact is needed. The corresponding layer is called "contact". You may insert a metal-to-polysilicon contact in the layout using a direct macro situated in the palette. (B) Supply Connections The next design step consists in adding supply connections, that is the positive supply VDD and the ground supply VSS. We use the metal2 layer (Second level of metallization) to create horizontal supply connections. Enlarging the supply metal lines reduces the resistance and avoids electrical overstress. The simplest way to build the physical connection is to add a

metal/Metal2 contact that may be found in the palette. The connection is created by a plug called "via" between metal2 and metal layers. The final layout design step consists in adding polarization contacts. These contacts convey the VSS and VDD voltage supply close to the bulk regions of the device. Remember that the n-well region should always be polarized to a high voltage to avoid short-circuit between VDD and VSS. Adding the VDD polarization in the nwell region is a very strict rule. (C) Interconnects Up to 6 metal layers are available for signal connection and supply purpose. A significant gap exists between the 0.7µm 2-metal layer technology and the 0.12µm technology in terms of interconnects efficiency. Firstly, the contact size is 6 lambda in 0.7µm technology, and only 4 lambda in 0.12µm. This features a significant reduction of device connection to metal and metal2, as shown in figure 4-8. Notice that a MOS device generated using 0.7µm design rules is still compatible with 0.12µm technology. But a MOS device generated using 0.12µm design rules would violate several rules if checked in 0.7µm technology. Secondly, the stacking of contacts is not allowed in micro technologies. This means that a contact from poly to metal2 requires a significant silicon area as contacts must be drawn in a separate location. In deep-submicron technology (Starting 0.35µm and below), stacked contacts are allowed. 4.2.5 Simulation A simulation window appears with inputs and output, shows the tphl, tplh and tp of the circuit. The power consumption is also shown on the right bottom portion of the window. If you are unable to meet the specifications of the circuit change the transistor sizes. Generate the layout again and run the simulations till you achieve your target delays. Depending on the input sequences assigned at the input the output is observed in the simulation. The power value is also given. 4.2.6 Checking The Layout The Design Rule Checker (DRC) scans the design and verifies a set of design rules. The errors are highlighted in the display window, with an appropriate message giving the nature of

the error. Details about the position and type of error(s) appear on the screen. Only an error-free layout can be sent to fabrication.

Chapter 5 VERILOG HDL
5.1 WHAT IS HDL ? A typical Hardware Description Language (HDL) supports a mixed-level description in which gate and net list constructs are used with functional descriptions. This mixedlevel capability enables you to describe system architectures at a high level of abstraction, then incrementally refine a design’s detailed gate-level implementation. HDL descriptions offer the following advantages: • We can verify design functionality early in the design process. A design written as an HDL description can be simulated immediately. Design simulation at this high level at the gate-level before implementation — allows you to evaluate architectural and design decisions. • An HDL description is more easily read and understood than a netlist or schematic description. HDL descriptions provide technology-independent documentation of a design and its functionality. Because the initial HDL design description is technology independent, you can use it again to generate the design in a different technology, without having to translate it from the original technology. • Large designs are easier to handle with HDL tools than schematic tools.

5.2 VERILOG OVERVIEW: 5.2.1 Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description Language is a language used to describe a digital system, for example, a microprocessor or a memory or a simple flip-flop. This just means that, by using a HDL one can describe any hardware (digital) at any level.

Verilog provides both behavioral and structural language structures. These structures allow expressing design objects at high and low levels of abstraction. Designing hardware with a language such as Verilog allows using software concepts such as parallel processing and object-oriented programming. Verilog has a syntax similar to C and Pascal. 5.2.2 Design Styles Verilog like any other hardware description language permits the designers to create a design in either Bottom-up or Top-down methodology. 5.2.3 Bottom-Up Design The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standard gates. With increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new design practices it would be impossible to handle the new complexity. 5.2.4 Top-Down Design The desired design-style of all designers is the top-down design. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are mix of both the methods, implementing some key elements of both design styles. Complex circuits are commonly designed using the top down methodology. Various specification levels are required at each stage of the design process. 5.2.5 Abstraction Levels Of Verilog Verilog supports a design at many different levels of abstraction. Three of them are very important: • • Behavioral level Register-Transfer Level



Gate Level

5.2.6 Behavioral Level This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other. Functions, Tasks and Always blocks are the main elements. There is no regard to the structural realization of the design. 5.2.7 Register-Transfer Level Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing possibility; operations are scheduled to occur at certain times. Modern definition of a RTL code is "Any code that is synthesizable is called RTL code". 5.2.8 Gate Level Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this Netlist is used for gate level simulation and for backend. 5.3 VLSI DESIGN FLOW 5.3.1 Introduction Design is the most significant human endeavor: It is the channel through which creativity is realized. Design determines our every activity as well as the results of those activities; thus it includes planning, problem solving, and producing. Typically, the term "design" is applied to the planning and production of artifacts such as jewelry, houses, cars, and cities. Design is also found in problem-solving tasks such as mathematical proofs and

games. Finally, design is found in pure planning activities such as making a law or throwing a party. More specific to the matter at hand is the design of manufacturable artifacts. This activity uses all facets of design because, in addition to the specification of a producible object, it requires the planning of that object's manufacture, and much problem solving along the way. Design of objects usually begins with a rough sketch that is refined by adding precise dimensions. The final plan must not only specify exact sizes, but also include a scheme for ordering the steps of production. Additional considerations depend on the production environment; for example, whether one or ten million will be made, and how precisely the manufacturing environment can be controlled. A semiconductor process technology is a method by which working circuits can be manufactured from designed specifications. There are many such technologies, each of which creates a different environment or style of design.

Chapter 6 SIMULATION RESULTS
6.1 SCHEMATIC DESIGN FOR CIRCUIT:-

6.2 GENERATING VERILOG FILE:-

6.3 LAYOUT IN MICROWIND:-

6.4 ANALYSIS FOR VOLTAGE VS TIME :-

6.5 ANALYSIS FOR VOLTAGE VS CURRENT :-

6.6 ANALYSIS FOR FREQUENCY VS TIME :-

Chapter 7 APPLICATIONS AND ADVANTAGES
APPLICATIONS: • • • • Performance analysis of power gating designs in low power VLSI circuits. Resource allocation and binding approach for low leakage power. Scaling down of the CMOS technology feature size and threshold voltage for achieving high performance has resulted in increase of leakage power dissipation. A sleep transistor is implemented in a multi-finger configuration in layout to provide sufficient current. ADVANTAGES: • Mature technology: CMOS processes are well established and continue to become more mature. The powerful trust by leading edge digital memory and processors has led to continuous improvement and down scaling of CMOS processes.



Design resources: Circuit and system design in CMOS is supported by vast number resources. Many design techniques and design libraries for analog and digital design are available.



Availability: CMOS processes are now readily available for prototype designs through fabrication brokers, at low prices. This has boosted the design knowledge by real implementations, rather than pure theoretical treatments.



Price: CMOS is the cheapest process available, when compared against other technologies with the same minimum feature size.

LIMITATIONS: • Second order effects: In the scaling process some second order device characteristics, such as subthreshold operation, are usually ignored or paid less attention, and their cancellation is more desired than their improvement. • • Mismatch: Mismatch in CMOS devices is relatively high. Photodetectors: The photodetector structures are not characterized in any of the processes. It is the designer's responsibility to assure that the photodetectors function as desired in CMOS technology.

Chapter 8 CONCLUSION
In nanometer scale CMOS technology, sub threshold leakage power consumption is a great challenge. Although previous approaches are effective in some ways, no perfect solution for reducing leakage power consumption is yet known. Therefore, designers choose techniques based upon technology and design criteria. Scaling down of the CMOS technology feature size and threshold voltage for achieving high performance has resulted in increase of leakage power dissipation. We have presented an efficient methodology for reducing leakage power in VLSI design. The sleepy keeper technique results in ultra low static power consumption with state saving. Furthermore, the sleepy keeper approach is applicable to single and multiple threshold voltages. With application of dual Vth, sleepy keeper is the most efficient approach to reduce leakage current with the smallest delay and area increases while simultaneously preserving precise logic state in sleep mode. In terms of

area, the sleepy keeper approach is expected to be more attractive for complex logic circuits, because the portion of increased area for the required additional transistors will be smaller for complex logic circuits than for simple logic circuits (e.g., for an inverter).

FUTURE SCOPE:
For future work, scientists are planing to investigate why the sleepy keeper approach increases dynamic power consumption over the sleepy stack approach, aiming to reduce this increase in dynamic power consumption.

REFERENCES: 1 M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep submicron Cache Memories,” Proc. of International Symposium on Low Power Electronics and Design, pp. 90-95, July 2000. 2 J.C. Park, V. J. Mooney III and P. Pfeiffenberger, “Sleepy Stack Reduction of Leakage Power,” Proc. of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 148- 158, September 2004. 3 J. Park, “Sleepy Stack: a New Approach to Low Power VLSI and Memory,” Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005.

4

S. Mutoh, T. Douseki,. Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, “1-V Power Supply High-speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of Solis-State Circuits, vol. 30, no. 8, pp. 847–854, August 1995.

5

N. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir and V. Narayanan, “Leakage Current: Moore’s Law Meets Static Power,” IEEE Computer, vol. 36, pp. 68–75, December 2003.

6

K.-S. Min, H. Kawaguchi and T. Sakurai, “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clockgating Scheme in Leakage Dominant Era,” IEEE International Solid-State Circuits Conference,

7 8

pp. 400-401, February 2003. Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks,” Proc. of International Symposium on Low Power Electronics and Design, pp. 239-244, August 1998.

9

N. Karmakar, M. Z. Sadi, M. K. Alam and M. S. Islam, “A novel dual sleep approach to low leakage and area efficient VLSI design” Proc. 2009 IEEE Regional Symposium on Micro and Nano Electronics (RSM2009), Kota Bharu, Malaysia, August 10-12, 2009, pp. 409-414.

Appendix A VERILOG CODE FOR THE DESIGN

module lpr(b,c,a,out1); input(b,c,a); output(out1); pmos #(1) pmos(w3,w1,b); //2.0u 0.12u nmos #(1) nmos(w3,w4,b); //1.0u 0.12u pmos #(1) pmos(w5,w1,w3); //2.0u 0.12u

nmos #(1) nmos(w5,w4,w3); //1.0u 0.12u pmos #(1) pmos(w6,w1,w5); //2.0u 0.12u nmos #(1) nmos(w6,w4,w5); //1.0u 0.12u pmos #(1) pmos(out1,w1,w6); //2.0u 0.12u nmos #(1) nmos(out1,w4,w6); //1.0u 0.12u pmos #(1) pmos(w1,vdd,a); //2.0u 0.12u nmos #(1) nmos(vdd,w9,vdd); //1.0u 0.12u nmos #(1) nmos(w10,w1,vdd); //1.0u 0.12u nmos #(1) nmos(w4,vss,c); //1.0u 0.12u pmos #(1) pmos(w12,w4,vss); //2.0u 0.12u pmos #(1) pmos(vss,w13,vss); //2.0u 0.12u //simulation parameters in verilog format Always #10 b=~b #20 c=~c #30 a=~a //simulation process // b CLK 10 10 //c CLK 20 20 //a CLK 40 40

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