Xilinx - Solutions for Automotive
Content
Xilinx Solutions for
Automotive
Overview
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Automotive Market Overview
Automotive Applications
Challenges in Automotive Design
Xilinx Solutions for Automotive Applications
Customer Testimonials
Worldwide Market for
Automotive Electronics
Remote Key less Entry , Alarms, etc.
Instrumentation, Trip Computer
Climate Control, Adaptiv e & Passiv e
Cruise Control, Park Assis t, etc.
Brake-by -Wire, Conv entional/Adaptiv e
Airbag, ABS (Electronic Stability )
MOST, CAN, FlexRay , etc
Engine Management
Electronic Pow er Steering
Steer-by -w ire, etc.
Courtesy : IMS
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Automotive Semiconductors
• “It is now estimated that the cost of the electronics
in a new car rises by 9-16 percent each year. In
the 2001 model year, electronics accounted for 19
percent of a mid-sized vehicle's cost. In the year
2005, it may be 25 percent for mid-sized cars and
possibly 50 percent for luxury models. ”
Source: http://www.spectrum.ieee.org/WEBONLY/publicfeature/apr02/ecar.html Apr 12th, 02
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New Automotive
Applications
• Over 100 million vehicles are
registered in the US every year
• Average daily commute: 82
minutes
– Huge opportunity for productivity
while driving
• High potential for applications
in
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Communication
Music-on-demand
Real-time traffic information
Remote vehicle maintenance
Telematics
What is Telematics /
Infotainment?
• Wireless exchange or delivery of communication, information, and
other content between the auto and/or occupants and external
sources
– Navigation & route guidance
– Real-time information (traffic, news, business directories, Internet access /
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email)
Entertainment (broadcast & onboard)
Automated transactions (tolls, purchases)
Position reporting (via GPS)
Communications (broadcast, two way)
Stored onboard information databases
Services on demand (voice activated systems, vehicle tracking and
recovery)
New Revenue Opportunities for
Automotive Manufacturers
• Allows brand differentiation
• Recurring revenues from monthly services
• Mobile commerce enabled by GPS
– Advertisements/promotions based on location
• Multimedia specialized content transmission
– Stocks, news, weather, sports
• Better customer relationship management
• Remote diagnostics for regular maintenance checks
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Telematics Enabled
Car Sales
Courtesy: Telematics Research Group
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Automotive Market Dynamics
A Xilinx Perspective
• New business models for car manufacturers
– Common HW/SW platforms with ability for customization
• Unprecedented data processing and bandwidth demands
– Video (MPEG-2, MPEG-4), DSP (Software Defined Radios, etc.), and
connectivity (PCI, etc.)
• Networking comes to the vehicle
– Interfacing to multiple control networks remains a challenge (CAN, FlexRay)
– Providing high-speed media interfaces (MOST, IEEE1394, etc.)
– Enabling wireless technologies (Bluetooth, 3G, DAB, DVB-T)
• Time-to-market pressures and cost sensitivity remain drivers
• Multiple standards and no clear market direction
• ASSP solutions are not readily available
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Xilinx in Automotive
Applications
Communication
& Information
• GPS Navigation
• Driver Information
Systems
Entertainment
• Multimedia Systems
• Audio Systems
• Rear-seat
Entertainment
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Safety
• Distance Control
• Collision Avoidance
• Driver Support
Systems
Comfort
• Adaptive Cruise
Control
• Body Electronics
Control
• Voice Recognition
CarCube™ - The Telematics
Platform from Acunia & Xilinx
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Flexible & high performance
• MPEG-4 decode @ VGA 30fps
•
Speech recognition/text to speech
•
Wireless data (GPRS)
•
Voice communication
•
GPS with dead reckoning
•
Automotive compliant connectors
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Mass storage
•
Car bus connectivity
•
USB/expansion header
•
Steering wheel controls
More Info: www.xilinx.com/esp/reference_boards
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CarCube™ – A Programmable
Telematics Platform
The Xingu Architecture
Next Platform
More functionality
Lower cost
Customize Software
Customize Hardware
HMI
Voice recognition
Video Codecs, etc.
Support various
• Peripherals
• Car bus connectivity
• Memories (Flash,
SRAM, SDRAM
• Displays
Hardware acceleration
DSP for SDRs
More Info: www.xilinx.com/esp/reference_boards
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Automotive Applications
Issues and Challenges
• Integrating different standards
– Networking (MOST, CAN?)
– Video (LVDS?)
– System interfaces (PCI?)
• System control & peripherals
• µC & µP obsolescence
• Offloading H/W intensive
blocks from host CPU
• Software Defined Radios
• High-performance memory
support (DDR, QDR)
• Interfacing to various Flash
types (CF+, MMC/SD, etc.)
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EMI signal management
Display control
Content protection/encryption
Industrial temp parts
Overall cost management
Dynamic nature of products
– Multiple products required to
sell into different geographies
– Evolving specifications
– Competitive pressures to bring
new features rapidly to market
– In the field bug fixes and feature
enhancements
Applications for In-Vehicle
Networking
In Cockpit
Under the
Hood
Body
electronics
Information
Entertainment
LIN
CAN
IDB-C
IEEE-1394
MOST
IDB-1394
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What is LIN?
• LIN (Local Interconnect Network)
– Low cost body electronics network
– Consortium members include: Audi, BMW, Motorola,
DaimlerChrysler, VW and Volvo
– Open source (i.e., no license)
– www.lin-subbus.org
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What is CAN?
• Controller Area Network
• Originated in automotive industry as communications bus in
automobiles
• CAN is a communications bus used for distributed applications
• Used in safety-critical applications
• Uses twisted-pair media to carry signal
• Bus architecture
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•
CAN Applications and
Protocols
Applications
– Body electronics control (mirrors, defroster, air conditioning,
etc…)
– Receive engine diagnostic information from sensors
– Use CAN with IDB-C protocol stack for low-end multimedia
applications
• Proprietary protocols
– Example: ECU to ECU communication in a vehicle
• Open protocols based on CAN
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IDB-C (automotive)
J1939 (automotive)
DeviceNet (industrial)
CANOpen (industrial)
Key Features of MOST
• Designed for relatively low cost high-speed multimedia
applications
• Ease of use
– Simple connectors
– Plug-n-Play – Self identifying devices
• Wide application range
– Supports synchronous and asynchronous data transfer
– Supports multiple masters
– Supports up to 64 devices
• Robust
– High degree of data integrity
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MOST Automotive
Applications
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What is IDB-C?
• IDB-C is an automotive in-vehicle network architecture
– Managed by the IDB Forum
– IDB-C is defined in the SAE J2366 – ITS Data Bus series of
specifications
• Technology:
– IDB-C defines a set of standard interfaces
– IDB-C is based on CAN 2.0B (Controller Area Network) silicon
and physical layer, specifically on SAE J2284 - High Speed
CAN.
• History and implementation of IDB-C
– Specification currently in final review cycle
– Initial deployment in some model year 2002 vehicles
• IDB-C has been endorsed by the AMI-C consortium
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IDB-C Connectivity
• Ability to communicate diagnostic data, status,
control commands, and analog signals
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Speeds
1394b
3.2 Gbps
1394a
400 Mbps
MOST
45 Mbps
High speed
IDB-1394
IDB-C
CAN
LIN
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1 Mbps –
50 Kbps
< 20 Kbps
Low speed
IDB-C Physical Media
• Composed of multiple buses
1100101
Data bus (CAN) – transmits messages
Low impedance stereo audio bus (LISA)
– carries analog signals (3 pairs)
IDB-C
Key mode – carries state of vehicle ignition
Power bus
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What is IEEE-1394?
• Specification for a high
speed serial
communications bus
• Goal: Provide a single
serial bus connecting
consumer devices
together
• Also known as firewire
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IEEE-1394 Versions
• IEEE-1394 - 1995
– Initial version
– Maximum speed at 200 Mbps
• IEEE-1394a - 2000
– Increase maximum speed to 400 Mbps
• IEEE-1394b
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Longer cable lengths
Increase maximum speed to 3.2 Gbps
Makes use of optical fiber technology
Still in development
What is IDB-1394?
• IDB-1394 is an automotive in-vehicle network
architecture
– Managed by the IDB Forum
– Built on 1394 technology
– IDB-1394 supplements the
following standards:
• IEEE 1394-1995
• IEEE 1394a-2000
• IEEE p1394b
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IDB
Application Layer
CA N
Transport Layer
IEEE-1394
Transport Layer
CA N
Data Link Layer
IEEE-1394
Data Link Layer
CA N
Physical Layer
IEEE-1394
Physical Layer
Automotive Networking:
Summary
Infotainment
& Telematics
Systems
In-Vehicle
Devices
Under the
hood
CA N
In-cockpit
LIN
CA N
MOST
IDB- C
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Mobile
Consumer Devices
External
Infrastructure
Cellular
GPS
802.11b
Satellite Radio
IEEE-1394
Digital Terrestrial
Radio
IDB-1394
AM/FM Radio
Bluetooth
USB
Ir DA
PCMCIA
Serial
802.11b
IEEE-1394
In-Car Digital Convergence
• Technologies are based on multiple,
new and changing standards
– Bluetooth, WAP, GPS, MOST, CAN, etc.
• Integration of multiple complex
technologies in auto environment
– Display, computing, audio, RF, etc.
• Requires flexible solution
• Time-to-market pressures as
automotive is shrinking from 6 years to 2
• Traditional solution challenges
– Microcontroller - Insufficient compute capability
– ASIC - Design cycle flexibility, upgradeability
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Bridging Automotive Networks
Bridging Automotive
Networks
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Control Network
CAN
CAN
Multimedia Network
MOST
MOST
VAN
VAN
IEEE1394
IEEE1394
LIN
LIN
USB
USB
IDB
IDB
PCI
PCI
Proprietary
Proprietary
Proprietary
Proprietary
GPS Antenna
Wheel Sensors
Gyroscope
GPS Controller Unit
CAN Controller IP
• Features
– Industry proofed (Bosch
reference CAN model)
– CAN 2.0B, 1 Mbps
– Easy parallel interfaces
– Access to internal status
– Error reporting
– Fully synchronous
http://www.memecdesign.com/can_core/
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Lowest Cost Parallel
Interconnect Solutions
• Best value in popular cores
– PCI 32/33 effective cost below 75 cents* ($ .75)
• Physical interfaces and system elements
– 25 I/O standards, DDR I/O registers, DCMs
• Popular IP cores
– Pre-engineered, Drop-in functionality
– Fully compliant, Pre-verified
PCI 32/33 and 64/33
PCI 32-bit, 33 MHz under $ .75!
* Based on pricing for 2004, 250K units
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Xilinx PCI Solutions
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Networking Comes to Cars!
•Com fort
•Pow er Seat
•Pow er Mirrors
•Sunroof
•Climate Sensors
•Security
•Alar m
•Keyless Entry
•Non Safety Sensors
•Multimedia
•Radio
•DV D/CD
•TV/Internet
•Navigation
•GPS
•Instrumentation
•Cell Phone
•Voice Recognition
Controller Area Netw ork (CAN)
Vehicle Area Netw ork (VAN)
Local Interconnect Netw ork (LIN)
Intelligent Transportation Systems Data Bus ( IDB)
Media-Or iented Systems Transfer (MOST)
ISO 9141
J1850
Time- Triggered Protocol ( TTP/C)
D2B
Gateway
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•Engine Control
•Cruise Control
•Brakes
•ABS/TCS
•Brake-by-Wire
•Safety
•Airbags
•Collision Avoidance
Mobile Multimedia Link
IEEE1394
Connected Car PC
Domestic Digital Bus
Flex Ray
AutoPilot
Multi Media Link
Auto PC
Universal Serial Bus ( USB)
Car Multimedia System
32-bit CPU
SDRAM
SDRAM
RF
Tuner
External
Controls
Speakers
AC97
Codec
Drive
Unit
DVD
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Processor Interface
TFT LCD
DDR Memory
Controller
VGA Controller
Filtering &
Formatting
PCI Bridge
MOST Entertainment
User Interface
CAN 2.0B
Controller
Body
Electronics
AC 97 I/F
PCMCIA
ATAPI / IDE
Discrete CLK
Logic DLLs
Network
Plug-in Card
FPGA DSP Advantages
• Off the shelf devices
• Faster time-to-market
• Rapid adoption of
standards
• Real-time prototyping
Flexibility of DSP Processors
•
•
•
•
Parallel processing
Support high data rates
Optimal bit widths
No real-time SW coding
Performance of Custom ICs
Xilinx DSP Solutions Offer the Best of Both
Worlds at a Low Cost!
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Xilinx DSP Solutions
Performance and Flexibility
• Multi-billions MACs per second!
• Tremendous parallel processing capability
– Distributed DSP resources, segmented routing and flexible architecture allow
optimized implementation of algorithms
– No instruction flow overhead
• High-memory bandwidth
– Distributed RAM to store DSP coefficients and FIR filters
– True dual-port BlockRAM
• Optimized data buffering and storage
• Applications like FFT for next generation HDTV, video line buffers
• DLL for multi-rate clocks
• High I/O bandwidth and flexible interfaces
– Supports 20 high-speed signal & memory interface standards
• LVDS, LVTTL, SSTL, HSTL, GTL+, PECL …
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Enabling High-Speed DSP
Conventional DSP/Software
Data In
• Fix ed inflex ible architecture
Reg
Loop
Algorithm
256 times
– Typically 1-4 MA C units
– Fix ed data width
MAC unit
Data Out
e.g. 256 Tap FIR Filter = 256 MAC operatio ns per sample
256 MAC operations in 256 clock cycles in DSP!!
• Serial processing limits data
throughput
– Time-shared MA C unit
– High clock frequency creates
difficult system-c hallenge
Per for mance
Limitations
FPGA Performance Advantage
Data In
C0
Reg0
Reg1
C1
Reg255
Reg255
Reg2
C2
C255
• Flexible architecture
– Distribut ed DSP resources (LUT,
registers, multipliers, & memory )
• Parallel processing maximizes
data throughput
Data Out
– Support any level of parallelism
– Optimal performance/cost
tradeoff
e.g. 256 Tap FIR Filter = 256 MAC operations per sample
All 256 MAC operations in 1clock cycle in FPGA !!
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Unprecedented MathWorks/Xilinx
Partnership for Productivity
• The MathWorks & Xilinx have
an unprecedented strategic
partnership for DSP
MATLABTM
Algorithm Development
and Analysis
– Joint engineering for
robust/easy-to-use solutions
– Joint marketing/sales for easier
access to tools
• Seminars
• Promotions
– Joint DSP training worldwide for
rapid learning
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SimulinkTM
System-Level Design
Unrivaled DSP Performance
per Dollar
• Nearly 3 billion MACs/sec per
dollar
• Cost effective solution for low
cost DSP applications such as:
Embedded DSP Capability
Up to 104 18bit Multipliers!
18 Bit
36 Bit
– Digital communications,
video/imaging, & industrial control
18 Bit
• Simple design flow
– MathWorks (MATLAB/Simulink)
• Complete DSP solution
– Silicon, software, IP, services,
specialists & development
systems
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Simple and Familiar DSP Design Flow
The Only Complete Solution!
Highest Performance/Integration
Shortest Design Time
Familiar Design Flows
+ Leading- Edge Pr ocesses
+ 556 Embedded Multipliers (300MHz)
Advanced DSP Algorithms/Core s
DSP Development Boards
• Comprehensive Library
• Fast Turnaround
• Exceptional Performance
DSP Design Services
• 50+ Field DSP Experts
• Processor, I/O Experts too
DSP Training Classes
www.xilinx.com/dsp
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Dedicated Field Specialists
DSP Customer Hotline
SDR for Automotive
For Broadcast TV, Radio, GPS & Telephony
Digital Down/Up Conversion (DDC)
– Channel Center
– Decimation/Interpolation rates
– Compensation Filters
– Matched Filter a = {0.25,0.35,...}
FEC
– Convolutional
– Reed-Solomon
– Concatenated Coding
– Turbo CC/PC
– (De-)Interleave
Beam Forming
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Modulation Format
– QPSK
– DQPSK
– p/4 DQPSK
– {16,64,256,1024} QAM
– OFDM
– OFDM CDMA
Soft Radio
Digital
Signal
Processing
Engine
Security
Channel Access
– CDMA
– TDMA
DSSS
– Rake, track, acquire
– Multi User Detection (MUD)
– ICU
Network Interface Definition
Xilinx XtremeDSP
Development board
Courtesy of Nallatech : http://www.nallatech.com
• Suitable for SDR and 3G/4G algorithm and multimode transceiver development
• http://www.xilinx.com/ipcenter/dsp/development_kit.htm
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Image/Video Processing
• The Problem
– Industry is pushing for higher levels of video quality using
less bandwidth and processing limits are being reached
• How do you meet performance requirements? Can you remain
compatible with continuously evolving formats and standards?
• Xilinx Solutions
– Move computationally intensive portions like motion estimation and DCT from either
MPEG codec or a processor into low-cost Xilinx FPGA
• Deliver required performance whilst allowing processor to focus on tasks like running OS
– Use Xilinx XtremeDSP technology which exploits inherent parallelism in FPGAs to
perform DSP algorithms faster than any software or dedicated DSP device
– Allows experimentation with HW-SW design partitioning
• Develop new techniques or algorithms that lead directly to product differentiation
• Xilinx Image/Video Processing IP
– Color space conversion (RGB2YCrCb, YCrCb2RGB, RGB2YUV, YUV2RGB,etc.),
DCT/iDCT, FIR filters, DA FIR, FFTs ,MACs, MPEG-2 (SD & HD), JPEG, Huffman,
wavelet, scaling, rotation, enhancement
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Adaptive Cruise Control &
Collision Avoidance
SDRAM
SDRAM
Cameras
DDR Memory I/F
32-bit Soft-CPU
Other
Peripherals
Other DSP
Functions
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Obstacle
Detection
LVDS
Rx
Hardware
Decisions
Lane
Detection
Discrete CLK
Logic DLLs
Image
LVDS
Capture
Tx
Pipeline
PHY
6-Channel
CAN
Controller
CCD
CCD
Gyroscopes
PHY
Laser
PHY
Radar
PHY
Wheel Sensors
PHY Accelerator
PHY Brakes
Driver Support Systems:
Adaptive Cruise Control
• Adaptive cruise control or collision avoidance systems
– Video processing systems - rear view mirror & dash board
• Intensive digital signal processing required
– Xilinx FPGAs used aid with video image manipulation (DSP)
• Xilinx FPGAs offer extremely fast parallel digital signal
processing
• Parallel processing maximizes data throughput
– Support any level of parallelism
– Optimal performance/cost tradeoff
• FPGAs also support serial processing
– Standard digital signal processors process signals serially
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32-bit
Embedded
CPU
Applications
• Web tablets
• Internet appliances
•Telematics
• High-end PDAs
Processor Interface
Partial MPEG-4 H/W
Acceleration
Motion Estimation
Motion Compensation
DCT / IDCT
Other Custom Logic
Memory Controller
SRAM
SDRAM
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Dedicated
H/W
acceleration
blocks
Soft Processor Roadmap
A complete range of low-cost solutions that can be customized for any application
175
150
100 DMIPS
MHz
125
--bbiitt
2
2
3
3
e
BBllaazze
o
r
o
r
c
i
M
Mic
82 DMIPS
MicroBlaze
MicroBlaze 16-bit
16-bit
100
75
1/3
1/3 the
the size
size of
of 32-bit
32-bit MB
MB
49 DMIPS
49 DMIPS
50
½ the size of 16-bit MB
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2001
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2002
2003
2004
2005
MicroBlaze Soft Processor +
Spartan-3 FPGA
• Reduce design cost and inventory
– Integrate more features into one device
– Multiple designs addressed with a single processor solution
• Solve µC, µP obsolescence
– Buying the source code guarantees product availability
– Port the core across Xilinx product lines (Spartan and Virtex)
• Customized processor and peripheral set address
evolving design requirements
– An entire menu of peripherals to choose from and modify
– Reprogram your code to meet changing standards and
protocols
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MicroBlaze & Spartan-3 FPGAs: Industry’s
Lowest Cost Soft Processor Solution
• Effective cost - as low as $1.40
• Customized controller and peripheral
set to meet exact and evolving
design requirements
• Complete solution includes HW, SW,
tools and design examples
– Embedded Development Kit (EDK) support
offering common development environment
with Virtex-II Pro PowerPC-based solutions
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MicroBlaze Solution
• Soft processor core
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–
–
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32-bit - Harvard Bus RISC architecture
Size: 950 logic cells in Virtex-II and Virtex-II Pro
Size: 1050 logic cells in Spartan-IIE and Spartan-3
Speed: 150 MHz, 125 D-MIPS in Virtex-II Pro (-7)
32 general purpose registers; 3 Operand instruction format
• IBM CoreConnnect bus
• Standard peripheral set
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MicroBlaze IP Peripherals
Development Kit
• MicroBlaze CPU
• OPB arbiter
• Watchdog timer/timebase
• Timer/counter block
• Interrupt controller
• SRAM controller
• Flash memory controller
• ZBT memory controller
• BRAM
• UART Lite
• GPIO
• SPI master and slave
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Additional Peripherals
• UART 16550
• UART 16450
• IIC master & slave
• Ethernet 10/100 MAC
• ATM Utopia Level 2
• SDRAM
• DDR
System Diagram
r31
Machine Status Reg
I-LMB
Register
File
32 x 32bit
Program Counter
r1
r0
Control Unit
Instruction Buffer
Shift /
Add / Multiply
Multipl
Logical Subtr act Multiply
Data Bus Controller
Instruction Bus Controller
Address
side
LMB
Data Side
LMB
D-LMB
y
PROCESSOR
TM
CoreConnect
OPB I/F
Interrupt
Controller
UART
I-OPB
Off-Chip
Memory
0-4GB
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TM
CoreConnect
OPB I/F
D-OPB
Watchdog
Timer
General
Purpose I/O
PERIPHERALS
Timer /
Counters
Off-Chip
Memory
0-4GB
PicoBlaze
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PicoBlaze Application Examples
•
•
•
•
•
•
•
•
•
•
•
•
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Front panel switches and displays for set top box
Dynamic loop bandwidth multiplexer for frame to frame analysis
Link layer of IEEE 1394 interface
Microcontroller for compact flash programming engine
DECT radio/repeater
PCI board programming controller
Communications controller
Preprocessing for network processor
Motor controller
Programmable power supply controller
Part of Media Access Controller
Controller in broadcast video equipment and many more...
Memory Interfaces Are Not
All The Same
• Areas of variation
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–
–
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–
–
–
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Type – SRAM, SDRAM, SGRAM, Flash,….
Bit support
Density
Configuration sizes
OEM/ Vendor
Clock frequency
I/O performance
Burst size
Page size
CAS latency
Refresh cycle
Formats supported - Line doubling and quadrupling
Memory for Displays
Spartan Memory Controller
Reference Designs
• DRAM reference designs
– 64-bit DDR DRAM controller
– 16-bit DDR DRAM controller
– SDRAM controller
• SRAM reference designs
– ZBT SRAM controller
– QDR SRAM controller
• Embedded memory reference
designs
–
–
–
–
–
Data-width conversion FIFO
200 MHz FIFO
CAM for ATM applications
CAM using shift registers
CAM using Block SelectRAM
• Flash controller
– NOR / NAND flash controller
These Reference Designs are Available for Immediate
Download at the Memory Corner
http://www.xilinx.com/memory/
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Maximum Bandwidth
On-chip SelectRAM+™ Memory
Cache Tag memory
Large FIFOs
Packet buffers
Video line buffers
Deep/Wide
DSP coefficients
Scratch pad
Small FIFOs
Wide/shallow
Distributed RAM
Block RAM
Block RAM
Kilobytes
Bytes
High Speed Memory Interface
Excellent for large memory requirements
Megabytes
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Port B
Port A
External
Spartan-3
True Dual-Port
Block RAM
Multiple Storage Standards
• Many storage technologies addressing information appliance market
• Need for multi-standard support in these applications
CoolRunner-II offers flexibility to act as storage controller
between multiple technologies
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Display Controller & Driver
Xilinx
Non-Xilinx
Programmable
Programmable
Display
Display
Controller
Controller
* = Odd
** = Ev en
Backlight
Backlight
R
G
B
Graphics
Graphics
Processing
Processing
Panel
Panel
Timing
Timing
HSYNC
VSYNC
CLK
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R*
G*
B*
R**
G**
B**
LVDS
LVDS
R*
G*
B*
R**
G**
B**
HSYNC
HSYNC
VSYNC
VSYNC
CLK
CLK
FPGA Benefits and Value
Display and Timing Control
• Leverage existing designs/chipset to support multiple
display types
• Faster time-to-market
• Improved inventory control
• Customize products for different geographies
• Reduce exposure to supply issues
– Flexibility to efficiently manage component supply problems
• React quickly to competitive pressures
– Bringing new features/capabilities rapidly to market
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Content Protection &
Encryption
• Critical capability that requires high performance, yet is still highly
fluid and not standardized
– High performance content protection
• Real-time encoding/decoding of multi-Gbps data streams
• Flexibility
– Several methods of data encryption
•
•
•
•
RSA (Rivest-Shamir-Adleman), Diffie-Hellman, RC4/RC5
Secure Hashing Algorithm (SHA), Blowfish
Elliptic Curves, ElGamal, LUC (Lucas Sequence)
DES (Data Encryption Standard) & Triple-DES (TDES)
• Xilinx FPGAs with encryption IP
– AES, DES, Triple DES, proprietary
• Technology tutorials on eSP
– Encryption cores supported in Spartan-3
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Encryption - FPGAs
Add Significant Value
• Spartan-3 encryption
solutions are NIST
approved
• The programmable
nature of these
solutions allows easy
customization/flexibility
based on end
application requirement
• Hardware-based
solutions provide higher
performance
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Xilinx FPGAs Add Value By
Minimizing EMI Issues
• Xilinx offers “EMI friendly FPGAs”
–
–
–
–
–
–
Single-ended I/Os
Programmable output drive
Solve signal integrity issues even after PCB layout
Clock management
LVDS clock distribution
LVDS chip-to-chip connectivity
• Significant cost reduction
– EMI compliance testing and re-design is very expensive
• Time-to-market
– Get your product to market ahead of the competition / FCC
compliance
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Cost Management Through
System Integration
•
Replacing discrete parts
–
–
–
–
–
–
–
–
–
–
•
Benefits
–
–
–
–
–
64
Dual port memory/ FIFO
Clock buffers
Localized clock drivers
DLLs
Level translators
Hot socketing
Schmitt triggers
TTL devices
Backplane drivers
Board deskew
Cost savings
Fewer components
Board area savings
Higher reliability
Less EMI issues
Integration = BOM Reduction
Targeted for integration
into one-chip PLD solution
Courtesy: 9t htee.c om
65
Reducing the Overall BOM
Re-programmability
250KU Pricing
* High-volume pricing
estimate
Additional features using
Programmable Logic for
FREE !!
Time-to-market
Board Area
Power Savings
Solution Cost
Performance
Additional Logic
Additional Memory
$11.82
$5.73
$3.16
$1.96
$0.91
Additional I/O
Clock Management
$5.09*
Buffers / Drivers
$2.57*
UART
$2.20*
Watchdog Timer
$1.05*
Discrete Logic
Chips
$0.91*
Standard Solutions
66
Save $7.87
3S50
TQ144C
Spartan-3 Solution
$3.95
Introducing
Spartan-3
Xilinx’ Latest Solution for the
Automotive Markets
The Spartan-3 Platform:
A New Class of Spartan FPGAs
Advanced FPGA
Logic with Staggered
Pad Technology
XCITE
Digitally
Controlled
Impedance
90 nm
18 Bit
18 Bit
36 Bit
Embedded
XtremeDSP
Functionality
SelectIO™-Ultra
Technology
VCCIO
Z
Z
Impedance
Z Contro l
DCM
High Performance
Sync Dual-Port™
RAM
68
DCM™ Digital
Clock
Management
Highest Density with Low Cost
90 nm Process Delivers Higher Yields at Higher Densities
100
Density Leadership
90 nm
Process Yield %
80
60
40
180 nm
20
0
0.5
69
“The companies that get into 90nm
production first will get a tremendous
advantage in lower cost….. Rivals who
are late in 90nm process technology
will fall behind and may not be able to
catch up.”
Dan Hutcheson
VLSI Research, Inc.
1
1.5
2
2.5
Density (Million Gates)
3
- Faster performance
- Large density devices
- Lower cost devices
Spartan-3 Product Matrix
Device
System Gates
Logic Cells
Dedicated Multipliers
Block RAM Blocks
XC3S50
50K
1,728
-
XC3S200
200K
4,320
12
12
Block RAM Bits
Distributed RAM Bits
DCMs
I/O Standards
12K
24
216K
30K
4
24
288K
56K
4
24
432K
120K
4
24
576K
208K
4
24
720K
320K
4
24
1,728K
432K
4
24
1,872K
520K
4
24
Max Differential I/O
Max Single Ended I/O
22x22mm
TQ144
30.6x30.6mm
PQ208
17x17mm
FT256
23x23mm
FG456
27x27mm
FG676
31x31mm
FG900
56
124
97
124
76
173
116
264
175
391
221
487
270
565
312
712
344
784
141
173
141
173
264
173
333
391
333
487
489
565
633
633
70
XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000
400K
1000K
1500K
2000K
4000K
5000K
8,064
17,280
29,952
46,080
62,208
74,880
16
24
32
40
96
104
16
24
32
40
96
104
Spartan-3 Summary
71
Performance & Density
PLD Application Trends
Counters
Adders
Data Path
Memory
Controllers
uControllers
7400 Series
1980s
72
1990s
Industrial
Medical Imaging
Test and Measurement
Industrial Automation
PCI/PCI-X
Control systems
FEC
Consumer
FFT/FIR Filters
Set-Top Boxes/HDTV s
IMA (ATM)
Telematics
Encryption
Home Networking
MP3 Decoder
Networking
xDSL Modems
Line Cards
Computers
Graphic Cards
Printers
2000s
Price
FPGA Price Reduction
Time
10,000% Reduction
Price of 100K FPGA Gates Over Time
73
CoolRunner-II CPLD
One Ultimate CPLD Solution for All Designs
High Performance
3.5ns tPD, fmax 303Mhz
Improved features
Storage Systems, Routers
Lowest Power
Low Cost
12mW*
0.18µ = small die size
Lowest cost packaging ~20uA typical stand-by
Set-Top Box, Cell phone Handheld, Portable Equipment
* Estimated 128 macrocell dev ic e, Eight 16-bit counters @ 50M Hz
74
CoolRunner-II Family Overview
XC2C32
XC2C64
XC2C128
XC2C256
XC2C384
XC2C512
T pd (ns)*
3.5
4.0
4.5
5.0
6.0
6.0
Max. I/O
I/O Banks
33
1
64
1
100
2
184
2
240
4
270
4
I/O
Standards
Clock Doubler,
Input Hysteresis
Clock Divide,
CoolCLOCK,
DataGATE
LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS
15*,18,25,33
15*,18,25,33
15*,18,25,33
15*,18,25,33
15*,18,25,33
15*,18,25,33
SSTL 2-1,3-1
SSTL 2-1,3-1
SSTL 2-1,3-1
SSTL 2-1,3-1
HSTL 1
HSTL 1
HSTL 1
HSTL 1
yes
n ot
not
neece ss ar y n ec es sa r y
VQ44
PC44
CP56
Packages
* Note: T
75
PD
yes
VQ44
PC44
CP56
VQ100
yes
yes
yes
yes
yes
yes
yes
yes
VQ100
CP132
TQ144
VQ100
CP132
TQ144
PQ208
FT256
TQ144
PQ208
FT256
FG324
PQ208
FT256
FG324
speeds are preliminary and 1.5V LVCMOS inputs need hysteresis
CoolRunner-II I/O Support
I/O Standard
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
1.5V I/O
HSTL-1
SSTL2-1
SSTL3-1
VCCIO
Input
V REF
Board Termination
Voltage (VTT)
3.3
N/A
N/A
3.3
N/A
N/A
2.5
N/A
N/A
1.8
N/A
N/A
1.5
N/A
N/A
1.5
0.75
0.75
2.5
1.25
1.25
3.3
1.5
1.5
• Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V and
3.3V logic levels on all parts
• LVTTL and LVCMOS available on all devices
• SSTL2-I, SSTL-3-I and HSTL-I on 128 macrocell and
denser devices
76
Low Cost Packaging Options
17.6 mm
44 PLCC
12 mm
8 mm
6 mm
6 mm
Uses standard IR techniques
for mounting to PC board
77
8 mm
56 CP
12 mm
132 CP
17.6 mm
44 VQFP
CoolRunner Reference Designs
• Finish designs faster with FREE reference designs
• Increase the capability of the CPLDs you use
Type
PDA
Processor
Periphe ral
Encoder
De coder
Wireless
Refe rence
Number
XPATH Module Design
XAPP356
8 Channel DVM Springboard XAPP146
Springboard Module Design XAPP147
8051 Microcontroller Interface XAPP349
SPI
XAPP348
IrDA and UART
XAPP345
UARTS
XAPP341
SMBus Controller
XAPP353
Manchester Encoder/Decoder XAPP339
16b/20b Encoder/Decoder
XAPP336
XAPP333
I2C Bus Controller
Wireless Transciever
XAPP358
Reference Design
Lanaguage
Macrocell
VHDL
Pocket C, VHDL
Pocket C, VHDL
VHDL
VHDL
VHDL or Verilog
VHDL or Verilog
VHDL
VHDL or Verilog
VHDL
VHDL or Verilog
VHDL
225
184
67
57
135
87
61
158
55
76
131
156
Recommended
%
Target Device Utilizatiion
XC2C384
58
XC2C256
71
XC2C128
52
XC2C64
89
XC2C256
52
XC2C128
67
XC2C128
47
XC2C256
61
XC2C64
85
XC2C128
59
XC2C256
51
XC2C256
60
Coming soon – N x N Crosspoint Switch, MP3 Player, NAND Flash Interface, Error Detection & Correction
78
Xilinx IQ Solutions
Silicon for Automotive
Applications
Introducing IQ Products
• Why IQ?
– New array of devices guaranteed over an extended
temperature range
– Consists of CPLD and FPGA families already available in
I Grade - and the addition of selected devices with an
extended temperature ‘Q’ grade option
– IQ - it’s the intelligent choice for automotive designers!!
• For FPGAs Q grade means:
– -40°C to +125°C junction temperature
• For CPLDs Q grade means:
– -40°C to +125°C ambient temperature
Ambient = the temperature of the air surrounding the device
Junction = is the temperature of the die in the package
80
Quality and Traceability
• Full mask set control
– Every time a part is ordered it will have the same
die revision for up to 10 years (if required)
• Fab, assembly and test flow consistency (if required)
– Manufactured in the same fab location and same package
manufacturer location
• Traceability required for AEC and TS16949 standards
• Fully characterized to operate from –40ºC to +125ºC
(ambient temperature for CPLDs and junction
temperature for FPGAs)
• All Xilinx production partner fabs are qualified to QS9000
• PPAP data available on request
81
XCS30XL TQ144 di ssipating 600mW in still air
125°C
105°C
Q-grade
TJ = 125° C
I-grade
TJ = 100° C
C-grade
TJ = 85° C
85°C
TJ
70°C
Chip Temperature
Rise
vs. Ambient
TA
XCS30XL TQ144 di ssipating 1.5W in still air
155°C
140°C
Temperature is design dependant
- May be able to use Xpower to
determine customer design power
consumption
Q-grade
TJ = 125° C
125°C
105°C
I-grade
TJ = 100° C
C-grade
TJ = 85° C
85°C
70°C
TA
82
TJ
IQ Solutions
• Multiple components
– Programmable products
– IP cores
– System solution boards
– Design services
– eSP web portal
– Customer education
• PLD family members available in the range of
-40°C to +125 C :
Device Type
Spartan XL
XC9500XL
Release Schedule
CoolRunner XPLA3
XCS05XL, XCS10XL, XCS20XL, XCS30XL, XCS40XL - NOW
XC9536XL, XC9572XL - NOW
XC9535, XC9572 - NOW
XCR3032XL, XCR3064XL, XCR3128XL, XCR3256XL, XCR3384XL, XCR3512XL - NOW
Spartan-II
XC2S15, XC2S30, XC2S50, XC2S100, XC2S150, XC2S200 - NOW
CoolRunner-II
Spartan-IIE
Q3CY03
XC9500
83
Q2CY03
The Xilinx IQ Total Solution
• eSP web portal dedicated to accelerating all
phases of product development
– Automotive (new)
– Telematics (new)
– GPS
– DVD
• System solution boards
– Turn-key solutions
developed with
partners to
accelerate product
development
84
• Design services
– Providing concept
to completion
– Bridging the
technology and
knowledge gap
• IP - LogiCores &
AllianceCore
– Ex: multiplexers,
parallel to serial
converters, error
correction, and
encryption
Density
Automotive Silicon Road Map
2.5V
15K - 200K Gates
50K - 600K Gates
1.8V
3.3V
5k - 40k Gates
XC9500
5V
35-72
Macrocells
32-512 Macrocells
32-512 Macrocells
36-72 Macrocells
Time
85
Xilinx Quality Standard Roadmap
Q1’ CY05
ISO9000/QML/PURE/
TL9000/QS9000
Q4’ CY03
ISO9000/QML/PURE/TL9000
TODAY
ISO9000:2000
ISO9000/QML/PURE
ISO-9000:1994 meet
minimum requirements
QML, PURE Certified
ISO-14000 ( Q4CY2001)
Quality systems
− focus on re-estabilization
− Meet customer rqts.
Wim’s Quality Initiatives
− Internalize w orldw ide
− WW training
− Continuous drive needed
as part of our “values”
86
ISO-9000:2000
PAST
ISO9000/QML/PURE
TL9000 (Telec. Stds.)
Emphasis on
continuous
improvement
Customer input is
significant
Top management
quality review
Analysis & Use of
Data ( FOL --> EOL,
SPC, Metrics)
Comple te d in July 02
QS9000 or TS16949
Systems Expectations for
Automotive Industry
Customer and Supplier
relationship
Top Mgmt Involvement
Telecom Industry Standards
Des ign Process Control
Des ign Control, NPI,
Traceability/ Pr od. I.D.,
¾Des ign Control,
Pr oduct Lifecycle,
NPI, Traceability/
PCN/PDN)
Pr od. I.D., Product
Significant Involvement and
Lifecycle, PCN/PDN)
Participation of Top Mgmt
Specific Emphasis on
(Softw are, Hardw are)
statistical tools &
Emphasis on continuous
techniques continuous
improvement and customer
satisfaction
improvement
High on balanced metrics
¾Gauge R&R; SPC
and communication
Charts, FMEA
systems, tracking results
¾Supplier - customer
relationship
¾performance feedback
¾problem escalation &
resolution
Xilinx Automotive IP
• Ready-made and customizable DSP building blocks
– DSP functions
• FIR filters, DA FIR, FFTs, MAC, sine, cosine, etc.
– Base arithmetic functions
• Addition, subtraction, multiplication, division, square-root
– Memory functions
• Asynchronous FIFOs, synchronous FIFOs, block memory modules,
frame buffers, CAMs, shift-registers, flip-flops
– Basic logic functions
• Gate modules, multiplexers, decoders, accumulators, comparators,
counters
www.xilinx.com/ipcenter
87
Xilinx Automotive IP
• Microprocessor
– 8, 16, 32-bit soft processors
• Peripherals
– UART, SPI, timers, DMAs
• Memory controllers
– SRAM: ZBT, QDR
– SDRAM: SDRAM, DDR
– Flash: CompactFlash, MMC, SD card, MemoryStick, IDE
• System interfaces
– PCI, PCI-X, CAN, Rapid I/O
• Engine control - Zionix
– Tunable “TPU” (spark, fuel control), PWM, fuel injection, position tracking
www.xilinx.com/ipcenter
88
Xilinx Automotive IP
• Encoding/Decoding
– Compression
• DCT/IDCT, motion compensation/estimation
• DWT
• MPEG-4, MPEG-2, JPEG2000 CODEC
– Color space conversion
• RGB2YCrCb, YCrCb2RGB, RGB2YUV, YUV2RGB, etc.
– Forward error correction
• Reed-Solomon, Viterbi, Convolutional
• Encryption/Decryption
– AES (Rijndael), DES, TDES, RSA, MD5, Blowfish, SHA, etc.
www.xilinx.com/ipcenter
89
Shorter Development Cycles
Increase Revenue Potential
ASIC SOC designs average 14-24 months
Specification
Implementation
Verification
Prototyping
Evaluation
Development time
averages 55% less with
FPGA*
FPGA designs average 6-12 months
0
1
2
3
4
5
6
7
8
9
10
11
12
Units of time (person-months)
Source: Harvard S tudy
90
* Based on an average of 391 different sized designs
13
14
15
16
17
18
Xilinx Maximizes Profitability
In The Market
• Products that are 6 months late and on budget earn 33% less profit over 5 yrs+
• A delay every 4 weeks equals 14% loss in market share#
Market Peak
(Time in Market Advantage)
Profit for first
to market
Field
Upgradability
with Xilinx
Reduced Profit
for Late Comers
Xilinx Product Availability
Start of market window
2:1 TTM Advantage with Xilinx
* Sourc e: Current and Emerging Embedded Markets and Opportunities – Elect ronicMarket Forec asters
† Source: McKinsey & Co. , # Source: John Chambers
WindRiver Systems, Inc.
91
End of market window
Summary
• Rapid growth and change occurring in automotive
applications
• Designers of automotive electronics presented with
numerous issues and challenges
• Telematics a key enabler to incremental revenues for car
manufacturers
• Time-to-market, flexibility, reprogrammability desired
• Xilinx solutions are the perfect answer for automotive
applications
92
Other Customer
Testimonials
Xilinx in Infotainment
Systems – Siemens VDO
• Siemens VDO Dayton
– Integrated entertainment system
– CD tuner w/ MP3, 3D display, and
hands free phone
• Spartan-II FPGAs
– Perform peripheral
interfacing and audio control
– Selected for
• Field reprogrammability to
accomodate changing standards
• Ease-of-use, low cost
Siemens VDO has been using Xilinx FPGAs for its
advance in-car systems since 1997
94
95
Automotive Test Equipment
• In-car bus networks are changing - CAN may be adopted in US
• Changing standards mean the need for adaptive and
reconfigurable test equipment
• Auto Xray used Spartan FPGAs in their automotive handheld
testers so that their customers never have to buy a new unit simply upgrade the hardware over the Internet
• The scanner is battery powered so needed low power devices Spartan-XL power down mode or CoolRunner CPLDs
"Vehicle standards are constantly changing and the Spartan
FPGAs provide us with the ability to reprogram our hardware
whenever necessary. The Xilinx FPGA allows our customers
to upgrade software and hardware right over the Internet"
Bill Miller, President of AutoXray
96
97
Spartan Automotive
Application Example
• Application: In-car navigation system
• Device: XC2S50, Spartan-II, 50k system gates
• Reasons for using Xilinx:
– Software and technical support
was of the highest quality
– Moving from prototype to production
was seamless
– Device can be easily upgraded to give extra functionality and
features
– The price was surprisingly low and competed well with the
ASIC alternative but with no NRE
98
SiRF Case Study
"With very low power
• FCC recently issued Enhanced-911
consumption, chip scale
(E-911) initiative
packaging and minimal
• Requires all cellular companies to
heat dissipation, CoolRunner
be able to connect emergency calls
CPLDs were an easy choice”
- Greg Turetzky, SiRF
and deliver their location to within
150m to 911 operators
• SiRF developed a chipset to enable GPS in cell phones for this
initiative but needed a way to link signals to processor interface
• Stiff competition in this emerging market means time-to-market is
paramount
• CoolRunner CPLDs were the ideal solution for the interface
99
Automotive
Overview
•
•
•
•
•
2
Automotive Market Overview
Automotive Applications
Challenges in Automotive Design
Xilinx Solutions for Automotive Applications
Customer Testimonials
Worldwide Market for
Automotive Electronics
Remote Key less Entry , Alarms, etc.
Instrumentation, Trip Computer
Climate Control, Adaptiv e & Passiv e
Cruise Control, Park Assis t, etc.
Brake-by -Wire, Conv entional/Adaptiv e
Airbag, ABS (Electronic Stability )
MOST, CAN, FlexRay , etc
Engine Management
Electronic Pow er Steering
Steer-by -w ire, etc.
Courtesy : IMS
3
Automotive Semiconductors
• “It is now estimated that the cost of the electronics
in a new car rises by 9-16 percent each year. In
the 2001 model year, electronics accounted for 19
percent of a mid-sized vehicle's cost. In the year
2005, it may be 25 percent for mid-sized cars and
possibly 50 percent for luxury models. ”
Source: http://www.spectrum.ieee.org/WEBONLY/publicfeature/apr02/ecar.html Apr 12th, 02
4
New Automotive
Applications
• Over 100 million vehicles are
registered in the US every year
• Average daily commute: 82
minutes
– Huge opportunity for productivity
while driving
• High potential for applications
in
–
–
–
–
5
Communication
Music-on-demand
Real-time traffic information
Remote vehicle maintenance
Telematics
What is Telematics /
Infotainment?
• Wireless exchange or delivery of communication, information, and
other content between the auto and/or occupants and external
sources
– Navigation & route guidance
– Real-time information (traffic, news, business directories, Internet access /
–
–
–
–
–
–
6
email)
Entertainment (broadcast & onboard)
Automated transactions (tolls, purchases)
Position reporting (via GPS)
Communications (broadcast, two way)
Stored onboard information databases
Services on demand (voice activated systems, vehicle tracking and
recovery)
New Revenue Opportunities for
Automotive Manufacturers
• Allows brand differentiation
• Recurring revenues from monthly services
• Mobile commerce enabled by GPS
– Advertisements/promotions based on location
• Multimedia specialized content transmission
– Stocks, news, weather, sports
• Better customer relationship management
• Remote diagnostics for regular maintenance checks
7
Telematics Enabled
Car Sales
Courtesy: Telematics Research Group
8
Automotive Market Dynamics
A Xilinx Perspective
• New business models for car manufacturers
– Common HW/SW platforms with ability for customization
• Unprecedented data processing and bandwidth demands
– Video (MPEG-2, MPEG-4), DSP (Software Defined Radios, etc.), and
connectivity (PCI, etc.)
• Networking comes to the vehicle
– Interfacing to multiple control networks remains a challenge (CAN, FlexRay)
– Providing high-speed media interfaces (MOST, IEEE1394, etc.)
– Enabling wireless technologies (Bluetooth, 3G, DAB, DVB-T)
• Time-to-market pressures and cost sensitivity remain drivers
• Multiple standards and no clear market direction
• ASSP solutions are not readily available
9
Xilinx in Automotive
Applications
Communication
& Information
• GPS Navigation
• Driver Information
Systems
Entertainment
• Multimedia Systems
• Audio Systems
• Rear-seat
Entertainment
10
Safety
• Distance Control
• Collision Avoidance
• Driver Support
Systems
Comfort
• Adaptive Cruise
Control
• Body Electronics
Control
• Voice Recognition
CarCube™ - The Telematics
Platform from Acunia & Xilinx
•
Flexible & high performance
• MPEG-4 decode @ VGA 30fps
•
Speech recognition/text to speech
•
Wireless data (GPRS)
•
Voice communication
•
GPS with dead reckoning
•
Automotive compliant connectors
•
Mass storage
•
Car bus connectivity
•
USB/expansion header
•
Steering wheel controls
More Info: www.xilinx.com/esp/reference_boards
11
CarCube™ – A Programmable
Telematics Platform
The Xingu Architecture
Next Platform
More functionality
Lower cost
Customize Software
Customize Hardware
HMI
Voice recognition
Video Codecs, etc.
Support various
• Peripherals
• Car bus connectivity
• Memories (Flash,
SRAM, SDRAM
• Displays
Hardware acceleration
DSP for SDRs
More Info: www.xilinx.com/esp/reference_boards
12
Automotive Applications
Issues and Challenges
• Integrating different standards
– Networking (MOST, CAN?)
– Video (LVDS?)
– System interfaces (PCI?)
• System control & peripherals
• µC & µP obsolescence
• Offloading H/W intensive
blocks from host CPU
• Software Defined Radios
• High-performance memory
support (DDR, QDR)
• Interfacing to various Flash
types (CF+, MMC/SD, etc.)
13
•
•
•
•
•
•
EMI signal management
Display control
Content protection/encryption
Industrial temp parts
Overall cost management
Dynamic nature of products
– Multiple products required to
sell into different geographies
– Evolving specifications
– Competitive pressures to bring
new features rapidly to market
– In the field bug fixes and feature
enhancements
Applications for In-Vehicle
Networking
In Cockpit
Under the
Hood
Body
electronics
Information
Entertainment
LIN
CAN
IDB-C
IEEE-1394
MOST
IDB-1394
14
What is LIN?
• LIN (Local Interconnect Network)
– Low cost body electronics network
– Consortium members include: Audi, BMW, Motorola,
DaimlerChrysler, VW and Volvo
– Open source (i.e., no license)
– www.lin-subbus.org
15
What is CAN?
• Controller Area Network
• Originated in automotive industry as communications bus in
automobiles
• CAN is a communications bus used for distributed applications
• Used in safety-critical applications
• Uses twisted-pair media to carry signal
• Bus architecture
16
•
CAN Applications and
Protocols
Applications
– Body electronics control (mirrors, defroster, air conditioning,
etc…)
– Receive engine diagnostic information from sensors
– Use CAN with IDB-C protocol stack for low-end multimedia
applications
• Proprietary protocols
– Example: ECU to ECU communication in a vehicle
• Open protocols based on CAN
–
–
–
–
17
IDB-C (automotive)
J1939 (automotive)
DeviceNet (industrial)
CANOpen (industrial)
Key Features of MOST
• Designed for relatively low cost high-speed multimedia
applications
• Ease of use
– Simple connectors
– Plug-n-Play – Self identifying devices
• Wide application range
– Supports synchronous and asynchronous data transfer
– Supports multiple masters
– Supports up to 64 devices
• Robust
– High degree of data integrity
18
MOST Automotive
Applications
19
What is IDB-C?
• IDB-C is an automotive in-vehicle network architecture
– Managed by the IDB Forum
– IDB-C is defined in the SAE J2366 – ITS Data Bus series of
specifications
• Technology:
– IDB-C defines a set of standard interfaces
– IDB-C is based on CAN 2.0B (Controller Area Network) silicon
and physical layer, specifically on SAE J2284 - High Speed
CAN.
• History and implementation of IDB-C
– Specification currently in final review cycle
– Initial deployment in some model year 2002 vehicles
• IDB-C has been endorsed by the AMI-C consortium
20
IDB-C Connectivity
• Ability to communicate diagnostic data, status,
control commands, and analog signals
21
Speeds
1394b
3.2 Gbps
1394a
400 Mbps
MOST
45 Mbps
High speed
IDB-1394
IDB-C
CAN
LIN
22
1 Mbps –
50 Kbps
< 20 Kbps
Low speed
IDB-C Physical Media
• Composed of multiple buses
1100101
Data bus (CAN) – transmits messages
Low impedance stereo audio bus (LISA)
– carries analog signals (3 pairs)
IDB-C
Key mode – carries state of vehicle ignition
Power bus
23
What is IEEE-1394?
• Specification for a high
speed serial
communications bus
• Goal: Provide a single
serial bus connecting
consumer devices
together
• Also known as firewire
24
IEEE-1394 Versions
• IEEE-1394 - 1995
– Initial version
– Maximum speed at 200 Mbps
• IEEE-1394a - 2000
– Increase maximum speed to 400 Mbps
• IEEE-1394b
–
–
–
–
25
Longer cable lengths
Increase maximum speed to 3.2 Gbps
Makes use of optical fiber technology
Still in development
What is IDB-1394?
• IDB-1394 is an automotive in-vehicle network
architecture
– Managed by the IDB Forum
– Built on 1394 technology
– IDB-1394 supplements the
following standards:
• IEEE 1394-1995
• IEEE 1394a-2000
• IEEE p1394b
26
IDB
Application Layer
CA N
Transport Layer
IEEE-1394
Transport Layer
CA N
Data Link Layer
IEEE-1394
Data Link Layer
CA N
Physical Layer
IEEE-1394
Physical Layer
Automotive Networking:
Summary
Infotainment
& Telematics
Systems
In-Vehicle
Devices
Under the
hood
CA N
In-cockpit
LIN
CA N
MOST
IDB- C
27
Mobile
Consumer Devices
External
Infrastructure
Cellular
GPS
802.11b
Satellite Radio
IEEE-1394
Digital Terrestrial
Radio
IDB-1394
AM/FM Radio
Bluetooth
USB
Ir DA
PCMCIA
Serial
802.11b
IEEE-1394
In-Car Digital Convergence
• Technologies are based on multiple,
new and changing standards
– Bluetooth, WAP, GPS, MOST, CAN, etc.
• Integration of multiple complex
technologies in auto environment
– Display, computing, audio, RF, etc.
• Requires flexible solution
• Time-to-market pressures as
automotive is shrinking from 6 years to 2
• Traditional solution challenges
– Microcontroller - Insufficient compute capability
– ASIC - Design cycle flexibility, upgradeability
28
Bridging Automotive Networks
Bridging Automotive
Networks
29
Control Network
CAN
CAN
Multimedia Network
MOST
MOST
VAN
VAN
IEEE1394
IEEE1394
LIN
LIN
USB
USB
IDB
IDB
PCI
PCI
Proprietary
Proprietary
Proprietary
Proprietary
GPS Antenna
Wheel Sensors
Gyroscope
GPS Controller Unit
CAN Controller IP
• Features
– Industry proofed (Bosch
reference CAN model)
– CAN 2.0B, 1 Mbps
– Easy parallel interfaces
– Access to internal status
– Error reporting
– Fully synchronous
http://www.memecdesign.com/can_core/
30
Lowest Cost Parallel
Interconnect Solutions
• Best value in popular cores
– PCI 32/33 effective cost below 75 cents* ($ .75)
• Physical interfaces and system elements
– 25 I/O standards, DDR I/O registers, DCMs
• Popular IP cores
– Pre-engineered, Drop-in functionality
– Fully compliant, Pre-verified
PCI 32/33 and 64/33
PCI 32-bit, 33 MHz under $ .75!
* Based on pricing for 2004, 250K units
31
Xilinx PCI Solutions
32
Networking Comes to Cars!
•Com fort
•Pow er Seat
•Pow er Mirrors
•Sunroof
•Climate Sensors
•Security
•Alar m
•Keyless Entry
•Non Safety Sensors
•Multimedia
•Radio
•DV D/CD
•TV/Internet
•Navigation
•GPS
•Instrumentation
•Cell Phone
•Voice Recognition
Controller Area Netw ork (CAN)
Vehicle Area Netw ork (VAN)
Local Interconnect Netw ork (LIN)
Intelligent Transportation Systems Data Bus ( IDB)
Media-Or iented Systems Transfer (MOST)
ISO 9141
J1850
Time- Triggered Protocol ( TTP/C)
D2B
Gateway
33
•Engine Control
•Cruise Control
•Brakes
•ABS/TCS
•Brake-by-Wire
•Safety
•Airbags
•Collision Avoidance
Mobile Multimedia Link
IEEE1394
Connected Car PC
Domestic Digital Bus
Flex Ray
AutoPilot
Multi Media Link
Auto PC
Universal Serial Bus ( USB)
Car Multimedia System
32-bit CPU
SDRAM
SDRAM
RF
Tuner
External
Controls
Speakers
AC97
Codec
Drive
Unit
DVD
34
Processor Interface
TFT LCD
DDR Memory
Controller
VGA Controller
Filtering &
Formatting
PCI Bridge
MOST Entertainment
User Interface
CAN 2.0B
Controller
Body
Electronics
AC 97 I/F
PCMCIA
ATAPI / IDE
Discrete CLK
Logic DLLs
Network
Plug-in Card
FPGA DSP Advantages
• Off the shelf devices
• Faster time-to-market
• Rapid adoption of
standards
• Real-time prototyping
Flexibility of DSP Processors
•
•
•
•
Parallel processing
Support high data rates
Optimal bit widths
No real-time SW coding
Performance of Custom ICs
Xilinx DSP Solutions Offer the Best of Both
Worlds at a Low Cost!
35
Xilinx DSP Solutions
Performance and Flexibility
• Multi-billions MACs per second!
• Tremendous parallel processing capability
– Distributed DSP resources, segmented routing and flexible architecture allow
optimized implementation of algorithms
– No instruction flow overhead
• High-memory bandwidth
– Distributed RAM to store DSP coefficients and FIR filters
– True dual-port BlockRAM
• Optimized data buffering and storage
• Applications like FFT for next generation HDTV, video line buffers
• DLL for multi-rate clocks
• High I/O bandwidth and flexible interfaces
– Supports 20 high-speed signal & memory interface standards
• LVDS, LVTTL, SSTL, HSTL, GTL+, PECL …
36
Enabling High-Speed DSP
Conventional DSP/Software
Data In
• Fix ed inflex ible architecture
Reg
Loop
Algorithm
256 times
– Typically 1-4 MA C units
– Fix ed data width
MAC unit
Data Out
e.g. 256 Tap FIR Filter = 256 MAC operatio ns per sample
256 MAC operations in 256 clock cycles in DSP!!
• Serial processing limits data
throughput
– Time-shared MA C unit
– High clock frequency creates
difficult system-c hallenge
Per for mance
Limitations
FPGA Performance Advantage
Data In
C0
Reg0
Reg1
C1
Reg255
Reg255
Reg2
C2
C255
• Flexible architecture
– Distribut ed DSP resources (LUT,
registers, multipliers, & memory )
• Parallel processing maximizes
data throughput
Data Out
– Support any level of parallelism
– Optimal performance/cost
tradeoff
e.g. 256 Tap FIR Filter = 256 MAC operations per sample
All 256 MAC operations in 1clock cycle in FPGA !!
37
Unprecedented MathWorks/Xilinx
Partnership for Productivity
• The MathWorks & Xilinx have
an unprecedented strategic
partnership for DSP
MATLABTM
Algorithm Development
and Analysis
– Joint engineering for
robust/easy-to-use solutions
– Joint marketing/sales for easier
access to tools
• Seminars
• Promotions
– Joint DSP training worldwide for
rapid learning
38
SimulinkTM
System-Level Design
Unrivaled DSP Performance
per Dollar
• Nearly 3 billion MACs/sec per
dollar
• Cost effective solution for low
cost DSP applications such as:
Embedded DSP Capability
Up to 104 18bit Multipliers!
18 Bit
36 Bit
– Digital communications,
video/imaging, & industrial control
18 Bit
• Simple design flow
– MathWorks (MATLAB/Simulink)
• Complete DSP solution
– Silicon, software, IP, services,
specialists & development
systems
39
Simple and Familiar DSP Design Flow
The Only Complete Solution!
Highest Performance/Integration
Shortest Design Time
Familiar Design Flows
+ Leading- Edge Pr ocesses
+ 556 Embedded Multipliers (300MHz)
Advanced DSP Algorithms/Core s
DSP Development Boards
• Comprehensive Library
• Fast Turnaround
• Exceptional Performance
DSP Design Services
• 50+ Field DSP Experts
• Processor, I/O Experts too
DSP Training Classes
www.xilinx.com/dsp
40
Dedicated Field Specialists
DSP Customer Hotline
SDR for Automotive
For Broadcast TV, Radio, GPS & Telephony
Digital Down/Up Conversion (DDC)
– Channel Center
– Decimation/Interpolation rates
– Compensation Filters
– Matched Filter a = {0.25,0.35,...}
FEC
– Convolutional
– Reed-Solomon
– Concatenated Coding
– Turbo CC/PC
– (De-)Interleave
Beam Forming
41
Modulation Format
– QPSK
– DQPSK
– p/4 DQPSK
– {16,64,256,1024} QAM
– OFDM
– OFDM CDMA
Soft Radio
Digital
Signal
Processing
Engine
Security
Channel Access
– CDMA
– TDMA
DSSS
– Rake, track, acquire
– Multi User Detection (MUD)
– ICU
Network Interface Definition
Xilinx XtremeDSP
Development board
Courtesy of Nallatech : http://www.nallatech.com
• Suitable for SDR and 3G/4G algorithm and multimode transceiver development
• http://www.xilinx.com/ipcenter/dsp/development_kit.htm
42
Image/Video Processing
• The Problem
– Industry is pushing for higher levels of video quality using
less bandwidth and processing limits are being reached
• How do you meet performance requirements? Can you remain
compatible with continuously evolving formats and standards?
• Xilinx Solutions
– Move computationally intensive portions like motion estimation and DCT from either
MPEG codec or a processor into low-cost Xilinx FPGA
• Deliver required performance whilst allowing processor to focus on tasks like running OS
– Use Xilinx XtremeDSP technology which exploits inherent parallelism in FPGAs to
perform DSP algorithms faster than any software or dedicated DSP device
– Allows experimentation with HW-SW design partitioning
• Develop new techniques or algorithms that lead directly to product differentiation
• Xilinx Image/Video Processing IP
– Color space conversion (RGB2YCrCb, YCrCb2RGB, RGB2YUV, YUV2RGB,etc.),
DCT/iDCT, FIR filters, DA FIR, FFTs ,MACs, MPEG-2 (SD & HD), JPEG, Huffman,
wavelet, scaling, rotation, enhancement
43
Adaptive Cruise Control &
Collision Avoidance
SDRAM
SDRAM
Cameras
DDR Memory I/F
32-bit Soft-CPU
Other
Peripherals
Other DSP
Functions
44
Obstacle
Detection
LVDS
Rx
Hardware
Decisions
Lane
Detection
Discrete CLK
Logic DLLs
Image
LVDS
Capture
Tx
Pipeline
PHY
6-Channel
CAN
Controller
CCD
CCD
Gyroscopes
PHY
Laser
PHY
Radar
PHY
Wheel Sensors
PHY Accelerator
PHY Brakes
Driver Support Systems:
Adaptive Cruise Control
• Adaptive cruise control or collision avoidance systems
– Video processing systems - rear view mirror & dash board
• Intensive digital signal processing required
– Xilinx FPGAs used aid with video image manipulation (DSP)
• Xilinx FPGAs offer extremely fast parallel digital signal
processing
• Parallel processing maximizes data throughput
– Support any level of parallelism
– Optimal performance/cost tradeoff
• FPGAs also support serial processing
– Standard digital signal processors process signals serially
45
32-bit
Embedded
CPU
Applications
• Web tablets
• Internet appliances
•Telematics
• High-end PDAs
Processor Interface
Partial MPEG-4 H/W
Acceleration
Motion Estimation
Motion Compensation
DCT / IDCT
Other Custom Logic
Memory Controller
SRAM
SDRAM
46
Dedicated
H/W
acceleration
blocks
Soft Processor Roadmap
A complete range of low-cost solutions that can be customized for any application
175
150
100 DMIPS
MHz
125
--bbiitt
2
2
3
3
e
BBllaazze
o
r
o
r
c
i
M
Mic
82 DMIPS
MicroBlaze
MicroBlaze 16-bit
16-bit
100
75
1/3
1/3 the
the size
size of
of 32-bit
32-bit MB
MB
49 DMIPS
49 DMIPS
50
½ the size of 16-bit MB
25
2001
47
2002
2003
2004
2005
MicroBlaze Soft Processor +
Spartan-3 FPGA
• Reduce design cost and inventory
– Integrate more features into one device
– Multiple designs addressed with a single processor solution
• Solve µC, µP obsolescence
– Buying the source code guarantees product availability
– Port the core across Xilinx product lines (Spartan and Virtex)
• Customized processor and peripheral set address
evolving design requirements
– An entire menu of peripherals to choose from and modify
– Reprogram your code to meet changing standards and
protocols
48
MicroBlaze & Spartan-3 FPGAs: Industry’s
Lowest Cost Soft Processor Solution
• Effective cost - as low as $1.40
• Customized controller and peripheral
set to meet exact and evolving
design requirements
• Complete solution includes HW, SW,
tools and design examples
– Embedded Development Kit (EDK) support
offering common development environment
with Virtex-II Pro PowerPC-based solutions
49
MicroBlaze Solution
• Soft processor core
–
–
–
–
–
32-bit - Harvard Bus RISC architecture
Size: 950 logic cells in Virtex-II and Virtex-II Pro
Size: 1050 logic cells in Spartan-IIE and Spartan-3
Speed: 150 MHz, 125 D-MIPS in Virtex-II Pro (-7)
32 general purpose registers; 3 Operand instruction format
• IBM CoreConnnect bus
• Standard peripheral set
50
MicroBlaze IP Peripherals
Development Kit
• MicroBlaze CPU
• OPB arbiter
• Watchdog timer/timebase
• Timer/counter block
• Interrupt controller
• SRAM controller
• Flash memory controller
• ZBT memory controller
• BRAM
• UART Lite
• GPIO
• SPI master and slave
51
Additional Peripherals
• UART 16550
• UART 16450
• IIC master & slave
• Ethernet 10/100 MAC
• ATM Utopia Level 2
• SDRAM
• DDR
System Diagram
r31
Machine Status Reg
I-LMB
Register
File
32 x 32bit
Program Counter
r1
r0
Control Unit
Instruction Buffer
Shift /
Add / Multiply
Multipl
Logical Subtr act Multiply
Data Bus Controller
Instruction Bus Controller
Address
side
LMB
Data Side
LMB
D-LMB
y
PROCESSOR
TM
CoreConnect
OPB I/F
Interrupt
Controller
UART
I-OPB
Off-Chip
Memory
0-4GB
52
TM
CoreConnect
OPB I/F
D-OPB
Watchdog
Timer
General
Purpose I/O
PERIPHERALS
Timer /
Counters
Off-Chip
Memory
0-4GB
PicoBlaze
53
PicoBlaze Application Examples
•
•
•
•
•
•
•
•
•
•
•
•
54
Front panel switches and displays for set top box
Dynamic loop bandwidth multiplexer for frame to frame analysis
Link layer of IEEE 1394 interface
Microcontroller for compact flash programming engine
DECT radio/repeater
PCI board programming controller
Communications controller
Preprocessing for network processor
Motor controller
Programmable power supply controller
Part of Media Access Controller
Controller in broadcast video equipment and many more...
Memory Interfaces Are Not
All The Same
• Areas of variation
–
–
–
–
–
–
–
–
–
–
–
55
Type – SRAM, SDRAM, SGRAM, Flash,….
Bit support
Density
Configuration sizes
OEM/ Vendor
Clock frequency
I/O performance
Burst size
Page size
CAS latency
Refresh cycle
Formats supported - Line doubling and quadrupling
Memory for Displays
Spartan Memory Controller
Reference Designs
• DRAM reference designs
– 64-bit DDR DRAM controller
– 16-bit DDR DRAM controller
– SDRAM controller
• SRAM reference designs
– ZBT SRAM controller
– QDR SRAM controller
• Embedded memory reference
designs
–
–
–
–
–
Data-width conversion FIFO
200 MHz FIFO
CAM for ATM applications
CAM using shift registers
CAM using Block SelectRAM
• Flash controller
– NOR / NAND flash controller
These Reference Designs are Available for Immediate
Download at the Memory Corner
http://www.xilinx.com/memory/
56
Maximum Bandwidth
On-chip SelectRAM+™ Memory
Cache Tag memory
Large FIFOs
Packet buffers
Video line buffers
Deep/Wide
DSP coefficients
Scratch pad
Small FIFOs
Wide/shallow
Distributed RAM
Block RAM
Block RAM
Kilobytes
Bytes
High Speed Memory Interface
Excellent for large memory requirements
Megabytes
57
Port B
Port A
External
Spartan-3
True Dual-Port
Block RAM
Multiple Storage Standards
• Many storage technologies addressing information appliance market
• Need for multi-standard support in these applications
CoolRunner-II offers flexibility to act as storage controller
between multiple technologies
58
Display Controller & Driver
Xilinx
Non-Xilinx
Programmable
Programmable
Display
Display
Controller
Controller
* = Odd
** = Ev en
Backlight
Backlight
R
G
B
Graphics
Graphics
Processing
Processing
Panel
Panel
Timing
Timing
HSYNC
VSYNC
CLK
59
R*
G*
B*
R**
G**
B**
LVDS
LVDS
R*
G*
B*
R**
G**
B**
HSYNC
HSYNC
VSYNC
VSYNC
CLK
CLK
FPGA Benefits and Value
Display and Timing Control
• Leverage existing designs/chipset to support multiple
display types
• Faster time-to-market
• Improved inventory control
• Customize products for different geographies
• Reduce exposure to supply issues
– Flexibility to efficiently manage component supply problems
• React quickly to competitive pressures
– Bringing new features/capabilities rapidly to market
60
Content Protection &
Encryption
• Critical capability that requires high performance, yet is still highly
fluid and not standardized
– High performance content protection
• Real-time encoding/decoding of multi-Gbps data streams
• Flexibility
– Several methods of data encryption
•
•
•
•
RSA (Rivest-Shamir-Adleman), Diffie-Hellman, RC4/RC5
Secure Hashing Algorithm (SHA), Blowfish
Elliptic Curves, ElGamal, LUC (Lucas Sequence)
DES (Data Encryption Standard) & Triple-DES (TDES)
• Xilinx FPGAs with encryption IP
– AES, DES, Triple DES, proprietary
• Technology tutorials on eSP
– Encryption cores supported in Spartan-3
61
Encryption - FPGAs
Add Significant Value
• Spartan-3 encryption
solutions are NIST
approved
• The programmable
nature of these
solutions allows easy
customization/flexibility
based on end
application requirement
• Hardware-based
solutions provide higher
performance
62
Xilinx FPGAs Add Value By
Minimizing EMI Issues
• Xilinx offers “EMI friendly FPGAs”
–
–
–
–
–
–
Single-ended I/Os
Programmable output drive
Solve signal integrity issues even after PCB layout
Clock management
LVDS clock distribution
LVDS chip-to-chip connectivity
• Significant cost reduction
– EMI compliance testing and re-design is very expensive
• Time-to-market
– Get your product to market ahead of the competition / FCC
compliance
63
Cost Management Through
System Integration
•
Replacing discrete parts
–
–
–
–
–
–
–
–
–
–
•
Benefits
–
–
–
–
–
64
Dual port memory/ FIFO
Clock buffers
Localized clock drivers
DLLs
Level translators
Hot socketing
Schmitt triggers
TTL devices
Backplane drivers
Board deskew
Cost savings
Fewer components
Board area savings
Higher reliability
Less EMI issues
Integration = BOM Reduction
Targeted for integration
into one-chip PLD solution
Courtesy: 9t htee.c om
65
Reducing the Overall BOM
Re-programmability
250KU Pricing
* High-volume pricing
estimate
Additional features using
Programmable Logic for
FREE !!
Time-to-market
Board Area
Power Savings
Solution Cost
Performance
Additional Logic
Additional Memory
$11.82
$5.73
$3.16
$1.96
$0.91
Additional I/O
Clock Management
$5.09*
Buffers / Drivers
$2.57*
UART
$2.20*
Watchdog Timer
$1.05*
Discrete Logic
Chips
$0.91*
Standard Solutions
66
Save $7.87
3S50
TQ144C
Spartan-3 Solution
$3.95
Introducing
Spartan-3
Xilinx’ Latest Solution for the
Automotive Markets
The Spartan-3 Platform:
A New Class of Spartan FPGAs
Advanced FPGA
Logic with Staggered
Pad Technology
XCITE
Digitally
Controlled
Impedance
90 nm
18 Bit
18 Bit
36 Bit
Embedded
XtremeDSP
Functionality
SelectIO™-Ultra
Technology
VCCIO
Z
Z
Impedance
Z Contro l
DCM
High Performance
Sync Dual-Port™
RAM
68
DCM™ Digital
Clock
Management
Highest Density with Low Cost
90 nm Process Delivers Higher Yields at Higher Densities
100
Density Leadership
90 nm
Process Yield %
80
60
40
180 nm
20
0
0.5
69
“The companies that get into 90nm
production first will get a tremendous
advantage in lower cost….. Rivals who
are late in 90nm process technology
will fall behind and may not be able to
catch up.”
Dan Hutcheson
VLSI Research, Inc.
1
1.5
2
2.5
Density (Million Gates)
3
- Faster performance
- Large density devices
- Lower cost devices
Spartan-3 Product Matrix
Device
System Gates
Logic Cells
Dedicated Multipliers
Block RAM Blocks
XC3S50
50K
1,728
-
XC3S200
200K
4,320
12
12
Block RAM Bits
Distributed RAM Bits
DCMs
I/O Standards
12K
24
216K
30K
4
24
288K
56K
4
24
432K
120K
4
24
576K
208K
4
24
720K
320K
4
24
1,728K
432K
4
24
1,872K
520K
4
24
Max Differential I/O
Max Single Ended I/O
22x22mm
TQ144
30.6x30.6mm
PQ208
17x17mm
FT256
23x23mm
FG456
27x27mm
FG676
31x31mm
FG900
56
124
97
124
76
173
116
264
175
391
221
487
270
565
312
712
344
784
141
173
141
173
264
173
333
391
333
487
489
565
633
633
70
XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000
400K
1000K
1500K
2000K
4000K
5000K
8,064
17,280
29,952
46,080
62,208
74,880
16
24
32
40
96
104
16
24
32
40
96
104
Spartan-3 Summary
71
Performance & Density
PLD Application Trends
Counters
Adders
Data Path
Memory
Controllers
uControllers
7400 Series
1980s
72
1990s
Industrial
Medical Imaging
Test and Measurement
Industrial Automation
PCI/PCI-X
Control systems
FEC
Consumer
FFT/FIR Filters
Set-Top Boxes/HDTV s
IMA (ATM)
Telematics
Encryption
Home Networking
MP3 Decoder
Networking
xDSL Modems
Line Cards
Computers
Graphic Cards
Printers
2000s
Price
FPGA Price Reduction
Time
10,000% Reduction
Price of 100K FPGA Gates Over Time
73
CoolRunner-II CPLD
One Ultimate CPLD Solution for All Designs
High Performance
3.5ns tPD, fmax 303Mhz
Improved features
Storage Systems, Routers
Lowest Power
Low Cost
12mW*
0.18µ = small die size
Lowest cost packaging ~20uA typical stand-by
Set-Top Box, Cell phone Handheld, Portable Equipment
* Estimated 128 macrocell dev ic e, Eight 16-bit counters @ 50M Hz
74
CoolRunner-II Family Overview
XC2C32
XC2C64
XC2C128
XC2C256
XC2C384
XC2C512
T pd (ns)*
3.5
4.0
4.5
5.0
6.0
6.0
Max. I/O
I/O Banks
33
1
64
1
100
2
184
2
240
4
270
4
I/O
Standards
Clock Doubler,
Input Hysteresis
Clock Divide,
CoolCLOCK,
DataGATE
LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS LVTTL,LVCMOS
15*,18,25,33
15*,18,25,33
15*,18,25,33
15*,18,25,33
15*,18,25,33
15*,18,25,33
SSTL 2-1,3-1
SSTL 2-1,3-1
SSTL 2-1,3-1
SSTL 2-1,3-1
HSTL 1
HSTL 1
HSTL 1
HSTL 1
yes
n ot
not
neece ss ar y n ec es sa r y
VQ44
PC44
CP56
Packages
* Note: T
75
PD
yes
VQ44
PC44
CP56
VQ100
yes
yes
yes
yes
yes
yes
yes
yes
VQ100
CP132
TQ144
VQ100
CP132
TQ144
PQ208
FT256
TQ144
PQ208
FT256
FG324
PQ208
FT256
FG324
speeds are preliminary and 1.5V LVCMOS inputs need hysteresis
CoolRunner-II I/O Support
I/O Standard
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
1.5V I/O
HSTL-1
SSTL2-1
SSTL3-1
VCCIO
Input
V REF
Board Termination
Voltage (VTT)
3.3
N/A
N/A
3.3
N/A
N/A
2.5
N/A
N/A
1.8
N/A
N/A
1.5
N/A
N/A
1.5
0.75
0.75
2.5
1.25
1.25
3.3
1.5
1.5
• Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V and
3.3V logic levels on all parts
• LVTTL and LVCMOS available on all devices
• SSTL2-I, SSTL-3-I and HSTL-I on 128 macrocell and
denser devices
76
Low Cost Packaging Options
17.6 mm
44 PLCC
12 mm
8 mm
6 mm
6 mm
Uses standard IR techniques
for mounting to PC board
77
8 mm
56 CP
12 mm
132 CP
17.6 mm
44 VQFP
CoolRunner Reference Designs
• Finish designs faster with FREE reference designs
• Increase the capability of the CPLDs you use
Type
PDA
Processor
Periphe ral
Encoder
De coder
Wireless
Refe rence
Number
XPATH Module Design
XAPP356
8 Channel DVM Springboard XAPP146
Springboard Module Design XAPP147
8051 Microcontroller Interface XAPP349
SPI
XAPP348
IrDA and UART
XAPP345
UARTS
XAPP341
SMBus Controller
XAPP353
Manchester Encoder/Decoder XAPP339
16b/20b Encoder/Decoder
XAPP336
XAPP333
I2C Bus Controller
Wireless Transciever
XAPP358
Reference Design
Lanaguage
Macrocell
VHDL
Pocket C, VHDL
Pocket C, VHDL
VHDL
VHDL
VHDL or Verilog
VHDL or Verilog
VHDL
VHDL or Verilog
VHDL
VHDL or Verilog
VHDL
225
184
67
57
135
87
61
158
55
76
131
156
Recommended
%
Target Device Utilizatiion
XC2C384
58
XC2C256
71
XC2C128
52
XC2C64
89
XC2C256
52
XC2C128
67
XC2C128
47
XC2C256
61
XC2C64
85
XC2C128
59
XC2C256
51
XC2C256
60
Coming soon – N x N Crosspoint Switch, MP3 Player, NAND Flash Interface, Error Detection & Correction
78
Xilinx IQ Solutions
Silicon for Automotive
Applications
Introducing IQ Products
• Why IQ?
– New array of devices guaranteed over an extended
temperature range
– Consists of CPLD and FPGA families already available in
I Grade - and the addition of selected devices with an
extended temperature ‘Q’ grade option
– IQ - it’s the intelligent choice for automotive designers!!
• For FPGAs Q grade means:
– -40°C to +125°C junction temperature
• For CPLDs Q grade means:
– -40°C to +125°C ambient temperature
Ambient = the temperature of the air surrounding the device
Junction = is the temperature of the die in the package
80
Quality and Traceability
• Full mask set control
– Every time a part is ordered it will have the same
die revision for up to 10 years (if required)
• Fab, assembly and test flow consistency (if required)
– Manufactured in the same fab location and same package
manufacturer location
• Traceability required for AEC and TS16949 standards
• Fully characterized to operate from –40ºC to +125ºC
(ambient temperature for CPLDs and junction
temperature for FPGAs)
• All Xilinx production partner fabs are qualified to QS9000
• PPAP data available on request
81
XCS30XL TQ144 di ssipating 600mW in still air
125°C
105°C
Q-grade
TJ = 125° C
I-grade
TJ = 100° C
C-grade
TJ = 85° C
85°C
TJ
70°C
Chip Temperature
Rise
vs. Ambient
TA
XCS30XL TQ144 di ssipating 1.5W in still air
155°C
140°C
Temperature is design dependant
- May be able to use Xpower to
determine customer design power
consumption
Q-grade
TJ = 125° C
125°C
105°C
I-grade
TJ = 100° C
C-grade
TJ = 85° C
85°C
70°C
TA
82
TJ
IQ Solutions
• Multiple components
– Programmable products
– IP cores
– System solution boards
– Design services
– eSP web portal
– Customer education
• PLD family members available in the range of
-40°C to +125 C :
Device Type
Spartan XL
XC9500XL
Release Schedule
CoolRunner XPLA3
XCS05XL, XCS10XL, XCS20XL, XCS30XL, XCS40XL - NOW
XC9536XL, XC9572XL - NOW
XC9535, XC9572 - NOW
XCR3032XL, XCR3064XL, XCR3128XL, XCR3256XL, XCR3384XL, XCR3512XL - NOW
Spartan-II
XC2S15, XC2S30, XC2S50, XC2S100, XC2S150, XC2S200 - NOW
CoolRunner-II
Spartan-IIE
Q3CY03
XC9500
83
Q2CY03
The Xilinx IQ Total Solution
• eSP web portal dedicated to accelerating all
phases of product development
– Automotive (new)
– Telematics (new)
– GPS
– DVD
• System solution boards
– Turn-key solutions
developed with
partners to
accelerate product
development
84
• Design services
– Providing concept
to completion
– Bridging the
technology and
knowledge gap
• IP - LogiCores &
AllianceCore
– Ex: multiplexers,
parallel to serial
converters, error
correction, and
encryption
Density
Automotive Silicon Road Map
2.5V
15K - 200K Gates
50K - 600K Gates
1.8V
3.3V
5k - 40k Gates
XC9500
5V
35-72
Macrocells
32-512 Macrocells
32-512 Macrocells
36-72 Macrocells
Time
85
Xilinx Quality Standard Roadmap
Q1’ CY05
ISO9000/QML/PURE/
TL9000/QS9000
Q4’ CY03
ISO9000/QML/PURE/TL9000
TODAY
ISO9000:2000
ISO9000/QML/PURE
ISO-9000:1994 meet
minimum requirements
QML, PURE Certified
ISO-14000 ( Q4CY2001)
Quality systems
− focus on re-estabilization
− Meet customer rqts.
Wim’s Quality Initiatives
− Internalize w orldw ide
− WW training
− Continuous drive needed
as part of our “values”
86
ISO-9000:2000
PAST
ISO9000/QML/PURE
TL9000 (Telec. Stds.)
Emphasis on
continuous
improvement
Customer input is
significant
Top management
quality review
Analysis & Use of
Data ( FOL --> EOL,
SPC, Metrics)
Comple te d in July 02
QS9000 or TS16949
Systems Expectations for
Automotive Industry
Customer and Supplier
relationship
Top Mgmt Involvement
Telecom Industry Standards
Des ign Process Control
Des ign Control, NPI,
Traceability/ Pr od. I.D.,
¾Des ign Control,
Pr oduct Lifecycle,
NPI, Traceability/
PCN/PDN)
Pr od. I.D., Product
Significant Involvement and
Lifecycle, PCN/PDN)
Participation of Top Mgmt
Specific Emphasis on
(Softw are, Hardw are)
statistical tools &
Emphasis on continuous
techniques continuous
improvement and customer
satisfaction
improvement
High on balanced metrics
¾Gauge R&R; SPC
and communication
Charts, FMEA
systems, tracking results
¾Supplier - customer
relationship
¾performance feedback
¾problem escalation &
resolution
Xilinx Automotive IP
• Ready-made and customizable DSP building blocks
– DSP functions
• FIR filters, DA FIR, FFTs, MAC, sine, cosine, etc.
– Base arithmetic functions
• Addition, subtraction, multiplication, division, square-root
– Memory functions
• Asynchronous FIFOs, synchronous FIFOs, block memory modules,
frame buffers, CAMs, shift-registers, flip-flops
– Basic logic functions
• Gate modules, multiplexers, decoders, accumulators, comparators,
counters
www.xilinx.com/ipcenter
87
Xilinx Automotive IP
• Microprocessor
– 8, 16, 32-bit soft processors
• Peripherals
– UART, SPI, timers, DMAs
• Memory controllers
– SRAM: ZBT, QDR
– SDRAM: SDRAM, DDR
– Flash: CompactFlash, MMC, SD card, MemoryStick, IDE
• System interfaces
– PCI, PCI-X, CAN, Rapid I/O
• Engine control - Zionix
– Tunable “TPU” (spark, fuel control), PWM, fuel injection, position tracking
www.xilinx.com/ipcenter
88
Xilinx Automotive IP
• Encoding/Decoding
– Compression
• DCT/IDCT, motion compensation/estimation
• DWT
• MPEG-4, MPEG-2, JPEG2000 CODEC
– Color space conversion
• RGB2YCrCb, YCrCb2RGB, RGB2YUV, YUV2RGB, etc.
– Forward error correction
• Reed-Solomon, Viterbi, Convolutional
• Encryption/Decryption
– AES (Rijndael), DES, TDES, RSA, MD5, Blowfish, SHA, etc.
www.xilinx.com/ipcenter
89
Shorter Development Cycles
Increase Revenue Potential
ASIC SOC designs average 14-24 months
Specification
Implementation
Verification
Prototyping
Evaluation
Development time
averages 55% less with
FPGA*
FPGA designs average 6-12 months
0
1
2
3
4
5
6
7
8
9
10
11
12
Units of time (person-months)
Source: Harvard S tudy
90
* Based on an average of 391 different sized designs
13
14
15
16
17
18
Xilinx Maximizes Profitability
In The Market
• Products that are 6 months late and on budget earn 33% less profit over 5 yrs+
• A delay every 4 weeks equals 14% loss in market share#
Market Peak
(Time in Market Advantage)
Profit for first
to market
Field
Upgradability
with Xilinx
Reduced Profit
for Late Comers
Xilinx Product Availability
Start of market window
2:1 TTM Advantage with Xilinx
* Sourc e: Current and Emerging Embedded Markets and Opportunities – Elect ronicMarket Forec asters
† Source: McKinsey & Co. , # Source: John Chambers
WindRiver Systems, Inc.
91
End of market window
Summary
• Rapid growth and change occurring in automotive
applications
• Designers of automotive electronics presented with
numerous issues and challenges
• Telematics a key enabler to incremental revenues for car
manufacturers
• Time-to-market, flexibility, reprogrammability desired
• Xilinx solutions are the perfect answer for automotive
applications
92
Other Customer
Testimonials
Xilinx in Infotainment
Systems – Siemens VDO
• Siemens VDO Dayton
– Integrated entertainment system
– CD tuner w/ MP3, 3D display, and
hands free phone
• Spartan-II FPGAs
– Perform peripheral
interfacing and audio control
– Selected for
• Field reprogrammability to
accomodate changing standards
• Ease-of-use, low cost
Siemens VDO has been using Xilinx FPGAs for its
advance in-car systems since 1997
94
95
Automotive Test Equipment
• In-car bus networks are changing - CAN may be adopted in US
• Changing standards mean the need for adaptive and
reconfigurable test equipment
• Auto Xray used Spartan FPGAs in their automotive handheld
testers so that their customers never have to buy a new unit simply upgrade the hardware over the Internet
• The scanner is battery powered so needed low power devices Spartan-XL power down mode or CoolRunner CPLDs
"Vehicle standards are constantly changing and the Spartan
FPGAs provide us with the ability to reprogram our hardware
whenever necessary. The Xilinx FPGA allows our customers
to upgrade software and hardware right over the Internet"
Bill Miller, President of AutoXray
96
97
Spartan Automotive
Application Example
• Application: In-car navigation system
• Device: XC2S50, Spartan-II, 50k system gates
• Reasons for using Xilinx:
– Software and technical support
was of the highest quality
– Moving from prototype to production
was seamless
– Device can be easily upgraded to give extra functionality and
features
– The price was surprisingly low and competed well with the
ASIC alternative but with no NRE
98
SiRF Case Study
"With very low power
• FCC recently issued Enhanced-911
consumption, chip scale
(E-911) initiative
packaging and minimal
• Requires all cellular companies to
heat dissipation, CoolRunner
be able to connect emergency calls
CPLDs were an easy choice”
- Greg Turetzky, SiRF
and deliver their location to within
150m to 911 operators
• SiRF developed a chipset to enable GPS in cell phones for this
initiative but needed a way to link signals to processor interface
• Stiff competition in this emerging market means time-to-market is
paramount
• CoolRunner CPLDs were the ideal solution for the interface
99
