42119887 Automated Attendance Using Rfid

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ACKNOWLEDGEMENT We extend our sincere thanks to our management trustees DR.S.GUNASEKARAN, DR.T.O .SINGARAVEL, DR.M.MUTHUSAMY, DR.S.RAMALINGAM, and our respected principal DR.S.SUNDARAM for providing all fac ilities for the successful completion of this project. We express our heartfelt thanks to our head of the department MR.N.SHANMUGASUNDARAM, M.E., for his valuab le guidance and encouragement throughout the project period and also making vari ous arrangements required for our project. We wish to express our gratitude and thanks to our guide MRS.V.SANGEETHA, M.E., for her valuable contribution in brin ging out this project successfully. Our sincere thanks to all of our staff membe rs, librarian of electronics and communication engineering department for their extended help and co-operation to do this project. III

TABLE OF CONTENTS CHAPTER NO TITLE ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS PAGE NO VI VII VIII IX 1. INTRODUCTION 1.1 objectives 1 1 2 2 2 2. SYSTEM ANALYSIS 2.1 Existing System 2.1.1Drawbacks 2.2 Proposed system 2 3 3 3 4 4 5 11 11 11 13 16 18 3. SYSTEM SPECIFICATIONS 3.1 Hardware requirements 3.2 Software requirements 4. PROJECT DESCRIPTION 4.1 Block Diagram 4.1.1 Components of system 5. MICROCONTROLLER 5.1 Introduction 5.2 Features of ATMEGA8515 5.3 Pin configuratio n ATMEGA8515 5.4 Architecture of ATMEGA8535 5.5 Architectural overview IV

5.6 Serial Communication 5.6.1 Introduction of RS-232 5.6.2 Bit streams 5.6.3 RS -232 Physical Properties 5.6.4 USART 20 20 21 24 24 5. SOFTWARE DESCRIPTION 5.1 AVR studio 5.2 line by line debugging 5.3 work space window 5.4 memory windo w 5.5 debugging strategies 27 27 27 28 29 30 6. CONCLUSION AND FUTUREWORKS 6.1 Conclusion 6.2 Future works 31 31 31 32 7. REFERENCES V

ABSTRACT ‘AUTOMATIC ATTENDANCE SYSTEM ’ is designed to collect and manage student’s attendance records from RFID devices installed in a class rooms. Based on the verification of student identification at the entrances, the system could generate sophistica ted student attendance data for analysis purposes. Class room automation is base d on personalized profiles. Profiles can be edited on the run time without makin g any changes in the hardware. The database software is smart enough to mark the attendance if and only if the card holder spent a minimum time required for att endance in classroom. Embedded module will keep on checking whether any person entering or leaving. The RFID system consists of an RFID tag, a reader, and a userinterface display. When the tag is energized by the RF field, it transmits back the contents of its memory by modulating the incoming RF field. The reader detects and demodulates the signal and identifies the tag. Entering will be considered if persons from IR SLOT 1 to IRSLOT 2, leaving is co nsidered from IR SLOT 2 to IRSLOT 1. VI

LIST OF FIGURES FIG NO 4.1 4.2 4.3 4.4 5.1 5.2 5.3 5.4 TITLE Basic block diagram Pin diagram of RFID Reader IR Sensor Diagram of LCD Display Pin configuration Architecture of ATMEGA8515 Architecture Overview USART Block D iagram PAGENO 4 6 8 8 13 16 18 25 VII

LIST OF TABLES TABLE NO. 4.1 4.2 5.1 TITLE Frequency chart of RFID Pin configura tion of LCD Display RS-232C Interface Signals. PAGE 7 9 21 VIII


LIST OF ABBREVIATIONS 1. RF 2. ID 3. RFID 4. UART 5. IDE 6. EEPROM Radio Frequency Identification Radio Frequency Identification Universal Asynchro nous Receiver/Transmitter Integrated Development Environment Electrically Erasab le Programmable Read-Only Memory Infrared Sensor Liquid Crystal Display 7. IR SENSOR 8. LCD -

CHAPTER 1 INTRODUCTION The two major problems faced by organizations are time consuming manual attendan ce and wastage of electrical power. Our project is going to solve these problems by using RFID technology. The project is designed to store up to 50 card IDs bu t it is easily scalable up to 65000 card IDs but for that it requires external m emory. Radio Frequency Identification (RFID) is an automatic identification meth od, relying on storing and remotely retrieving data using devices called RFID ta gs or transponders. So the RFID is a wireless identification. Normally the RFID system comprises of two main parts: RFID Reader and RFID Tag. RFID Reader is an integrated or passive network which is used to interrogate information from RFID tag. The RFID Reader may consist of antenna, filters, modulator, demodulator, c oupler and a micro processor. 1.1 OBJECTIVE The aim of the project is to design a system that have a small coverage area and can be use for authentication or identification purposes. “AUTOMATED ATTENDANCE U SING RFID” is to maintain the attendance at real-time that can be monitored on PC. The objectives of this project is to develop a portable RFID Based Attendance S ystem that is able to: 1. Store students ID and name. 2. Display the students en try stored in EEPROM on LCD display. 3. Uniquely identify the students data. 4. Track and display absentees data. 1

CHAPTER 2 SYSTEM ANALYSIS 2.1 EXISTING SYSTEM A barcode reader is an electronic device for reading printed barcodes. It consis ts of a light source, a lens and a light sensor translating optical impulses int o electrical ones. The hand-held laser scanner has to be close to the bar code i n order to do its job. It reads only a bar code up to 2 inches away. In this pro ject, the Barcode scanner is interfaced with the micro controller and when the b arcode card is brought to the sight of the scanner, it reads the data on the bar code card and displays on the LCD. If the data of the card is matched with the d ata in the program memory then it compares and adds attendance credit to his rec ord. If the data is not matched it displays unauthorized. 2.1.1 DRAWBACKS i. Require line of sight to be read ii. Can only be read individually iii. Canno t be read if damaged or dirty iv. Can only identify the type of item v. Cannot b e updated vi. Most barcode scanners require a human to operate (labour intensive ) 2.2 PROPOSED SYSTEM Embedded module will keep on checking whether any person entering or leaving. En tering will be considered if persons from IR SLOT 1 to IRSLOT 2, leaving is cons idered from IR SLOT 2 to IRSLOT 1.If any person enters ID is getting from RF Tag , if it is valid ID then the person will come inside. System will acquire the da ta from tag and check with EEPROM.Then the person details displayed in LCD and a lso display the no of person’s presence and absence. 2

CHAPTER 3 SYSTEM SPECIFICATION 3.1HARDWARE REQUIREMENTS The electronic hardware parts can be further divided into three parts which is i nput, control system and output. The RFID reader and tag are the devices used as the input. Other than that, IR slots are act as input. The control system was d eveloped using ATMEGA 8515 microcontroller. Meanwhile, the 2x16 LCD display and buzzer are chosen as output of the electronic hardware parts. A Passive Infrared sensor is also used in the hardware part. It is usually infrared radiation that is invisible to the human eye but it can identified human, passes in front of a n infrared source 3.2 SOFTWARE REQUIREMENTS The microcontroller needs to be programmed first before it can be used in the el ectronic hardware. The C programming language is chosen to program the ATMEGA 85 15 microcontroller under AVR STUDIO 4. Correct and functional code ensures the m icrocontroller to work properly and accordingly. The layout of the printed circu it board is designed by using manual routing of the connections of each electron ic component involved in developing the system. AVR Studio 4 provides a complete set of features including debugger supporting run control including source and instruction-level stepping and breakpoints; registers, memory and I/O views; and target configuration and management as well as full programming support for sta ndalone programmers. 3


4.1.1 COMPONENTS OF SYSTEM The figure below shows the basic block diagram of the AUTOMATED ATTENDANCE USING RFID. It contains the following blocks: 1. RFID reader 2. RFID tags 3. Infrared sensors 4. LCD display 5. Microcontrolle r 6. Power supply unit RFID READER A reader (now more typically referred to as an RFID interrogator) is basically a radio frequency (RF) transmitter and receiver, controlled by a micr oprocessor or digital signal processor. The reader, using an attached antenna, c aptures data from tags, then passes the data to the controller for processing. T he reader decodes the data encoded in the tags integrated circuit (silicon chip) and the data is passed to the microcontroller for processing. FEATURES OF RFID READER a. Low cost solution for reading passive RFID transponde r tags. b. c. d. e. f. g. h. i. Industrial grade casing for better outlook and p rotection. Integrated RFID reader, antenna, LED, power cable and data cable. Eve ry reader has been tested before is being shipped. 9600 baud RS232 serial interf ace (output only) to PC. Fully operation with 5VDC power supply. Buzzer as sound indication of activity. Bi-colour LED for visual indication of activity. Standa rd RS232 serial cable (female) ready to plug to desktop PC or Laptop. j. 2m reading range. k. 0.1s response time. l. Operating frequency: 125KHz 5

FIGURE 4.2 PIN DIAGRAM OF RFID READER RFID TAGS Tags also sometimes are called “transponders”. RFID tags can come in many forms and sizes. Some can be as small as a grain of rice. Data is stored in the IC and transmitted through. The antenna to a reader. The two commonly used RFID Transponders are Active (that do contain an internal battery power source that p owers the tags chip) and Passive (that do not have an internal power source, but are externally powered typical from the reader) RFID Transponders. WORKING OF RFID Information is sent to and read from RFID tags by a reader using radio waves. In passive systems, which are the most common, an RFID reader tran smits an energy field that “wakes up” the tag and provides the power for the tag to respond to the reader. Data collected from tags is then passed through communica tion interfaces (cable or wireless) to ATMEGA 8515 in the same manner that data scanned from bar code labels is captured and passed to computer systems for inte rpretation, storage, and action. 6

FREQUENCIES OF RFID RFID deployments tend to use unlicensed frequencies for thei r cost benefits. There are four commonly used frequencies: Frequency Band 125KHz to 134 KHz Description Operating Range < .5M or 1.5ft. Benefits Drawbacks Low Frequency 13.56 MHz High Frequency Ultrahigh Frequency (UHF) < 1M or 3ft. 3m or 9ft. Works well Around water and metal products. Low cost of tags EPC standard Built around This frequency Short read range and slower read rates Higher read rate than LF Does not work we ll around items of high water or metal content Fastest read Rates 860 MHz to 930MHz 2.4GHz Microwave 1m or3 ft. Most Expensive TABLE 4.1 FREQUENCY CHART OF RFID INFRARED SENSOR Infrared radiation exists in the electromagnetic spectrum at a w avelength that is longer than visible light. It cannot be seen but it can be det ected. Objects that generate heat also generate infrared radiation and those obj ects include animals and the human body whose radiation is strongest at a wavele ngth of 9.4um. The pyroelectric sensor is made of a crystalline material that ge nerates a surface electric charge when exposed to heat in the form of infrared r adiation. When the amount of radiation striking the crystal changes, the amount of charge also changes and can then be measured with a sensitive FET device buil t into the sensor. The sensor elements are sensitive to radiation over a wide ra nge so a filter window is added to the TO5 package to limit detectable radiation to the 8 to 14mm range which is most sensitive to human body radiation. 7

FIGURE 4.3 IR SENSORS An IR emitting body moving across the front of a sensor wi ll expose first one, then both and then the other sensor element. The output sig nal waveform from an analog sensor shows that for motion in one direction, first a positive, then zero and then a negative transition results. Motion in the oth er direction will produce first a negative, then zero and then a positive transi tion. LCD DISPLAY The display support 2X16 characters, which means, the LCD can support 2 lines on the display and each line can display up to 16 characters which is relevant as the only essential output to be displayed is the student’s name and ID. Besides LC D Display, the output is displayed on LCD. The diagram of LCD display is shown i n Figure 4.4 and the detailed connections of the LCD is shown in table 4.2 FIGURE 4.4 DIAGRAM OF LCD DISPLAY 8

Table 4.2 Pin connections of LCD Display. EEPROM EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed. In ATM EGA 8515, the data EEPROM and Flash program memory is readable and writable duri ng normal operation (over the full VDD range). This memory is not directly mappe d in the register file space. Instead, it is indirectly addressed through the Sp ecial Function Registers. 9

There are six SFRs used to read and write this memory: 1. 2. 3. 4. 5. 6. EECON1 EECON2 EEDATA EEDATH EEADR EEADRH When interfacing to the data memory block, EEDATA holds the 8-bit data for read/ write and EEADR holds the address of the EEPROM location being accessed. These d evices have 128 or 256 bytes of data EEPROM (depending on the device), with an a ddress range from 00h to FFh. On devices with 128 bytes, addresses from 80h to FFh are unimplemented and will wraparound to the beginning of data EEPROM memory. When writing to unimplemented locations, the on-chip charge pump will be turned off. When interfacing the pro gram memory block, the EEDATA and EEDATH registers form a two-byte word that hol ds the 14-bit data for read/write and the EEADR and EEADRH registers form a twobyte word that holds the 13-bit address of the program memory location being acc essed. These devices have 4 or 8K words of 17 programs Flash, with an address 0000h to 1FFFh for the ATMEGA 8515. Addresses above the range of the respective device wi ll wraparound to the beginning of program memory. 10

CHAPTER 5 MICROCONTROLLER 5.1 INTRODUCTION The new ATMega8515 Controller is the ideal solution for use as a standard contro ller in many applications. The small compact size combined with easy program upd ates and modifications make it ideal for use in machinery and control systems, s uch as alarms, card readers, real-time monitoring applications and much more. Th is board is ideal as the brains of your robot or at the centre of your home-moni toring system. Save time and money, by simply building your ancillary boards and monitoring circuits around this inexpensive and easy to use controller. 5.2 FEATURES OF ATMEGA 8515 1. High-performance, Low-power AVR® 8-bit Microcontrol ler 2. RISC Architecture a. 130 Powerful Instructions – Most Single Clock Cycle Ex ecution b. 32 x 8 General Purpose Working Registers c. Fully Static Operation d. Up to 16 MIPS Throughput at 16 MHz e. On-chip 2-cycle Multiplier 3. Non-volatil e Program and Data Memories a. 8K Bytes of In-System Self-programmable Flash b. Endurance: 10,000 Write/Erase Cycles c. Optional Boot Code Section with Independ ent Lock bits d. In-System Programming by On-chip Boot Program e. True Read-Whil e-Write Operation f. 512 Bytes EEPROM g. Endurance: 100,000 Write/Erase Cycles h . 512 Bytes Internal SRAM i. Up to 64K Bytes Optional External Memory Space j. P rogramming Lock for Software Security 11

4. Peripheral Features a. – One 8-bit Timer/Counter with Separate Prescaler and Co mpare Mode b. One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, an d Capture Mode c. Three PWM Channels d. Programmable Serial USART e. Master/Slav e SPI Serial Interface f. Programmable Watchdog Timer with Separate On-chip Osci llator g. On-chip Analog Comparator 5. Special Microcontroller Features a. Power-on Reset and Programmable Brown-out Detection b. Internal Calibrated RC Oscillator c. External and Internal Interru pt Sources d. Three Sleep Modes: Idle, Power-down and Standby 6. I/O and Packages a. 35 Programmable I/O Lines b. 40-pin PDIP, 44-lead TQFP, 44-l ead PLCC, and 44-pad QFN/MLF 7. Operating Voltages a. 2.7 - 5.5V for ATmega8515L b. 4.5 - 5.5V for ATmega8515 8. Speed Grades a. 0 - 8 MHz for ATmega8515L b. 0 - 16 MHz for ATmega8515 12


Port A (PA7...PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (sele cted for each bit). The Port A output buffers have symmetrical drive characteris tics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The PortA pins are tristated when a reset condi tion becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega8515 Port B (PB7...PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (sele cted for each bit). The Port B output buffers have symmetrical drive characteris tics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated . The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8515. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (sele cted for each bit). The Port C output buffers have symmetrical drive characteris tics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated . The Port C pins are tri-stated when a reset condition becomes active, even if th e clock is not running. 14

Port D (PD7...PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (sele cted for each bit). The Port D output buffers have symmetrical drive characteris tics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated . The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8515 Port E(PE2...PE0) Port E is a 3-bit bi-directional I/O port with internal pull-up resistors (selec ted for each bit). The Port E output buffers have symmetrical drive characterist ics with both high sink and source capability. As inputs, Port E pins that are e xternally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if t he clock is not running. Port E also serves the functions of various special features of the ATmega8515. RESET Reset input. A low level on this pin for longer than the minimum pulse length wi ll generate a reset, even if the clock is not running. Shorter pulses are not gu aranteed to generate a reset. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock oper ating circuit. XTAL2 Output from the inverting Oscillator amplifier. 15

5.4 ARCHITECTURE OF ATMEGA8515 BLOCK DIAGRAM FIGURE 5.2 ARCHITECTURE OF ATMEGA8515 The ATmega8515 is a low-power CMOS 8-bit m icrocontroller based on the AVR enhanced RISC architecture. By executing powerfu l instructions in a single clock cycle, the ATmega8515 achieves throughputs appr oaching 1 MIPS per MHz allowing the system designer to optimize power consumptio n versus processing speed. 16

The AVR core combines a rich instruction set with 32 general purpose working reg isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruct ion executed in one clock cycle. The resulting architecture is more code efficie nt while achieving throughputs up to ten times faster than conventional CISC mic rocontrollers. The ATmega8515 provides the following features: 8K bytes of In-System Programmab le Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, a n External memory interface, 35 general purpose I/O lines, 32 general purpose wo rking registers, two flexible Timer/Counters with compare modes, Internal and Ex ternal interrupts, a Serial Programmable USART, a programmable Watchdog Timer wi th internal Oscillator, a SPI serial port, and three software selectable power s aving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, a nd Interrupt system to continue functioning. The Power-down mode saves the Regis ter contents but freezes the Oscillator, disabling all other chip functions unti l the next interrupt or hardware reset. In Standby mode, the crystal/resonator O scillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured us ing Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be reprogrammed InSystem thro ugh an SPI serial interface, by a conventional non-volatile memory programmer, o r by an On-chip Boot program running on the AVR core. The boot program can use a ny interface to download the application program in the Application Flash memory . Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-programmable Flash on a monol ithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a h ighly flexible and cost effective solution to many embedded control applications . The ATmega8515 is supported with a full suite of program and system developmen t tools including: C Compilers, Macro assemblers, Program debugger/simulators, E mulators, and Evaluation kits. 17 In-circuit

5.5 ARCHITECTURE OVERVIEW Block Diagram of the AVR Architecture FIGURE 5.3 ARCHITECTURE OVERVIEW In order to maximize performance and parallelis m, the AVR uses Harvard architecture with separate memories and buses for progra m and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre -fetched from the Program memory. This concept enables instructions to be execut ed in every clock cycle. The Program memory is In-System re programmable Flash m emory. 18

The fast-access Register File contains 32 x 8-bit general purpose working regist ers with a single clock cycle access time. This allows single-cycle Arithmetic L ogic Unit (ALU) operation. In a typical ALU operation, two operands are output f rom the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabli ng efficient address calculations. One of these address pointers can also be use d as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in thi s section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be execu ted in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly a ddress the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Applic ation Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data S RAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset rou tine (before subroutines or interrupts are executed). The Stack Pointer SP is re ad/write accessible in the I/O space. The data SRAM can easily be accessed throu gh the five different addressing modes supported in the AVR architecture. 19

The memory spaces in the AVR architecture are all linear and regular memory maps . A flexible interrupt module has its Control Registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts h ave a separate interrupt vector in the Interrupt Vector table. The interrupts ha ve priority in accordance with their Interrupt Vector position. The lower the In terrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Contr ol Registers, SPI, and other I/O functions. The I/O Memory can be accessed direc tly, or as the Data Space locations following those of the Register File.\ 5.6 to of in Serial Communication Serial communication is often used either to control or receive data from an embedded microprocessor. Serial communication is a form I/O in which the bits of a byte begin transferred appear one after the other a timed sequence on a single wire.

5.6.1 Introduction of RS-232 RS-232 is a straightforward, universal, and commonl y implemented serial interface. Despite its limited 15 m transmission distance, its low cost and easy wiring features make RS-232 the first choice for many appl ications. RS-232 establishes two-way (full-duplex) communications, with signals represented by voltage levels measured with respect to a system common ground (p ower/logic ground). Serial communication requires that you specify the following four parameters: • • • • • Th e baud rate of the transmission The number of data bits encoding a character The number of data bits encoding a character The sense of the optional parity bit T he number of stop bits 20

Pin Description 1 Protective Ground 2 Transmitted Data 3 Received Data Pin Description 10 (Reserved for Data Set Testing) 11 Unassigned 12 Sec. Rec d. Line Sig. Detector Pin Description 19 Secondary Request to Send 20 Data Terminal Ready 21 Signal Qu ality Detector 4 Request to Send 5 Clear to Send 13 Sec. Clear to Send 14 Secondary Transmitted Data 15 Transmission Signal Eleme nt Timing 6 Data Set Ready 7 Signal Ground (Common Return) 8 Received Line Signal 16 Secondary Received Data 17 Receiver Signal Element Timing Detector (DCE Sourc e) 9 (Reserved for data set 18 Unassigned testing) 22 Ring Indicator 23 Data Signal Rate Selector (DTE/DCE Source) 24 Transmit Sign al Element (DCE Source) Timing (DTE Source) 25 Unassigned TABLE5.1 RS-232C Interface Signals. 5.6.2 BIT STREAMS The RS232 standard describes a communication method where info rmation is sent bit by bit on a physical channel. The information must be broken up in data words. The length of a data word is variable. On PC s a length betwe en 5 and 8 bits can be selected. This length is the net information length of ea ch word. For proper transfer additional bits are added for synchronization and e rror checking purposes. It is important, that the transmitter and receiver use t he same number of bits. Otherwise, the data word may be misinterpreted, or not r ecognized at all. 21



With synchronous communication, a clock or trigger signal must be present which indicates the beginning of each transfer. The absence of a clock signal makes an asynchronous communication channel cheaper to operate. Less lines are necessary in the cable. A disadvantage is, that the receiver can start at the wrong momen t receiving the information. Resynchronization is then needed which costs time. All data received in the resynchronization period is lost. Another disadvantage is that extra bits are needed in the data stream to indicate the start and end o f useful information. These extra bits take up bandwidth. Data bits are sent wit h a predefined frequency, the baud rate. Both the transmitter and receiver must be programmed to use the same bit frequency. After the first bit is received, th e receiver calculates at which moments the other data bits will be received. It will check the line voltage levels at those moments. With RS232, the line voltag e level can have two states. The on state is also known as mark, the off state a s space. No other line states are possible. When the line is idle, it is kept in the mark state. START BIT RS232 defines an asynchronous type of communication. This means, that sending of a data word can start on each moment. If starting at each moment is possible, this can pose some problems for the receiver to know w hich is the first bit to receive. To overcome this problem, each data word is st arted with an attention bit. This attention bit, also known as the start bit, is always identified by the space line level. Because the line is in mark state wh en idle, the start bit is easily recognized by the receiver. DATA BITS Directly following the start bit, the data bits are sent. A bit value 1 causes the line t o go in mark state, the bit value 0is represented by a space. The least signific ant bit is always the first bit sent. 22

PARITY BIT For error detecting purposes, it is possible to add an extra bit to t he data word automatically. The transmitter calculates the value of the bit depe nding on the information sent. The receiver performs the same calculation and ch ecks if the actual parity bit value corresponds to the calculated value. STOP BITS Suppose that the receiver has missed the start bit because of noise on the transmission line. It started on the first following data bit with a space value. This causes garbled date to reach the receiver. A mechanism must be prese nt to resynchronize the communication. To do this, framing is introduced. The pe riod of time lying between the start and stop bits is a constant defined by the baud rate and number of data and parity bits. The start bit has always space val ue, the stop bit always mark value. If the receiver detects a value other than m ark when the stop bit should be present on the line, it knows that there is a sy nchronization failure. This causes a framing error condition in the receiving UA RT. The device then tries to resynchronize on new incoming bits. For desynchroni zing, the receiver scans the incoming data for valid start and stop bit pairs. T his works, as long as there is enough variation in the bit patterns of the data words. The stop bit identifying the end of a data frame can have different lengt hs. Actually, it is not a real bit but a minimum period of time the line must be idle (mark state) at the end of each word. On PC s this period can have three l engths: the time equal to 1, 1.5 or 2 bits. 1.5 bits is only used with data word s of 5 bits length and 2 only for longer words. A stop bit length of 1 bit is po ssible for all data word sizes. 23


5.6.3 RS-232 PHYSICAL PROPERTIES The RS232 standard describes a communication me thod capable of communicating in different environments. This has had its impact on the maximum allowable voltages etc. on the pins. In the original definition, the technical possibilities of that time were taken into account. The maximum b aud rate defined for example is 20 kbps. With current devices like the 16550A UA RT, maximum speeds of 1.5 Mbps are allowed. 5.6.4 USART USART stands for Univers al Synchronous Asynchronous Receiver Transmitter. It is sometimes called the Ser ial Communications Interface or SCI FEATURES The Universal Synchronous and Asynchronous serial Receiver and Transmit ter is a highly flexible serial communication device. The main features are: • Ful l Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchron ous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Suppor ted by Hardware • Data Over Run Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate In terrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode 24


The dashed boxes in the block (listed from the top): Clock ters are shared by all units. tion logic for external clock baud rate generator.

diagram separate the three main parts of the USART Generator, Transmitter and Receiver. Control regis The clock generation logic consists of synchroniza input used by synchronous slave operation, and the

The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Tran smitter consists of a single write buffer, a serial Shift Register, Parity Gener ator and control logic for handling different serial frame formats. The write bu ffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and d ata recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, cont rol logic, a Shift Register and a two level receive buffer (UDR). The Receiver s upports the same frame formats as the Transmitter, and can detect frame error, d ata overrun and parity errors. 26

CHAPTER – 6 SOFTWARE DESCRIPTION AVRSTUDIO 4 AND ATMEGA8515 Atmel offers both 8-bit and 32-bit AVR flash microcon trollers. AVR combines the most code-efficient architecture for c and assembly p rogramming with the ability to tune system parameters throughout the entire life cycle of your key products. No other microcontrollers deliver more computing pe rformance at lower power consumption. Combined with industry leading development tools and design support, you get to market faster. And once there, you can eas ily and cost-effectively refine and improve your product offering. 6.1 AVR STUDI O AVR studio 4 is an integrated development environment (IDE). just like any oth er IDE, AVR studio 4 is project based. a project is like an environment for a pa rticular program that is being written. it keeps track of what files are open, c ompilation instructions, as well as the current graphical user interface (GUI) s elections. 6.2 LINE-BY-LINE DEBUGGING Line-By-Line debugging is the best way to take control of the simulation. it allows the programmer to verify data in regis ters and memory. there are several ways to get into line-by-line debugging mode. the first would be to start the simulation in line-by-line debug mode by clicki ng on the debug icon, or through the menu debug->start debugging. When the progr am is in run mode, hitting the pause key will halt the simulation and put it int o line-by-line mode. Also, if a break point was set in the code, the simulation will automatically pause at the break point and put the simulation into line-byline mode. 27

When running in line-by-line mode, several new buttons will be activated. These allow you to navigate through the program. a. Step into (f11) – steps into the cod e. Normal operation will run program lineby-line, but will step into routine cal ls such as the rcall command. b. Step over (f10) – steps over routine calls. Norma l operation will run program line-by-line, but will treat routine calls as a sin gle instruction and not jump to the routine instructions. c. Step out (shift+f11 ) – steps out of routine calls. This will temporarily put the simulation into run mode for the remainder of the routine and will pause at the next instruction aft er the routine call. d. run to cursor (ctrl+f10) – runs simulation until cursor is reached. the cursor is the blinking line indicating where to type. Place the cu rsor by putting the mouse over the instruction we want to stop at and hit the ru n to cursor icon. After experimenting around with these four commands, we will b e able to navigate through the code with ease. 6.3WORKSPACE WINDOW The workspace window holds valuable information about the project and the simulation. There a re three areas of the workspace windows signified by tabs at the bottom; project , I/O, and info. The project window contains all the information related to the project such as files and file structuring. From here, files can be created, des troyed, rearranged, or organized. You can also use this window to select which f ile appears in the editor window. The I/O window contains all the registers asso ciated with the simulated chip. By default, this window should automatically be displayed when simulation is run in line-by-line mode. I/O window in workspace s hows an example of what the I/O window looks like during the lab 1 simulation. 28

By expanding this window, additional information is available such as bits and a ddress of the registers. it is in this window where you can simulate input on th e ports. The node labelled I/O atmega128 contains all the special registers asso ciated with the chip. By expanding the I/O atmega8515 node, you have access to t he ports and can simulate input or interrupts through them. The info window disp lays information about the current chip that is being simulated. This informatio n contains names and addresses of registers and external pins. it is a good poin t of reference when programming for the chip. 6.4 MEMORY WINDOWS In actuality, a ll of the registers are actually parts of memory within the atmega8515. In addit ion to the register memory, the atmega8515 has several other memory banks, inclu ding the program memory, data memory, and EEPROM memory. of course, no good simu lator is complete without being able to view and/or modify this memory, and AVR studio 4 is no exception. To view the memory window, follow the menu command vie w->memory window or hit alt+4. The window will pop up on top and can sometimes g et in the way. a good way to organize it is to drag the window down next to the message window at the bottom and it will slide in right next to it. Expanding th e window will also show additional information. The main area of the memory wind ow contains three sets of information; the address of the line in the blue, the data of the memory in hexadecimal format, and the ASCII equivalent of that data. The pull down menu on the top left allows you to select the various memory bank s available for the atmega8515. To edit the memory, just place the cursor in the hexadecimal data area and type in the new data. 29

6.5 DEBUGGING STRATEGIES Debugging code can be the most time consuming process i n programming. here are some tips and strategies that can help with this process : A. Comment, comment, comment. Unless it is absolutely blatantly obvious of wha t the code is doing, comment every line of code. Even if the code is obvious, at least comment what the group of instruction is doing, for example, “initializing stack pointer”. B. Pick a format and stick with it. The format is how you lay out your code. a single programming format will make reading the code a lot easier. C. Before writing any actual code, write it out in pseudo-code and convince your self that it works. D. Break the code down into small routines and function call s. Small sections of code are much easier to debug than one huge section of code . E. Wait loops should be commented out during debugging. The simulator is much slower than the actual chip and extensive wait loops take up a lot of time. F. U se breakpoints to halt the simulation at the area known to be buggy. Proper use of breakpoints can save a lot of time and frustration. G. Carefully monitor the i/o window and memory windows throughout the simulation. These windows will indi cate any problem. H. Make sure the AVR instruction is actually supported by the atmega85c35. I. The atmega85c35 has certain memory ranges; so make sure that whe n manipulating data 30

CHAPTER 7 CONCLUSION AND FUTURE WORK 7.1 CONCLUSION The objective of this projec t that is “AUTOMATED ATTENDANCE USING RFID” was to design a system based on RFID tec hnology that will not only change the hectic manual attendance procedure but als o automate user’s office. The final design of the project accomplished the idea of multinode environment which is responsible for automatic attendance and office automation according to the personalized profile of the RFID card holder. The de sign also deals with the issues (reliable data transfer) of multinode environmen t. This project facilitates the users in numerous ways like time saving in atten dance procedure, security, employees’ attendance management and many more. 7.2 FUT URE WORKS With the coming availability of low cost, short range radios along wit h advances in wireless networking, it is expected that wireless ad hoc sensor ne tworks will become commonly deployed. This project can be improvised by using ex ternal memory because the project design has a capability of handling 65000 card IDs which is large enough for any organization but the limitation lies in the m icrocontroller storage capacity. This limitation can be overcome by the use of N VRAM with the reader node which will not only make the design scalable but also flexible. NVRAM not only provide us extra memory but also enable us to add cards IDs on the run time 31

CHAPTER 8 REFERENCE INTERNET 1. Moxa Success Story – Attendance Recording System http://www.moxa.com/solutions/ success_stories_Attendance_Recording_System.html (Accessed on 5th September, 200 7) 2. Atmel Corporation, www.atmel.com/products/8051/ (Accessed on 4th October,2007) 3. Francisco Silva, Victor Filipe and Antnio Pereira. Automatic co ntrol of students attendance in classrooms using RFID. The Third International C onference on Systems and Networks Communications. Sliema, Malta. 2008. 4. Wikipe dia, RFID Radio-frequency identification. URL http://en.wikipedia.org/wiki/Rfid. BOOKS 1. Mohammad Ali Mazidi, “The 8051 Microcontroller and Embedded Systems Using Assembly and C”, Second Edition, p 28 32

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