Alu ALU Code for VHDL using XILING

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ALU Code for VHDL using XILING

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IMPLEMENTATION OF
ARITHMETIC LOGIC UNIT
USING VHDL
SUBMITTED BY:
MENTORED BY:
MILIND SINGLA 2K12/EC/98
DR. S. INDU
MOHIT YADAV 2K12/EC/99
PIYUSH KUMAR 2K12/EC/120

INTRODUCTION

The Arithmetic Logic Unit (ALU) is essentially the heart of a CPU.
This is what allows the computer to add, subtract, and to
perform basic logical operations such as AND/OR. Since every
computer needs to be able to do these simple functions, they
are always included in a CPU.
After the information has been processed by the ALU, it is sent
to the computer memory.

Even the simplest microprocessors contain an ALU for purposes
such as maintaining timers. The processors found inside

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modern CPUs and graphics processing units
accommodate very powerful and very complex ALUs.

(GPUs)

HISTORY

Hungarian-American
pure
and
applied
mathematician,
physicist, and polymath, John von Neumann, proposed the ALU
concept in 1945, when he wrote a report on the foundations for
a new computer called the EDVAC.

Cascadable 8 Bit ALU Texas Instruments SN74AS888

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OPERATIONS
An ALU must process numbers using the same formats as the
rest of the digital circuit. The format of modern processors is
almost always the two's complement binary number
representation.
The ones' complement and two's complement number systems
allow for subtraction to be accomplished by adding the
negative of a number in a very simple way which negates the
need for specialized circuits to do subtraction; however,
calculating the negative in two's complement requires adding a
one to the low order bit and propagating the carry. An
alternative way to do two's complement subtraction of A−B is
to present a one to the carry input of the adder and use ¬B
rather than B as the second input. The arithmetic, logic and
shift circuits introduced in previous sections can be combined
into one ALU with common selection.
BASIC FUNCTIONS PERFORMED BY AN ALU

OPERATION
TYPE
Arithmetic
Arithmetic
Arithmetic
Arithmetic
Logic
Logic
Logic
Logic

OPERATION

FUNCTION

A+B
A-B
A+1
A-1
A⋀B
A⋁B
A⊕B
A’

Addition
Subtraction
Increment A
Decrement A
AND operation
OR operation
XOR operation
Complement A

Engineers can design an arithmetic logic unit to calculate most
operations. The more complex the operation, the more
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expensive the ALU is, the more space it uses in the processor,
and the more power it dissipates. Therefore, engineers
compromise. They make the ALU powerful enough to make the
processor fast, yet not so complex as to become prohibitive.
The options vary from the fastest and most expensive one to
the slowest and least expensive one. Therefore, while even the
simplest computer can calculate the most complicated formula,
the simplest computers will usually take a long time doing that
because of the several steps for calculating the formula.
.

VHDL
VHDL (Very High Speed Integrated Circuit Hardware Description
Language) is a hardware description language used in
electronic design to describe digital and mixed-signal systems
such as field-programmable gate arrays and integrated circuits.

 VHDL is commonly used to write text models that describe a
logic circuit. Such a model is processed by a synthesis
program. A simulation program is used to test the logic
design using simulation models to represent the logic circuits
that interface to the design. This collection of simulation
models is commonly called a testbench.
 VHDL has constructs to handle the parallelism inherent in
hardware designs. VHDL is strongly typed and is not case
sensitive. In order to directly represent operations which are
common in hardware, VHDL has an extended set of boolean
operators including NAND and NOR.

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 VHDL has file input and output capabilities, and can be used
as a general-purpose language for text processing, but files
are more commonly used by a simulation testbench for
stimulus or verification data.
 When a VHDL model is translated into the "gates and wires"
that are mapped onto a programmable logic device such as a
CPLD or FPGA, then it is the actual hardware being
configured, rather than the VHDL code being "executed" as if
on some form of a processor chip.

VHDL SIMULATORS

 Aldec Active-HDL
 Cadence Incisive (Past products: NC-VHDL)
 Mentor Graphics ModelSim. Special versions of this
product used by various FPGA vendors e.g. Altera, Lattice
 Synopsys VCS-MX
 Xilinx Vivado (a.k.a. xsim). Based on iSim from the
previous ISE tool-chain

ADVANTAGES OF VHDL

 The key advantage of VHDL, when used for systems
design, is that it allows the behavior of the required
system to be described (modeled) and verified (simulated)
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before synthesis tools translate the design into real
hardware (gates and wires).
 Allows the description of a concurrent system. VHDL is a
dataflow
language,
unlike
procedural
computing
languages such as BASIC, C, and assembly code, which all
run sequentially, one instruction at a time.
 A VHDL project is multipurpose. Being created once, a
calculation block can be used in many other projects.
 A VHDL project is portable. Being created for one element
base, a computing device project can be ported on
another element base, for example VLSI with various
technologies.

CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity alu4 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
z : out STD_LOGIC;
cout : out STD_LOGIC;
s1 : in STD_LOGIC;
s2 : in STD_LOGIC;
s3 : in STD_LOGIC);
end alu4;
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architecture Behavioral of alu4 is
begin
process (s1, s2, s3, a, b)
begin
if ( s1 = '0' and s2 = '0' and s3 = '0' ) then
z <= a xor b xor cin;
cout <= (a xor b) and cin;
elsif ( s1 = '0' and s2 = '0' and s3 = '1' ) then
z<= a xor b xor cin;
cout <= ((not a) and b) or ((not a) and cin) or ( b and
cin );
elsif ( s1 = '0' and s2 = '1' and s3 = '0' ) then
z<= a and b;
elsif ( s1 = '0' and s2 = '1' and s3 = '1' ) then
z<= a or b;
elsif ( s1 = '1' and s2 = '0' and s3 = '0' ) then
z<= a nand b;
elsif ( s1 = '1' and s2 = '0' and s3 = '1' ) then

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z<= a xor b;
elsif ( s1 = '1' and s2 = '1' and s3 = '0' ) then
z<= not a ;
elsif ( s1 = '1' and s2 = '1' and s3 = '1' ) then
z<= a xor '1';
cout <= a;
end if;
end process;
end Behavioral;

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