Apple Macbook M38A

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Content

 

8

7

6

2

3

4

5

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

REV

06/22/06

PAGE 1 2 3

D

C

JD

JD

JD

JD

RT

RT

JD

JD

4 5

JD

6

RT

4 5 RT 6 JD 7 JD 8 JD 9 JD 10 JD 11 JH 12 JH 13 JH 14 JH 15 JH 16

7 8 9 (M42) 10 M42 11 M1 12 M1 13 14 M1 15 M1 16

MS MS

M1

PS

JH

PS

JH

M1

B

M1 M42

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34

MS

MS PS PS PS PS PS

PS PS JD JD   JD JD JD JD JD PS  

PS

PS RT JD  

38 41 42 43 44 45 46

(M42)

47

JD JD JD JD JD JD JD JD JD

1 2 3

JD

(M42)

MS

CIRCUIT

PDF

(M42)

M1

A

DRI

TABLE OF CONTENTS SYSTEM BLOCK DIAGRAM POWER BLOCK DIAGRAM TABLETEST ITEMS & REVISION HISTORY FUNC POWER CONNECTOR / POWER ALIAS CPU - BUS INTERFACE CPU - PWR & GND CPU - DECAPS CPU - THERMAL SENSOR CPU - ITP CONN NB - CPU INTERFACE NB - VIDEO INTERFACE NB - MISC INTERFACES NB - DDR2 INTERFACE NB - POWER 1

RX

SO SO SO SO RP RP

59 60 61 63 65 66 67 68 72 73 74 75 76

JD JD MS

30 31 JD 32 JD 33 JD 34 JD 35 JD 36 JD 37 JD 38 JD 39 JD 40 JD 41

DDR2 - TERMINATION DDR2 - VTT SUPPLY CLOCKS - GENERATOR CLOCKS - TERMINATIONS ATA (SATA AND IDE) CONN’S LAN - YUKON’S PCIE INTERFACE LAN - YUKON’S PWR, MISC LAN - CONN FIREWIRE - FW323-06 FIREWIRE - DECAPS FIREWIRE - CONN’S USB - CONN’S

POWER 2 GROUNDS DECAPS CONFIG STRAPS RTC,LAN,AUDIO,ATA,CPU,LPC PCIE,SPI,USB,DMI,PCI SMB,GPIO,PM,CLKS POWERS AND GROUNDS DECAPS MISC SMB BUS CONNECTIONS - SO-DIMM CONN A - SO-DIMM CONN B (REVERSED)

RP RP RP RP RP JH M1 M1 M1 M1 M1 M1

M1 M1 M1 JH JH JH JH

MS JH MS MS MS JD PT PT PT PT RT RT RT

RP

NB NB NB NB SB SB SB SB SB SB SB DDR2 DDR2

RT

53 54 58

DRI

MS

17 18 JH 19 JH 20 JD 21 JD 22 JD 23 JD 24 JD 25 JD 26 JD 27 JD 28 JD 29 JD

PAGE

77 78 79

80 81 83 84 85 86 87 88 89

90 91 92 93

94 95 96 97

RT RT RT RT RT JH JH JH JH JH JH JH

JH JH JH JH JH JH JH

43 JD 44 MS 45

ZONE

445818

13

ENG APPD

DESCRIPTION OF CHANGE

ECN

ENGINEERING RELEASED

DATE

DATE

0 6 /2 2 /0 6

0 6 /2 2 /0 4

CIRCUIT

PDF JD

1 CK APPD

M38A - DVT

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

D

PCI-E - AIRPORT MINI-PCIE CONN PCI-E - UNUSED PORTS SMC - H8S2116

MS

46 47 48 JD 49 MS 50 MS 51 JD 52 JD 53 JD 54 JD 55 JD 56 RT 57 RT 58 MS

JH

SMC - LPC+ SMB BUSSES, MISC SMC CONN SMC - GPU/NB THERMAL SENSOR SMC - SPI BOOTROM SMC - FANS SMC - FANS SMC - TPM AUDIO - CODEC,VREG,MIC BIAS AUDIO - INTERNAL SPEAKER AMP AUDIO - I/O CONN’S,EMC AUDIO - DETECT TRANSLATORS VR - CPU CORE VR - CPU I-V SENSE CKT

C

RT

59 60 61 RT 62 RT 63 RT 64 JH 65 JH 66 JH 67 JH 68 JH 69 JH 70 JH 71

VR - "S0" 1.2V & 2.5V (GRAFIX) VR - "S0" 1.8V VR - "S3" 1.8V VR - "S0" 1.5V VR - "S0" 1.05V VR - "S3" 3.3V AND 5V GPU - M56 PCI-E GPU - VCORE SUPPLY GPU - M56 CORE PWR GPU - M56 FRAME BUFFER GPU - MISC GPU - GDDR SDRAM A GPU - GDDR SDRAM B

72 73 74 JH 75 JH 76 JH 77 JH 78

GPU GPU GPU GPU GPU GPU GPU

RT RT

JH

JH

JH

-

B

M56 GPIO,DVO,MISC M56 CLOCKS M56 VIDEO INTERFACES INTERNAL DISPLAY CONN’S TP’S TMDS,INVERTER,EXT VGA EXTERNAL DISPLAY CONN’S

DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

METRIC

XX

X.XX

DRAFTER

DESIGN CK

ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

X.XXX

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

ANGLES

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART TITLE

DO NOT SCALE DRAWING

SCH,MLB,M38A NONE SIZE

MATERIAL/FINISH NOTED AS THIRD ANGLE PROJECTION

8

7

6

5

4

3

APPLICABLE

D

DRAWING NUMBER

051-7148 SHT

2

1

REV.

13

1

OF

110

 

8

6

7

CPU

1

J1101

ITP CONN

(1.83/2.17GHZ) CORE (~1.2V) PAGE 8 J9700

2

3

4

5 J0700

PAGE 11

PAGE 7

J9402

MINI-DVI

LVDS

(TMDS - VGA)

(INTERNAL)

64-BIT FSB

D

PAGE 97

PAGE 94

D

667MHZ

J2800 J2900 PAGE 12

GDDR3 U8900, U8950

64-BIT 1.8V/700MHZ(?)

PA 9G 3E  7  8

FRAME BUFFER A

 S  E  G  A  P

PA 9G 3E

 E  G  A  P

U8400

PCIE

NB

PCIE X16 2.5GHZ

13

PAGE 89

DIMM

1.8V/667MHZ

PARALLEL

64-BIT

TERM

 E

 N G  A  I P  A  M

CORE (1.05V)

PAGE

DDR2 - DUAL CHAN

 R  O  M 5  E 1  M

U1200

 4  8

GPU

 Y

PAGE 16-17

PAGES 30

PAGES 87

PAGE 28-29

U3301

DMI

MISC

CK410

PAGE 14

PAGE 14

GDDR3 64-BIT 1.8V/700MHZ(?)

4-BIT DMI

CLOCKS

TERMS

PAGE 33

PAGE 34

1.2V/800MHZ J2901 ALS+ATS TSENS

CONTROL = 2.5V

U9000, U9050

U1000 CPU TSENS

FRAME BUFFER B

C

U6100 GPU+NB TSENS

C

J6601 HD TSENS

PAGE 90

J6602 ODD TSENS

U6300/01

SPI BOOTROM

J6500,J6501,J6600 FAN CONNS

PAGE 63 RMT MLB

FAN

U5800

U6700

SMC

J6000

TPM

PAGE 58

LPC+ CONN

PAGE 67

PAGE 60

JE310/JE320/JE330

SATA CONNECTOR HARD DRIVE

 S A T A 2

1.2V/1.5GHZ

 S A T A  0

PAGE 38

JC901

UATA   CONNECTOR

P S A A  G E T   2 A 1

UATA/133

3.3V/133MHZ

OPTICAL

PAGE 22

PAGE 22

SB

0

 E  G  A  P

2

4

PAGE 47

4-BIT (3.3V/33MHZ)

 1  2  2

 B  S E  G  U A

CORE (1.05V)

J4700

BT CONN

PAGE 47 3

7

 A  R  E  M  A  C

PAGE 48

 R  I

J5300 (AIRPORT CONN)

 7  ,  3

 P

NOT USED

 5

P P A  C P  G  #   O E I 1R   T 2 2 E

X1 - 1.5GHZ

 C  P  L

CONNECTORS

 1  2

 4  ,  2  ,  0

P  #   O 2 -R  5 T

X1 - 1.5GHZ

SPI

U2100

 U A T A

P A  G E   2 1

PAGE 38

B

DMI

JE350

BNDI INTERFACE

USB

JC900

 6

CORE PAGE 24

PAGE 23

PCI

P

 O  #   0 R T

B

GPIOS  3

 B 2  M E  G  S A

AZALIA

 P

PAGE 22

PAGE 21

J2800 J2900 DIMM’S

U3301 CK410M

J5300 AIRPORT

33MHZ 32-BIT

U6800

MINI-PCIE AIRPORT

YUKON

FW323-06

GIG ETHERNET

FIREWIRE A

OPTICAL OUT J7303

COMBO OUT CONNECTOR

PAGE 68 PORT A

PAGE 153

PORT C PORT F

PAGE 44 PAGE 41

PAGE 53

A

S/PDIF

AUDIO CODEC STA9221

U4101

J5300

0

1

JD600

ETHERNET CONNECTOR PAGE 43

System Block Diagram

2

J7301  F  I  D  P   /  S

2 Diff pairs

4 Diff pairs

LINE OUT

PORT B

PAGE 72

SPEAKER

J7300

LINE IN

CONNECTOR PAGE 73

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

PAGE 73

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

MIC IN BNDI

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

INTERFACE

SIZE

OPTICAL IN

APPLE COMPUTER INC.

0 51 51 -7 -7 14 14 8 SHT NONE

7

6

5

4

3

2

REV.

DRAWING NUMBER

D SCALE

8

A

NOTICE OF PROPRIETARY PROPERTY

CONNECTOR

JE350

JE000, JE001

FIREWIRE A CONNECTORS PAGE 46

SPEAKER AMP

2

1

OF

13 110

 

8

6

7

2

3

4

5

1

AC/DC POWER SUPPLY 12V, 180W, 15A S5

DC/DC BOARD

D

D 12V, 12A

12V_S5

5V, 4A

12V_S0

PPVCORE_CPU_S0 1.3V @ 36A

CPU_CORE

PAGE 75

PP1V05_S0 1.05V @ 8.9A PAGE 81

PP1V8_S3 1.8V @ 10A

5V_S5

5V_S0

FANS HARD DRIVE LCD SPEAKER AMP

CPU_FSB NB_CORE NB_FSB SB_CORE

PP4V5_AUDIO_ANALOG 4.5V @ ?A

PP3V3_S3

3_3V_S0

ENET

FET PAGE 83

PP1V2_S3 1.2V @ 2.5A

NB_GPIO GPU_GPIO

PP2V5_S0 2.5V @ 0.9A PAGE 77

ENET_CORE

PAGE 77

PP1V2_S0

PP0V9_S0 0.9V @ 1A

GPU_PCIE

FET PAGE 77

PAGE 31

PP1V5_S0 1.5V @ 8A

AUDIO

OPTICAL HARD DRIVE

PP5V_S3

NB_DRAM DRAM_CORE DRAM_IO

3_3V_S5

PAGE 68

FET PAGE 83

PAGE 79

C

3.3V, 4A

C

USB

CPU_AVDD NB_PCIE SB_IO

PAGE 80

PP1V0R1V2_S0_GPU 1.2V @ 15A

GPU_CORE

PAGE 85

PP1V8_S0 1.8V @ 8A

GPU_DRAM GDDR_IO

PAGE 78

PANEL INVERTER FIREWIRE

B

B

Power Block Diagram

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148   13

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

3

1

OF

110

 

8

6

7

3

4

5

2

1

COMMON TABLE_5_HEAD

TABLE_5_HEAD

P AR T#

QTY

D ES C RI PT I ON

REFERENCE

DESIGNATOR(S)

CRITICAL

P AR T #

BOM OPTION

QTY

D ES CR I PT IO N

REFERENCE

DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_ITEM

511S0025

1

IC,CPU-SKT,479BGA

J0700

TABLE_5_ITEM

051-7148

C RITICA L

1

PCB,SCHEM,MLB,M38A

SCH1

820-2052

1

PCB,FAB,MLB,M38A

341T0040

1

EFI ROM,M38A

U6301

114S0 264

1

3.01K,1%,1/16W,402,MF-LF

R8522

341T0 039

1

IC,SMC,M38A

17_INCH_LCD TABLE_5_ITEM

TABLE_5_ITEM

338S0328

1

IC,945PM,NORTHBRIDGE

U 1200

CRITICAL

34 3S0385

1

IC,SB,652BGA

U 2100

CRITICAL

338S0344

1

IC,ATI,M56P,GRAFIXCTLR,880BGA,LF

U 8400

CRITICAL

359S0101

1

IC,CY28445-5,CLK GEN,68PIN QFN

U 33  01

CRITICAL

338S0270

1  

IC,88E8053,GIGABIT

U 4101

CRITICAL

34 1S1797

1

IC,ENET LAN ROM

U 4102

CRITICAL

TABLE_5_ITEM

D

(341S1908 - DEVEL) (341S1909 - FINAL) (335S0384 - BLNK)

MLB1

1 7_INC H_LCD 17_INCH_LCD

U5800

CRITICAL

1 7_INC H_LCD

U8400

CRIT ICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

(341S1907 - PROG) (338S0274 - BLNK)

GPU_VCORE_1P2V TABLE_5_ITEM

TABLE_5_ITEM

ENET XCVR,64P QFN,NO

TABLE_5_ITEM

338S0 315

1

IC,ATI,M56LP,GRAFIX

114S0287

1

5.11 K,1%, 1/16 W,40 2,MF -LF

CTLR,880BGA,LF

R8522

G PU_V CORE_ 0P95 3V

GPU_B26_LP

114S0 281

1

4.53K,1%,1/16W,402,MF-LF

R8522

GPU_VCORE_1P0V

337S3 299

1

2.00G HZ ME ROM

CPU

CRITICAL

2 P00_CP U

337S3 293

1

2.16GHZ MEROM

CPU

CRIT ICAL

2P16_CPU

TABLE_5_ITEM

(335S0382)

TABLE_5_ITEM

TABLE_5_ITEM

33 8S0279

1

IC,FW32306,1394A

LINK,TQFP

U 4400

CRITICAL

D

TABLE_5_ITEM

CRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

UNSCREENED P/N 353S1235

341S1789

1

IC,TPM,TSSOP,28P

 

35 3S1465

1

IC,CPU VREG,IMVP,TWO PHASE

U 67 00

C RI TI CA L

U 7500

C RITICA L

L EM EN U TABLE_5_ITEM

TABLE_5_ITEM

128S0078

3  

82 5-6447

1

CAP,EL,AL,330UF,20%,16V,10X12.7MM,SMD,LF

C7517,C7518,C7910  

CRITICAL

X14

C RITICA L

TABLE_5_ITEM

MLB

LABEL,48.0X4.8

 

C

C

TABLE_ALT_HEAD

P AR T N UM BE R

ALTERNATE FOR PART NUMBER

126S 0096

126S0076

1 2 6S 0 0 86

1 2 6S 0 0 78

128S0080

128S0078

B OM O PT IO N

REF DES   COMMENTS: TABLE_ALT_ITEM

C78 01

 

SANYO

W16CE680KX

680UF 16V

LF

TABLE_5_HEAD

P AR T #

QTY

D ES CR I PT IO N

REFERENCE

DESIGNATOR(S)

CRITICAL

BOM OPTION

C699,C940,C1900,C1901,C1968 SANYO W6CE330FS 330UF 6.3V LF TABLE_ALT_ITEM

TABLE_5_ITEM

333S0354

4

IC,SGRAM,GDDR3,8MX32,700MHZ,136FBGA

U8900,U8950,U9000,U9050   CRITICAL

ATI_FB_128M_SAMSUNG

333S0358

4

IC,SGRAM,GDDR3,8MX32,700MHZ,136FBGA

U8900,U8950,U9000,U9050

CRIT ICAL

ATI_FB_128M_HYNIX

333S0 376

4

IC,SGRAM,GDDR3,8MX32,700MHZ,136FBGA

U8900,U8950,U9000,U9050

CRIT ICAL

ATI_FB_128M_INFINEON

TABLE_ALT_ITEM

C7517,C7518,C7910

SANYO

16SVP330M 330UF 16V SMD LF

TABLE_5_ITEM

TABLE_ALT_ITEM

124-0338

124-0333

  

C7501,C8014

CAP,AL,EL,680UF,16V,RAD,10X12.5MM

TABLE_5_ITEM

TABLE_ALT_ITEM

138S0580

138S0552

 

22UF 0805

TABLE_ALT_ITEM

353S1321

353S1105

3 7 8S 0 1 41

3 7 8S 0 1 40

353S 1461

353S1 465

U7910

LM339 TABLE_ALT_ITEM

LED601,LED602,LED603 LED

TABLE_ALT_ITEM

U75 00

 

CPU

REGULATOR -

ISL9504

TABLE_5_HEAD

P AR T #

QTY

D ES CR I PT IO N

CRITICAL

BOM OPTION

U8900,U8950,U9000,U9050

REFERENCE

DESIGNATOR(S)

CRIT ICAL

ATI_FB_256M_SAMSUNG

IC,SGRAM,GDDR3,16MX32,700MHZ,136FBGA

U8900,U8950,U9000,U9050

CRITICAL

ATI_FB_256M_HYNIX

IC,SGRAM,GDDR3,16MX32,700MHZ,136FBGA

U8900,U8950,U9000,U9050

CRIT ICAL

ATI_FB_256M_INFINEON

TABLE_5_ITEM

333S0350

4

333S0351

4  

333S0 377

4  

IC,SGRAM,GDDR3,16MX32,700MHZ,136FBGA

TABLE_5_ITEM

TABLE_5_ITEM

B

B

Table Items

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

4

1

OF

13 110

 

8 88 76 61 59 41 26 11 10 6

97 88 75 6

88 6

6

7 88 83 81 80 79 78 77 11 6 5

PP5V_S0

83 81 80 79 59 6 5

PP12V_S0

"S0" RAILS

PP12V_S5

77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80 79 79

1

CRITICAL NOSTUFF

20% 2 6.3V ELEC CASE-C1

M-RT-TH

1

R601

D

10K

PU ON PAGE 76 IS USED

5% 1/16W MF-LF 2 402

2

3

4

5

6

7

8

9

10

11

SYS_POWERFAIL_L

76

1

C699 330UF

J600

HM9606E-P2

76 75 5

12

81 34

PP0V9_S0 MAKE_BASE=TRUE VOLTAGE=0.9V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

P PV C CO O RE _C _C PU

=PP0V9_S0_MEMVTT_LDO =PP0V9_S0_MEM_TERM

= PP PP VC OR OR E_ S S0 0 _C PU PU

31 77

PP1V05_S0

=PP1V2_S3_LAN

42

POWER (TRICKLE)

=PP3V3_S5_SB

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80 MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

30

=PPVCORE_S0_NB

16 19

=PP1V05_S0_CPU

5 7 8 9 11

=PP1V05_S0_FSB_NB

5 12 19

83 59 53 6 17 19

P P1 V8 _S 3 MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

21 24 25

=PPVCORE_S0_SB

24 25

= PP 1V 8_ S3 _M EM _N B

6 14 16 19

=PP1V8_S3_MEM_NB

6 14 16 19

=PP1V8_S3_MEM

5 28 29

=PP1V8_S0_MEMVTT

31

PP3V3_S3 MAKE_BASE=TRUE

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

19

=PP1V05_S0_SB_CPU_IO

23 25 26

=PP3V3_S5_SB_USB

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

22

=PP3V3_S5_SB_PM

11 23

=PP3V3_S5_SB_VCCSUS3_3

24 25

=PP3V3_S5_SB_VCCSUS3_3_USB

24 25

=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA 79 5

=PP1V05_S0_NB

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

ALWAYS ON WHEN UNIT HAS AC

8 9

=PP1V05_S0_NB_VTT

P/N 518-0189

PP1V2_S3

1 "S5" RAILS

ON IN RUN AND SLEEP

MAKE_BASE=TRUE VOLTAGE=1.25V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

MAKE_BASE=TRUE VOLTAGE=1.05V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

VOLTAGE=0 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 0

"S3" RAILS

ONLY ON IN RUN

PP5V_S5

2

3

4

5

PP3V3_S0

=PP3V3_S3_ENET

41 42

=PP3V3_S3_TPM

67

=PP3V3_S3_1V2REG

77

=PP3V3_S3_BT

47

83 81 80 79 59 6 5

D

24

=PP3V3_S5_SB_IO

22 27

=PP3V3_S5_FW

44 45 46

=PP3V3_S5_SMC

58 59

=PP3V3_S5_DEBUG

60

=PP3V3_S5_ROM

63

=PP5V_S5_SB

25

=PP12V_S5_FW

46

=PP12V_S5_CPU

76

PP5V_S5 MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

=PP3V3_S3_USB 1

C610

=PP3V3_S3_VGASYNC

0.1UF

U601 74LVC1G04DBVG4

5 88 79 77 58 23

IN

2

PM_SLP_S3_L

2

20% 10V CERM 402

80 11

SYS_PWRUP_L

4

PP1V5_S0 MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

SOT23-5

88 83 81 80 79 78 77 11 6 5

=PP1V5_S0_CPU

8

=PP1V5_S0_NB_PCIE

13 19

=PP1V5_S0_NB_VCCAUX

6 16 17 19

=PP1V5_S0_NB_VCCD_HMPLL

17 19

3

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

1

C600

0.1UF

20% 10V 2 CERM 402

C CRITICAL

1

U600

22

IN

14

74LC125

7

125 1 TSSOP

3

2

PLT_RST_L

R618 68

2

94

GPU_PWM_RST_L

OUT

5% 1/16W 402 MF-LF

U600_3

68 2 R619

1

58

SMC_LRESET_L

=PP1V5_S0_NB_VCCAUX

6 16 17 19

=PP1V5_S0_NB_PLL

19

=PP1V5_S0_NB

19

=PP1V5_S0_NB_TVDAC

19

=PP1V5_S0_NB_3GPLL

19

=PP1V5_S0_SB_VCC1_5_A_ARX

24 25

=PP1V5_S0_SB_VCCSATAPLL

24 25

=PP1V5_S0_SB_VCC1_5_A_ATX

24 25

=PP1V5_S0_SB_VCCUSBPLL

24 25

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

24 25

=PP1V5_S0_SB_VCC1_5_A

24 25

=PP1V5_S0_SB =PP1V5_S0_AIRPORT

OUT

83 60

PP5V_S3 MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

=PP5V_S3_USB

47

=PP5V_S3_BNDI

47

=PP5V_S0_MEMVTT

31

PP12V_S5 MAKE_BASE=TRUE VOLTAGE=12V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

C

GND RAILS XW601 SM   NOSTUFF 74

1

GND_AUDIO

2

XW602 SM

25 74 72

53

GND_AUDIO_SPKRAMP

1

 

2

NOSTUFF

5% 1/16W 402 MF-LF

R611 CRITICAL

1

U600 6

5

U600_6

2

14

NB_RST_IN_L

84

PEG_RESET_L

OUT

88 77 11

R612

125 4 TSSOP

7

68

5% 1/16W 402 MF-LF

74LC125

14

1

68

2

OUT

PP2V5_S0 MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

5% 1/16W 402 MF-LF

CHASSIS GND =PP2V5_S0_NB_VCCA_3GBG

U600

1

74LC125

14

8

9

68

2

42

ENET_RST_L

U600_8

R615 1

68

2

67

TPM_LRESET_L

88 76 61 59 41 26 11 10 6

OUT

5% 1/16W 402 MF-LF

B U600

1

74LC125 14

MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

68

2

53

AIRPORT_RST_L

OUT

5% 1/16W 402 MF-LF

11

R617

U600_11

7

PP3V3_S0

R616

CRITICAL

12

125 13 TSSOP

1

68

2

60

DEBUG_RST_L

OUT

5% 1/16W 402 MF-LF

97 93 91 88

=PP3V3_S0_GPU 1

C650 0.1UF

20% 10V 2 CERM 402

U650

5 94 91

GPU_DIGON

74AHC1G32

1

2

U650_4

32 97 88 75 6

3 1 79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

83 59 53 6

1

R602 1K

5% 1/16W

MF-LF 2 402

I TS TS _P LU LU GG ED ED _I N

R605

1

R600 1K

5% 1/16W

MF-LF 2 402

LED601 2

GREEN-3.6MCD 2.0X1.25MM-SM

SILKSCREEN:1

MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

17 19 19 22 25 27

=PP3V3_S0_SB_GPIO

21 23

=PP3V3_S0_SB_VCC3_3

24 25

=PP3V3_S0_SB_VCC3_3_PCI

24 25

=PP3V3_S0_SB_VCC3_3_IDE

24 25

=PP3V3_S0_SB_PCI

26

=PP3V3_S0_SB_PM

26

=PP3V3_S0_PATA

38

=PP3V3_S0_FAN

59 65 66

=PP3V3_S0_HD_TSENS

66

=PP3V3_S0_ODD_TSENS

66

=PP3V3_S0_SB_3V3_1V5_VCCHDA

24 25

=PP3V3_S0_TPM

67

=PPSPD_S0_MEM

28 29

73

GND_CHASSIS_AUDIO_EXTERNAL

47

GND_CHASSIS_USB

46 97

OMIT

GND_CHASSIS_FIREWIRE

33 34

ZH704P1

GND_CHASSIS_VGA GND_CHASSIS_RJ45

ZH601

4P25R3P5 ZH701P1 NOSTUFF 1

75 68 72 73 74 44

=PP3V3_S0_SB_VCCLAN3_3

24 25

77 14 19 20

=PP5V_S0_SB

25

C604

0.01UF

20% 16V 2 CERM 402

73

GND_CHASSIS_AUDIO_INTERNAL

OMIT

C601

ZH702P1

1

OMIT

ZH603 NOSTUFF 4P25R3P5 C602 ZH703P1 1 0.01UF

20% 16V 2 CERM 402

38

88 6

GREEN-3.6MCD 2.0X1.25MM-SM

PP12V_S0

MAKE_BASE=TRUE VOLTAGE=12V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

Power Conn / Alias

NOSTUFF 1

C603

=PP5V_S0_AUDIO

20% 16V 2 CERM 402

68

MAKE_BASE=TRUE

=PP12V_S0_FAN

60

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

65 66

  OMIT 2

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

PP12V_S0_AUDIO_SPKRAMP

=PP12V_S0_AUDIO_SPKRAMP

72

SIZE

MAKE_BASE=TRUE

GREEN-3.6MCD 2.0X1.25MM-SM

APPLE COMPUTER INC.

SILKSCREEN:2

7

051-7148

SCALE

6

5

4

3

2

REV.

DRAWING NUMBER

D

SHT NONE

8

A

0.01UF

PP5V_S0_AUDIO

XW605 SM 1

1

GND_CHASSIS_BNDI MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM VOLTAGE=0 MAKE_BASE=TRUE

4P25R3P5

0.01UF

1

XW604 SM   OMIT

OMIT

ZH606

160R138 47

ZH602

NOSTUFF 1

20% 16V 2 CERM 402

53

=PP3V3_S0_2V5REG =PP3V3_S0_NB

1

LCD_SHOULD_ON

LED603

VOLTAGE=0 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

1

OMIT

=PP3V3_S0_IMVP

SILKSCREEN:3

GND_CHASSIS_IO_RIGHT MAKE_BASE=TRUE

43

4P25R3P5

=PP3V3_S0_PCI

2

2

5% 1/16W MF-LF 402

B

=PP3V3_S0_AUDIO

=PP5V_S0_PATA

0

1

ZH604

=PP3V3_S0_CK410

=PP5V_S0_DEBUG

1

2

LED602 2

=PP3V3_S0_NB_VCC_HV =PP3V3_S0_SB

1

5% 1/10W MF-LF 2 603

I TS _A _A LI VE 1

1

PP5V_S0

820

PP3V3_S3

=PP3V3_S0_NB_PM =PP3V3_S0_NB_TVDAC

=PP3V3_S0_AIRPORT

SM-LF

4

A

R603

GND_CHASSIS_IO_LEFT MAKE_BASE=TRUE VOLTAGE=0 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

OUT

5% 1/16W 402 MF-LF

125 10 TSSOP

7

NOSTUFF

17 19

R614

CRITICAL

6

1

OF

 

13 110

 

8

6

7

2

3

4

5

1

OMIT

J0700 12 12 12 12 5 12 12 12 12 12

D

12 12 12 12 12 12 5

12 5 12 5 12 5 12 5 12 5

12 12 12 12 12 12 12 12 12 12 12 5 12 12 12

C

12 12 5

21 5 21 21 5

21 5 21 5 21 5 21 5

IO IO IO IO IO

IO IO IO IO IO

FSB_A_L<3>

J4

A3*

FSB_A_L<4>

L4

A4*

FSB_A_L<5>

M3

A5*

FSB_A_L<6>

K5

A6*

FSB_A_L<7>

M1

IO

FSB_A_L<8>

N2

IO

FSB_A_L<9>

A9*

N3

A10*

FSB_A_L<11>

P5

A11*

IO

FSB_A_L<12>

P2

A12*

FSB_A_L<13>

L1

A13*

IO

FSB_A_L<14>

P4

A14*

IO

FSB_A_L<15>

P1

A15*

R1

A16*

IO

FSB_A_L<16>

LOCK*

H4

12 5

FSB_LOCK_L

IO

RESET*

B1

FSB_CPURST_L

IN

RS0*

F3

IN

RS1*

FSB_REQ_L<2>

K2

REQ2*

HIT*

G6

12 5

FSB_REQ_L<3>

J3

REQ3*

HITM*

E4

FSB_REQ_L<4>

L5

REQ4* BPM0*

AD4

11

XDP_BPM_L<0>

BPM1*

AD3

11

XDP_BPM_L<1>

BPM2*

AD1

11

XDP_BPM_L<2>

BPM3*

AC4

11

XDP_BPM_L<3>

Y2

A17*

U5

A18*

FSB_A_L<19>

R3

A19*

FSB_A_L<20>

W6

A20*

FSB_A_L<21>

U4

A21*

FSB_A_L<22>

FSB_A_L<26>

T3

A26*

IO

FSB_A_L<27>

W3

A27*

IO

FSB_A_L<28>

W5

A28*

IN

IN

IO

FSB_A_L<18>

FSB_A_L<29>

Y4

FSB_A_L<30>

W2

FSB_A_L<31>

Y1

FSB_ADSTB_L<1>

V4

A31* ADSTB1*

CPU_A20M_L

A6

A20M*

CPU_FERR_L

A5

FERR*

CPU_IGNNE_L

C4

IGNNE*

CPU_STPCLK_L CPU_INTR

D5 C6

STPCLK* LINT0

CPU_NMI

B4

LINT1

CPU_SMI_L

A3

SMI*

TP_CPU_A32_L

PLACE TESTPOINT ON

12 5

 1  P  U  O  R  G  R  D  D  A

 S  L  A  N  G  I  S  P  T  I   /  P  D  X

IN IN

FSB_HIT_L

IO

=PP1V05_S0_CPU 5 6 7 8 9 11

IO

AC2

11

XDP_BPM_L<4>

AC1

11

XDP_BPM_L<5>

AC5

11 7 5

XDP_TCK

IN

AA6

11 7 5

XDP_TDI

IN

AB3

TMS

AB5

TRST*

AB6

DBR*

C20

11 5

26 11

NOTE: DUMMY

J0700

12 5 12 12

NO SPACE FOR ITP

IN

12

1

OUT

XDP_TRST_L

XDP_DBRESET_L

OMIT

1% 1/16W MF-LF 402

IO

IN

PIN

2

IO

XDP_TMS

11 7 5 11 5

XDP_TDO

2 402

IO

R0703 54.9

1% 1/16W MF-LF

IO

TDI

1

54.9

IO

TCK TDO

R0701

IO

PREQ*

PRDY*

D

IN

FSB_TRDY_L

FSB_HITM_L

FSB_IERR# WITH A GND 0.1" AWAY

1

R0704

CONNECTOR, NEED TERM

68

ON ITP SIGNALS?

2

12 12

5% 1/16W MF-LF 402

12 12

OUT

12

PIN ACTUALLY DRIVEN BY ITP

A29* A30*

IO

CPU_INIT_L

12

FSB_A_L<17>

2

1% 1/16W MF-LF 402

IO

21 5

12 11 5

SYMBOL NEED TO CHECK

54.9

IO

B3

G2

IO

R0702

IO

INIT*

TRDY*

IO

1

IO

FSB_IERR_L

IO

A25*

IN

FSB_DBSY_L

FSB_BREQ0_L

FSB_RS_L<2>

T5

IN

12 5

12 5

CPU SCH AND PCB

IO

D20

FSB_RS_L<1>

FSB_A_L<25>

IN

F1

5 6 7 8 9 11

IO

IERR*

FSB_RS_L<0>

IO

IN

E1

BR0*

FSB_DRDY_L

12

A24*

OUT

DBSY*

12

12

A23*

IN

F21

FSB_DEFER_L

12

A22*

IO

DRDY*

12

G3

R4

IO

H5

FSB_BPRI_L

F4

U2

IO

FSB_BNR_L

12

RS2*

ADSTB0*

Y5

IO

FSB_ADS_L

12 5

G5

REQ0* REQ1*

FSB_ADSTB_L<0>L2

FSB_A_L<24>

IO

12

E2

DEFER*

 L  O  R  T  N  O  C

 R  D  D  A

H1

BNR*

K3 H2

IO

FSB_A_L<23>

IO

 0  P  U  O  R  G

ADS* BPRI*

FSB_REQ_L<0> FSB_REQ_L<1>

IO

IO

IO

(1 OF 4)

A8*

J1

FSB_A_L<10>

IO

BGA

A7*

IO

IO

=PP1V05_S0_CPU

YONAH-SKT CPU

PROCHOT*

 M THERMDA  R  E THERMDC  H  TTHERMTRIP*

D21

59

A24

10

CPU_THERMD_P

A25

10

CPU_THERMD_N

C7

59 21 14

CPU_PROCHOT_L TO SMC

CPU_PROCHOT_L

IN

OUT

12

AND CPU VR TO INFORM

12

CPU IS HOT

12

OUT

PM_THRMTRIP_L

12

OUT

12 12

PM_THRMTRIP#

 K  L  C  H

BCLK0

A22

34 5

FSB_CLK_CPU_P

BCLK1

A21

34 5

FSB_CLK_CPU_N

12

SHOULD CONNECT TO 12 5

IN ICH6-M AND GMCH IN

12 5

WITHOUT T-ING (NO

12 5

STUB)

AA4 RSVD2

TP_CPU_A34_L

AB2 RSVD3

TP_CPU_A35_L

AA3 RSVD4

TP_CPU_A36_L

M4

RSVD5

TP_CPU_A37_L

N5

RSVD6

TP_CPU_A38_L

T2

RSVD7

TP_CPU_A39_L

V3

RSVD8

TP_CPU_APM0_L

B2

RSVD9

TP_CPU_APM1_L

C3

RSVD10

TP_CPU_HFPLL

B25 RSVD11

T22

D3

TP_CPU_SPARE2

C1

TP_CPU_SPARE3

SPARE[7-0],HFPLL: 12

ROUTE TO TP VIA AND

12

PLACE GND VIA W/IN 1000 MILS

RSVD17

AF1

TP_CPU_SPARE4

RSVD18

D22

TP_CPU_SPARE5

12

RSVD19

C23

TP_CPU_SPARE6

12

RSVD20

C24

TP_CPU_SPARE7

12

12

12

=PP1V05_S0_CPU

12

11 7 5

XDP_TMS

1

2

5

2

11 7 5

XDP_TDI

1

54.9

12

FSB_D_L<37>

IO

IO

FSB_D_L<6>

E25 D6*

D38*

U25

12

FSB_D_L<38>

IO

FSB_D_L<7>

E23 D7*

D39*

U22

12

FSB_D_L<39>

IO

FSB_D_L<8>

K24 D8*

D40*

AB25

12

FSB_D_L<40>

IO

IO

FSB_D_L<9>

G24 D9*

D41*

W22

12 5

FSB_D_L<41>

IO

FSB_D_L<10>

J24 D10*

D42*

Y23

12

FSB_D_L<42>

FSB_D_L<11>

J23 D11*

D43*

AA26

12

FSB_D_L<43>

FSB_D_L<12>

H26 D12*

D44*

Y26

12

FSB_D_L<44>

FSB_D_L<13>

F26 D13*

D45*

Y22

12

FSB_D_L<45>

IO

FSB_D_L<14>

K22 D14*

D46*

AC26

12

FSB_D_L<46>

IO

IO

FSB_D_L<15>

H25 D15*

D47*

AA24

12

FSB_D_L<47>

IO

IO

IO IO IO IO

1

54.9

 A  T  A  D

IO IO IO

34

OUT OUT

IO

IO

IO IO

IO IO

FSB_DINV_L<2>

IO IO

12

FSB_D_L<48>

FSB_D_L<17>

K25 D17*

D49*

AC23

12

FSB_D_L<49>

FSB_D_L<18>

P26 D18*

D50*

AB22

12

FSB_D_L<50>

IO

FSB_D_L<19>

R23 D19*

D51*

AA21

12

FSB_D_L<51>

IO

IO

FSB_D_L<20>

L25 D20*

D52*

AB21

12

FSB_D_L<52>

IO

FSB_D_L<21>

L22 D21*

D53*

AC25

12

FSB_D_L<53>

FSB_D_L<22>

L23 D22*

D54*

AD20

12

FSB_D_L<54>

FSB_D_L<23>

M23 D23*

D55*

AE22

12

FSB_D_L<55>

FSB_D_L<24>

P25 D24*

D56*

AF23

12

FSB_D_L<56>

FSB_D_L<25>

P22 D25*

D57*

AD24

12

FSB_D_L<57>

FSB_D_L<26>

P23 D26*

D58*

AE21

12

FSB_D_L<58>

FSB_D_L<27>

T24 D27*

D59*

AD21

12 5

FSB_D_L<59>

FSB_D_L<28>

R24 D28*

D60*

AE25

12

FSB_D_L<60>

FSB_D_L<29>

L26 D29*

D61*

AF25

12

FSB_D_L<61>

FSB_D_L<30>

T25 D30*

D62*

AF22

12

FSB_D_L<62>

FSB_D_L<31>

N24 D31*

12

FSB_D_L<63>

IO IO

IO IO IO IO IO IO IO IO IO IO

 1  P  R  G

 3  P  R  G

 A  T  A  D

 A  T  A  D

D63*

AF26

FSB_DSTBN_L<1>

M24 DSTBN1*

DSTBN3*

AD23

12 5

FSB_DSTBN_L<3>

FSB_DSTBP_L<1>

N25 DSTBP1*

DSTBP3*

AE24

12 5

FSB_DSTBP_L<3>

FSB_DINV_L<1>

M26 DINV1*

DINV3*

AC20

IO

CPU_GTLREF

AD26 GTLREF NC

MISC

C26 TEST1 D25 TEST2

R26

CPU_COMP<0>

COMP1

U26

CPU_COMP<1>

COMP2

U1

COMP3

V1

DPRSTP*

E5

DPSLP*

B5

B22 BSEL0

CPU_BSEL<1>

B23 BSEL1

DPWR*

C21 BSEL2

PWRGOOD

D6

SLP*

D7

PSI*

AE6

NOSTUFF

R0730 1

2

0

D24

IO IO

IO

LAYOUT NOTE:

IO

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE

IO

TRACE LENGTH SHORTER THAN 0.5".

IO

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

IO

TRACE LENGTH SHORTER THAN 0.5".

IO IO IO IO IO IO

R0716

1

R0717

1

R0718

1

R0719

1

2

IO

27.4

402

IO

FSB_DINV_L<3>

COMP0

CPU_BSEL<0> CPU_BSEL<2>

12 5

C

IO

AC22

CPU_TEST2 OUT

12 5

IO

D48*

R0722 XDP_TCK

 A  T  A  D

 2  P  R  G

IO

N22 D16*

1% 1/16W MF-LF 402

11 7 5

 0  P  R  G

IO

FSB_D_L<16>

IO

CPU_TEST1

1% 1/16W MF-LF 402

34

2

U23

LAYOUT NOTE: 0.5" MAX LENGTH

34

R0721

D37*

A2

R0706 2.0K

1% 1/16W MF-LF 402

G25 D5*

V23

RSVD15

2

FSB_D_L<5>

DINV2*

12

1

IO

J26 DINV0*

12

54.9

FSB_D_L<36>

IO

TP_CPU_SPARE1

R0720

12

FSB_DSTBP_L<2>

F6

12 5

W25

FSB_DSTBN_L<2>

RSVD14

5 6 7 8 9 11

D36*

12 5

1

B

F23 D4*

12 5

12

12 5

IO

FSB_D_L<4>

IO

Y25

TP_CPU_SPARE0

1% 1/16W MF-LF 402

IO

FSB_D_L<35>

W24

D2

12 5

FSB_D_L<34>

12

DSTBP2*

RSVD13

1K

12

V26

DSTBN2*

12

R0705

FSB_D_L<33>

V24

D35*

G22 DSTBP0*

TP_CPU_EXTBREF

11 9 8 7 6 5

12

D34*

H22 D3*

H23 DSTBN0*

12

=PP1V05_S0_CPU

FSB_D_L<32>

AB24

E26 D2*

FSB_D_L<3>

IO

FSB_DINV_L<0>

12

RSVD16

12

F24 D1*

FSB_D_L<2>

IO

FSB_DSTBP_L<0>

12

RSVD12

AA23

D33*

E22 D0*

FSB_D_L<1>

IO

FSB_DSTBN_L<0>

12 5

 D  E  V  R  E  S  E  R

D32*

BGA

(2 OF 4)

FSB_D_L<0>

IO

IO

IO

AA1 RSVD1

TP_CPU_A33_L

YONAH-SKT CPU

IO

1%

2

54.9

2

27.4

B

402

CPU_COMP<2> CPU_COMP<3> 75 21

CPU_DPRSTP_L

21

CPU_DPSLP_L

12 5

FSB_DPWR_L

21 12

CPU_PWRGD

FSB_SLPCPU_L 75

CPU_PSI_L

2 1%

54.9

402

IN IN IN IN IN IN

2

402

1

1% 1/16W MF-LF 402

R0707 51

2

5% 1/16W MF-LF 402

1NOSTUFF

R0712 1K 5% 1/16W MF-LF

2 402

CPU 1 OF 2-FSB

A

SYNC_MASTER=MASTER

SYNC_DATE=05/03/2005

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF 7

1

110

A

 

8

6

7

3

4

5

2

1

OMIT A4 VSS_1 A8 VSS_2

6 8 9

=PPVCORE_S0_CPU OMIT

A14 VSS_4 6 8 9

A16 VSS_5 A19 VSS_6

A7 VCC_1 VCC_68 AB20 A9 VCC_2 VCC_69 AB7 YONAH-SKT A10 VCC_3 VCC_70 AC7 CPU A12 VCC_4 VCC_71 AC9 BGA A13 VCC_5 VCC_72 AC12 (3 OF 4) A15 VCC_6 VCC_73 AC13

J0700

D

A17 VCC_7 A18 VCC_8

VCC_74 AC15 VCC_75 AC17

A20 VCC_9 B7 VCC_10

VCC_76 AC18 VCC_77 AD7

B9 VCC_11

VCC_79 AD10 VCC_80 AD12 VCC_81 AD14

B15 VCC_15 B17 VCC_16

VCC_82 AD15 VCC_83 AD17

B18 VCC_17 B20 VCC_18

VCC_84 AD18 VCC_85 AE9

C9 VCC_19 C10 VCC_20 C12 VCC_21

VCC_86 AE10 VCC_87 AE12

C17 VCC_24 C18 VCC_25 D9 VCC_26 D10 VCC_27 D12 VCC_28 D14 VCC_29

C

D15 VCC_30 D17 VCC_31 D18 VCC_32 E7 VCC_33 E9 VCC_34 E10 VCC_35 E12 VCC_36 E13 VCC_37 E15 VCC_38 E17 VCC_39 E18 VCC_40 E20 VCC_41 F7 VCC_42 F9 VCC_43 F10 VCC_44 F12 VCC_45 F14 VCC_46 F15 VCC_47 F17 VCC_48 F18 VCC_49 F20 VCC_50 AA7 VCC_51 AA9 VCC_52 AA10 VCC_53 AA12 VCC_54 AA13 VCC_55 AA15 VCC_56 AA17 VCC_57

B

AA18 VCC_58 AA20 VCC_59 AB9 VCC_60 AC10 VCC_61 AB10 VCC_62 AB12 VCC_63 AB14 VCC_64 AB15 VCC_65 AB17 VCC_66 AB18 VCC_67

YONAH-SKT

CPU BGA (4 OF 4)

P6

VSS_83 P21 VSS_84 P24 VSS_85 R2 VSS_86 R5 VSS_87 R22

A23 VSS_7

VSS_88 R25

A26 VSS_8

VSS_89 T1

B6 VSS_9

VSS_90 T4

B8 VSS_10

VSS_91 T23

B11 VSS_11

VSS_92 T26

B13 VSS_12

VSS_93 U3

B16 VSS_13

VSS_94 U6

B19 VSS_14

VSS_95 U21

B21 VSS_15

VSS_96 U24

B24 VSS_16

VCC_78 AD9

B10 VCC_12 B12 VCC_13 B14 VCC_14

C13 VCC_22 C15 VCC_23

J0700 VSS_82

A11 VSS_3

=PPVCORE_S0_CPU

C5 VSS_17

VSS_97 V2 VSS_98 V5

C8 VSS_18

VSS_99 V22

C11 VSS_19

VSS_100 V25

C14 VSS_20

VSS_101 W1

C16 VSS_21

VSS_102 W4

C19 VSS_22

VSS_103 W23

C2 VSS_23

VSS_104 W26

C22 VSS_24

VSS_105 Y3

C25 VSS_25

VSS_106 Y6

D1 VSS_26

VSS_107 Y21

D4 VSS_27

VSS_108 Y24

VCC_90 AE17 VCC_91 AE18

D8 VSS_28

VSS_109 AA2

D11 VSS_29

VSS_110 AA5

VCC_92 AE20 VCC_93 AF9

D13 VSS_30

VSS_111 AA8

D16 VSS_31

VSS_112 AA11

D19 VSS_32

VSS_113 AA14

D23 VSS_33

VSS_114 AA16

D26 VSS_34

VSS_115 AA19

E3 VSS_35

VSS_116 AA22

E6 VSS_36

VSS_117 AA25

VCC_88 AE13 VCC_89 AE15

VCC_94 AF10 VCC_95 AF12 VCC_96 AF14 VCC_97 AF15 VCC_98 AF17 VCC_99 AF18 VCC_100 AF20 VCCP_1 V6 VCCP_2 G21

=PP1V05_S0_CPU 5

6 7 9 11

VCCP_3 J6 VCCP_4 K6 VCCP_5 M6 VCCP_6 J21 VCCP_7 K21 VCCP_8 M21

=PP1V5_S0_CPU 6

8

VCCP_9 N21 VCCP_10 N6 VCCP_11 R21 VCCP_12 R6

C0800

1

1

10UF

0.01UF

VCCP_13 T21 VCCP_14 T6 VCCP_15 V21 VCCP_16 W21

=PP1V5_S0_CPU 6

20% 16V CERM 402

8

C0801

2

2

20% 6.3V X5R 603

VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE2

75

CPU_VID<0>

75

CPU_VID<1>

75

CPU_VID<2>

75

CPU_VID<3>

75

CPU_VID<4>

75

CPU_VID<5>

75

CPU_VID<6>

OUT

2

VSS_126 AB26

F11 VSS_46

VSS_127 AC3

F13 VSS_47

VSS_128 AC6

F16 VSS_48

VSS_129 AC8

F19 VSS_49

VSS_130 AC11

F2 VSS_50

VSS_131 AC14

F22 VSS_51

VSS_132 AC16

F25 VSS_52

VSS_133 AC19

G4 VSS_53

VSS_134 AC21

G1 VSS_54

VSS_135 AC24

VSS_139 AD11 VSS_140 AD13 VSS_141 AD16

J2 VSS_61

VSS_142 AD19

J5 VSS_62

VSS_143 AD22

J22 VSS_63

VSS_144 AD25

J25 VSS_64

VSS_145 AE1

R0802

K1 VSS_65

VSS_146 AE4

100

K4 VSS_66

VSS_147 AE8

6 8 9

1% 1/16W MF-LF 402

VSSSENSE AE7

75

CPU_VCCSENSE_P CPU_VCCSENSE_N

OUT

R0803

K23 VSS_67

VSS_148 AE11

K26 VSS_68

VSS_149 AE14

L3 VSS_69

VSS_150 AE16

L6 VSS_70

VSS_151 AE19

TO CONNECT A DIFFERENCTIAL PROBE

L21 VSS_71

VSS_152 AE23

BETWEEN VCCSENSE AND VSSSENSE AT THE

L24 VSS_72

VSS_153 AE26

PROVIDE A TEST POINT (WITH NO STUB) OUT

LOCATION WHERE THE TWO 54.9 OHM

M2 VSS_73

VSS_154 AF3

RESISTORS TERMINATE THE 55 OHM

M5 VSS_74

VSS_155 AF6

M22 VSS_75

VSS_156 AF8

M25 VSS_76

VSS_157 AF11

N1 VSS_77

VSS_158 AF13

N4 VSS_78

VSS_159 AF16

N23 VSS_79

VSS_160 AF19

N26 VSS_80

VSS_161 AF21

P3 VSS_81

VSS_162 AF24

TRANSMISSION LINE

100

2

VSS_124 AB19 VSS_125 AB23

F8 VSS_45

VSS_138 AD8

LAYOUT NOTE:

TO VCCSENSE_P/N WITH NO STUB

VSS_123 AB16

E24 VSS_43 F5 VSS_44

H24 VSS_60

75

LAYOUT NOTE: CONNECT R0802-03

VSS_122 AB13

E21 VSS_42

VSS_137 AD5

VCCSENSE AF7

1

E19 VSS_41

H21 VSS_59

OUT

OUT

VSS_121 AB11

VSS_136 AD2

=PPVCORE_S0_CPU

1

VSS_120 AB8

H6 VSS_58

OUT

OUT

VSS_119 AB4

E16 VSS_40

H3 VSS_57

OUT

OUT

VSS_118 AB1

E14 VSS_39

G26 VSS_56

VCCA B26

VID0 AD6 VID1 AF5

E8 VSS_37 E11 VSS_38

G23 VSS_55

VCCA=1.5 ONLY

1% 1/16W MF-LF 402

D

C

B

CPU 2 OF 2-PWR/GND

A

SYNC_MASTER=MASTER

SYNC_DATE=05/03/2005

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF 8

1

110

A

 

8

6

7

2

3

4

5

1

CPU HEATSINK MOUNTING HOLES D

D

C950

1

11 9 8 7 6 5

66

C951

C PU _H S_ ZH 60 8

2

20% 16V CERM 402

C PU _H S_ ZH 60 9

1

1

C952

1

20% 16V CERM 402

2

CPU_HS_ZH610

1

C953

1

1

0.01UF

0.01UF

0.01UF

0.01UF 20% 16V CERM 402

1

4P75R4

4P75R4

4P75R4

4P75R4

ZH610

ZH609

ZH608

ZH607 CPU_HS_ZH607

OMIT

OMIT

OMIT

OMIT

2

20% 16V CERM 402

2

=PP1V05_S0_CPU

CRITICAL 1

OMIT

C940

ZH611

330UF

20% 2 6.3V ELEC CASE-C1

6P5R3P2 1

C

C

VCCP CORE DECOUPLING 11 9 8 7 6 5

=PP1V05_S0_CPU

C926

PLACE INSIDE SOCKET CAVITY

1

ON L8 (NORTH SIDE SECONDARY)

20% 10V 2 CERM 402

0.1UF

C934

1

0.1UF

20% 10V 2 CERM 402

1

C935 0.1UF

20% 10V 2 CERM 402

B 8 6

CAVITY ON L8 (NORTH SIDE

1

C923 22UF

1

C924

1

SECONDARY)

20% 6.3V 2 X5R 805

PLACE 8 INSIDE SOCKET

1

CAVITY ON L8 (SOUTH SIDE

22UF

SECONDARY)

20% 6.3V 2 X5R 805

PLACE 6 INSIDE SOCKET

1

C911 22UF

1

C918

1

20% 6.3V 2 X5R 805

C925 22UF

PRIMARY)

20% 6.3V 2 X5R 805

PLACE 6 INSIDE SOCKET

1

22UF

20% 6.3V 2 X5R 805

A

PRIMARY)

C922 22UF

20% 6.3V 2 X5R 805

1

C913

1

22UF

20% 6.3V 2 X5R 805

1

C937 0.1UF

20% 10V 2 CERM 402

1

C938 0.1UF

20% 10V 2 CERM 402

C908 22UF

1

C912

1

C901 22UF

1

C904

1

C919 22UF

20% 6.3V 2 X5R 805

1

1

C921 22UF

20% 6.3V 2 X5R 805

C916 22UF

20% 6.3V 2 X5R 805

C917 22UF

20% 6.3V 2 X5R 805

C930

1

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

B

C900 22UF

1

C902

1

20% 6.3V 2 X5R 805

22UF

20% 6.3V 2 X5R 805

1

C909 22UF

C931 22UF

20% 6.3V 2 X5R 805

C907 22UF

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

1

C939 22UF

20% 6.3V 2 X5R 805

1

C929 22UF

20% 6.3V 2 X5R 805

1

C920 22UF

20% 6.3V 2 X5R 805

NOSTUFF

C914

1

1

1

20% 6.3V 2 X5R 805

NOSTUFF

C915

1

NOSTUFF

C906

1

22UF

22UF

C903

CPU DECAPS & VID<>

22UF

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

C905 22UF

20% 6.3V 2 X5R 805

NOSTUFF 1

C932 22UF

22UF

20% 6.3V 2 X5R 805

NOSTUFF 1

1

22UF

22UF

22UF

20% 6.3V 2 X5R 805

C928 22UF

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

NOSTUFF 1

NOSTUFF CAVITY ON L1 (SOUTH SIDE

0.1UF

C910 22UF

20% 6.3V 2 X5R 805

NOSTUFF CAVITY ON L1 (NORTH SIDE

C936

20% 10V 2 CERM 402

VCC CORE DECOUPLING

=PPVCORE_S0_CPU

PLACE 8 INSIDE SOCKET

1

20% 6.3V 2 X5R 805

A

NOTICE OF PROPRIETARY PROPERTY CRITICAL 1

C941

CRITICAL 1

470UF

SOUTH SIDE SECONDARY

3 2

20% 2.5V TANT D2T

C942

470UF

3 2

20% 2.5V TANT D2T

C943

1

20% 2.5V TANT D2T

1

C944

3 2

20% 2.5V TANT D2T

1

C945

3

20% 2 2.5V TANT D2T

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

C946 470UF

470UF

470UF

470UF

3 2

CRITICAL

CRITICAL

CRITICAL

CRITICAL 1

3

20% 2 2.5V TANT D2T

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

9

1

OF

13 110

 

8

6

7

2

3

4

5

1

NOTE: IF CPU T DIODE TO BE READ IN OFF STATE,

CPU THERMAL SENSOR

THEN THIS SHOULD BE S5

PP3V3_S0

D

1

6 11 26 41 59 61 76 88

D

C1001 0.1UF

2 LAYOUT NOTE:

10% 16V X5R 402

1

1

10K

ADD GND GUARD TRACES FOR CPU_THERMD_P/N ROUTE ON SAME LAYER WITH 0.254MM TRACE WIDTH &

R1000

SPACING.

2

5% 1/16W MF-LF 402

R1001 10K

2

5% 1/16W MF-LF 402

NOSTUFF

1

VDD ALERT*/ CRITICAL THM2*

CPU_TSENS_INT

R1002 OUT

7

CPU_THERMD_P

1

499

2

NOSTUFF

1% 1/16W MF-LF 402

1

R1017 IN

7

CPU_THERMD_N

1

THERM_DX_P

2

D+

10

THERM_DX_N

3

D-

2

C1000

MSOP

20% 50V CERM 402

THM*

R1005 6

THRM_ALERT_L  

4

1

SCLK

8

SDATA

7

0

2

58 23

5% 1/16W MF-LF 402

THRM_THM

ADT7461

0.001UF

CPU_TSENS_INT 499

10

U1000

59 59

PM_THRM_L

=SMB_THRM_CLK

=SMB_THRM_DATA

IO

IO IO

GND 5

2

1% 1/16W MF-LF 402

NOTE: SYMBOL SHOULD BE SHOWN ADT7461A

C

C

LAYOUT NOTE: PLACE R1002 AND R1018 SUCH THAT THEY

SHARE ONE PAD

PLACE R1017 AND R1019 SUCH THAT THEY

SHARE ONE PAD

CPU_TSENS_EXT

CPU_TSENS_EXT

CRITICAL

R1018

J1000

1

SM-2MT-BLK-LF 3

1

CPU_THERMD_EXT_P

2

CPU_THERMD_EXT_N

0

2

5% 1/16W MF-LF 402

THERM_DX_P 10 THERM_DX_N 10

CPU_TSENS_EXT 4

R1019 1

TEMPORARILY REMOVED BOMOPTION=CPU_TSENS_EXT

0

2

5% 1/16W MF-LF 402

B

B

CPU TEMP SENSOR

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF 10

1

110

 

8

6

7

2

3

4

5

1

C1150 0.1UF

80 79 77 76 66 65 59 26 6 5 83 81

PP3V3_S5

1

PP12V_S5

2

5 6 11 77 78 79 80 81 83 88

10% 16V X5R 402

D

D

C1151 0.1UF 1

2 10% 16V X5R 402

C1152 0.1UF 1

2 10% 16V X5R 402

C1153 0.1UF

88 77 11 6

PP2V5_S0

1

PP12V_S5

2

5 6 11 77 78 79 80 81 83 88

10% 16V X5R 402

CPU ITP700FLEX DEBUG SUPPORT

C1154 0.1UF 1

2 10% 16V X5R 402

C

C

C1155 0.1UF 1

2 10% 16V X5R 402

DEVELOPMENT 11 9 8 7 6 5

=PP1V05_S0_CPU

J1101

52435-2872

1

R1101 1R1103 54.9

1% 1/16W MF-LF 2 402

C1156 0.1UF

88 76 61 59 41 26 10 6

PP3V3_S0

1

PP1V5_S0

2

F-RT-SM 29

54.9

1% 1/16W MF-LF 2 402

OUT OUT

6 11 80

OUT

10% 16V X5R 402

OUT

R1102 7 5

IN

XDP_TDO

1

0.1UF

34

(FROM CK410M HOST 133/167MHZ)

IN

FSB_CPURST_L

1

C1158

23 6

0.1UF

PP2V5_S0

1

PP1V5_S0

2

2 3

(TCK)

34

IN IN

XDP_BPM_L<5>

6

11 7

22.6 2

OUT

5

XDP_TCK

1

8

(FBO)

IO

C1199 56PF

5% 50V 2 CERM 402

9

11

ITPRESET_L XDP_BPM_L<5>

7 11

NOSTUFF

7

12 13 14

IO

7

XDP_BPM_L<4>

IO

7

XDP_BPM_L<3>

7

XDP_BPM_L<2>

15 16

B

17 18

6 11 80

1

R1104

IO

240

19 20

5% 1/16W MF-LF

IO

7

XDP_BPM_L<1>

7

XDP_BPM_L<0>

21 22

2 402

C1159

IO

0.1UF

23

NC

2

NOTE: PLACE C1199 AT J1101 PINS 13 AND 14

4 5

ITP_TDO CPU_XDP_CLK_N CPU_XDP_CLK_P

=PP3V3_S5_SB_PM

10% 16V X5R 402

1

XDP_TCK

1

NC

10

R1100 12 7 5

5

XDP_TDI XDP_TMS XDP_TRST_L NC

1% 1/16W MF-LF 402

88 77 11 6

7 5

22.6 2 1% 1/16W MF-LF 402

2 10% 16V X5R 402

B

7 5

11 7

C1157 1

7 5

(AND WITH RESET BUTTON)

OUT

26 7

XDP_DBRESET_L

10% 16V X5R 402

24 25

11 9 8 7 6 5

=PP1V05_S0_CPU

26

(DBA#) INDICATE THAT ITP IS USING TAP I/F, (DEBUG PORT ACTIVE)

NC IN 945GM CHIPSET SYSTEM.

(DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC (DEBUG PORT RESET)

27

1

C1100

28

0.1UF

10% 16V 2 X5R 402

C1160

30

518S0320

0.1UF

88 83 81 80 79 78 77 11 6 5

PP12V_S5

1

PP1V5_S0

2

1

R1106

6 11 80

10% 16V X5R 402

ITP TCK SIGNAL LAYOUT NOTE: ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX CONNECTOR’S FBO PIN.

680

5% 1/16W MF-LF

2 402

CPU ITP700FLEX DEBUG SYNC_DATE=5/23/05

SYNC_MASTER=MASTER

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051- 7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

11

1

110

A

 

8

6

7

7 5

D

7 7 7 7 7 7 7

7 7 7 7 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 7 7 7 7 7 7 7 7 7 7

R1220

1

1

54.9 1% 1/16W MF-LF 402

B

2

2

R1225

7

221

7

1% 1/16W MF-LF 402

HD0*

J1

HD1*

FSB_D_L<2>

H1

HD2*

FSB_D_L<3>

J6

HD3*

IO

FSB_D_L<4>

H3

HD4*

7 7 7 7 7

1

1% 1/16W MF-LF 402

19 12 6 5

7

R1226

1

100

2

2

1% 1/16W MF-LF 402

C1226

7

0.1uF 2

7

10% 16V X5R 402

7

1

34 5

221

54.9 1% 1/16W MF-LF 402

34 5

R1235

2

2

IO

FSB_A_L<5> FSB_A_L<6>

IO

7

FSB_A_L<7>

IO

G12

G11

HA7*

F11

HA8*

K2

HD5*

7

FSB_A_L<8>

G1

HD6*

945GM

F9

7

FSB_A_L<9>

FSB_D_L<7>

G2

HD7*

NB

HA10*

H11

7

FSB_A_L<10>

K9

BGA

HA11* HA12*

7

K1

HD8* HD9*

J12

IO

FSB_D_L<8> FSB_D_L<9>

G14

7

FSB_A_L<11> FSB_A_L<12>

IO

FSB_D_L<10>

K7

HD10*

HA13*

D9

7

FSB_A_L<13>

J8

(1 OF 10)

HA9*

IO IO IO

IO IO

HD11*

HA14*

J14

7

FSB_A_L<14>

FSB_D_L<12>

H4

HD12*

HA15*

H13

7

FSB_A_L<15>

IO

FSB_D_L<13>

J3

HD13*

HA16*

J15

7

FSB_A_L<16>

IO

FSB_D_L<14>

K11

HD14*

HA17*

F14

7

FSB_A_L<17>

FSB_D_L<15>

G4

HD15*

HA18*

D12

7

FSB_A_L<18> FSB_A_L<19>

IO IO

IO

IO IO

FSB_D_L<16>

T10

HD16*

HA19*

A11

7

FSB_D_L<17>

W11

HD17*

HA20*

C11

7

FSB_A_L<20>

FSB_D_L<18>

T3

HD18*

HA21*

A12

7

FSB_A_L<21>

IO

FSB_D_L<19>

U7

HD19*

HA22*

A13

7

FSB_A_L<22>

IO

IO

FSB_D_L<20>

U9

HD20*

HA23*

E13

7

FSB_A_L<23>

IO

FSB_D_L<21>

U11

HD21*

HA24*

G13

7

FSB_A_L<24>

IO

FSB_D_L<22>

T11

HD22*

HA25*

F12

7

FSB_A_L<25>

IO

IO

FSB_D_L<23>

W9

HD23*

HA26*

B12

7

FSB_A_L<26>

IO

FSB_D_L<24>

T1

HD24*

HA27*

B14

7 5

FSB_A_L<27>

IO

FSB_D_L<25>

T8

HD25*

HA28*

C12

7

FSB_A_L<28>

IO

IO

FSB_D_L<26>

T4

HD26*

HA29*

A14

7

FSB_A_L<29>

IO

FSB_D_L<27>

W7

HD27*

HA30*

C14

7

FSB_A_L<30>

FSB_D_L<28>

U5

HD28*

HA31*

D14

7

FSB_A_L<31>

FSB_D_L<29>

T9

HD29*

FSB_D_L<30>

W6

HD30*

IO

FSB_D_L<31>

T5

HD31*

IO

FSB_D_L<32>

IO IO IO

IO

IO

IO IO IO IO

AB7

HD32*

FSB_D_L<33>

AA9

HD33*

IO

FSB_D_L<34>

W4

HD34*

IO

FSB_D_L<35>

IO

IO IO IO IO IO IO IO IO IO IO

W3

HD35*

FSB_D_L<36>

Y3

HD36*

FSB_D_L<37>

Y7

HD37*

FSB_D_L<38>

W5

HD38*

FSB_D_L<39>

Y10

FSB_D_L<40>

AB8

HD39* HD40*

FSB_D_L<41>

W2

HD41*

FSB_D_L<42>

AA4

HD42*

FSB_D_L<43>

AA7

HD43*

FSB_D_L<44>

AA2

HD44*

FSB_D_L<45>

AA6

HD45*

FSB_D_L<46>

FSB_BPRI_L

1

HBREQ0*

C7

7 5

FSB_BREQ0_L

B7

HDBSY*

A7

7 5

FSB_DBSY_L

HDEFER*

C3

7

FSB_DEFER_L

HDPWR*

J9

7 5

OUT

FSB_DPWR_L

IO

7

FSB_DRDY_L

HDRDY*

H8

HDVREF

K13

HDINV0*

FSB_CPURST_L

J7

7 5

FSB_DINV_L<0>

IO OUT IO

HD51*

HDSTBN2* HDSTBN3*

AC4

7 5

FSB_DSTBN_L<3>

HDSTBP0*

K3

7 5

FSB_DSTBP_L<0>

HDSTBP1*

T6

7 5

FSB_DSTBP_L<1>

IO

HDSTBP2*

AA5

7 5

FSB_DSTBP_L<2>

IO

HDTSBP3*

AC5

7 5

FSB_DSTBP_L<3>

IO

FSB_D_L<55>

IO

FSB_D_L<56>

HD55* HD56*

AC1

HD57*

AD7

HD58*

FSB_D_L<59> FSB_D_L<60>

AC6 AB5

HD59* HD60*

FSB_D_L<61>

AD10

HD61*

FSB_D_L<62>

AD4

HD62*

FSB_D_L<63>

AC8

HD63*

NB_FSB_XRCOMP

E1

HXRCOMP

NB_FSB_XSCOMP

E2

HXSCOMP

NB_FSB_XSWING

E4

HXSWING

NB_FSB_YRCOMP

Y1

HYRCOMP

NB_FSB_YSCOMP

U1

HYSCOMP

W1

HYSWING

FSB_CLK_NB_P

AG2

HCLKIN

FSB_CLK_NB_N

AG1

HCLKIN*

HHIT*

D3

7 5

FSB_HIT_L

HHITM*

D4

7 5

FSB_HITM_L

HLOCK*

B3

7 5

FSB_LOCK_L

HREQ0*

D8

7 5

FSB_REQ_L<0>

HREQ1*

G8

7 5

FSB_REQ_L<1>

HREQ2*

B8

7 5

FSB_REQ_L<2>

HREQ3*

F8

7 5

FSB_REQ_L<3>

HREQ4*

A8

7 5

FSB_REQ_L<4>

HRS0*

B4

7

FSB_RS_L<0>

HRS1*

E6

7

FSB_RS_L<1>

HRS2*

D6

7

FSB_RS_L<2>

HSLPCPU*

E3

7

FSB_SLPCPU_L

HTRDY*

E7

7

FSB_TRDY_L

10% 16V X5R 402

R1211 200

0.1uF 2 2

1% 1/16W MF-LF 402

IO

FSB_DSTBN_L<2>

HD54*

C1211

1

IO

7 5

HDINV1*

C

1% 1/16W MF-LF 402

IO

HCPURST*

11 7 5

2

IO

OUT

Y5

IO

IN

7

FSB_DSTBN_L<1>

IO

IN

F6

7 5

HD53*

IO

HBPRI*

IO

T7

HD52*

IO

NB_FSB_VREF FSB_BNR_L

HDSTBN1*

AB3

FSB_D_L<58>

5 7 5

HD50*

FSB_D_L<54>

IO

FSB_ADSTB_L<1>

C6

FSB_DSTBN_L<0>

FSB_D_L<53>

IO

FSB_ADSTB_L<0>

7 5

J13

7 5

IO

IO

7 5

C13

HAVREF HBNR*

K4

AC11

FSB_D_L<57>

B9

HADSTB1*

HDSTBN0*

FSB_D_L<52>

IO

HADSTB0*

FSB_DINV_L<3>

AB11

AD9

 S  O  H

IO

FSB_DINV_L<2>

FSB_D_L<51>

AD1

7

FSB_DINV_L<1>

AC9

AC2

 T

FSB_ADS_L

E8

R1210 100

7 5

FSB_D_L<50>

IO

1

HADS*

5 6 12 19

IO

7 5

HD49*

=PP1V05_S0_FSB_NB

IO

7 5

AB4

IO

IO

U3

FSB_D_L<49>

IO

IO

W8

HD48*

IO

IO

AB10

HD47*

AA1

IO

IO

HDINV3*

HD46*

Y8

FSB_D_L<48>

IO

IO

HDINV2*

AA10

FSB_D_L<47>

IO

D

IO

IO

FSB_D_L<11>

1

IO

IO

IO

NB_FSB_YSWING 1

IO

FSB_A_L<4>

7

E11

HA6*

FSB_D_L<6>

=PP1V05_S0_FSB_NB

R1230

FSB_A_L<3>

7

C9

HA5*

FSB_D_L<5>

IO 1

24.9

U1200

7

7 5

H9

HA4*

IO

7 5

R1221

HA3*

OMIT

IO

IO

7

7

=PP1V05_S0_FSB_NB

F1

FSB_D_L<1>

IO

IO

IO

7

19 12 6 5

FSB_D_L<0>

IO

7

7

C

IO

2

3

4

5

IO IO IO IO IO IO IO

B

IO

IO IO IO

IO IO IO IO IO

OUT OUT OUT

OUT OUT

1% 1/16W MF-LF 402

NB CPU Interface

A

S YN C C_ _M MA A ST E ER R =( M MA A ST E ER R)

R1231

1

24.9 1% 1/16W MF-LF 402 2

1

R1236

1

100 1% 1/16W MF-LF 2 402

S YN C C_ _ DA T TE E =( M MA A ST E ER R)

NOTICE OF PROPRIETARY PROPERTY

C1236

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

0.1uF 2

10% 16V X5R

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

12

1

110

A

 

8

6

7

2

3

4

5

=PP1V5_S0_NB_PCIE 1

D

19

Can leave all signals NC if

LVDS is not implemented

Tie VCC_TXLVDS and VCCA_LVDS to GND.

19

If SDVO is used

19

VCCD_LVDS must remain powered with proper decoupling.

19

Otherwise, tie VCCD_LVDS to GND also.

19 19 19

19 19 19

19 19 19 19

19 19 19

19 19 19

19 19 19

19

C

19 19

TV-Out Signal Usage:

19

Composite: DACA only

19

S-Video: DACB & DACC only Component: DACA, DACB & DACC

19 19

Unused DAC outputs must remain powered, but can omit

19

filtering components.

19

Unused DAC outputs should

connect to GND through 75-ohm resistors.

19

LVDS_BKLTCTL

D32

L_BKLTCTL

LVDS_BKLTEN

J30

L_BKLTEN

LVDS_CLKCTLA

H30

L_CLKCTLA

LVDS_CLKCTLB

H29

L_CLKCTLB

IO

LVDS_DDC_CLK

G26

L_DDC_CLK

IO

LVDS_DDC_DATA

G25

L_DDC_DATA

LVDS_IBG

B38

L_IBG

TP_LVDS_VBG

C35

L_VBG

OUT OUT OUT OUT

IO

OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT

LVDS_VDDEN

F32

L_VDDEN

LVDS_VREFH

C33

L_VREFH

LVDS_VREFL

C32

L_VREFL

LVDS_A_CLK_N

A33

LA_CLK*

LVDS_A_CLK_P

A32

LA_CLK

LVDS_B_CLK_N

E27

LB_CLK*

LVDS_B_CLK_P

E26

LB_CLK

LVDS_A_DATA_N<0>

C37

LA_DATA0*

LVDS_A_DATA_N<1>

B35

LA_DATA1*

LVDS_A_DATA_N<2>

A37

LA_DATA2*

LVDS_A_DATA_P<0> LVDS_A_DATA_P<1>

B37 B34

OUT

LVDS_B_DATA_N<0>

G30

LB_DATA0*

LVDS_B_DATA_N<1>

D30

LB_DATA1*

LVDS_B_DATA_N<2>

F29

LB_DATA2*

LVDS_B_DATA_P<0>

F30

LB_DATA0

LVDS_B_DATA_P<1>

D29

LB_DATA1

LVDS_B_DATA_P<2>

F28

LB_DATA2

OUT OUT OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT

A36

D40

BGA

EXP_A_COMPO

D38

EXP_A_RXN0

F34

84

PEG_D2R_N<0>

IN

SDVO_TVCLKIN#

EXP_A_RXN1

G38

84

PEG_D2R_N<1>

IN

SDVO_INT#

EXP_A_RXN2

H34

84

PEG_D2R_N<2>

IN

SDVO_FLDSTALL#

EXP_A_RXN3

J38

84

PEG_D2R_N<3>

EXP_A_RXN4

L34

84

PEG_D2R_N<4>

EXP_A_RXN5 EXP_A_RXN6

M38

84

N34

84

PEG_D2R_N<5> PEG_D2R_N<6>

EXP_A_RXN7

P38

84

PEG_D2R_N<7>

EXP_A_RXN8

R34

84

PEG_D2R_N<8>

EXP_A_RXN9

T38

84

PEG_D2R_N<9>

IN

EXP_A_RXN10

V34

84

PEG_D2R_N<10>

IN

EXP_A_RXN11

W38

84

PEG_D2R_N<11>

EXP_A_RXN12

Y34

84

PEG_D2R_N<12>

EXP_A_RXN13

AA38

84

PEG_D2R_N<13>

EXP_A_RXN14

AB34

84

PEG_D2R_N<14>

EXP_A_RXN15

AC38

84

PEG_D2R_N<15>

EXP_A_RXP0

D34

84

PEG_D2R_P<0>

IN

SDVO_TVCLKIN

EXP_A_RXP1

F38

84

PEG_D2R_P<1>

IN

SDVO_INT

EXP_A_RXP2

G34

84

PEG_D2R_P<2>

IN

SDVO_FLDSTALL

EXP_A_RXP3

H38

84

PEG_D2R_P<3>

EXP_A_RXP4

J34

84

PEG_D2R_P<4>

IN

EXP_A_RXP5

L38

84

PEG_D2R_P<5>

IN

EXP_A_RXP6

M34

84

PEG_D2R_P<6>

EXP_A_RXP7

N38

84

PEG_D2R_P<7>

EXP_A_RXP8

P34

84

PEG_D2R_P<8>

EXP_A_RXP9

R38

84

PEG_D2R_P<9>

EXP_A_RXP10

T34

84

PEG_D2R_P<10>

EXP_A_RXP11

V38

84

PEG_D2R_P<11>

EXP_A_RXP12

W34

84

PEG_D2R_P<12>

EXP_A_RXP13

Y38

84

PEG_D2R_P<13>

EXP_A_RXP14 EXP_A_RXP15

AA34

84

AB38

84

PEG_D2R_P<14> PEG_D2R_P<15>

EXP_A_TXN0

F36

84

PEG_R2D_C_N<0>

EXP_A_TXN1

G40

84

PEG_R2D_C_N<1>

EXP_A_TXN2

H36

84

PEG_R2D_C_N<2>

EXP_A_TXN3

J40

84

PEG_R2D_C_N<3>

EXP_A_TXN4

L36

84

PEG_R2D_C_N<4>

EXP_A_TXN5

M40

84

EXP_A_TXN6

N36

EXP_A_TXN7

(3 OF 10)

 S  D  V  L

LA_DATA2

TV_DACA_OUT

A16

TV_DACA_OUT

TV_DACB_OUT

C18

TV_DACB_OUT

TV_DACC_OUT

A19

TV_DACC_OUT

TV_IREF

J20

TV_IREF

TV_IRTNA

B16

TV_IRTNA

TV_IRTNB

B18

TV_IRTNB

TV_IRTNC

B19

TV_IRTNC

 S  C  I  H  P  A  R  G  V  T

Tie DACx_OUT, IRTNx, and IREF to 1.5V power

rail.

19

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and VCCA_TVBG to 1.5V power rail.

19

Tie VSSA_TVBG to GND.

19 19

CRT Disable 19

19

Tie VCCA_CRTDAC to VCC Core

19

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

19 19 19

OUT OUT

CRT_DDC_CLK

C26

CRT_DDC_DATA

C25

C

IN IN IN IN IN IN IN IN

SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE#

P40

84

PEG_R2D_C_N<7>

OUT

SDVOC_CLKN

EXP_A_TXN8

R36

84

PEG_R2D_C_N<8>

EXP_A_TXN9

T40

84

PEG_R2D_C_N<9>

EXP_A_TXN10

V36

84

PEG_R2D_C_N<10>

CRT_DDC_CLK

OUT

IO

IN

OUT

B22

IO

IN

PEG_R2D_C_N<6>

CRT_GREEN_L

OUT

IN

84

OUT

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie HSYNC and VSYNC to GND.

IN

SDVOB_BLUE#

CRT_GREEN

B21

IN

OUT

C22

CRT_RED_L

IN

PEG_R2D_C_N<5>

CRT_GREEN

OUT

IN

SDVOB_GREEN#

CRT_BLUE*

A21

IN

OUT

D23

OUT

IN

SDVOB_RED#

CRT_BLUE_L

CRT_RED

IN IN

OUT

CRT_BLUE

OUT

IN IN IN

OUT

E23

CRT_GREEN* CRT_RED CRT_RED*

 A  G  V

EXP_A_TXN11

W40

84

PEG_R2D_C_N<11>

CRT_DDC_DATA

EXP_A_TXN12

Y36

84

PEG_R2D_C_N<12>

CRT_HSYNC_R

G23

HSYNC

EXP_A_TXN13

AA40

84

PEG_R2D_C_N<13>

CRT_IREF

J22

CRT_IREF

EXP_A_TXN14

AB36

84

PEG_R2D_C_N<14>

CRT_VSYNC_R

H23

CRT_VSYNC

EXP_A_TXN15

AC40

84

PEG_R2D_C_N<15>

EXP_A_TXP0

D36

84

PEG_R2D_C_P<0>

EXP_A_TXP1

F40

84

PEG_R2D_C_P<1>

EXP_A_TXP2

G36

84

PEG_R2D_C_P<2>

EXP_A_TXP3

H40

84

PEG_R2D_C_P<3>

EXP_A_TXP4

J36

84

PEG_R2D_C_P<4>

EXP_A_TXP5

L40

84

PEG_R2D_C_P<5>

EXP_A_TXP6

M36

84

PEG_R2D_C_P<6>

EXP_A_TXP7

N40

84

PEG_R2D_C_P<7>

EXP_A_TXP8

P36

84

PEG_R2D_C_P<8>

EXP_A_TXP9

R40

84

PEG_R2D_C_P<9>

EXP_A_TXP10

T36

84

PEG_R2D_C_P<10>

EXP_A_TXP11

V40

84

PEG_R2D_C_P<11>

EXP_A_TXP12

W36

84

PEG_R2D_C_P<12>

EXP_A_TXP13

Y40

84

PEG_R2D_C_P<13>

EXP_A_TXP14

AA36

84

PEG_R2D_C_P<14>

EXP_A_TXP15

AB40

84

PEG_R2D_C_P<15>

B

D

SDVO Alternate Function

OUT

CRT_BLUE

OUT

 S  S  E  R  P  X  E   I  C  P

PEG_COMP

OUT

TV-Out Disable 19

1% 1/16W MF-LF 402

EXP_A_COMPI

LA_DATA1

LVDS_A_DATA_P<2>

2

945GM NB

LA_DATA0

OUT

6 19

R1310 24.9

OMIT

U1200 LVDS Disable

1

OUT OUT OUT OUT OUT OUT OUT OUT OUT

SDVOB_RED

OUT

SDVOB_GREEN

OUT

SDVOB_BLUE

OUT

SDVOB_CLKP

OUT

SDVOC_RED

OUT

SDVOC_GREEN

OUT

SDVOC_BLUE

OUT

SDVOC_CLKP

B

OUT OUT OUT OUT OUT OUT OUT OUT

NB PEG / Video Interfaces

A

S YN C C_ _M MA A ST E ER R =( M MA A ST E ER R)

S YN C C_ _ DA T TE E =( M MA A ST E ER R)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

13

1

110

A

 

8

6

7

R1440

1

1

2

2

10K 5% 1/16W MF-LF 402

D

R1441 10K

OMIT

5% 1/16W MF-LF 402

RSVD3

(2 OF 10)

SM_CK2

AW7

F7

RSVD4

SM_CK3

RSVD5

NC

(H_PCREQ#)

NC NC NC

AF11

TP_NB_XOR_FSB2_H7

H7

TP_NB_TESTIN_L

J19

RSVD9

(TV_DCONSEL1)

NB_TV_DCONSEL1

J29

RSVD10

A41

RSVD11

NC

(LA_DATAN3)

TP_NB_XOR_LVDS_A35

A35

RSVD12

(LA_DATAP3)

TP_NB_XOR_LVDS_A34

A34

RSVD13

(LB_DATAN3)

TP_NB_XOR_LVDS_D28

D28

RSVD14

(LB_DATAP3)

TP_NB_XOR_LVDS_D27

D27

RSVD15

NB_BSEL<0>

K16

CFG0

34 IN

NB_BSEL<1>

K18

CFG1

34

NB_BSEL<2>

J18

CFG2

IN

IN IN

NB_CFG<3>

IN

NB_CFG<4>

20 20 20

2

23

100

22 33

MEM_CLK_N<2>

SM_CK3*

AY40

29

MEM_CLK_N<3>

SM_CKE0

AU20

30 28

MEM_CKE<0>

SM_CKE1

AT20

30 28

MEM_CKE<1>

SM_CKE2

BA29

30 29

MEM_CKE<2>

SM_CKE3

AY29

30 29

MEM_CKE<3>

SM_CS0*

AW13

30 28

MEM_CS_L<0>

SM_CS1*

AW12

30 28

MEM_CS_L<1>

SM_CS2*

AY21

30 29

MEM_CS_L<2>

SM_CS3*

AW21

30 29

MEM_CS_L<3>

SMOCDCOMP0

AL20

NC

SMOCDCOMP1

AF10

NC

BA13

30 28

MEM_ODT<0>

SM_ODT1

BA12

30 28

MEM_ODT<1>

IN

NB_CFG<7>

D19

CFG7

IPU

SM_ODT2

AY20

30 29

MEM_ODT<2>

NB_CFG<8>

D16

CFG8

IPU

SM_ODT3

AU21

30 29

MEM_ODT<3>

NB_CFG<9>

G16

CFG9

IPU

NB_CFG<10>

E16

CFG10 IPU

NB_CFG<11>

D15

CFG11 IPU

IN

NB_CFG<12>

G15

CFG12 IPU

IN

NB_CFG<13>

IN

K15

CFG13 IPU

NB_CFG<14>

C15

CFG14 IPU

IN

NB_CFG<15>

H16

CFG15 IPU

IN

NB_CFG<16>

IN IN IN OUT

G18

NB_CFG<17>

H15

CFG17 IPU

NB_CFG<18>

J25

CFG18 IPD

NB_CFG<19>

K27

CFG19 IPD

NB_CFG<20>

J26

CFG20 IPD

PM_BMBUSY_L

G28

PM_BM_BUSY*

F25

PM_EXTTS0*

H26

PM_EXTTS1*

PM_THRMTRIP_L

IN

IO IO OUT OUT

CFG16 IPU

G6

PW_THRMTRIP*

 G  F  C

SMRCOMP*

AT9

SMVREF0

AK1

19 5

SMVREF1

AK41

19 5

MEM_VREF_NB_1

G_CLKIN* G_CLKIN

AF33

34 5

AG33

34 5

NB_CLK100M_GCLKIN_N NB_CLK100M_GCLKIN_P

MEM_VREF_NB_0

D_REFSSCLKIN

 M  P

A27

19

NB_CLK_DREFCLKIN_N

A26

19

NB_CLK_DREFCLKIN_P

C40

19

NB_CLK_DREFSSCLKIN_N

D41

19

NB_CLK_DREFSSCLKIN_P

DMI_RXN0

AE35

22 5

DMI_S2N_N<0>

DMI_RXN1

AF39

22

DMI_S2N_N<1>

DMI_RXN2

AG35

22

DMI_S2N_N<2>

DMI_RXN3

AH39

22

DMI_S2N_N<3> DMI_S2N_P<0>

PWROK

DMI_RXP0

AC35

NB_RST_IN_L_R

AH34

RSTIN*

DMI_RXP1

AE39

22

DMI_S2N_P<1>

DMI_RXP2

AF35

22

DMI_S2N_P<2>

DMI_RXP3

AG39

22

DMI_S2N_P<3>

DMI_TXN0

AE37

22 5

DMI_N2S_N<0>

DMI_TXN1

AF41

22

DMI_N2S_N<1>

DMI_TXN2

AG37

22

DMI_N2S_N<2>

SDVO_CTRLCLK

H27

SDVO_CTRLDATA

NB_SB_SYNC_L

K28

ICH_SYNC*

CLK_NB_OE_L

H32

CLK_REQ*

 C  S I  I M  M D

D1

NC0

DMI_TXN3

22

DMI_N2S_N<3>

NC1

AH41

C41

NC

C1

NC2

DMI_TXP0

AC37

22 5

DMI_N2S_P<0>

NC

BA41

NC3

DMI_TXP1

AE41

22

DMI_N2S_P<1>

NC

BA40

NC4

DMI_TXP2

AF37

22

DMI_N2S_P<2>

NC

BA39

NC5

DMI_TXP3

AG41

22

DMI_N2S_P<3>

NC

BA3

NC6

NC

BA2

NC

BA1

NC

B41

NC

B2

NC10

NC

AY41

NC11

NC

AY1

NC12

NC

AW41

NC13

NC

AW1

NC14

NC

A40

NC15

NC

A4

NC16

NC

A39

NC17

NC

A3

NC18

NC

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

1 OUT

R1410

OUT

80.6

OUT OUT

2

IN

1

6 16 19

1% 1/16W MF-LF 402

C

IN

R1411 80.6 1%

 K D_REFCLKIN*  L D_REFCLKIN  C D_REFSSCLKIN*

AH33

H28

OUT

MEM_RCOMP

SMRCOMP

22 5

SDVO_CTRLDATA

OUT

MEM_RCOMP_L

AV9

VR_PWRGOOD_DELAY

SDVO_CTRLCLK

OUT

=PP1V8_S3_MEM_NB

SM_ODT0

IPU

NC

B

29

IPU

5

19

AY7

CFG6

2

19

IPU

SM_CK2*

CFG5

OUT

5% 1/16W MF-LF 402

CFG4

28

E18

PM_DPRSLPVR

75 26 5

E15

AT1

MEM_CLK_N<0> MEM_CLK_N<1>

F15

PM_EXTTS_L<0>

R1430

IPU

MEM_CLK_P<3>

28

NB_CFG<6>

IN 1

10K

CFG3

F18

 R  D  D

MEM_CLK_P<2>

29

AW35

NB_CFG<5>

IN

20

 G  N  I  X  U  M

29

AW40

SM_CK0* SM_CK1*

IN

IN

IN

=PP3V3_S0_NB

 D  V  S  R

RSVD8

K30

IN

NB_RST_IN_L

RSVD7

NB_TV_DCONSEL0

IN

1

RSVD6

(TV_DCONSEL0)

20

IN

F3

AG11

(H_EDRDY#) (H_PLLMON1#)

20

6

BGA

MEM_CLK_P<1>

R32

C

IN

MEM_CLK_P<0>

28

NC

20

IN

28

AR1

(D_PLLMON1)

34

75 23

AY35

SM_CK1

RSVD1

(VSS_MCHDETECT)

59 58

SM_CK0

RSVD2

T32

(TESTIN#)

5% 1/16W MF-LF 402

945GM NB

NC

(H_PROCHOT#)

D

U1200

(D_PLLMON1#)

(H_PLLMON1)

R1420

1

=PP3V3_S0_NB

20 19 14 6

20 19 14 6

2

3

4

5

IN IN

2

1/16W MF-LF 402

IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT

B

OUT OUT OUT OUT

NC7 NC8 NC9

 C  N

NB Misc Interfaces

A

S YN C C_ _M MA A ST E ER R =( M MA A ST E ER R)

S YN C C_ _ DA T TE E =( M MA A ST E ER R)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

14

1

110

A

 

8

6

7

D

OMIT

28 28 28 28 28 28 28 5 28 28 28 28 28 28 28 5 28 28 5 28 28 28 28 28 28

C

28 28 28 5 28 28 28 28 28 28 28 28 28 28 28 28 28 28 5 28 28 28 28 28 28 28 28 5 28

B

28 28 28 28 28

MEM_A_DQ<0>

AJ35

SA_DQ0

IO

MEM_A_DQ<1>

AJ34

SA_DQ1

IO

MEM_A_DQ<2>

AM31

SA_DQ2

AM33

IO

MEM_A_DQ<3> MEM_A_DQ<4>

AJ36

SA_DQ3 SA_DQ4

IO

MEM_A_DQ<5>

AK35

SA_DQ5

MEM_A_DQ<6>

AJ32

SA_DQ6

IO

MEM_A_DQ<7>

AH31

SA_DQ7

IO

MEM_A_DQ<8>

AN35

SA_DQ8

MEM_A_DQ<9>

AP33

SA_DQ9

MEM_A_DQ<10>

AR31

IO

IO

IO

IO IO IO IO IO

AP31 AN38

SA_DQ12

MEM_A_DQ<13>

AM36

SA_DQ13

MEM_A_DQ<14>

AM34

SA_DQ14

IO

MEM_A_DQ<15>

AN33

SA_DQ15

MEM_A_DQ<16>

AK26

SA_DQ16

IO

MEM_A_DQ<17>

IO

MEM_A_DQ<18>

IO

AL27 AM26

MEM_A_DQ<19>

AN24

SA_DQ18

MEM_A_DQ<20>

AK28

SA_DQ20

MEM_A_DQ<21>

AL28

SA_DQ21

MEM_A_DQ<22>

AM24

SA_DQ22

MEM_A_DQ<23>

AP26

SA_DQ23

MEM_A_DQ<24>

AP23

SA_DQ24

MEM_A_DQ<25>

AL22

SA_DQ25

IO

MEM_A_DQ<26>

AP21

SA_DQ26

IO

MEM_A_DQ<27>

IO IO

AN20

SA_DQ27

MEM_A_DQ<28>

AL23

SA_DQ28

IO

MEM_A_DQ<29>

AP24

SA_DQ29

IO

MEM_A_DQ<30>

AP20

SA_DQ30

IO

IO

MEM_A_DQ<31>

AT21

SA_DQ31

MEM_A_DQ<32>

AR12

SA_DQ32

IO

MEM_A_DQ<33>

AR14

SA_DQ33

IO

MEM_A_DQ<34>

AP13

SA_DQ34

MEM_A_DQ<35>

AP12

SA_DQ35

IO

IO IO IO IO IO

AU12

30 28

MEM_A_BS<0>

SA_BS1

AV14

30 28

MEM_A_BS<1>

SA_BS2

BA20

30 28

MEM_A_BS<2>

MEM_A_DQ<36>

AT13

MEM_A_DQ<37>

AT12

SA_DM0

 A  Y  R  O  M  E  M

OUT OUT OUT

AL14

SA_DQ38

AL12

SA_DQ39

28

MEM_A_DM<1>

AL26

28

MEM_A_DM<2>

SA_DM3

AN22

28 28

AM14

SA_DM5

AL9

SA_DM6

AR3

SA_DM7

AH4

28 28 28

OUT

MEM_A_DM<0>

AM35

OUT OUT OUT

MEM_A_DM<3>

OUT

MEM_A_DM<4>

OUT

MEM_A_DM<5>

OUT

MEM_A_DM<6>

OUT

MEM_A_DM<7>

OUT

AK33

28 5

MEM_A_DQS_P<0>

SA_DQS1

AT33

28 5

MEM_A_DQS_P<1>

SA_DQS2

AN28

28 5

MEM_A_DQS_P<2>

IO

SA_DQS3

AM22

28 5

MEM_A_DQS_P<3>

IO

SA_DQS4

AN12

28 5

MEM_A_DQS_P<4>

SA_DQS5

AN8

28 5

MEM_A_DQS_P<5>

SA_DQS6

AP3

28 5

MEM_A_DQS_P<6>

SA_DQS7

AG5

28 5

MEM_A_DQS_P<7>

SA_DQS2* SA_DQS3*

28 5

AK32

28 5

AU33

28 5

AN27

28 5

AM21

IO IO

IO IO IO IO

MEM_A_DQS_N<0>

IO

MEM_A_DQS_N<1>

IO

MEM_A_DQS_N<2>

IO

MEM_A_DQS_N<3>

IO

MEM_A_DQS_N<4>

SA_DQS4*

AM12

 M  E

SA_DQS5*

AL8

28 5

MEM_A_DQS_N<5>

SA_DQS6*

AN3

28 5

MEM_A_DQS_N<6>

IO

 T  S  Y  S

SA_DQS7*

AH5

28 5

MEM_A_DQS_N<7>

IO

 R  D  D

28 5

IO IO

29

29 29 29 5 29 29 5 29 29 29 29

29 29 29 29 29 29 29 29 29 29 5 29 29 5 29 29 29 29 29

SA_MA0

AY16

30 28

MEM_A_A<0>

SA_MA1

AU14

30 28

MEM_A_A<1>

SA_MA2

AW16

30 28

MEM_A_A<2>

SA_MA3

BA16

30 28

MEM_A_A<3>

SA_MA4

BA17

30 28

MEM_A_A<4>

SA_MA5

AU16

30 28

MEM_A_A<5>

SA_MA6

AV17

30 28

MEM_A_A<6>

SA_MA7

AU17

30 28

MEM_A_A<7>

OUT

SA_MA8

AW17

30 28

MEM_A_A<8>

OUT

AT16

30 28

MEM_A_A<9>

SA_MA9

29

29

SA_DQS0

SA_DQS1*

SA_DQ37

MEM_A_DQ<39>

28

AJ33

29

29

MEM_A_CAS_L

SA_DM2

SA_DQS0*

SA_DQ36

MEM_A_DQ<38>

30 28

AY13

SA_DM1

SA_DM4

SA_DQ19

IO

IO

SA_BS0

SA_CAS*

SA_DQ17

IO

IO

BGA

SA_DQ11

IO

IO

945GM NB

SA_DQ10

MEM_A_DQ<12>

OUT OUT OUT OUT OUT OUT OUT

OUT

29 29 29 29 29 29 29 29 5 29

MEM_A_DQ<40>

AK9

SA_DQ40

MEM_A_DQ<41>

AN7

SA_DQ41

MEM_A_DQ<42>

AK8

SA_DQ42

MEM_A_DQ<43>

AK7

SA_DQ43

MEM_A_DQ<44>

AP9

SA_DQ44

MEM_A_DQ<45>

AN9

SA_DQ45

MEM_A_DQ<46>

AT5

SA_DQ46

MEM_A_DQ<47>

AL5

SA_DQ47

IO

MEM_A_DQ<48>

AY2

SA_DQ48

IO

MEM_A_DQ<49>

AW2

SA_DQ49

IO

MEM_A_DQ<50>

AP1

SA_DQ50

29

IO

MEM_A_DQ<51>

AN2

SA_DQ51

29

MEM_A_DQ<52>

AV2

SA_DQ52

29

MEM_A_DQ<53>

AT3

SA_DQ53

29

MEM_A_DQ<54> MEM_A_DQ<55>

AN1 AL2

SA_DQ54 SA_DQ55

29

MEM_A_DQ<56>

AG7

SA_DQ56

29

MEM_A_DQ<57>

AF9

SA_DQ57

29

MEM_A_DQ<58>

AG4

SA_DQ58

29

MEM_A_DQ<59>

AF6

SA_DQ59

29

MEM_A_DQ<60>

AG9

SA_DQ60

29

MEM_A_DQ<61>

AH6

SA_DQ61

29

MEM_A_DQ<62>

AF4

SA_DQ62

29 5

MEM_A_DQ<63>

AF8

SA_DQ63

29

IO IO IO IO IO IO IO IO

IO IO

D

U1200

(4 OF 10)

MEM_A_DQ<11>

1

OMIT

U1200 28

2

3

4

5

SA_MA10 SA_MA11 SA_MA12 SA_MA13

AU13

30 28

AV20 AV12

AW14

SA_RCVENIN*

AK23

SA_WE*

30 28

AT17

SA_RAS* SA_RCVENOUT*

30 28

AK24 AY14

30 28

30 28

MEM_A_A<10>

OUT

MEM_A_A<11>

OUT

MEM_A_A<12>

OUT

MEM_A_A<13>

OUT

29 29 29 29 29 5 29

MEM_A_RAS_L

OUT

NC

29 29

NC 30 28

29 5

MEM_A_WE_L

OUT

29

MEM_B_DQ<0>

AK39

SB_DQ0

IO

MEM_B_DQ<1>

AJ37

SB_DQ1

IO

MEM_B_DQ<2>

AP39

SB_DQ2

AR41

IO

MEM_B_DQ<3> MEM_B_DQ<4>

AJ38

SB_DQ3 SB_DQ4

IO

MEM_B_DQ<5>

AK38

SB_DQ5

MEM_B_DQ<6>

AN41

SB_DQ6

IO

MEM_B_DQ<7>

AP41

SB_DQ7

IO

MEM_B_DQ<8>

AT40

SB_DQ8

MEM_B_DQ<9>

AV41

SB_DQ9

MEM_B_DQ<10>

AU38

IO

IO

IO

IO IO IO IO IO

MEM_B_DQ<11>

AV38

MEM_B_DQ<12>

AP38

SB_DQ12

MEM_B_DQ<13>

AR40

SB_DQ13

MEM_B_DQ<14>

AW38

SB_DQ14

MEM_B_DQ<15>

AY38

SB_DQ15

MEM_B_DQ<16>

BA38

SB_DQ16

IO

MEM_B_DQ<17>

IO

MEM_B_DQ<18> MEM_B_DQ<19>

AV36 AR36 AP36 BA36

SB_DQ20

MEM_B_DQ<21>

AU36

SB_DQ21

MEM_B_DQ<22>

AP35

SB_DQ22

MEM_B_DQ<23>

AP34

SB_DQ23

MEM_B_DQ<24>

AY33

SB_DQ24

MEM_B_DQ<25>

BA33

SB_DQ25

IO

MEM_B_DQ<26>

AT31

SB_DQ26

IO

MEM_B_DQ<27>

IO

AU29

SB_DQ27

MEM_B_DQ<28>

AU31

SB_DQ28

IO

MEM_B_DQ<29>

AW31

SB_DQ29

IO

MEM_B_DQ<30>

AV29

SB_DQ30

IO

IO

MEM_B_DQ<31>

AW29

MEM_B_DQ<32>

AM19

SB_DQ32

MEM_B_DQ<33>

AL19

SB_DQ33

IO

MEM_B_DQ<34>

AP14

SB_DQ34

MEM_B_DQ<35>

AN14

SB_DQ35

IO IO IO IO IO

MEM_B_DQ<36> MEM_B_DQ<37>

AN17 AM16

SB_DQ36 SB_DQ37

MEM_B_DQ<38>

AP15

SB_DQ38

MEM_B_DQ<39>

AL15

SB_DQ39

MEM_B_DQ<40>

AJ11

SB_DQ40

MEM_B_DQ<41>

AH10

SB_DQ41

MEM_B_DQ<42>

AJ9

SB_DQ42

MEM_B_DQ<43>

AN10

SB_DQ43

MEM_B_DQ<44>

AK13

SB_DQ44

MEM_B_DQ<45>

AH11

SB_DQ45

MEM_B_DQ<46>

AK10

SB_DQ46

MEM_B_DQ<47>

AJ8

SB_DQ47

IO

MEM_B_DQ<48>

BA10

SB_DQ48

IO

MEM_B_DQ<49>

IO

MEM_B_DQ<50>

IO

MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53>

AY9

SB_DQ53

MEM_B_DQ<54> MEM_B_DQ<55>

AW5 AY5

SB_DQ54 SB_DQ55

MEM_B_DQ<56>

AV4

SB_DQ56

MEM_B_DQ<57>

AR5

SB_DQ57

MEM_B_DQ<58>

AK4

SB_DQ58

MEM_B_DQ<59>

AK3

SB_DQ59

MEM_B_DQ<60>

AT4

SB_DQ60

MEM_B_DQ<61>

AK5

SB_DQ61

MEM_B_DQ<62>

AJ5

SB_DQ62

MEM_B_DQ<63>

AJ3

SB_DQ63

IO IO IO IO IO IO IO IO

IO IO

MEM_B_BS<1>

30 29

MEM_B_BS<2>

AR24

30 29

MEM_B_CAS_L

SB_DM0

AK36

29

MEM_B_DM<0>

SB_DM1

AR38

29

MEM_B_DM<1>

SB_DM2

AT36

29

MEM_B_DM<2>

SB_DM3

BA31

29

MEM_B_DM<3>

SB_DM4

AL17

29

MEM_B_DM<4>

SB_DM5

AH8

29

MEM_B_DM<5>

SB_DM6

BA5

29

MEM_B_DM<6>

SB_DM7

AN4

29

MEM_B_DM<7>

OUT OUT OUT

AW10

SB_DQ49

BA4

SB_DQ50

AW4

SB_DQ51

AY10

SB_DQ52

OUT OUT OUT OUT OUT OUT OUT OUT OUT

MEM_B_DQS_P<0>

SB_DQS1

AT39

29 5

MEM_B_DQS_P<1>

SB_DQS2

AU35

29 5

MEM_B_DQS_P<2>

IO

SB_DQS3

AR29

29 5

MEM_B_DQS_P<3>

IO

SB_DQS4

AR16

29 5

MEM_B_DQS_P<4>

SB_DQS5

AR10

29 5

MEM_B_DQS_P<5>

IO

SB_DQS6

AR7

29 5

MEM_B_DQS_P<6>

IO

SB_DQS7

AN5

29 5

MEM_B_DQS_P<7>

SB_DQS0*

AM40

29 5

MEM_B_DQS_N<0>

SB_DQS1*

AU39

29 5

MEM_B_DQS_N<1>

SB_DQS2*

AT35

29 5

MEM_B_DQS_N<2>

SB_DQS3*

AP29

29 5

MEM_B_DQS_N<3>

SB_DQS4*

AP16

29 5

MEM_B_DQS_N<4>

 M  E

SB_DQS5*

AT10

29 5

MEM_B_DQS_N<5>

SB_DQS6*

AT7

29 5

MEM_B_DQS_N<6>

 T  S  Y  S

SB_DQS7*

AP5

29 5

MEM_B_DQS_N<7>

 R  D  D

 Y  R  O  M  E  M

SB_DQ31

IO

IO

MEM_B_BS<0>

30 29

AY28

29 5

SB_DQ19

MEM_B_DQ<20>

IO

30 29

AV23

SB_BS2

AM39

 B

SB_DQ18

IO

IO

AT24

SB_BS1

SB_DQS0

SB_DQ17

IO

IO

SB_BS0

SB_CAS*

SB_DQ11

IO

IO

BGA

SB_DQ10

IO

IO

945GM NB (5 OF 10)

IO IO

IO

IO IO

IO IO IO IO IO IO

SB_MA0

AY23

30 29

MEM_B_A<0>

SB_MA1

AW24

30 29

MEM_B_A<1>

SB_MA2

AY24

30 29

MEM_B_A<2>

SB_MA3

AR28

30 29

MEM_B_A<3>

SB_MA4

AT27

30 29

MEM_B_A<4>

OUT

SB_MA5

AT28

30 29

MEM_B_A<5>

OUT

SB_MA6

AU27

30 29

MEM_B_A<6>

SB_MA7

AV28

30 29

MEM_B_A<7>

OUT

SB_MA8

AV27

30 29

MEM_B_A<8>

OUT

AW27

30 29

MEM_B_A<9>

SB_MA10

AV24

30 29

MEM_B_A<10>

SB_MA11

BA27

30 29

MEM_B_A<11>

SB_MA12

AY27

30 29

MEM_B_A<12>

SB_MA13

AR23

30 29

MEM_B_A<13>

SB_RAS*

AU23

30 29

MEM_B_RAS_L

SB_RCVENIN*

AK16

NC

SB_RCVENOUT*

AK18

NC

SB_WE*

AR27

30 29

MEM_B_WE_L

SB_MA9

C

IO

OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

B

OUT

5

28 28 28 28 28 28 5 28 28 28 28

IO IO IO IO IO IO IO IO IO IO

29

IO IO IO IO IO IO IO IO IO IO

NB DDR2 Interfaces

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

15

1

110

A

 

8

7

6

OMIT 19

=PP2V5_S0_NB_VCCSYNC

H22

VCCSYNC

19

=PP2V5_S0_NB_VCC_TXLVDS

C30

VCC_TXLVDS0

19

PP1V5_S0_NB_VCC3G

B30 A30

D

BGA

VTT3

V14

(8 OF 10)

T14

VTT5

R14

VCC3G1

VTT6

P14

Y41

VCC3G2

VTT7

N14

V41

VCC3G3

VTT8

M14

R41

VCC3G4

VTT9

L14

N41

VCC3G5

L41

VCC3G6

AC33 G41 H41 F21 E21 G21

VCCA_3GPLL VCCA_3GBG VSSA_3GBG VCCA_CRTDAC0 VCCA_CRTDAC1

 R  E  W  O  P

AD13

VTT11

AC13

VTT12

AB13

VTT13

AA13

VTT14 VTT15

Y13

VTT16

V13

VTT17

U13

VTT18

T13

19

PP1V5_S0_NB_VCCA_DPLLA

B26

VCCA_DPLLA

VTT19

R13

19

PP1V5_S0_NB_VCCA_DPLLB

C39

VCCA_DPLLB

VTT20

N13

19

PP1V5_S0_NB_VCCA_HPLL

AF1

VCCA_HPLL

VTT21

M13

=PP2V5_S0_NB_VCCA_LVDS

A38

L13

VCCA_LVDS

VTT22

19

B39

AB12

GND_NB_VSSA_LVDS

VSSA_LVDS

VTT23

19

VTT24

AA12

19

PP1V5_S0_NB_VCCA_MPLL

AF2

VCCA_MPLL

VTT25

Y12

H20

W12

PP3V3_S0_NB_VCCA_TVBG

VCCA_TVBG

VTT26

19

V12

GND_NB_VSSA_TVBG

G20

VSSA_TVBG

VTT27

19

VTT28

U12

19

PP3V3_S0_NB_VCCA_TVDACC

19

19 6

PP3V3_S0_NB_VCCA_TVDACB PP3V3_S0_NB_VCCA_TVDACA

E20

VCCA_TVDACC0

VTT29

T12

F20

VCCA_TVDACC1

VTT30

R12

C20

VCCA_TVDACB0

VTT31

P12

D20

VCCA_TVDACB1

VTT32

N12

E19

VCCA_TVDACA0

VTT33

M12

F19

VCCA_TVDACA1

VTT34

L12

VTT35

R11

VTT36

P11

VTT37

N11

AH1

=PP1V5_S0_NB_VCCD_HMPLL

AH2

19

19

19 6

19

19 16 6

VCCD_HMPLL0 VCCD_HMPLL1

A28

VCCD_LVDS0

VTT38

M11

B28

VCCD_LVDS1

VTT39

R10

C28

VCCD_LVDS2

VTT40

PP1V5_S0_NB_VCCD_TVDAC

D21

VCCD_TVDAC

=PP3V3_S0_NB_VCC_HV

A23 B23 B25

=PP1V5_S0_NB_VCCD_LVDS

H19

PP1V5_S0_NB_VCCD_QTVDAC =PP1V5_S0_NB_VCCAUX

B

VTT41

C

N10 M10

VCC_HV0

VTT43

P9

VCC_HV1

VTT44

N9

VCC_HV2

VTT45

M9

VTT46

R8

VTT47

P8

AK31

VCCAUX0

VTT48

N8

AF31

VCCAUX1

VTT49

M8

AE31

VCCAUX2

VTT50

P7

AC31

VCCAUX3

VTT51

N7

AL30

VCCAUX4

VTT52

M7

AK30

VCCAUX5

VTT53

R6

AJ30

VCCAUX6

VTT54

P6

AH30

VCCAUX7

VTT55

M6

AG30

VCCAUX8

VTT56

A6

AF30

VCCAUX9

VTT57

R5

AE30

VCCAUX10

VTT58

P5

C1713 0.47UF 10% 6.3V CERM-X5R 402

AD30

VCCAUX11

VTT59

N5

AC30

VCCAUX12

VTT60

M5

AG29

VCCAUX13

VTT61

P4

AF29

VCCAUX14

VTT62

N4

AE29

VCCAUX15

VTT63

M4

AD29

R3

NB_VTTLF_CAP3

VCCAUX16

VTT64

AG28

VCCAUX17 VCCAUX18

VTT65 VTT66

N3

AF28

VCCAUX19

VTT67

M3

AE28

VCCAUX20

VTT68

R2

AH22

VCCAUX21

VTT69

P2

AJ21

VCCAUX22

VTT70

M2

AH21

VCCAUX23

VTT71

D2

NB_VTTLF_CAP2

AJ20

VCCAUX24

VTT72

AB1

NB_VTTLF_CAP1

AH20

VCCAUX25

VTT73

R1

AH19

VCCAUX26

VTT74

P1

C1711

P19

VCCAUX27

VTT75

N1

0.47UF

VTT76

M1

10% 6.3V CERM-X5R 402

1

B

2

P3

AC29

A

6 19

P10

VTT42

VCCD_QTVDAC

1

W13

GND_NB_VSSA_CRTDAC

VSSA_CRTDAC

2

D

VTT10

19

19

C

VTT2

W14

VTT4

PP1V5_S0_NB_VCCA_3GPLL

PP2V5_S0_NB_VCCA_CRTDAC

AB14

VCC3G0

=PP2V5_S0_NB_VCCA_3GBG

19

VCC_TXLVDS2

AC14

VTT1

AB41

19

GND_NB_VSSA_3GBG

VCC_TXLVDS1

=PP1V05_S0_NB_VTT VTT0

945GM NB

U1200

AJ41

19 6 19

3

4

5

P16

VCCAUX28

AH15

VCCAUX29

P15

VCCAUX30

AH14

VCCAUX31

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

1

1

C1712

2

2

20% 6.3V X5R 402

0.22UF

NB Power 2 SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

17

1

110

A

 

8

6

7

5

3

4

OMIT AC41

VSS_0

AA41

VSS_1

U1200

W41

VSS_2

945GM

T41

VSS_3

P41

VSS_4

AG34

VSS_99

AF34 AE34

VSS_102

C34

VSS_103

AW33

VSS_104

AV33

VSS_105

AR33

VSS_106

AE33

VSS_107

AB33

VSS_11

VSS_108

Y33

VSS_12

VSS_109

V33

VSS_13

VSS_110

T33

AG40

VSS_14

VSS_111

R33

AF40

VSS_15

VSS_112

M33

AE40

VSS_16

VSS_113

H33

B40

VSS_17 VSS_18

VSS_114 VSS_115

G33

AW39

VSS_19

VSS_116

D33

AV39

VSS_20

VSS_117

B33

AR39

VSS_21

VSS_118

AH32

AN39

VSS_22

VSS_119

AG32

AJ39

VSS_23

VSS_120

AF32

VSS_121

AE32

VSS_122

AC32

VSS_123

AB32

VSS_27

VSS_124

G32

VSS_28

VSS_125

B32

VSS_29

VSS_126

AY31

VSS_30

VSS_127

AV31

VSS_31

VSS_128

AN31

VSS_32

VSS_129

AJ31

VSS_33

VSS_130

AG31

VSS_34

VSS_131

AB31

VSS_35

VSS_132

Y31

VSS_36

VSS_133

AB30

H39

VSS_37

VSS_134

E30

G39

VSS_38

VSS_135

AT29

F39

VSS_39

VSS_136

AN29

D39

VSS_40

VSS_137

AB29

AT38

VSS_41

VSS_138

T29

AM38

VSS_42

VSS_139

N29

AH38

VSS_43

VSS_140

K29

VSS_141

G29

VSS_142

E29

F41 AV40 AP40 AN40 AK40 AJ40 AH40

AY39

AC39 AB39 AA39 Y39 W39 V39 T39 R39 P39 N39 M39 L39 J39

AG38 AF38

VSS_5

BGA

(9 OF 10)

VSS_6 VSS_7 VSS_8 VSS_9 VSS_10

VSS_24 VSS_25 VSS_26

VSS_44 VSS_45

VSS

VSS_46

VSS_143

C29

C38

VSS_47

VSS_144

B29

VSS_48

VSS_145

A29

VSS_49

VSS_146

BA28

VSS_50

VSS_147

AW28

VSS_51

VSS_148

AU28

VSS_52

VSS_149

AP28

VSS_53

VSS_150

AM28

VSS_54

VSS_151

AD28

VSS_55

VSS_152

AC28

R37

VSS_56

VSS_153

W28

P37

VSS_57

VSS_154

J28

N37

VSS_58

VSS_155

E28

M37

VSS_59

VSS_156

AP27

L37

VSS_60

VSS_157

AM27

VSS_158

AK27

VSS_159

J27

VSS_160

G27

VSS_161

F27

VSS_65

VSS_162

C27

VSS_66

VSS_163

B27 AN26

AH37 AB37 AA37 Y37 W37 V37 T37

J37 H37 G37 F37 D37 AY36 AW36

VSS_61 VSS_62 VSS_63 VSS_64

VSS_67

VSS_164

AH36

VSS_68 VSS_69

VSS_165 VSS_166

K26

AG36

VSS_70

VSS_167

F26

VSS_71

VSS_168

D26

VSS_72

VSS_169

AK25

VSS_73

VSS_170

P25

C36

VSS_74

VSS_171

K25

B36

VSS_75

VSS_172

H25

BA35

VSS_76

VSS_173

E25

AV35

VSS_77

VSS_174

D25

AR35

VSS_78

VSS_175

A25

AH35

VSS_79

VSS_176

BA24

VSS_177

AU24

VSS_178

AL24

VSS_179

AW23

AE36 AC36

AB35 AA35 Y35 W35 V35 T35 R35 P35 N35

A

M35 L35 J35 H35

VSS_180

U1200

VSS_273

J11

AN23

VSS_181

945GM

VSS_274

D11

AM23

VSS_182

VSS_275

B11

AH23

VSS_183

VSS_276

AV10

AC23

VSS_184

VSS_277

AP10

W23

VSS_185

VSS_278

AL10

K23

VSS_186

VSS_279

AJ10

J23

VSS_187

VSS_280

AG10

F23

VSS_188

VSS_281

AC10

C23

VSS_189

VSS_282

W10

AA22

VSS_190

VSS_283

U10

K22

VSS_191

VSS_284

BA9

G22

VSS_192

VSS_285

AW9

F22

VSS_193

VSS_286

AR9

E22

VSS_194

D22

VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92

G35

VSS_93

F35

VSS_94

D35

VSS_95

AN34

VSS_96

NB BGA

(10 OF 10)

VSS

VSS_287

AH9

VSS_195

VSS_288

AB9

A22

VSS_196

VSS_289

Y9

BA21

VSS_197

VSS_290

R9

AV21

VSS_198

VSS_291

G9

AR21

VSS_199

VSS_292

E9

AN21

VSS_200

VSS_293

A9

AL21

VSS_201

VSS_294

AG8

AB21

VSS_202

VSS_295

AD8

Y21

VSS_203

VSS_296

AA8

P21

VSS_204

VSS_297

U8

K21

VSS_205

VSS_298

K8

J21

VSS_206

VSS_299

C8

H21

VSS_207

VSS_300

BA7

C21

VSS_208

VSS_301

AV7

AW20

VSS_209

VSS_302

AP7

AR20

VSS_210

VSS_303

AL7

AM20

VSS_211

VSS_304

AJ7

AA20

VSS_212

VSS_305

AH7

K20

VSS_213

VSS_306

AF7

B20

VSS_214

VSS_307

AC7

A20

VSS_215

VSS_308

R7

AN19

VSS_216

VSS_309

G7

AC19

VSS_217

VSS_310

D7

W19

VSS_218

VSS_311

AG6

K19

VSS_219

VSS_312

AD6

G19

VSS_220

VSS_313

AB6

C19

VSS_221

VSS_314

Y6

AH18 P18

VSS_222 VSS_223

VSS_315 VSS_316

U6 N6

H18

VSS_224

VSS_317

K6

D18

VSS_225

VSS_318

H6

A18

VSS_226

VSS_319

B6

AY17

VSS_227

VSS_320

AV5

AR17

VSS_228

VSS_321

AF5

AP17

VSS_229

VSS_322

AD5

AM17

VSS_230

VSS_323

AY4

AK17

VSS_231

VSS_324

AR4

AV16

VSS_232

VSS_325

AP4

AN16

VSS_233

VSS_326

AL4

AL16

VSS_234

VSS_327

AJ4

J16

VSS_235

VSS_328

Y4

F16

VSS_236

VSS_329

U4

C16

VSS_237

VSS_330

R4

AN15

VSS_238

VSS_331

J4

AM15

VSS_239

VSS_332

F4

AK15

VSS_240

VSS_333

C4

N15

VSS_241

VSS_334

AY3

M15

VSS_242

VSS_335

AW3

L15

VSS_243

VSS_336

AV3

B15

VSS_244

VSS_337

AL3

A15

VSS_245

VSS_338

AH3

BA14

VSS_246

VSS_339

AG3

AT14

VSS_247

VSS_340

AF3

AK14

VSS_248

VSS_341

AD3

AD14

VSS_249

VSS_342

AC3

AA14

VSS_250

VSS_343

AA3

U14

VSS_251

VSS_344

G3

K14

VSS_252

VSS_345

AT2

H14

VSS_253

VSS_346

AR2

E14

VSS_254

VSS_347

AP2

AV13

VSS_255

VSS_348

AK2

AR13

VSS_256

VSS_349

AJ2

AN13

VSS_257

VSS_350

AD2

AM13

VSS_258

VSS_351

AB2

AL13

VSS_259

VSS_352

Y2

AG13

VSS_260

VSS_353

U2

P13

VSS_261

VSS_354

T2

F13

VSS_262

VSS_355

N2

D13

VSS_263

VSS_356

J2

B13

VSS_264

VSS_357

H2

AY12

VSS_265

VSS_358

F2

AC12

VSS_266

VSS_359

C2

K12

VSS_267

VSS_360

AL1

H12

VSS_268

E12

VSS_269

AD11

VSS_270

AA11

VSS_271

Y11

VSS_272

M26

AN36

AF36

AT23

F33

AE38

AK37

B

AK34

VSS_98

AC34

J41

C

VSS_97

VSS_100 VSS_101

M41

D

NB

2

1

OMIT

D

C

B

NB Grounds SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

18

1

110

A

 

8

6

7

2

3

4

5

LVDS DISABLE

TVOUT DISABLE 13

Power Interface These are the power signals that leave the

IN

D

16 6 =PPVCORE_S0_NB 19

NB "block"

=PP1V05_S0_FSB_NB

IN

=PP1V05_S0_NB

6

=PP1V05_S0_NB_VTT

6 17 19

=PP1V5_S0_NB

6 19

=PP1V5_S0_NB_PCIE

6 13

IN IN

13

CRT_RED_L

13

CRT_GREEN CRT_GREEN_L

13 13

CRT_IREF

13

13

13

=PP1V5_S0_NB_PLL

13

6 19

=PP1V5_S0_NB_TVDAC

6 19

CRT_VSYNC_R

13

13

6 17

CRT_HSYNC_R

13

13

IN

=PP1V5_S0_NB_VCCD_LVDS

17 19

IN IN

IN IN IN IN IN

=PP2V5_S0_NB_VCCSYNC

=PP1V5_S0_NB_VCCAUX

6 16 17 19

=PP1V8_S3_MEM_NB

6 14 16 19

13 17

13

TRUE

CRT_DDC_CLK

13

TP_CRT_DDC_DATA

TRUE

CRT_DDC_DATA

13

17 19

13

6 17 19

17

=PP2V5_S0_NB_VCCA_LVDS

17 19

=PP3V3_S0_NB

6 6 17 19

DISPLAY DISABLE L1934 FERR-120-OHM-0.2A

=PP1V5_S0_NB_PLL

19 6

1

PP1V5_S0_NB_VCCA_HPLL

C

C1934

1

1

22uF These 4 0.1uF caps should

TP_NB_VCCA_DPLLA

TRUE

TP_NB_VCCA_DPLLB

C1935

 

TRUE

2

L1936 FERR-120-OHM-0.2A

1

1

LVDS_A_DATA_N<2>

TRUE

TP_LVDS_A_DATA_N<2>

LVDS_A_DATA_P<0>

TRUE

TP_LVDS_A_DATA_P<0>

LVDS_A_DATA_P<1>

TRUE

TP_LVDS_A_DATA_P<1>

IO

LVDS_A_DATA_P<2>

TRUE

TP_LVDS_A_DATA_P<2>

IO

LVDS_B_DATA_N<0>

TRUE

TP_LVDS_B_DATA_N<0>

LVDS_B_DATA_N<1>

TRUE

TP_LVDS_B_DATA_N<1>

IO

LVDS_B_DATA_N<2>

TRUE

TP_LVDS_B_DATA_N<2>

IO

LVDS_B_DATA_P<0>

TRUE

TP_LVDS_B_DATA_P<0>

IO

L VD S_ B_D AT A_ P< 1>

TRUE

T P_ LVD S_ B_ DA TA_ P< 1>

LVDS_B_DATA_P<2>

TRUE

TP_LVDS_B_DATA_P<2>

LVDS_BKLTEN

TRUE

LVDS_VDDEN

TRUE

LVDS_IBG

TRUE

GND_NB_VSSA_LVDS

TRUE

LVDS_VREFH

TRUE

TP_LVDS_VREFH

LVDS_VREFL

TRUE

TP_LVDS_VREFL

OUT OUT

19 17

=PP2V5_S0_NB_VCCA_LVDS

19 17

=PP1V5_S0_NB_VCCD_LVDS

19 17

=PP2V5_S0_NB_VCC_TXLVDS

PP1V5_S0_NB_VCCA_DPLLB

17

IN

13

NB_CLK_DREFCLKIN_P NB_CLK_DREFSSCLKIN_P NB_CLK_DREFSSCLKIN_N

BI

C1965

1

4.7uF 2

B

19 16 14 6

TP_LVDS_BKLTEN TP_LVDS_VDDEN TP_LVDS_IBG

OUT

13

OUT

14

13

OUT

14

LVDS_BKLTCTL

2

2

C1966

TRUE

TP_LVDS_CLKCTLA

TRUE

TP_LVDS_CLKCTLB

IN

LVDS_DDC_CLK

TRUE

TP_LVDS_DDC_CLK

IN

LVDS_DDC_DATA

TRUE

TP_LVDS_DDC_DATA

17

C1937

TVOUT DISABLE

20% 10V CERM 402

C1967

1

2.2UF

20% 6.3V CERM 603

2

C

TP_LVDS_BKLTCTL

TRUE

LVDS_CLKCTLB

IN

=PP1V5_S0_NB

PP3V3_S0_NB_VCCA_TVDACA

17

PP3V3_S0_NB_VCCA_TVDACB

17

PP3V3_S0_NB_VCCA_TVDACC

17

PP3V3_S0_NB_VCCA_TVBG

17

=PP1V05_S0_NB_VTT

1

D

TP_GND_NB_VSSA_LVDS

LVDS_CLKCTLA

IN

13

14 14

19 6

19 17 6

TP_LVDS_B_CLK_P

IO

0.1uF

22uF 20% 6.3V X5R 805

TP_LVDS_A_DATA_N<1>

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

2 0603

C1936

17

NB_CLK_DREFCLKIN_N

PP1V5_S0_NB_VCCA_MPLL

TRUE

IN

13

20% 10V CERM 402

be within 5 mm of NB edge

1

PP1V5_S0_NB_VCCA_DPLLA

0.1uF

20% 6.3V  2 X5R 805

Layout Note:

LVDS_A_DATA_N<1>

TP_LVDS_B_CLK_N

17

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

2 0603

IO

IN

13

6 14 20

=PP3V3_S0_NB_TVDAC

TP_LVDS_A_DATA_N<0>

IN

13

=PP3V3_S0_NB_VCC_HV

TRUE

IN

13

=PP2V5_S0_NB_VCCA_3GBG

IN

LVDS_A_DATA_N<0>

IO

13

TP_CRT_DDC_CLK

=PP2V5_S0_NB_VCC_TXLVDS

IN

IO

17 19

GND_NB_VSSA_CRTDAC

17 19

TRUE

IO

13

=PP2V5_S0_NB_VCCSYNC

IO

IO

13

=PP1V5_S0_NB_VCCD_HMPLL

TP_LVDS_A_CLK_P

TRUE

IO

13

IN

IN

TP_LVDS_A_CLK_N

TRUE

LVDS_B_CLK_N

IO

13

13

CRT_BLUE CRT_BLUE_L

TRUE

LVDS_A_CLK_P LVDS_B_CLK_P

IO

13

13

LVDS_A_CLK_N

IO

13

13 6 16 19

IN

17

CRT_RED 5 6 12

=PPVCORE_S0_NB

IN

PP2V5_S0_NB_VCCA_CRTDAC

13

IN

1

1

0.22uF

10% 6.3V CERM1 603

NOSTUFF

=PPVCORE_S0_NB

C1968

2

20% 6.3V ELEC CASE-C1

1

Layout Note:

Place in cavity

Place on the edge

1

C1900

1

C1901

330UF 2

Layout Note:

13

TV_DACA_OUT

13

TV_DACB_OUT

20% 6.3V ELEC CASE-C1

2

1

10UF

330UF

20% 6.3V ELEC CASE-C1

C1902

2

C1903

1

2

1

1UF

10UF

20% 6.3V CERM 805-1

C1904

20% 6.3V CERM 805-1

2

C1905

1

0.22uF

10% 6.3V CERM 402

2

C1906

1

0.22uF

20% 6.3V X5R 402

2

20% 6.3V X5R 402

0.22uF 2

20% 6.3V X5R 402

IN IN

TV_IREF

13

C1907

IN

TV_DACC_OUT

13

330UF

20% 6.3V X5R 402

2

19 16 6

13

TV_IRTNA

13

TV_IRTNB

13

TV_IRTNC

IN IN IN IN

B

=PP1V8_S3_MEM_NB GND_NB_VSSA_TVBG

R1982 1

1K

R1980

2

1

MEM_VREF_NB_1 5% 1/16W MF-LF 402

1

R1983

1K

5% 1/16W MF-LF 2 402

1

2

MEM_VREF_NB_0 5% 1/16W MF-LF 402

0.1UF 2

1K

5 14

C1982

1

R1981 1K

5% 1/16W MF-LF 2 402

20% 16V CERM 603

1

5 14

C1981

6

2

=PP1V5_S0_NB_TVDAC

PP1V5_S0_NB_VCCD_TVDAC

19

0.1UF

PP1V5_S0_NB_VCCD_QTVDAC

L1970 91NH

=PP1V5_S0_NB_3GPLL 1

PP1V5_S0_NB_VCC3G

1

Layout Note:

1

C1970

2

close to MCH

C1971

1

20% 2.5V POLY SMB2

2

C1972 10UF

10UF

220UF

Place L and C

=PP3V3_S0_NB_VCC_HV

17

20% 6.3V CERM 805-1

2

20% 6.3V CERM 805-1

THESE 2 CAPS SHOULD BE within 6.35 mm of NB edge

Layout Note: 10uF caps should be close to MCH

14

on opposite side.

C1914

1

10UF 2

20% 6.3V CERM 805-1

14

IN IN

SDVO_CTRLCLK

2

20% 10V CERM 402

1uH, 20%

NB (GM) Decoupling

Should be 1%

L1975 =PP1V5_S0_NB_3GPLL

19 17 16 6

=PP1V5_S0_NB_VCCAUX

C1916

1

2

PP1V5_S0_NB_3GPLL_F VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

C1918

1

0.51 1% 1/16W MF-LF 402

C1975

1

1

2

2

10UF

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

C1976 0.1uF 20%

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

10V CERM 402

GND_NB_VSSA_3GBG

3GPLL 10uF cap should be placed in cavity

SYNC_DATE=(MASTER)

17

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

6.3V CERM 805-1

Layout Note:

10V CERM 402

SYNC_MASTER=(MASTER)

PP1V5_S0_NB_VCCA_3GPLL

2

20%

0.1uF 20%

10V CERM 402

2 0805

0.1uF 20% 2

R1975

1.0UH-220MA-0.12-OHM 1

1

TP_SDVO_CTRLDATA

0.1uF

19 6

=PP2V5_S0_NB_VCCA_3GBG

TP_SDVO_CTRLCLK

SDVO_CTRLDATA

C1915

A 19 17 6

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

17

Layout Note: Route to caps, then GND

SIZE

APPLE COMPUTER INC.

051-7148 SHT NONE

7

6

5

4

3

2

REV.

DRAWING NUMBER

D SCALE

8

17

Layout Note:

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

2 1210

1

17

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

20% 16V CERM 603

19 6

19 17 6

17

13 OF

19

1

110

A

 

8

6

7

3

4

5

2

1

Internal pull-ups 00 = Partial Clock Gating Disable 01 = XOR Mode Enabled

NB_CFG<13:12>

D

NB_CFG<3>

RESERVED

NB_CFG<4>

RESERVED

NB_CFG<5>

High = DMIx4

DMI x2 Select

Low

14

10 = All-Z Mode Enabled

D

11 = Normal Operation

NB_CFG<14>

RESERVED

NB_CFG<15>

RESERVED

NB_CFG<5> Internal pull-up

NBCFG_DMI_X2 1

=

R2075 2.2K

DMIx2 2

5% 1/16W MF-LF 402

PROBABLY NOT NEEDED NB_CFG<16>

14

C

Internal pull-up

NB_CFG<6>

RESERVED

FSB Dynamic ODT

14

R2085

High = Enabled

2.2K

Low

5% 1/16W MF-LF 402

=

C

NBCFG_DYN_ODT_DISABLE 1

NB_CFG<16>

Disabled 2

NB_CFG<7> Internal pull-up

NO STUFF 1

NB_CFG<7>

High = Mobile CPU

CPU Strap

Low

=

R2077 2.2K

RESERVED 2

5% 1/16W MF-LF 402

NB_CFG<17>

RESERVED

=PP3V3_S0_NB

6 14 19 20

NBCFG_VCC_1V5 1

NB_CFG<18> NB_CFG<8>

RESERVED

VCC Select

R2058

High = 1.5V

2.2K

Low

5% 1/16W MF-LF 402

=

1.05V 2

NB_CFG<18>

14

B

B

Internal pull-down

14

NB_CFG<9> Internal pull-up

=PP3V3_S0_NB 1

NB_CFG<9> PCIE Graphics Lane Reversal

2.2K

Low

5% 1/16W MF-LF 402

=

Reversed 2

1

R2079

High = Normal

6 14 19 20

NBCFG_DMI_REVERSE

NBCFG_PEG_REVERSE

NB_CFG<19> DMI Lane Reversal

=

R2059 2.2K

High = Reversed Low

Normal 2

5% 1/16W MF-LF 402

NB_CFG<19>

14

Internal pull-down

=PP3V3_S0_NB 945 External Design Spec says reserved

NB_CFG<10>

RESERVED

High = Both active

PCIe Backward

Low

Interop. Mode

  14

=

R2060 2.2K

Only SDVO or PCIe x1

6 14 19 20

NBCFG_SDVO_AND_PCIE 1

NB_CFG<20>

2

5% 1/16W MF-LF 402

NB_CFG<20> Internal pull-down

PROBABLY NOT NEEDED NB Config Straps

A

SYNC_MASTER=(MASTER)

NB_CFG<11>

RESERVED

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

20

1

110

A

 

8

6

7

26 25 24 5

=PP3V3_S0_SB_GPIO

R2105 332K

1

R2194

1

D

10K

26

26

NOTE: EE_CS HAS INTERNAL PD,

IN

IN

SB_RTC_X1

AB1

SB_RTC_X2

AB2

SB_RTC_RST_L

AA3

SB_SM_INTRUDER_L

IN

ONLY ENABLED WHEN LAN_RST#=L

ICH7-M SB

RTCX1 RTCX2

INTRUDER* SB_INTVRMEN W4 INTVRMEN W1

TP_SB_XOR_Y1

Y1

TP_SB_XOR_Y2

Y2

TP_SB_XOR_W3

W3

TP_SB_XOR_V3

V3

TP_SB_XOR_U3

U3

LAD0 LAD1

 C  T  R

Y5

TP_SB_XOR_W1

BGA

(1 OF 6)

LAD2

RTCRST*

 C  P  L

LAD3 LDRQ0*

LDRQ1*/GPIO23 LFRAME*

EE_CS

AA6

67 60 58

LPC_AD<0>

AB5

67 60 58

LPC_AD<1>

IO

AC4

67 60 58

LPC_AD<2>

Y6

IO

67 60 58

LPC_AD<3>

AC3 AA5 AB3

IO

NOTE: LAD<0-3> HAVE INTERNAL 20K PU IO

TP_SB_DRQ0_L TP_SB_GPIO23 67 60 58

LPC_FRAME_L

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU IO

NOSTUFF OUT

A20GATE

(INT PU)

EE_DIN

A20M*

AE22

POR IS SMC WILL PUT LAN INT’F INTO RESET STATE TO SAVE PWR. INTEL CONFIRMS OK TO LEAVE PINS AS

C

68 68

68 68

OUT OUT OUT IN

ACZ_SYNC

R2195 R2198

ACZ_RST_L

R2197

ACZ_BITCLK

1

5% 1/16W MF-LF 402

1 1

NC

2 2 2

TP_SB_XOR_U5

U5

TP_SB_XOR_V4

V4

TP_SB_XOR_T5

T5

TP_SB_XOR_U7

U7

TP_SB_XOR_V6

V6

TP_SB_XOR_V7

V7

39 39

SB_ACZ_BITCLK

U1

SB_ACZ_SYNC

R6

39

SB_ACZ_RST_L

R5 T2

ACZ_SDATAIN<0> TP_SB_ACZ_SDIN1 TP_SB_ACZ_SDIN2

68

OUT

ACZ_SDATAOUT

R2196

T3

CPUSPL*

 N  A  L

LAN_RSTSYNC

TP1/DPRSTP* TP2/DPSLP*

LAN_RXD0 LAN_RXD1 (WEAK

FERR*

INT PU)

LAN_RXD2

GPIO49/CPUPWRGD

 U  P  C

LAN_TXD0 LAN_TXD1 LAN_TXD2

IGNNE* INIT3_3V* INIT* INTR

ACZ_BIT_CLK ACZ_SYNC ACZ_RST* ACZ_SDIN0 20K PD

ACZ_SDIN1 20K PD T1 ACZ_SDIN2

RCIN*

  /  A  7  I  9  L   A  C  A  Z  A

NMI SMI*

AH28

7 5

CPU_A20M_L

39

2

38 38 38 38

38 38 38 38

34 5 34 5

IN IN 38 38

IN IN OUT OUT

THRMTRIP*

SB_ACZ_SDATAOUT T4 ACZ_SDOUT

IN IN OUT OUT

SATA_A_D2R_N SATA_A_D2R_P

AE3

SATA_A_R2D_C_N

AG2

SATA_A_R2D_C_P

AH2

SATA_C_D2R_N

AF7

SATA_C_D2R_P

AE7

SATA_C_R2D_C_N

AG6

SATA_C_R2D_C_P

AH6

SB_CLK100M_SATA_N SB_CLK100M_SATA_P IN IN

AF1 AE1

SATA_RBIAS_N

AH10

SATA_RBIAS_P

AG10

DD1 DD2

SATA_0RXP

DD3

SATA_0TXN

DD4

SATA_0TXP

SATA_2RXP SATA_2TXN SATA_2TXP

DD5

 A  T  A  S

DD6

 E  D  I

DD7 DD8 DD9 DD10

SATA_CLKN

DD11

SATA_CLKP

DD12

SATARBIASN

DD13

SATARBIASP

DD14 DD15

38 5

B

38 38 38 38 5 38

OUT OUT OUT IN IN IN

IDE_PDIOR_L IDE_PDIOW_L IDE_PDDACK_L IDE_IRQ14 IDE_PDIORDY IDE_PDDREQ

AH25

CPU_DPRSTP_L

NOTE: PULLED UP PER INTEL OUT

5% 1/16W MF-LF 402

OUT

7

CPU_DPSLP_L

OUT

CPU_PWRGD

OUT

7 5

CPU_IGNNE_L

OUT

 2

1

R2199 10K

5% 1/16W MF-LF 2 402

 1

R2110

NOTE: R2110=56 IN CV.

54.9

CHANGED TO 54.9 FOR

MF-LF 402 1/16W 1%

AG26

7

AG24

7

AG22 AG21

60 59

AF22

7 5

AF25

FWH_INIT_L CPU_INIT_L 7 5

AG23

CPU_INTR

7 5

AF23

7 5

CPU_NMI

CPU_SMI_L

CPU_STPCLK_L

CPU_FERR_L

IN

R2100

OUT

NOTE: KEYBOARD CONTROLLER RESET CPU

OUT

=PP1V05_S0_SB_CPU_IO

NOSTUFF

OUT

NOTE: RISING-EDGE TRIGGERED AT CPU

1

0

2

MF-LF 402 1/16W 5%

SMC_RCIN_L

IN

CHANGED TO 54.9 FOR BOM CONSOLIDATION

2

OUT

OUT

AF26

6 21 24 25

C

NOTE: R2108=56 IN CV. 58

1 7 5

BOM CONSOLIDATION

OUT

CPU_RCIN_L

AH24

6 21 24 25

CPU_THERMTRIP_R

R2107 24.9 1

2

R2108

LAYOUT NOTE: R2108 TO BE

54.9

< 2 IN OF R2107 W/O STUB

MF-LF 402 1/16W 1%

59 14 7

PM_THRMTRIP_L

IN

MF-LF 402 1/16W 1%

DD0

SATA_0RXN

SATA_2RXN

TP_CPU_CPUSLP_L 75 7

=PP1V05_S0_SB_CPU_IO

6 21 23

2.2K 2

AH22

TP_SB_SATALED_L AF18 SATALED* AF3

AG27 AF24

STPCLK*

20K PD

1

1

SB_A20GATE

(INT PU)

LAN_CLK (WEAK INT PD)

NOTE:

=PP3V3_S0_SB_GPIO

R2101

EE_SHCLK EE_DOUT

D

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

5% 1/16W MF-LF 2 402

OMIT

U2100 OUT

6 21 23

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

402 MF-LF 1/16W 1%

26

1

PP3V3_S5_SB_RTC

2

26

2

3

4

5

AF15

DIOR* (HSTROBE) AH15 DIOW* (STOP) AF16 DDACK* AH16 IDEIRQ AG16 IORDY (DSTROBE) AE15 DDREQ

DA0 DA1 DA2 DCS1* DCS3*

AB15

38

IDE_PDD<0>

AE14

38

IDE_PDD<1>

AG13

38

IDE_PDD<2>

AF13

IO

38

IDE_PDD<3>

AD14

IO

38

IDE_PDD<4>

AC13

38

IDE_PDD<5>

AD12

38

IDE_PDD<6>

AC12

38

IDE_PDD<7>

AE12

38

IDE_PDD<8>

AF12

38 5

IDE_PDD<9>

AB13

38

IDE_PDD<10>

AC14

38

IDE_PDD<11>

AF14

38

IDE_PDD<12>

AH13

38

IDE_PDD<13>

AH14

38

IDE_PDD<14>

AC15

38

IDE_PDD<15>

AH17 AE17 AF17 AE16 AD16

38

IDE_PDA<0>

38

IDE_PDA<1>

38

IDE_PDA<2>

38

IDE_PDCS1_L

38

IDE_PDCS3_L

IO

LAYOUT NOTE: R2107 TO BE

IO

< 2 IN OF SB

IO IO IO IO

NOTE: DD<7> HAS INTERNAL 11.5K PD

IO IO IO IO IO IO IO IO

B

OUT OUT OUT OUT OUT

NOTE: DDREQ HAS INTERNAL 11.5K PD

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

ACZ_BIT_CLK

SB: 1 OF 4

INTEL HIGH DEFINITION AUDIO

AC ’07

A

SYNC_MASTER=N/A INTERNAL 20K PD ENABLED WHEN

ACZ_RST#

NOTICE OF PROPRIETARY PROPERTY

NONE

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

ACZ_SDIN[0-2]

INTERNAL 20K PD

ACZ_SDOUT

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

SYNC_DATE=N/A

INTERNAL 20K PD ONLY ENABLED IN S3COLD

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

INTERNAL 20K PD

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

ACZ_SYNC

INTERNAL 20K PD

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

21

1

OF

13 110

A

 

8

6

7 6

2

3

4

5

1

=PP3V3_S5_SB_USB

OMIT

R2223 1R2222 1R2226

1 1

R2225 10K

5% 1/16W MF-LF 2 402

1

1

R2250

R2200

10K

10K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

1

1

R2251

R2255 10K

10K

10K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

10K

U2100

10K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

41 5 41 5 41 41

D

47 22

USB_A_OC_L

22

USB_B_OC_L

47 22

USB_C_OC_L

22

USB_D_OC_L

47 22

USB_E_OC_L

53 5 53 5 53 53

54 54 54 54 22 22

SB_GPIO29 SB_GPIO30

22

SB_GPIO31

54 54 54 54

27 6

=PP3V3_S5_SB_IO

54 54 54

2

NOSTUFF

R2205

54

R2207

R2206

10K

MF-LF 1/16W 402 5%

2

2

10K

MF-LF 1/16W 402 5%

1

54

10K

MF-LF 1/16W 402 5%

1

54 54

1

54

PCIE_A_D2R_N

F26

PCIE_A_D2R_P

F25

PCIE_A_R2D_C_N

E28

PCIE_A_R2D_C_P

E27

IN

PCIE_B_D2R_N

H26

IN

PCIE_B_D2R_P

H25

PCIE_B_R2D_C_N

G28

PCIE_B_R2D_C_P

G27

IN

PCIE_C_D2R_N

K26

IN

PCIE_C_D2R_P

K25

PCIE_C_R2D_C_N

J28

PCIE_C_R2D_C_P

J27

IN

PCIE_D_D2R_N

M26

IN

PCIE_D_D2R_P

M25

PCIE_D_R2D_C_N

L28

PCIE_D_R2D_C_P

L27

PCIE_E_D2R_N

P26

PCIE_E_D2R_P

P25

PCIE_E_R2D_C_N

N28

PCIE_E_R2D_C_P

N27

PCIE_F_D2R_N

T25

PCIE_F_D2R_P

T24

PCIE_F_R2D_C_N

R28

PCIE_F_R2D_C_P

R27

IN IN OUT OUT

OUT OUT

OUT OUT

OUT OUT IN IN OUT OUT IN IN OUT OUT

ICH7-M SB

PERN1

DMI0RXN

PERP1

BGA

DMI0RXP

PETN1

(3 OF 6)

DMI0TXN DMI0TXP

PETP1 PERN2

DMI1RXN

PERP2

DMI1RXP

PETN2

DMI1TXN

PETP2

DMI1TXP DMI2RXN

PERN3 PERP3

 P  X

PETN3 PETP3

  E  I  C  P

PERN4 PERP4 PETN4

DMI2RXP

 I  M  D

DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP

PETP4

DMI_CLKN

PERN5

DMI_CLKP

PERP5 PETN5

DMI_ZCOMP

PETP5

DMI_IRCOMP

58

63 58

C

63 58

IO IO IO

IO IO

SPI_SCLK

R2

SPI_CE_L

P6

SPI_ARB

P1

SPI_SI

P5

SPI_SO

P2

47 22

IN 22

USB_A_OC_L

D3

USB_B_OC_L

C4

47 22

USB_C_OC_L

D5

22

USB_D_OC_L

D4

USB_E_OC_L 22 SB_GPIO29

C3

22

SB_GPIO30

A2

22

SB_GPIO31

B3

DMI_N2S_N<0>

14 5

DMI_N2S_P<0>

U28

14 5

DMI_S2N_N<0>

U27

14 5

DMI_S2N_P<0>

Y26

14

DMI_N2S_N<1>

Y25

14

DMI_N2S_P<1>

W28

14

DMI_S2N_N<1>

W27

14

DMI_S2N_P<1>

AB26

14

DMI_N2S_N<2>

AB25

14

DMI_N2S_P<2>

AA28

14

DMI_S2N_N<2>

AA27

14

DMI_S2N_P<2>

AD25

14

DMI_N2S_N<3>

AD24

14

DMI_N2S_P<3>

AC28

14

DMI_S2N_N<3>

AC27

14

DMI_S2N_P<3>

AE28

34 5

SB_CLK100M_DMI_N

AE27

34 5

SB_CLK100M_DMI_P

IN IN OUT OUT IN

D

IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN

USBP0N

PETN6

USBP0P

PETP6

USBP1N

SPI_CLK (INT SPI_ARB (INT

USBP2N

PD)

SPI_CS* PD)

 I  P  S

SPI_MOSI SPI_MISO

USBP2P USBP3N

 B  S  U

USBP3P USBP4N USBP4P USBP5N

OC0*

USBP5P

OC1*

USBP6N

OC2*

USBP6P

OC3*

USBP7N

OC6*/GPIO30

USBRBIAS*

OC7*/GPIO31

USBRBIAS

24 25

R2203

LAYOUT NOTE:

D25

1

PLACE R2203 < 1/2 IN FROM SB

DMI_IRCOMP_R

F1

47

USB_A_N

F2

IO

47

USB_A_P

IO

G4

53

USB_B_N

IO

G3

53

USB_B_P

H1

IO

47

USB_C_N

H2

IO

47

USB_C_P

J4

47

USB_D_N

J3

IO

47

USB_D_P

K1

IO

47

USB_E_N

K2

47

USB_E_P

L4

USB_F_N

L5 M1 M2 N4

USBP7P N3

OC4* OC5*/GPIO29

PP1V5_S0_SB_VCC1_5_B

IN

C25

1/16W

PERP6

E5 47 22

14 5

V25

PERN6

USBP1P 63 58 63 58

V26

USB_F_P

MF-LF

1% 402

EXTERNAL 0

AIRPORT

(MINI-PCIE)

EXTERNAL 1

IO

IO

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

CAMERA

C

EXTERNAL 2

IO IO

CF/SD

IO

47

USB_G_N

IO

47

USB_G_P

IO

47

USB_H_N

47

USB_H_P

BT

IO IO

IR

R2204

D2 D1

24.9 2

USB_RBIAS_PN

1

22.6 2 1% 1/16W MF-LF 402

VOLTAGE=0

LAYOUT NOTE: =PP3V3_S0_SB

PLACE R2204 < 1/2 IN FROM SB 6 25 27

NOTE:

GNT[0-3]# HAVE INT 20K PU ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

OMIT 44 44 44 44 44 44 44 44 44

B

44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44

IO IO IO IO IO IO

PCI_AD<0>

E18

PCI_AD<1>

C18

PCI_AD<2>

A16

PCI_AD<3>

F18

PCI_AD<4>

E16

PCI_AD<5>

A18

PCI_AD<6>

E17

IO

PCI_AD<7>

A17

PCI_AD<8>

A15

IO IO

PCI_AD<9>

C14

IO

PCI_AD<10>

E14

PCI_AD<11>

D14

IO

PCI_AD<12>

B12

PCI_AD<13>

C13

IO

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18> PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29>

AD0 AD1 AD2 AD3 AD4

GNT0*

ICH7-M SB

REQ1*

BGA

GNT1*

(2 OF 6)

REQ2*

AD5

GNT2*

AD6

REQ3*

AD7

GNT3*

AD8

REQ4*/GPIO22

AD9

GNT4*/GPIO48

AD10

GPIO1/REQ5*

AD11

GPIO17/GNT5*

26

E7

PCI_REQ0_L

R2298

IN

10K

TP_PCI_GNT0_L

C16

44 26

PCI_REQ1_L

D16

44

PCI_GNT1_L

26

PCI_REQ2_L

C17 D17

5% 1/16W MF-LF 2 402

IN

1

R2299 10K

5% 1/16W MF-LF 2 402

OUT IN

TP_PCI_GNT2_L

E13

26

F13

PCI_REQ3_L

IN

TP_PCI_GNT3_L

A13

SB_CRT_TVOUT_MUX

A14

IO

NOTE: FWH_WP_L NOT USED

B

TP_PCI_GNT4_L

C8

44

PCI_PME_FW_L

D8

IN

AD13 G15 AD14 G13 AD15 E12 AD16 C11 AD17 D11 AD18 A11 AD19 A10 AD20 F11 AD21 F10 AD22 E9 AD23 D9 AD24 B9 AD25 A8 AD26 A6 AD27 C7 AD28 B6 AD29 E6 AD30 D6 AD31

PCI_AD<30>

44

IO

PCI_AD<31>

44 26

IO

PCI_FRAME_L F16 FRAME*

IO

INT_PIRQA_L

A3

INT_PIRQB_L

B4

INT_PIRQC_L

C5

INT_PIRQD_L

B5

26 26 26 44 26

IO IO IO

TP_SB_XOR_AE5 TP_SB_XOR_AD5 TP_SB_XOR_AG4 TP_SB_XOR_AH4 TP_SB_XOR_AD9

OUT

1

C/BE0* C/BE1*

PCI

C/BE2* C/BE3* IRDY* PAR PCICLK DEVSEL* PERR* PLOCK* SERR* STOP* TRDY* PLTRST* PCIRST*

(INT 20K PU) PME*

B15

44

PCI_C_BE_L<0>

C12

44

PCI_C_BE_L<1>

D12

44

PCI_C_BE_L<2>

C15

44

PCI_C_BE_L<3>

A7

44 26

44 34 5

A12 C9

44 26

PCI_LOCK_L

44 26

PCI_SERR_L

F15

44 26

PCI_STOP_L

F14

44 26

B18 B19

IO IN

26

C26

R2211 1K

5% 1/16W MF-LF 2 402

(STRAPPED TO TOP-BLOCK SWAP MODE IE SB INVERTS A16 FOR ALL CYCLES TARGETING FWH BIOS SPACE)

IO

PCI_PAR

PCI_CLK_SB PCI_PERR_L

B10

STUFF - A16 SWAP OVERRIDE

IO

PCI_DEVSEL_L

44 26

E11

NO STUFF - DEFAULT

IO IO

PCI_IRDY_L

E10 A9

BOM NOTE FOR PD ON PCI_GNT3_L: IO

IO

PLT_RST_L PCI_RST_L

GNT5#

IO

STRAP

IO

INT I/F GPIO2/PIRQE*

PIRQB*

GPIO3/PIRQF*

PIRQC*

GPIO4/PIRQG*

PIRQD*

GPIO5/PIRQH*

IO OUT

11

UNSTUFF

AE5 RSVD0 AD5 RSVD1 AG4 RSVD2 AH4 RSVD3 AD9 RSVD4

MISC

RSVD5 RSVD6

NOTE: CHANGE SYMBOL TO RSVD[1-9]

RSVD7 RSVD8

MCH_SYNC*

TP_PCI_PME_L

26

SB_GPIO2

F7

26

SB_GPIO3

F8

26

SB_GPIO4

26

ODD_PWR_EN_L

PCI

10

UNSTUFF

STUFF

SPI

01

S TU FF

UNSTUFF

NOTE: GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H PU (NOMINAL=20K, SIMULATION=15K-35K)

SB: 2 OF 4

A14 = FWH_TBL_L

SYNC_MASTER=N/A

NOTICE OF PROPRIETARY PROPERTY

IO IO

TP_SB_XOR_AE9

AH8

TP_SB_XOR_AH8

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

IO

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

TP_SB_XOR_AG8

F21

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TP_SB_RSVD9 (AKA TP3, INTERNAL 20K PU) 14

SYNC_DATE=N/A

IO

AE9 AG8

AH20

UNSTUFF

OUT

G8

G7

GNT4# R2210

LPC (DEFAULT)

GNT5# HAS INT

PIRQA*

R2211

IO

PCI_TRDY_L 6

44

SB BOOT BIOS SELECT

IO

NOTE: R2210 WAS PD ON PIN

A

BOOT_LPC_SPI_L

60 58

AD12

IO

44

REQ0*

U2100

1

D7

NB_SB_SYNC_L

SIZE

IN

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

22

1

OF

13 110

A

 

8

6

7

2

3

4

5

1

NOTE FOR R2323 (DEF=NOSTUFF) STRAPPING @ PWROK RISING: SB WILL DISABLE TCO TIMER SYSTEM REBOOT FEATURE

=PP3V3_S0_SB_GPIO

6 21 23

=PP3V3_S5_SB

8 1

1

R2395

R2318

8.2K

10K

D 26 25 23 6

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

=PP3V3_S5_SB

1

R2396 10K

1/16W 402 2 MF-LF 5%

1

1

R2397 8.2K

NOSTUFF

R2327 10K

1/16W 402 2 MF-LF 5%

1

NOSTUFF

R2326 10K

1/16W 402 2 MF-LF 5%

1/16W MF-LF 2 402 5%

1

7

6

6 23 25 26

5

NO_REBOOT_MODE

RP2300

R2323

=PP3V3_S5_SB_PM OMIT

10K

5% 1/16W SM-LF

1K

1/16W 402 2 MF-LF 5%

1

2

3

U2100 ICH7-M SB

4

BGA

1

1

1

27

1

27

R2398

R2320

R2317

R2316

1K 1/16W

10K 1/16W

10K 1/16W

10K 1/16W

402 2 MF-LF 5%

402 2 MF-LF 5%

402 2 MF-LF 5%

402 2 MF-LF 5%

IO IO

(4 OF 6) C22 SMBCLK B22 SMBDATA  B SMB_LINK_ALERT_L A26 LINKALERT*  M B25 SMLINK<0>  S SMLINK0 A25 SMLINK<1> SMLINK1

SMB_CLK SMB_DATA

NOT USED

PM_RI_L

A28 A19

SB_SPKR 67 60 58 58 26 5

14

OUT IN IN

PM_SUS_STAT_L

A27

PM_SYSRST_L

A22

PM_BMBUSY_L SMB_ALERT_L

AB18 B23

NOTE: RESERVED FOR FUTURE 33 33

OUT OUT

PM_STPPCI_L

AC20

PM_STPCPU_L

AF21 A21

SB_GPIO26

67 60 58 44 5

IO

23

BIOS_REC

B21

23

FWH_MFG_MODE

E23 AG18

PM_CLKRUN_L TP_AZ_DOCK_EN_L

C

RESERVED FOR MOBILE AZALIA DOCKING INT’F

53 41 67 60 58

IN IO

58 10 IN

TP_AZ_DOCK_RST_L

AH21

INT_SERIRQ

AF20

PM_THRM_L

IN

VR_PWRGD_CK410

IO

58

IN

SMC_RUNTIME_SCI_L

IN

SMC_EXTSMI_L

U2 F20

PCIE_WAKE_L

26

58

AC19

TP_SB_GPIO6

AD22

AC21 AC18 E21

SUS_STAT*

GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP

CLK14 CLK48 SUSCLK SLP_S3* SLP_S4*

GPIO11/SMBALERT*  O  T

GPIO20/STPCPU*

SLP_S5*

 I  G PWROK  P  N  G  MGPIO16/DPRSLPVR  S  R  Y  W  S  P

GPIO26

TP0/BATLOW*

(INT 20K PU) PWRBTN*

GPIO27

AF19 SB_GPIO21 AH18 SB_GPIO19

GPIO28

LAN_RST*

GPIO32/CLKRUN*

RSMRST*

100 1 100 1

 

100 1

 

 

 2  2

R2302 R2303

 2

R2305

38

AC1 B2 C20

59

34 5

SB_CLK14P3M_TIMER

34 5

SB_CLK48M_USBCTLR

SUS_CLK_SB

PM_SLP_S3_L

D23

77 58

PM_SLP_S4_L

F22

58

PM_SLP_S5_L

AA4

26

PM_SB_PWROK

IN

75 14

PM_DPRSLPVR

OUT

AC22 C21

IN

IN

OUT OUT OUT

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

C23 C19

SATA_C_DET_L

IN

OUT

88 79 77 58 6

B24

PM_PWRBTN_L

IN

PM_LAN_ENABLE

IN

58

58

Y4

SERIRQ THRM* VRMPWRGD

GPIO6 GPIO7

GPIO

GPIO8

PM_BATLOW_L

SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F IN RESET STATE TO SAVE PWR

58

PM_RSMRST_L

R2399 GPIO9 GPIO10

WAKE*

58

E20

58 26

A20

58

DEF=GPI GPIO12 F19 E19 GPIO13 R4 DEF=GPI GPIO14 GPIO15 E22 R3 GPIO24 D20 GPIO25 OD GPIO35 AD21 AD20 GPIO38 AE20 DEF=GPI GPIO39

23

SMS_INT_L

SMC_SB_NMI

PATA_PWR_EN_L

1

IN

2

IDE_RESET_L

IN

C

100K

5% 1/16W 402 MF-LF

IN OUT

58 38

IN

NOTE:

GPIO33/AZ_DOCK_EN* GPIO34/AZ_DOCK_RST*

5% 1/16W 2 MF-LF 402

1/16W 402 2 MF-LF 5%

AH19

AE19 SB_GPIO37 GPIO37/SATA3GP

GPIO0/BM_BUSY*

8.2K

10K

SATA GPIO

SYS_RST*

GPIO18/STPPCI*

D

R2319 R2343

 S  K  L  C

RI* SPKR (INT WEAK PD)

6 11

1

1

SMC_WAKE_SCI_L

IN

OUT

SV_SET_UP 23

60

CRB_SV_DET 23 TP_SB_GPIO25_DO_NOT_USE SB_CLK100M_SATA_OE_L

33

TP_SB_GPIO38

OUT

IO 23

SATA_C_PWR_EN_L OUT

NOTE FOR GPIO25: - HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS - CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

=PP3V3_S5_SB 26 25 23 6

6 23 25 26

=PP3V3_S5_SB 1

R2390

B NOSTUFF

1

10K 2

1/16W 402

HI = PRESENT

10K 2

5% 1/16W MF-LF 2 402

SV_SET_UP IS LINDACARD DETECT

R2306 R2308

B

10K

NOTE: 1

LO = NOT PRESENT

1/16W 402

23

PATA_PWR_EN_L

MF-LF 5%

MF-LF 5%

SV_SET_UP 23

=PP3V3_S0_SB_GPIO

60

6 21 23

CRB_SV_DET 23 1

R2388 10K

1

1

LAYOUT NOTE: PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

10K

1/16W

2 402 MF-LF 5%

26 25 23 6

5% 1/16W MF-LF 2 402

NOSTUFF

R2307 R2309 0

1/16W

23

SATA_C_PWR_EN_L

2 402 MF-LF 5%

=PP3V3_S5_SB 1

A

SB: 3 OF 4

1

R2313

R2310

10K

10K

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

SYNC_MASTER=N/A

FWH_MFG_MODE

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

23

BIOS_REC 23 1

NOSTUFF

R2314 0

1/16W 402 2 MF-LF 5%

1

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

NOSTUFF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

R2311 10K

SIZE

1/16W 402 2 MF-LF 5%

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

OF

13

23   110

1

A

 

8

6

7 OMIT

P24 R18 U14

AD3

U2100 BGA

AB27

AE4

AD11

AE8

B1

AE11

D10

AE13

F4

AE18

B11 B14 B17

VSS

B26 B28

N26

C2

P3

C6

P4

C27

P12

D13

P13

D18

P14

D21

P15

D24

P16

E1

P17

E2

P27

E4

P28

E8 F3

R12

F5

R13

F12

R14

F27

R15

F28

R16

G1

R17

G2

T6

G5

T12

G6

T13 T14

G9 G14

T15

G21

T16

G24

T17

G25

U4

G26

U12

H3

U13

H4

U15

H5

U16

H24

U17

H27

U24

H28

U25

J2

U26

J5

AA22

U18

AD28

V11

D26

V12

D27

V14

D28

V16

E24

V17

E25

V18

H22

VCCA3GP

H23

VCC1_5_B

L22

AC16

N22

VCC3_3

AD13

N23

AD18

P22

AG12

P23

AG15

R22

AG19

R24

G11

W23

M4

Y28

M5

AA1

M12

=PP3V3_S0_SB_VCC3_3

AB7

N16

AE24

AG11

AE25

AG14

AF2

AG17

AF4

AG20

AF8

AG25

AF11

VCCSUS3_3 VCC3_3

25 24 6

25 6

=PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

AD2 AH11

K4 K5 L1

VCC1_5_A

USB VCCSUS3_3

N7

E3

=PP1V5_S0_SB_VCCUSBPLL

C1

VOLTAGE GENERATED INTERNALLY SO NO CONNECT HERE

25

T7

ATX

VCC1_5_A

VCC1_5_A

F17 G17 =PP1V5_S0_SB_VCC1_5_A

6 25

AB8 VCC1_5_A AC8 K7 VCCSAUS1_5

VCCSUS3_3

CHANGE SYMBOL TO 1.05

C28

VOLTAGE GENERATED INTERNALLY

G20

SO NO CONNECT HERE

VCCUSBPLL A1

AA2 Y7

=PP3V3_S5_SB_VCCSUS3_3_USB 6

AB17 VCC1_5_A AC17

AH9 =PP3V3_S5_SB_VCCSUS3_3

L6

M7

AG9

25 6

L3

VCC3_3

AF9

25 24 6

L2

L7 M6 VCCSATAPLL

AC10

AF10

B

K6

ARX

AB9

AE10

D22

K3

AB10

AD10

24 25

D19 G19

AH5 =PP1V5_S0_SB_VCCSATAPLL

25

5 21 25 26

VCCDMIPLL

AG5

25 6

M27

AD1

B27 AG28

PP3V3_S5_SB_RTC

=PP3V3_S5_SB_VCCSUS3_36

C24

Y23

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3_PCI6

A24

Y22

=PP1V5_S0_SB_VCC1_5_A_ARX

W5 P7

W22

Y27

N15

G16 VCCRTC

V23

AF6

N13

G12

V22

25 24 6

D15 F9

U23

25

C10

T28 U22

25 6

B7

T27

M3

N12

VCC3_3

T26

Y24

N11

PCI

T23

AF5

AC9

C

B16

T22

L26

AC5

25

B13

R26

Y3

AC2

=PP3V3_S0_SB_VCC3_3_IDE6

A5

R25

AE6

AC11

CODEC IC’S CONSIDERED SO FAR ARE 3.3V

R23

L25

N6

DEPENDING ON VIO OF AZALIA INTERFACE

AB20

IDE

W26

N5

VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V

6 21 25

AH26

M23

AD6

AB28

=PP1V05_S0_SB_CPU_IO

25

6

AB12

M22

AC7

AB24

=PP3V3_S0_SB_3V3_1V5_VCCHDA 6 =PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

AE26

AA7

L23

L15

M28

V_CPU_IO

K23

L13

N2

25

NOTE:

K22

W25

N1

S0 OR S3 IF NOT

W2

AE23

J23

W24

AB21

S3 IF INTERNAL LAN IS USED

=PP3V3_S0_SB_VCCLAN3_36

V1

VCC3_3/VCCHDA U6 VCCSUS3_3/VCCSUSHDA R7

J22

AC6

AB19

NOTE FOR VCCLAN_3_3:

W7

G23

K28

AB16

VCCLAN_3_3

G22

W6

AB14

VCC PAUX

F24

K27

M24

V5

F23

D

T11 U11

K24

AB11

P18 T18

J26

M16

P11

AD27

J25

AB6

M18

AD26

V28

M15

M11

AC26

V24

M14

L18

VCC1_05

V15

AB4

L17

BGA (5 OF 6)

AC25

V13

AA26

L16

CORE

J24

M13

6 25

L14

AC24

V2

AA25

=PPVCORE_S0_SB

L12

ICH7-M SB

E26

E15

R11

V5REF_SUS

U2100

AC23

B20

N25

V5REF

AB23

AE21

M17 N14

F6

AB22

B8

L24

L11

G10

AA23

AD23

R1

A

PP1V5_S0_SB_VCC1_5_B

AD19

J1

B

25 22

AD15

(6 OF 6)

G18

C

PP5V_S5_SB_V5REF_SUS

AD8

AE2

N18

PP5V_S0_SB_V5REF

25

AD17

AD7

AA24

N17

25

AD4

ICH7-M SB

V27

D

1

OMIT

A4 A23 N24

2

3

4

5

VCCLAN1_5

CHANGE SYMBOL TO 1.05

USB CORE VCC1_5_A

H6

SB: 4 OF 4

H7 J6 J7

SYNC_MASTER=N/A =PP1V5_S0_SB_VCC1_5_A_USB_CORE 6

25

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

AH1

AF27

AH3

AF28 AG1

AH7 AH12

AG3

AH23

AG7

AH27

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC. 0

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY

0

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

24

1

OF

13 110

A

 

8

6

7

=PPVCORE_S0_SB 6 27 22 6

6

24 6

1/16W MF-LF 402 5%

1

D2501 SOT23 VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

D 1

C2503

C2511

10% 16V 2 X5R 402

BAT54E3 3

=PP3V3_S5_SB_VCCSUS3_36

PLACE CAPS AT EDGE OF SB

0.1UF

PP5V_S0_SB_V5REF

PLACE < 2.54MM OF SB ON

SECONDARY OR

3.56MM ON PRIMARY NEAR PIN AG5

C2518

1

0.1UF

10% 16V 2 X5R 402

0

24

1

C2502

1

1UF

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

24 6

C2517

10% 0.1UF 16V 2 X5R 402

PLACEMENT NOTE:

=PP3V3_S0_SB_VCCLAN3_36

1

0

 1

24

=PP3V3_S5_SB_VCCSUS3_3_USB 6

10% 16V 2 X5R 402

PLACE CAP UNDER SB NEAR PINS V1, V5, W2, OR W7 0

1/16W MF-LF 402 5%

25 24 6

BAT54E3

PP5V_S5_SB_V5REF_SUS

C2504 0.1UF

C2513 0.1UF

10% 16V 2 X5R 402

24

PLACEMENT NOTE:

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON

24 6

SECONDARY OR

C2532 0.1UF

10% 16V 2 X5R 402

=PP3V3_S0_SB_3V3_1V5_VCCHDA 0

PLACEMENT NOTE:

1

PLACE < 2.54MM OF SB

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY OR

C2521 0.1UF

10% 16V 2 X5R 402

3.56MM ON PRIMARY NEAR PIN U6

0

C

0 24 6

=PP1V5_S0_SB_VCC1_5_A_ATX 1

C2514 1UF

10% 6.3V 2 CERM 402

=PP1V5_S0_SB_VCC1_5_A

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON

=PP1V5_S0_SB

1

PLACEMENT NOTE:

6 21 24

0

100-OHM-EMI SM-3 1

2

PP1V5_S0_SB_VCC1_5_B

0.1UF

AB8 AND AC8 OF SB

PLACE NEAR PINS AE23, AE26 & AH26

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

C2510

10% 16V 2 X5R 402

PLACE CAPS NEAR PINS PLACEMENT NOTE:

L2500

6 24

SECONDARY OR

3.56MM ON PRIMARY NEAR PIN AG9 =PP1V05_S0_SB_CPU_IO

25 6

24

3.56MM ON PRIMARY NEAR PIN AH11

0

PLACE C2504 < 2.54MM OF PIN F6 OF SB

10% 16V 2 X5R 402

C

K3 ... N7 OF SB 1

1

0.1UF

10% 16V 2 X5R 402

PLACE CAPS NEAR PINS

=PP3V3_S0_SB_VCC3_3

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

3

1

C2533

1

PLACEMENT NOTE:

D2500 SOT23

D

C2519 0.1UF

=PP5V_S5_SB 1

0.1UF

PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD2

=PP3V3_S5_SB

10

C2534

10% 16V 2 X5R 402

0

PLACEMENT NOTE:

R2501

1

10% 16V 2 X5R 402

A24 ... G19 AND P7 OF SB

=PP1V5_S0_SB_VCCSATAPLL 1

 2

C2531 0.1UF

PLACE CAPS NEAR PINS

20% 2 2.5V POLY CASE-C2

0

0

6

1

PLACEMENT NOTE:

C2516 330UF

10% 6.3V 2 CERM 402

PLACE C2503 < 2.54MM OF PIN AD17 OF SB

10% 16V 2 X5R 402

24 25

PLACEMENT NOTE:

PLACEMENT NOTE:

0.1UF

26 23 6

24

PLACEMENT NOTE:

=PP1V5_S0_SB_VCC1_5_A_ARX 1

R2502 100

1

1

=PP3V3_S0_SB

=PP5V_S0_SB 2

2

3

4

5

OF SB 0

22 24

155S0247 1

100-OHM,4A,0805

C2500 220UF

20% 2 2.5V POLY SMB2

1

C2505 1 C2506 1 C2507 0.1UF

10% 16V 2 X5R 402

1

0.1UF

0.1UF

25 24 6

=PP3V3_S5_SB_VCCSUS3_3

10% 16V 2 X5R 402

10% 16V 2 X5R 402

1

C2520 0.1UF

10% 16V 2 X5R 402

0

C2523 0.1UF

10% 16V 2 X5R 402

PLACEMENT NOTE:

1

C2522 0.1UF

10% 16V 2 X5R 402

1

C2524 4.7UF

20% 6.3V 2 CERM 603

PLACE C2520 NEAR PIN E3 OF SB 0

PLACEMENT NOTE:

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

6 24

0

PLACE C2500 & C2505-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY NEAR PINS D28, T28, AD28

=PP3V3_S0_SB_VCC3_3_IDE6

B

24

1

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON 24 6

=PP1V5_S0_SB_VCCUSBPLL

SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AA7 ...

C2515 0.1UF

=PP3V3_S0_SB_VCC3_3 1

C2509

10% 16V 2 X5R 402

PLACEMENT NOTE:

0.1UF

B

10% 16V 2 X5R 402

J7

C2525 0.1UF

AG19

10% 16V 2 X5R 402

1 25 24 6

C2512 0.1UF

SECONDARY OR

3.56MM ON PRIMARY NEAR PINS A1 ... 1

0

PLACEMENT NOTE: 0

PLACE C2520 NEAR PIN C1 OF SB

PLACE C2509 NEAR PIN B27 OF SB

10% 16V 2 X5R 402

0

=PP3V3_S0_SB_VCC3_3_PCI6

0

1

PLACEMENT NOTE: DISTRIBUTE IN PCI SECTION OF SB NEAR PINS A5 ... G16

C2526 0.1UF

10% 16V 2 X5R 402

1

C2527 0.1UF

10% 16V 2 X5R 402

1

24

C2528 0.1UF

10% 16V 2 X5R 402

0 152S0315

1UH,0.5A,20%,1206 25 6

=PP1V5_S0_SB

L2507

0.28-OHM

R2500

A

1

1

2

1/10W 5% MF-LF 603

1206

PP1V5_S0_SB_R

1

SB:DECOUPLING

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM 2

PP1V5_S0_SB_VCCDMIPLL

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

SYNC_MASTER=N/A

PP3V3_S5_SB_RTC 1

C2501 0.01UF

10% 16V 2 CERM 402

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON

1

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY

24

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

5 21 24 26

C2508 10UF

20% 6.3V 2 CERM 805-1

PLACEMENT NOTE: PLACE CAPS NEAR PIN W5 OF SB

SECONDARY SIDE OR 3.56MM ON PRIMARY

1

C2530 0.1UF

10% 16V 2 X5R 402

1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

C2529 0.1UF

10% 16V 2 X5R 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

0

APPLE COMPUTER INC.

0

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

OF

13

25   110

1

A

 

8

6

7 C2608

=PP3V3_S0_SB_PM

15PF 1

2

21

CRITICAL

CERM 50V 402 5%

 Y2600

 1

15PF

21

44 22

0.1UF 1

SB_RTC_X2

 2

2

IN

 1

23

OUT

SOT23-5-LF 4

PM_SB_PWROK

 2

25 24 21 5

44 22

1

 1

MIN_LINE_WIDTH=0.6MM

USE 1.9K

44 22 44 22

75 14 5

VR_PWRGOOD_DELAY

44 22

IN

22

U2601

2

ALL_SYS_PWRGD

77 58

IN

22

3

R2612

44 22

R2622

10K

PP3V3_S5_SB_RTC

44 22

NOTE: ISL6262 SPEC (P 5) SAID TO

1/16W MF-LF 402 5%

44 22

MC74VHC1G08  5

0

R2611 1.8K

20% 10V CERM 402

CERM 50V 402 5%

D

=PP3V3_S0_SB_PCI

1/16W MF-LF 402 5%

1

22

2

22

=PP3V3_S5_SB

1

22

SOT23 3

0

22 22

C2610

1

BAT54E3

44 22

1UF

22

10% 6.3V 2 CERM 402

D2601 1

BAT_2

R2600

SOT23 3

1

BAT54E3 2

R2607

C

22

21

SB_RTC_RST_L

88 76 61 59 41 26 11 10 6

PP3V3_S0

79 77 76 66 65 59 26 11 6 5 83 81 80

OUT

1

DEVELOPMENT

1

PCI_STOP_L

IO

PCI_SERR_L

IO

PCI_DEVSEL_L

IO

PCI_PERR_L

IO IN

PCI_LOCK_L PCI_REQ0_L

IN

PCI_REQ1_L

IN

PCI_REQ2_L

IN

PCI_REQ3_L

R2632 R2631 R2633 R2634

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

1

2

8.2K 8.2K

D

IO

INT_PIRQA_L

IO

INT_PIRQB_L

IO

INT_PIRQC_L

IO

INT_PIRQD_L

IO

SB_GPIO2

IO IO

SB_GPIO3 SB_GPIO4 SB_GPIO5

R2637 R2636 R2638 R2639 R2640 R2642 R2641 R2643

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

1

2

8.2K

PP3V3_S5 5

6 11 26 59 65 66 76 77 79 80 81 83

C2698 0.1UF

20% 10V 2 CERM 402

R2699

SB_SYSRST_4_PVT 1

OUT

SW_RST_BTN_L DEVELOPMENT

SM-LF

5% 1/16W MF-LF 2 402

DEVELOPMENT

MAX6816 2

IN

OUT

SOT143

GND

SPST

1

10K

5% 1/16W MF-LF 2 402

4

VCC

SW2600 0

R2651

10K

5% 1/16W MF-LF 402

U2699

BB1020

1

R2697

10K

SB_SM_INTRUDER_L

2

SM

C2699

20% 10V 2 CERM 402

 

1

0 21

J2600

PCI_TRDY_L

IO

2

DEVELOPMENT

0.1UF

10% 6.3V 2 CERM 402

1

2

PCI_IRDY_L

IO

1

PP3V3_S5

DEVELOPMENT

C2605

1

BAT_1

1

IO

R2623 R2624 R2625 R2626 R2627 R2628 R2630 R2629

MAKE_BASE=TRUE

2

R2606 402 MF-LF 1/16W 5%

ODD_PWR_EN_L

0

1M

1K

22

83 81 80

1UF

2

402 MF-LF 1/16W 5% 1 MIN_LINE_WIDTH=0.6MM

20K

PP3V3_S5

79 77 76 66 65 59 26 11 6 5

22

402 MF-LF 1 / 16 W 5%

MIN_LINE_WIDTH=0.6MM

IO

PCI_FRAME_L

10K

D2600 25 23 6

6

6

C2607

402 MF-LF 1/16W 5%

1

1

OUT

10M

SM-LF  4

2

SB_RTC_X1

R2609

32.768K

C2609 1

2

2

3

4

5

SW_RST_DEBNC

3

1

DEVELOPMENT 1

R2698

1

100K

2

5%

2

5

DEVELOPMENT

DEVELOPMENT

MC74VHC1G08

R2650

U2698

SOT23-5-LF 4 U2698_4

1

1K

2

58 23

58 23 5

PM_SYSRST_L

C

SMS_INT_L

OUT

5% 1/16W MF-LF 402

3

1/16W MF-LF 2 402

3

NOSTUFF

4

R2696 1

RESET 11 7

IN

0

2

5% 1/16W MF-LF 402

XDP_DBRESET_L

NOTE: R2696 CAN’T EXIST WITH BOTH ITP & SHOULD BE STUFFED WITH ITP & NO

DEVELOPMENT

DEVELOPMENT

B

B PP3V3_S0

6 10 11 26 41 59 61 76 88

C2611 0.1UF 1 2 20% 10V CERM 402

U2603

23

OUT

VR_PWRGD_CK410

5

74LVC1G04DBVG4 4

2

75

VR_PWRGD_CK410_L

IN

SOT23-5 3

33

OUT

CK410_PD_VTT_PWRGD_L

SB: MISC

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

0 51 51 -7 -7 14 14 8

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

OF

13

26   110

1

A

 

8

6

7

5

4

3

2

1

SB I2C BUSSES D

D 27 23 27 23

IO

SMB_CLK

IO

SMB_DATA

29 28

MAKE_BASE=TRUE

29 28

=I2C_MEM_SCL

IO

=I2C_MEM_SDA

IO

MAKE_BASE=TRUE

33 33

SMB_CK410_CLK SMB_CK410_DATA

=SMB_AIRPORT_CLK

53

=SMB_AIRPORT_DATA

53

IO IO

IO IO

=PP3V3_S0_SB

C

R2750 R2751

1

2

2.2K

1

2

2.2K

C

=PP3V3_S5_SB_IO

27 23

SMB_CLK

27 23

SMB_DATA

R2719 R2718

6 22 25

6 22

NOSTUFF 1

2

2.2K

1

2

2.2K

NOSTUFF

B

B

SB: SMB HUB

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT

SCALE NONE

8

7

6

5

4

3

2

REV.

0 51 51 -7 -7 14 14 8

D

OF

13

27   110

1

A

 

8

6

7

Page Notes

29 28 5

=PP1V8_S3_MEM

=PP1V8_S3_MEM 1

MEM_VREF

3

C2850

1

C2800

2.2UF

- =PPSPD_S0_MEM (2.5V - 3.3V)

20%

20%

6.3V

10V

603

CERM 402

CERM1 2

Signal aliases required by this page:

1

0.1uF

- =I2C_MEM_SCL - =I2C_MEM_SDA

15

MEM_A_DQ<0>

5

15

MEM_A_DQ<1>

7 9

2 15 5

MEM_A_DQS_N<0>

15 5

MEM_A_DQS_P<0>

11 13 15

BOM options provided by this page:

15

(NONE)

15

MEM_A_DQ<2>

17

MEM_A_DQ<3>

19 21

D

15

MEM_A_DQ<8>

15

MEM_A_DQ<9>

23 25 27

15 5

MEM_A_DQS_N<1>

15 5

MEM_A_DQS_P<1>

29 31 33

15 15

35 37

MEM_A_DQ<10> MEM_A_DQ<11>

39

DDR2 VRef

41

One 0.1uF per connector

15 5

MEM_A_DQ<16>

15

MEM_A_DQ<17>

43 45 47

29 28 6 5

=PP1V8_S3_MEM 1

15 5

MEM_A_DQS_N<2>

49

15 5

MEM_A_DQS_P<2>

51

R2800

53

1K

2

1% 1/16W MF-LF 402

5 28 29

VOLTAGE=0.9V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

C

55

15

MEM_A_DQ<19>

57

15

MEM_A_DQ<24>

61

15 5

MEM_A_DQ<25>

63 65

R2801

15

1K

2

MEM_A_DQ<18>

59

MEM_VREF

1

15

67

MEM_A_DM<3> NC

1% 1/16W MF-LF 402

69 71

15

MEM_A_DQ<26>

15

MEM_A_DQ<27>

73 75 77 79

30 14

MEM_CKE<0>

to drive MCH and DIMM connectors.

30 15

MEM_A_BS<2>

(See Capell Valley pg 47)

30 15

MEM_A_A<12>

89

30 15

MEM_A_A<9>

91

30 15

MEM_A_A<8>

81

Yellow uses 10K divider and TLV2463

NC

83

VREF VSS1 DQ0

CRITICAL

VSS0 DQ4

J2800 F-RT-SM1

DQ1

    D     T      S        M     M     I     D      O      S         2     R     D     D

VSS4 DQS0* DQS0 VSS6 DQ2 DQ3 VSS8 DQ8 DQ9

DQ5 VSS2 DM0 VSS5 DQ6 DQ7 VSS7 DQ12 DQ13 VSS9 DM1

VSS10

VSS11

DQS1*

CK0

DQS1

CK0*

VSS12

VSS13

DQ10

DQ14

DQ11

DQ15

VSS14

VSS15 KEY

VSS16

VSS17

DQ16

DQ20

DQ17

DQ21

VSS18

VSS19

DQS2*

NC0

DQS2

DM2

VSS21

VSS22

DQ18

DQ22

DQ19

DQ23

VSS23

VSS24

DQ24

DQ28

DQ25

DQ29

VSS25

VSS26

DM3

DQS3*

NC1

DQS3

VSS27

VSS28

DQ26

DQ30

DQ27

DQ31

VSS29

VSS30 NC/CKE1

CKE0 VDD0

VDD1

NC2

NC/A15

BA2 VDD2

NC/A14 VDD3

85 87

93 95

30 15

MEM_A_A<5>

97

30 15

MEM_A_A<3>

99

30 15

MEM_A_A<1>

30 15

MEM_A_A<10>

105

30 15

MEM_A_BS<0>

107

MEM_A_WE_L

109

101 103

30 15

111 30 15

MEM_A_CAS_L

30 14

MEM_CS_L<1>

113 115 117

30 14

119

MEM_ODT<1>

121

B

15

MEM_A_DQ<32>

15

MEM_A_DQ<33>

123 125 127

15 5

MEM_A_DQS_N<4>

129

15 5

MEM_A_DQS_P<4>

131 133

15

MEM_A_DQ<34>

15

MEM_A_DQ<35>

15

MEM_A_DQ<40>

15

MEM_A_DQ<41>

135 137 139 141 143 145

15

147

MEM_A_DM<5>

149 151

15

MEM_A_DQ<42>

15

MEM_A_DQ<43>

15

MEM_A_DQ<48>

157

15

MEM_A_DQ<49>

159

153 155

161

NC

163 165

15 5

MEM_A_DQS_N<6>

167

15 5

MEM_A_DQS_P<6>

169 171

15

MEM_A_DQ<50>

173

15

MEM_A_DQ<51>

175

15

MEM_A_DQ<56>

179

15

MEM_A_DQ<57>

181

177

A

183 185

15

MEM_A_DM<7>

15

MEM_A_DQ<58>

189

15 5

MEM_A_DQ<59>

191

=PPSPD_S0_MEM

C2851

1

2.2UF

1

193

0.1uF

20%

6.3V

CERM1 603

C2852 20%

2

10V

CERM 402

2

29 27

=I2C_MEM_SDA

29 27

=I2C_MEM_SCL

195 197 199

A11

A9

A7

A8

A6

VDD4

VDD5

A5

A4

A3

A2

A1

A0

VDD6

VDD7

A10/AP

BA1

BA0

RAS*

WE*

S0*

VDD8

VDD9

CAS*

ODT0

NC/S1*

NC/A13

VDD10

VDD11

NC/ODT1

NC3

VSS31

VSS32

DQ32

DQ36

DQ33

DQ37

VSS33

VSS34

DQS4*

DM4

DQS4

VSS35

VSS36

DQ38

DQ34

DQ39

DQ35

VSS37

VSS38

DQ44

DQ40

DQ45

DQ41

VSS39

VSS40

DQS5*

DM5

DQS5

VSS41

VSS42 DQ46

DQ42

DQ47

DQ43 VSS43

VSS44

DQ48

DQ52

DQ49

DQ53

VSS45

VSS46

NC_TEST

CK1

VSS47

CK1*

DQS6*

VSS48 DM6

DQS6 VSS49

VSS50

DQ50

DQ54 DQ55

DQ51 VSS51

VSS52

DQ56

DQ60 DQ61

DQ57 VSS53

VSS54

DM7

DQS7*

VSS55 DQ58

DQS7 VSS56

DQ59

DQ62

VSS57

DQ63

SDA

7

6

5

VSS58

SCL

SA0

VDDSPD

516S0403

8

2 TABLE_5_HEAD

4

MEM_A_DQ<4>

15

6

MEM_A_DQ<5>

15

MEM_A_DM<0>

15

14

MEM_A_DQ<6>

15

16

PART#

10

 QTY

DESCRIPTION

REFERENCE

DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

5 16S050 3

8

1

DDR2 SODIMM STD CONN

 

J2800

CRITIC AL

12

MEM_A_DQ<7>

5 15

20

MEM_A_DQ<12>

15

22

MEM_A_DQ<13>

15

MEM_A_DM<1>

15

30

MEM_CLK_P<0>

14

32

MEM_CLK_N<0>

14

MEM_A_DQ<14> MEM_A_DQ<15>

15

44

MEM_A_DQ<20>

15

46

MEM_A_DQ<21>

15

18

D

24 26 28

34 36 38

5 15

40 42

48 50

DIMM_OVERTEMP_L

52

29 59

MEM_A_DM<2>

15

56

MEM_A_DQ<22>

15

58

MEM_A_DQ<23>

15

62

MEM_A_DQ<28>

15

64

MEM_A_DQ<29>

15

68

MEM_A_DQS_N<3>

5 15

70

MEM_A_DQS_P<3>

5 15

74

MEM_A_DQ<30>

15

76

MEM_A_DQ<31>

15

MEM_CKE<1>

14 30

54

60

66

72

C

78 80 82 84

TP_MEM_A_A<15>

86

A12

187 29 6

1

5 6 28 29

OMIT

Power aliases required by this page: - =PP1V8_S3_MEM

2

3

4

5 29 28 6 5

GND

 1  2  3  4  5  0  0    0  0  0  2  2  2  2  2

SA1

TP_MEM_A_A<14>

88 90

MEM_A_A<11>

15 30

92

MEM_A_A<7>

15 30

94

MEM_A_A<6>

15 30

DDR2 Bypass Caps (For return current)

96

29 28 6 5

98

MEM_A_A<4>

15 30

100

MEM_A_A<2>

15 30

102

MEM_A_A<0>

15 30

=PP1V8_S3_MEM 1

1

C2801 10UF

106

MEM_A_BS<1>

15 30

108

MEM_A_RAS_L

15 30

110

MEM_CS_L<0>

14 30

MEM_ODT<0>

14 30

MEM_A_A<13>

15 30

1

C2802 10UF

20%

1

20%

6.3V 2 X5R

603

C2804 10UF

20%

6.3V 2 X5R

603

C2803 10UF

20%

6.3V 2 X5R

104

6.3V 2 X5R

603

603

112 114 116

1

C2810

1

0.1uF

118

NC

2

122 124

MEM_A_DQ<36>

15

126

MEM_A_DQ<37>

15

MEM_A_DM<4>

15

134

MEM_A_DQ<38>

15

136

C2811

1

0.1uF

20%

120

2

CERM 402

C2812

1

0.1uF

20%

10V

2

C2813 0.1uF

20%

10V CERM 402

20%

10V

2

CERM 402

10V CERM 402

B

128 1

130

C2814

1

0.1uF

132

MEM_A_DQ<39>

5 15

140

MEM_A_DQ<44>

15

142

MEM_A_DQ<45>

15

MEM_A_DQS_N<5>

5 15

MEM_A_DQS_P<5>

5 15

152

MEM_A_DQ<46>

15

154

C2815

1

0.1uF

20%

2

2

CERM 402

C2816

1

0.1uF

20%

10V

2

C2817 0.1uF

20%

10V CERM 402

20%

10V

2

CERM 402

10V CERM 402

138

1

C2818

1

0.1uF

144

148

2

C2819

1

2

CERM 402

1

10V

2

CERM 402

C2821 0.1uF

20%

20%

10V

C2820 0.1uF

0.1uF

20%

146

20%

10V

2

CERM 402

10V CERM 402

150

MEM_A_DQ<47>

5 15

158

MEM_A_DQ<52>

15

160

MEM_A_DQ<53>

15

164

MEM_CLK_P<1>

14

166

MEM_CLK_N<1>

14

MEM_A_DM<6>

15

156

162

168 170 172 174

MEM_A_DQ<54>

5 15

176

MEM_A_DQ<55>

15

180

MEM_A_DQ<60>

15

182

MEM_A_DQ<61>

15

DDR2 SO-DIMM Connector A

178

S YN C C_ _M MA A ST E ER R =( M MA A ST E ER R)

186

MEM_A_DQS_N<7>

188

MEM_A_DQS_P<7>

190

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

5 15

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

5 15

192

MEM_A_DQ<62>

15

194

MEM_A_DQ<63>

15

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

196 198 200

S YN C C_ _ DA T TE E =( M MA A ST E ER R)

NOTICE OF PROPRIETARY PROPERTY

184

APPLE COMPUTER INC.

ADDR=0xA0(WR)/0xA1(RD)

DRAWING NUMBER

D

SHT

SCALE

ALL NC’S

NONE

4

3

2

REV.

051-7148

13 OF

28

1

110

A

 

8

6

7

Page Notes

28 5

=PP1V8_S3_MEM

=PP1V8_S3_MEM 1

MEM_VREF

3

C2950

- =PP1V8_S3_MEM

1

C2900

2.2UF

- =PPSPD_S0_MEM (2.5V - 3.3V)

20%

6.3V

CERM1 603

Signal aliases required by this page:

20%

10V

2

CERM 402

- =I2C_MEM_SCL - =I2C_MEM_SDA

D

1

0.1uF

15

MEM_B_DQ<0>

5

15

MEM_B_DQ<1>

7 9

2 15 5

MEM_B_DQS_N<0>

15 5

MEM_B_DQS_P<0>

11 13 15

BOM options provided by this page:

15

MEM_B_DQ<2>

(NONE)

15

MEM_B_DQ<3>

17 19 21

NOTE: This page does not supply VREF. The reference voltage must be provided by another page.

15 5

MEM_B_DQ<8>

15

MEM_B_DQ<9>

23 25 27

15 5

MEM_B_DQS_N<1>

15 5

MEM_B_DQS_P<1>

29 31 33

15 15

35 37

MEM_B_DQ<10> MEM_B_DQ<11>

39 41 15

MEM_B_DQ<16>

15

MEM_B_DQ<17>

43 45 47

15 5

MEM_B_DQS_N<2>

49

15 5

MEM_B_DQS_P<2>

51 53

15

MEM_B_DQ<18>

55

15

MEM_B_DQ<19>

57

15

MEM_B_DQ<24>

61

15 5

MEM_B_DQ<25>

63

59

65 15

67

MEM_B_DM<3> NC

69 71

C

15

MEM_B_DQ<26>

15

MEM_B_DQ<27>

73 75 77

30 14

MEM_CKE<2>

30 15

MEM_B_BS<2>

79 81

NC

83

VREF VSS1 DQ0

VSS0

CRITICAL

DQ4

J2900 F-RT-SM1

DQ1

    V     E     R        M     M     I     D      O      S         2     R     D     D

VSS4 DQS0* DQS0 VSS6 DQ2 DQ3 VSS8 DQ8 DQ9

DQ5 VSS2 DM0 VSS5 DQ6 DQ7 VSS7 DQ12 DQ13 VSS9 DM1

VSS10

VSS11

DQS1*

CK0

DQS1

CK0*

VSS12

VSS13

DQ10

DQ14

DQ11

DQ15

VSS14

VSS15 KEY

VSS16

VSS17

DQ16

DQ20

DQ17

DQ21

VSS18

VSS19

DQS2*

NC0

DQS2

DM2

VSS21

VSS22

DQ18

DQ22

DQ19

DQ23

VSS23

VSS24

DQ24

DQ28

DQ25

DQ29

VSS25

VSS26

DM3

DQS3*

NC1

DQS3

VSS27

VSS28

DQ26

DQ30

DQ27

DQ31

VSS29

VSS30 NC/CKE1

CKE0 VDD0

VDD1

NC2

NC/A15

BA2 VDD2

NC/A14 VDD3

85 87

30 15

MEM_B_A<12>

89

30 15

MEM_B_A<9>

91

30 15

MEM_B_A<8>

93 95

30 15

MEM_B_A<5>

97

30 15

MEM_B_A<3>

99

30 15

MEM_B_A<1>

30 15

MEM_B_A<10>

105

30 15

MEM_B_BS<0>

107

MEM_B_WE_L

109

101 103

30 15

111 30 15

MEM_B_CAS_L

30 14

MEM_CS_L<3>

30 14

MEM_ODT<3>

113 115 117 119 121

B

15

MEM_B_DQ<32>

15

MEM_B_DQ<33>

123 125 127

15 5

MEM_B_DQS_N<4>

15 5

MEM_B_DQS_P<4>

129 131 133

15

MEM_B_DQ<34>

15

MEM_B_DQ<35>

15

MEM_B_DQ<40>

15

MEM_B_DQ<41>

15

MEM_B_DM<5>

135 137 139 141 143 145 147 149

15

MEM_B_DQ<42>

151

15

MEM_B_DQ<43>

153

15 5

MEM_B_DQ<48>

15

MEM_B_DQ<49>

155 157 159 161

NC

163 165

15 5

MEM_B_DQS_N<6>

167

15 5

MEM_B_DQS_P<6>

169 171

15

MEM_B_DQ<50>

173

15

MEM_B_DQ<51>

175

15

MEM_B_DQ<56>

179

15

MEM_B_DQ<57>

181

177

A

183 185

=PPSPD_S0_MEM

15

MEM_B_DM<7>

15

MEM_B_DQ<58>

189

15

MEM_B_DQ<59>

191

C2951

1

2.2UF

1

193

0.1uF

20%

6.3V

CERM1 603

C2952 20%

2

10V

CERM 402

2

28 27

=I2C_MEM_SDA

28 27

=I2C_MEM_SCL

195 197 199

A11

A9

A7

A8

A6

VDD4

VDD5

A5

A4

A3

A2

A1

A0

VDD6

VDD7

A10/AP

BA1

BA0

RAS*

WE*

S0*

VDD8

VDD9

CAS*

ODT0

NC/S1*

NC/A13

VDD10

VDD11

NC/ODT1

NC3

VSS31

VSS32

DQ32

DQ36

DQ33

DQ37

VSS33

VSS34

DQS4*

DM4

DQS4

VSS35

VSS36

DQ38

DQ34

DQ39

DQ35

VSS37

VSS38

DQ44

DQ40

DQ45

DQ41

VSS39

VSS40

DQS5*

DM5

DQS5

VSS41

VSS42

DQ42

DQ46

DQ43

DQ47

VSS43

VSS44

DQ48

DQ52

DQ49

DQ53

VSS45

VSS46

NC_TEST

CK1

VSS47

CK1*

DQS6*

VSS48 DM6

DQS6 VSS49

VSS50

DQ50

DQ54 DQ55

DQ51 VSS51

VSS52

DQ56

DQ60 DQ61

DQ57 VSS53

VSS54

DM7

DQS7*

VSS55 DQ58

DQS7 VSS56

DQ59

DQ62

VSS57

DQ63

SDA

7

6

5

VSS58

SCL

SA0

VDDSPD

516S0404

8

2

TABLE_5_HEAD

P A RT #

4

MEM_B_DQ<4>

15

6

MEM_B_DQ<5>

15

MEM_B_DM<0>

15

QTY

D ES CR I PT IO N

REFERENCE

DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

516S0504

1

DDR2 SODIMM REV CONN

 

 

J2900

CRITICAL

8 10 12 14

MEM_B_DQ<6>

16

MEM_B_DQ<7>

15

MEM_B_DQ<12>

15

5 15

18 20 22

MEM_B_DQ<13>

15

MEM_B_DM<1>

15

30

MEM_CLK_P<3>

14

32

MEM_CLK_N<3>

14

D

24 26 28

34 36 38

MEM_B_DQ<14> MEM_B_DQ<15>

15 15

40 42 44

MEM_B_DQ<20>

15

46

MEM_B_DQ<21>

15

48 50

DIMM_OVERTEMP_L

52

28 59

MEM_B_DM<2>

15

56

MEM_B_DQ<22>

15

58

MEM_B_DQ<23>

5 15

62

MEM_B_DQ<28>

15

64

MEM_B_DQ<29>

15

68

MEM_B_DQS_N<3>

5 15

70

54

60

66

MEM_B_DQS_P<3>

5 15

74

MEM_B_DQ<30>

15

76

MEM_B_DQ<31>

15

MEM_CKE<3>

14 30

72

C

78 80 82 84

TP_MEM_B_A<15>

5

86

A12

187 29 28 6

1

5 6 28 29

OMIT

Power aliases required by this page:

2

3

4

5 29 28 6 5

GND

 1  2  3  4  5  0  0  0  0  0  2  2  2  2  2

SA1

TP_MEM_B_A<14>

5

90

MEM_B_A<11>

15 30

92

MEM_B_A<7>

15 30

94

MEM_B_A<6>

15 30

88

DDR2 Bypass Caps (For return current)

96

29 28 6 5

98

MEM_B_A<4>

15 30

100

MEM_B_A<2>

15 30

102

MEM_B_A<0>

15 30

106

MEM_B_BS<1>

15 30

108

MEM_B_RAS_L

15 30

110

MEM_CS_L<2>

14 30

MEM_ODT<2>

14 30

MEM_B_A<13>

15 30

=PP1V8_S3_MEM

1

C2908

1

1UF

104

C2909

1

1

10% 402

402

402

C2911

6.3V 2 CERM

6.3V 2 CERM

6.3V 2 CERM

CERM 402

1UF

10%

10%

6.3V

C2910 1UF

1UF

10%

2

112 114 116

1

C2912

122

MEM_B_DQ<36>

15

126

MEM_B_DQ<37>

15

C2914

1

C2915 1UF

10%

10%

6.3V 2 CERM

6.3V 2 CERM

402

402

402

124

1

1UF

10%

6.3V 2 CERM

6.3V 2 CERM

NC

C2913 1UF

10%

120

1

1UF

118

402

B

128 130

MEM_B_DM<4>

15

134

MEM_B_DQ<38>

5 15

136

MEM_B_DQ<39>

15

1

C2916

1

1UF

132

C2917

1

1UF

10%

1

10%

6.3V 2 CERM

402

C2919 1UF

10%

6.3V 2 CERM

402

C2918 1UF

10%

6.3V 2 CERM

6.3V 2 CERM

402

402

138 140

MEM_B_DQ<44>

5 15

142

MEM_B_DQ<45>

15

146

MEM_B_DQS_N<5>

5 15

148

MEM_B_DQS_P<5>

5 15

1

144

C2920

1

1UF 10%

6.3V 2 CERM

150 152

MEM_B_DQ<46>

15

154

MEM_B_DQ<47>

15

158

MEM_B_DQ<52>

15

160

C2921 1UF

1

C2922

1

1UF

10%

10%

6.3V 2 CERM

402

6.3V 2 CERM

402

C2923 1UF 10%

6.3V 2 CERM

402

402

156

MEM_B_DQ<53>

15

164

MEM_CLK_P<2>

14

166

MEM_CLK_N<2>

14

MEM_B_DM<6>

15

174

MEM_B_DQ<54>

15

176

MEM_B_DQ<55>

15

180

MEM_B_DQ<60>

15

182

MEM_B_DQ<61>

15

162

168 170 172

DDR2 SO-DIMM Connector B

178

S YN C C_ _M MA A ST E ER R =( M MA A ST E ER R)

186

MEM_B_DQS_N<7>

188

MEM_B_DQS_P<7>

190

=PPSPD_S0_MEM

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

6 28 29

5 15

5 15

1

MEM_B_DQ<62>

5 15

194

MEM_B_DQ<63>

15

196

2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

R2900 10K

192

Resistor prevents pwr-gnd short

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5% 1/16W MF-LF 402

SIZE

ADDR=0XA4(WR)/0XA5(RD)

198 200

S YN C C_ _ DA T TE E =( M MA A ST E ER R)

NOTICE OF PROPRIETARY PROPERTY

184

APPLE COMPUTER INC.

MEM_B_SPD_SA1

DRAWING NUMBER

D

SHT

SCALE

ALL NC’S

NONE

4

3

2

REV.

051-7148

13 OF

29

1

110

A

 

8

7

6

3

4

5

2

1

One cap for each side of every RPAK, one cap for every two discrete resistors BOMOPTION shown at the top of each group applies to every part below it

6

29 28 14

IN

MEM_CS_L<3..0> 0 1 2 3

RP3000 R3001 RP3001 RP3002

56 56 56

=PP0V9_S0_MEM_TERM

3 1  

56

6 5%

2

2

7

4

5

5%

1/16W SM-LF 1/16W SM-LF

D 29 28 14

IN

MEM_CKE<3..0> 0 1 2 3

RP3003 RP3004 RP3005 RP3006

56

1

8

56

1

8

56

1

8

56

1

8

1/16W SM-LF

1/16W MF-LF 402 5% 5%

5% 1/16W SM-LF 1/16W  SM-LF 5%

1/16W   SM-LF

IN

MEM_ODT<3..0> 0 1 2 3

28 15

IN

MEM_A_A<13..0> 0 1 2 3 4 5 6 7 8 9

C

10 11 12 13

RP3000 R3009 RP3001 R3011

RP3007 RP3008 RP3007 RP3008 RP3007 RP3008 RP3007 RP3004 RP3008 RP3003 RP3009 RP3004 RP3003 R3025

4

56 56 56

1

56

1

5% 6

5%

56

4  

5

56

4

5

56

3

6

56

3

6

56

2

7

2

1/16W   SM-LF

5%

1/16W   SM-LF

0.1uF 2

IN

MEM_A_BS<2..0> 0 1 2

RP3009 RP3000 RP3003

20% 10V CERM 402

1

20% 10V CERM 402

C3030 20% 10V CERM 402

1/16W   SM-LF

5% 1/16W SM-LF

56

4

5

5%

1/16W   SM-LF

56

1

8

5%

1/16W   SM-LF

56

3

6

5%

1/16W   SM-LF

1

C3033 0.1uF

2

20% 10V CERM 402

C

5% 1/16W SM-LF

6

5%

2

1/16W   SM-LF

1

5% 1/16W MF-LF 402

2

C3011 0.1uF

2

0.1uF 2

5% 1/16W SM-LF

5 8

56

20% 10V CERM 402

5% 1/16W SM-LF 5%

8

4

3

C3010

C3035 0.1uF

2

28 15

C3007

5%   1/16W SM-LF

1

1

20% 10V CERM 402

0.1uF 2

1

5%

56

56

1

5% 1/16W SM-LF

7

1

1/16W SM-LF

1/16W SM-LF

1/16W MF-LF 402

56

56

2

1/16W MF-LF 402 5%

2 5%

56

1

5 2

3

56

C3005 0.1uF

5% 1/16W SM-LF 5% 1/16W SM-LF

29 28 14

D 1

20% 10V CERM 402

7

56

1

8

56

2

7

5% 1/16W SM-LF 5%

1/16W SM-LF

5% 1/16W SM-LF

28 15

IN

MEM_A_RAS_L

28 15

IN

MEM_A_CAS_L

28 15

IN

MEM_A_WE_L

B

RP3000 RP3009 RP3009

29 15

IN

MEM_B_A<0>

29 15

IN

MEM_B_A<3>

29 15

IN

MEM_B_A<2>

29 15

IN

MEM_B_A<10>

29 15

IN

29 15

IN

MEM_B_A<5>

29 15

IN

MEM_B_A<6>

29 15

IN

29 15 29 15 29 15

RP3011 RP3010 RP3011 R3035 RP3011 RP3010

MEM_B_A<4>

RP3006 RP3006 RP3010 RP3005 RP3010 RP3006 RP3005 RP3001

MEM_B_A<7>

IN

MEM_B_A<8>

IN

MEM_B_A<9>

IN

MEM_B_A<1>

29 15

IN

MEM_B_A<11>

29 15

IN

MEM_B_A<12>

29 15

IN

MEM_B_A<13>

56

2

7

56

4

5

56

3

6

56

3

56

6

2 1

1/16W   SM-LF

5%

1/16W   SM-LF

5% 8

B

5% 1/16W SM-LF

7 2

1

1/16W SM-LF 1/16W   SM-LF

5%

6

3

56 56 56

5% 5%

5%

1/16W   SM-LF

1/16W MF-LF 402

56

2

7

5% 1/16W SM-LF

56 56

4

5

3

6

5% 5%

1/16W   SM-LF 1/16W   SM-LF

56

1

8

5%

1/16W   SM-LF

56

4

5

5% 1/16W SM-LF

56

4

5

56

2

7

56

3

6

56

4

5

5%

1/16W   SM-LF

5%

1/16W   SM-LF

1

IN

MEM_B_BS<2..0> 0 1 2

RP3002 RP3011 RP3005

1/16W   SM-LF

5%

1/16W SM-LF

56

1

8

56

4

5

5%

56

2

7

5% 1/16W SM-LF

1/16W SM-LF

5% 1/16W SM-LF

A

29 15

IN

29 15

IN

29 15

IN

RP3001 RP3002 RP3002

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

56

1

8

56

3

6

56

2

7

20% 10V CERM 402

1

C3006 0.1uF

2

20% 10V CERM 402

5% 1/16W SM-LF 5%

1

C3009

1

1

20% 10V CERM 402

C3008 0.1uF

0.1uF 2

29 15

C3004 0.1uF

2

2

20% 10V CERM 402

C3013 0.1uF

2

20% 10V CERM 402

Memory Active Termination 5%

1/16W SM-LF

5%

1/16W SM-LF

5%

1/16W SM-LF

1

2

C3014

1

C3015

0.1uF

0.1uF

20% 10V CERM 402

20% 10V CERM 402

2

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D

SHT

SCALE NONE

8

7

6

5

4

3

2

REV.

051-7148

13 OF

30

1

110

 

8

6

7

3

4

5

2

1

Page Notes Power aliases required by this page: - =PP5V_S0_MEMVTT - =PP1V8_S0_MEMVTT - =PP0V9_S0_MEMVTT_LDO Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)

D

D

DDR2 Vtt Regulator

6

=PP5V_S0_MEMVTT

MEMVTT_EN_PU

1

R3100 1

C

6

C3100 1uF

1K 5% 1/16W MF-LF 402

2

10% 6.3V CERM 402

2

C

R3101

=PP1V8_S0_MEMVTT

1

220

5% 1/16W MF-LF 402

2

U3100_VDDQ

C3109

1

2.2UF 10% 6.3V CERM1 603

2

5

6

VDDQ

 

VCC

U3100 BD3533FVM MSOP-8

79

C3101

1

20% 10V CERM 402

2

7

VTT_IN

2

EN

VREF

If power inputs are not S0, 2

MEMVTT_EN can be used to disable MEMVTT in sleep.

4

MEMVTT_VREF

CRITICAL

1

0.1UF

10UF 20% 6.3V CERM 805-1

C3110

MEMVTT_EN

VTTS

3

C3102

VTT

8

10UF 20% 6.3V CERM 805-1

GND

1

2

1

?Can 5V be S0 if 1V8 is S3? =PP0V9_S0_MEMVTT_LDO

6

CRITICAL

C3105 150UF 20% 6.3V POLY SMC-LF

B

B

Memory Vtt Supply

A

S YN C C_ _M MA A ST E ER R =( M MA A ST E ER R)

S YN C C_ _ DA T TE E =( M MA A ST E ER R)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D

SHT

SCALE NONE

8

7

6

5

4

3

2

REV.

051-7148

13 OF

31

1

110

A

 

8

6

7

1

1

FERR-120-OHM-1.5A 1

2

10UF

2

1

6 33 34

C3310 1UF

20% 6.3V 2 CERM 805-1

10% 16V 2 X5R 402

=PP3V3_S0_CK410

0402-LF

5% 1/16W MF-LF 402

C3308 1 C3309 0.1UF

2.2

1

L3302

R3302 PP3V3_S0_CK410_VDD48

2

3

4

5

10% 6.3V 2 CERM 402

D

D L3301

FERR-120-OHM-1.5A 34 33 6

1

=PP3V3_S0_CK410

2

PP3V3_S0_CK410_VDD_CPU_SRC

PP3V3_S0_CK410_VDD_PCI

0402-LF 1

C3314

1

C3316 1 C3315 1 C3301 1 C3302 1 C3303 1 C3304 10UF

1UF

0.1UF 10%

20% 6.3V 2 CERM 805-1

10% 6.3V 2 CERM 402

16V

16V

0.1UF 10%

16V

16V

2 X5R

1

0.1UF 10%

0.1UF 10%

16V

16V

2 X5R

2 X5R

402

402

C3305 1 C3306 1 C3317 0.1UF 10%

16V

2 X5R

2 X5R

402

402

402

0.1UF 10%

0.1UF 10% 2 X5R

2 X5R

402

402

R3303

R3304 1

2.2

PP3V3_S0_CK410_VDDA

2

5% 1/16W MF-LF 402

1

PP3V3_S0_CK410_VDD_REF

C3312 1 C3311 10UF

20% 6.3V 2 CERM 805-1

1

0.1UF

Y3301

 3      8      4     D     D     V

2

5X3.2-SM

C

C3389 18PF

5% 50V 2 CERM 402

1

C3390

(PORT80 LPC 33MHZ)

34 34

OUT OUT

 

     0      C     R      S _     D     D     V

QFN

     1      C     R      S _     D     D     V

     2      C     R      S _     D     D     V

(EACH POWER PIN PLACED ONE 0.1UF) (PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

     3      C     R      S _     D     D     V

C

IN

CK410_FSB_TEST_MODE

CK410_PCI1_CLK CK410_PCI2_CLK CK410_PCI3_CLK OUT CK410_PCI4_CLK 34 OUT CK410_PCI5_FCTSEL1 (INT PD)

(FW PCI 33MHZ) (TPM LPC 33MHZ) (SMC LPC 33MHZ) (NOT USED) IO

34

34 34

VSSA

51

XIN

8

FSB

23

55 (INT PU)

23

CPUC0

44

34

CPUT0

45

34

CPUC1

41

34

CPUT1

42

34

CPUC2_ITP/SRCC_10 36

34

CPUT2_ITP/SRCT_10 37

34

SRCC_0/LCD100MC

57

OUT

58

PCI2

63

PCI3

64

PCI4

65

PCI5/FCTSEL1

68

PCIF0/ITP_SEL

1

56 (INT PU)

CPU_STP*

XOUT

OUT

34

PCI_STP*

OMIT

VDDA

39

50

CK410_PCIF0_CLK CK410_PCIF1_ITP_EN

(ICH7M PCI 33MHZ)

     2      7      8      5      1      1      2      3

    F     E     R _     D     D     V

U3301

34

5% 1/16W MF-LF 2402

     9      4

     0      1     I     I      C      C     P     P _ _     D     D     D     D     V     V

CY284455

=PP3V3_S0_CK410

R3301 10K

     1      7      6      6

    U     P      C _     D     D     V

5% 50V 2 CERM 402

38

1

     3      4

18PF

CK410_XTAL_IN CK410_XTAL_OUT

34 33 6

2

5% 1/16W MF-LF 402

10% 16V 2 X5R 402

CRITICAL

1

1

1

C3307 0.1UF

10% 16V 2 X5R 402

14.31818 1

10UF

20% 6.3V 2 CERM 805-1

PCI1

11

34 34

SRCC_1

14

SRCT_1

13

PCIF1

9

IN IN

CK410_CPU0_N CK410_CPU0_P

OUT

CK410_CPU1_N CK410_CPU1_P

OUT

OUT

OUT

CK410_CPU2_ITP_SRC10_N OUT CK410_CPU2_ITP_SRC10_P OUT

SRCT_0/LCD100MT 10

(INT PU) CLKREQ_1*

PM_STPPCI_L   PM_STPCPU_L

34

CK410_LVDS_N CK410_LVDS_P

34 CK410_SRC1_N 34 CK410_SRC1_P CK410_SRC_CLKREQ1_L

SRCC_2

16

34

SRCT_2

15

34

SRCC_3

19

CK410_SRC2_N CK410_SRC2_P

(FROM ICH7 GPIO18 STPPCI* ) (FROM ICH7 GPIO20 STPCPU* ) (CPU HOST 133/167MHZ) (GMCH HOST 133/167MHZ) (ITP HOST 133/167MHZ)

OUT OUT OUT

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ) (GPU PCI-E 100 MHZ )

OUT IN OUT OUT

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO? (ICH7M DMI 100 MHZ )

(PULL UP PIN 68 TO ENABLE ITP HOST CLK) (ICH SM BUS)

27 27

IN IO

SMB_CK410_CLK SMB_CK410_DATA CK410_IREF

B

47

SCLK

48

SDATA

40

IREF

5

VSS48

SRCT_3

18

(INT PU) CLKREQ_3*

59

SRCC_4

22

34

34 CK410_SRC3_N 34 CK410_SRC3_P CK410_SRC_CLKREQ3_L

34

SRCT_4

21

(INT PU) CLKREQ_4*

20

SRCC_5

24

34

SRCT_5

23

34

(INT PU) CLKREQ_5*

60

SRCC_6

27

34 23

SB_CLK100M_SATA_OE_L

1

R3300 475

1% 1/16W MF-LF 2 402

46

VSS_CPU

62

VSS_PCI0

66

VSS_PCI1

52

VSS_REF

31

VSS_SRC

69

14

26 25

SRCC_7

30

34

SRCT_7

29

34

SRCC_8

32

SRCT_8

33

(INT PU) CLKREQ_8*

34

THRML_PAD

CLK_NB_OE_L

CK410_SRC7_N CK410_SRC7_P

CK410_SRC8_N CK410_SRC8_P CK410_SRC_CLKREQ8_L 34 34

34

DOT96C/27MHZ_SPREAD 7

34

DOT96T/27MHZ_NON-SPREAD 6

34

OUT

26

4

34

REF0/FSC

54

34

(INT PD) REF1/FCTSEL0

53

34

CK410_PD_VTT_PWRGD_L CK410_USB48_FSA CK410_CLK14P3M_TIMER CK410_REF1_FCTSEL0

(FOR PCI-E CARD)

IN

OUT OUT IN

OUT OUT IN OUT OUT

(ICH SATA 100 MHZ)

B

(FROM ICH7 GPIO35)

(GMCH G_CLKIN 100 MHZ ) (FROM GMCH CLK_REQ*)

(WIRELESS PCI-E 100 MHZ )

IN OUT

(NOT USED )

OUT OUT

(GIGA LAN PCI-E 100 MHZ )

OUT IN

CK410_DOT96_27M_SPREAD_N CK410_DOT96_27M_NONSPREAD_P

(INT PD) VTT_PWRGD*/PD 2 FSA/48M

CK410_SRC5_N CK410_SRC5_P

34 CK410_SRC6_N 34 CK410_SRC6_P CK410_SRC_CLKREQ6_L

SRCT_6 (INT PU) CLKREQ_6*

53

CK410_SRC4_N CK410_SRC4_P

OUT

IN OUT OUT

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

OUT OUT

(FROM CPU VCORE PWR GOOD) (ICH7M USB 48MHZ) (ICH7M,SIO,LPC REF. 14.318MHZ)

IO

CLOCKS

A

FCTSEL1

FCTSEL0

PIN 6

P IN 7

P IN 1 0

SYNC_MASTER=CLOCK

P IN 1 1

0

0

DOT96T

DOT96C

100MT_SST

100MC_SST

0

1

DOT96T

DOT96C

SRCT0

SRCC0

1 1

0 1

SPREAD

SPREAD

OFF LOW

TBD

SRCT0 SRCT0

SRCC0 SRCC0

27M NON

SYNC_DATE=06/03/2005

NOTICE OF PROPRIETARY PROPERTY

* FOR INT. GRAPHIC SYSTEM

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

27M

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

* FOR EXT. GRAPHIC SYSTEM

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D

SHT

SCALE NONE

8

7

6

5

4

3

2

REV.

051- 7148

13 OF

33

1

110

A

 

8

6

7

NOTE: USE THESE PULL-DOWNS IF NOT CONNECTED TO

33

CK410_SRC_CLKREQ1_L (GPU CLK OE*)

33

CK410_SRC_CLKREQ3_L (SPARE CLK OE*)

33

CK410_SRC_CLKREQ8_L (YUKON CLK OE*)

D

R3495

1

R3494

1

2

1

2

1

6 33

1K

2

R3493

=PP3V3_S0_CK410

GPIO’S

2

3

4

5

1K 33

IO

CK410_PCI5_FCTSEL1

R3499

1

1/16W

1K

2

5%

1K

33 33

MF-LF 402

33 33

R3497 1

2.2K 2

IN IN IN IN

CK410_SRC3_P CK410_SRC3_N CK410_SRC7_P CK410_SRC7_N

33 33

1 1

 

33 33

1

 

1

 

 

       

2 2 2 2

R3492 R3491 R3490 R3489

SPARE_SRC3_P

R3488

SPARE_SRC3_N

 R3487

SPARE_SRC7_P

R3486 R3485

SPARE_SRC7_N

 

1

2

1

2

1

2

1

2

49.9 49.9 49.9 49.9

D

CK410_FSC 34

5% 1/16W MF-LF 402

33 33

33

IN

CK410_CLK14P3M_TIMER

IN

CK410_REF1_FCTSEL0

1 R3498 1 /1 6W 5 %

R3496

2 MF-LF 4 02

1

2

SB_CLK14P3M_TIMER OUT

33

5 23

TP_CLK14P3M_SPARE OUT

R3451 1

2.2K 2

34 12 5

FSB_CLK_NB_P

34 12 5

FSB_CLK_NB_N

CK410_FSA 34

5% 1/16W MF-LF 402

34 7 5

FSB_CLK_CPU_P

34 7 5

FSB_CLK_CPU_N

34

FSB_CLK_XDP_P

34

FSB_CLK_XDP_N

FSB FREQUENCY SELECT: 33

NO STUFF

STUFF

C

CPU DRIVEN

R3454 R3459 R3463

R3452 R3457 R3461

533MHZ

R3452 R3457 R3461

R3454 R3459 R3463

R3452

R3454 R3459 R3463

(133MHZ CPU CLK)

667MHZ

(166MHZ CPU CLK)

 

R3461

33

33

33

NOSTUFF

33

R3452 56

R3453 1 1 / 1 6W 34

1K 5%

2

2

1

33

5% 1/16W MF-LF 402

5 23

IN

CK410_PCI4_CLK

IN

CK410_PCI3_CLK

IN

CK410_PCI2_CLK

IN

CK410_PCI1_CLK

R3406

1

R3405

2

1

2

1

2

1

2

33

TP_PCI_CLK_SPARE OUT

R3404 R3403

33

33

IN IN

CK410_PCIF1_ITP_EN CK410_PCIF0_CLK

R3401 R3402

1 1

2  

2

33 33

58

PCI_CLK_TPM OUT

67

PCI_CLK_FW OUT

44

PCI_CLK_PORT80 OUT

AIRPORT_CLK100M_PCIE_P

53 34

AIRPORT_CLK100M_PCIE_N

2

2

1

R3433 R3434

1

2

1

2

1

2

R3435 R3436

2

1

2

49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9

C

5

PCI_CLK_SMC OUT

PCI_CLK_SB OUT

53 34

2

1

1

R3431 R3432

5 22

34 14 5

NB_CLK100M_GCLKIN_P

34 14 5

NB_CLK100M_GCLKIN_N

34 21 5

SB_CLK100M_SATA_P

34 21 5

SB_CLK100M_SATA_N

34 22 5

SB_CLK100M_DMI_P

34 22 5

SB_CLK100M_DMI_N

41 34 5

ENET_CLK100M_PCIE_P

41 34 5

ENET_CLK100M_PCIE_N

84 34 5

GPU_CLK100M_PCIE_P

84 34 5

GPU_CLK100M_PCIE_N

R3438 R3437

1

 

2

1

R3439 R3440 R3442 R3441

2

1

2

1

1

R3443 R3444

2

 

2

1

2

1

2

1

2

49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9

60

R3446 R3445

1

 

2

1

2

49.9 49.9

0

2 5%

5% 1/16W MF-LF 2 402

M F -L F 4 0 2

33 33

CPU_BSEL<0>

33 33

B

33 33 81 34 6

R3456

1 1/16W

1K 5%

33

NOSTUFF

CK410_CPU1_P

IN

CK410_CPU1_N

IN

CK410_CPU0_P

IN

CK410_CPU0_N

IN

CK410_CPU2_ITP_SRC10_P

IN

CK410_CPU2_ITP_SRC10_N

R3457

33

0

33

5% 1/16W MF-LF 2 402

2

33

33

MF-LF 402

CK410_FSB_TEST_MODE

1 1

 

1

 

1

 

1

 

33 33

1

   

 2  2  2  2

R3407 R3408 R3409 R3410

 2  2

R3411 R3412

CK410_SRC6_P

33

1

IN

CK410_SRC6_N

33 33 33

1

 

1

 

33 33

1

 

1

 

1

 

IN IN IN

CK410_SRC5_P CK410_SRC5_N CK410_SRC4_P

33

IN

CK410_SRC4_N

R3459 0

33

IN

CK410_SRC2_P

5% 1/16W MF-LF 2 402

33

33

CPU_BSEL<1>

33

33 33

33

PP1V05_S0

33

IN IN IN IN IN IN IN

CK410_SRC2_N CK410_SRC8_P CK410_SRC8_N CK410_SRC1_P CK410_SRC1_N

 

 2

 

33 33

1

33 33

1

 

1

 

1

 

1

 

33 33

FSB_CLK_NB_P OUT FSB_CLK_NB_N OUT FSB_CLK_CPU_P OUT FSB_CLK_CPU_N OUT

5 12 34 5 12 34

5 7 34 5 7 34

34

FSB_CLK_XDP_P

CPU_XDP_CLK_P

11

34

FSB_CLK_XDP_N

CPU_XDP_CLK_N

11

MAKE_BASE=TRUE

B

MAKE_BASE=TRUE

IN

1

81 34 6

33 33 33 33

1

1

5% 1K 1/16W MF-LF 2 402

R3458 NB_BSEL<1>

IN

PP1V05_S0 1

7

SB_CLK48M_USBCTLR OUT

1% 402 1/16W MF-LF

R3454

1K

33

33

1

1

R3455

14

2

M F -L F 4 0 2

CK410_FSA

1 / 1 6W

7

1

PP1V05_S0

1

NB_BSEL<0>

R3400

33 33

14

CK410_USB48_FSA

1/16W 5% MF-LF 402

R3457

81 34 6

IN

R3429 R3430

 

R3413

AIRPORT_CLK100M_PCIE_P OUT

34 53

2

    2  2  2  2  2  2  2  2  2  2

R3414 R3415 R3416 R3417 R3418 R3419 R3420 R3421 R3422 R3423 R3424

CK410_LVDS_P

AIRPORT_CLK100M_PCIE_N OUT NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N

OUT OUT

SB_CLK100M_SATA_P OUT SB_CLK100M_SATA_N OUT SB_CLK100M_DMI_P OUT SB_CLK100M_DMI_N OUT ENET_CLK100M_PCIE_P OUT ENET_CLK100M_PCIE_N OUT GPU_CLK100M_PCIE_P OUT GPU_CLK100M_PCIE_N OUT

34 53 5 14 34 5 14 34

5 21 34 5 21 34

5 22 34 5 22 34

5 34 41 5 34 41

5 34 84 5 34 84

TP_CK410_LVDS_P

CK410_LVDS_N

TP_CK410_LVDS_N

1

R3460 1K

A

R3462 14

NB_BSEL<2>

1 1/16W

34

1K 5%

 

NOSTUFF 1

R3461

5% 1/16W MF-LF 2 402

0

33 33

IN IN

CK410_DOT96_27M_SPREAD_N CK410_DOT96_27M_NONSPREAD_P

33 33

1

 

1

 

   

2 2

R3470 R3471

CK410_27M_SPREAD CK410_27M_NONSPREAD

OUT

92

OUT

92

CLOCKS:

5% 1/16W MF-LF 2 402

2

TERMINATIONS

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY

MF-LF 402

CK410_FSC

1

R3463

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

0

5%

1/16W MF-LF 2 402 7

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CPU_BSEL<2>

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D

SHT

SCALE NONE

8

7

6

5

4

3

2

REV.

051-7148

13 OF

34

1

110

A

 

8

6

7

2

3

4

5

1

PATA CONNECTOR 38 6

6

=PP5V_S0_PATA =PP3V3_S0_PATA

NO STUFF 1

NOSTUFF 1

R3852 10K

R3824 10K

CRITICAL

Per ATA Spec 1

R2389 1

F-ST-SM 51

R3851

5% 1/16W MF-LF 2 402

1K

Per ATA Spec 2

IDE_RESET_L

21 21

IDE_PDD<4>

13

14

IDE_PDD<12>

21

IDE_PDD<3>

15

16

21

IDE_PDD<2>

17

18

IDE_PDD<14>

21

21

IDE_PDD<1>

19

20

IDE_PDD<15>

21

21

IDE_PDD<0>

21

22

23

24

25

26

27

28

IDE_PDIOW_L

6

IDE_PDD<8>

8

IDE_PDD<9>

10 12

IDE_PDD<10> IDE_PDD<11>

21 5 21

21 21 21

IDE_PDD<13>

21

IDE_PDIOR_L

5 21

IDE_PDDACK_L IDE_IOCS16_PU

29

30

IDE_PDA<1>

31

32

21

IDE_PDA<0>

33

34

IDE_PDA<2>

21

21

IDE_PDCS1_L

35

36

IDE_PDCS3_L

21

IDE_DASP_L

37

38

39

40

41

42

43

44

45

46

47

48

49

50

2

IDE_CSEL_PD

C

NC

1

NC

C3805 0.1uF

1

C3806

C

10UF

20% 10V 2 CERM 805-2

20% 10V

OUT

NOTE: ATA-2, NOW OBSOLETE

NC

2 CERM

52

21

21

21

10pF 5% 50V CERM 402

Obsolete

9 11

IDE_IRQ14

NO STUFF

NC

5

IDE_PDIORDY

C3804 1

4

2

7

21

OUT

NC

IDE_PDD<6> IDE_PDD<5>

21

21

3

2

IDE_PDD<7>

21

OUT

1

IDE_RESET_L

38 23

21 5

D

1

R3853

4.7K NC

38 23

2

804RVS-0501S5RGM

1K

D

JC901

2

402

516S0327

IDE_PDDREQ

PLACE SHORT AT PACKAGE 21

SATA_RBIAS_N

21

SATA_RBIAS_P

OUT

SATA_RBIAS

38 6

MAKE_BASE=TRUE

1/16W MF-LF 402 1%

R3858 1R3859

DEVELOPMENT 1

0

R3857

499

R3897  2 24.9

PLACE C3805-06 CLOSE TO JC901 FOR PP5V_S0_PATA. APPLY A WIDE TRACE SHAPE FROM JC901 TO C3805-06. MIN_NECK & MIN_LINE WIDTH ARE CONTROLLED BY PP5V_S0 1MM / 0.6MM.

=PP5V_S0_PATA 1

OUT

DEVELOPMENT

1% 1/16W 402 MF-LF

PLACE < 0.5 IN FROM BALL OF U2100

LED3800

2

IDE_DASP_L_DS

1

6.2K

5% 1/16W MF-LF 2 402 NOTE:

???

5% 1/16W MF-LF 2 402 PER ATA7 SPEC STUFFED PER LARRY

2

 1

GREEN-3.6MCD

2.0X1.25MM-SM

"IDE ACTIVE"

0

B

B

SATA CONNECTOR JC900

VALUE=3900PF IN REFERENCE SCHEM

EP00-081-91

23

CAPS TO BE SAME DISTANCE

M-ST-SM

SATA_C_DET_L

OUT

NOTE: GO TO SB AND SMC

FROM SB WITHIN EACH PAIR

1 2

SATA_C_R2D_P

3

SATA_C_R2D_N

0.0047UF 1   402

2

C3803 1

0.0047UF

4 5

SATA_C_D2R_C_N

6

SATA_C_D2R_C_P

0.0047UF 1   402

2

2 402

C3800

0.0047UF

7

1

2 402

C3801 C3802

21

SATA_C_R2D_C_P

21

SATA_C_R2D_C_N

21

SATA_C_D2R_N

21

SATA_C_D2R_P

1

R3899

IN

100

IN

5% 1/16W MF-LF 2 402

OUT OUT

518S0251

SATA DIFF PAIR GND VIAS

GV3802

GV3801

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

GV3804

HOLE-VIA-P5RP25

21

HOLE-VIA-P5RP25

1

A

SATA PORT 0 IS NOT USED

1

1

GV3803

1

GV3805

21

IN IN

SATA_A_R2D_C_P

Disk Connectors

TP_SATA_A_R2D_P MAKE_BASE=TRUE

SATA_A_R2D_C_N

TP_SATA_A_R2D_N

HOLE-VIA-P5RP25

NOTICE OF PROPRIETARY PROPERTY

HOLE-VIA-P5RP25

1

21

1

21

HOLE-VIA-P5RP25 GV3807

OUT OUT

SATA_A_D2R_P

TP_SATA_A_D2R_P THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

MAKE_BASE=TRUE

SATA_A_D2R_N

TP_SATA_A_D2R_N MAKE_BASE=TRUE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

HOLE-VIA-P5RP25 GV3808

1

A

MAKE_BASE=TRUE

GV3806

1

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

0

APPLE COMPUTER INC.

0 51 -7 14 8

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF

38

1

110

 

8

6

7

42 41

1

C4101 0.1UF

C4102

C4103

1

0.1UF

10% 16V

10% 16V

1

0.1UF 10% 16V

2 X5R

402

C4104

1

0.1UF 10% 16V

2 X5R

402

1

=PP2V5_S3_ENET 1

2 X5R

2

3

4

5

C4105

1

10% 50V

2 CERM

2 CERM

402

C4150

0.001UF

0.001UF 10% 50V

2 X5R

402

402

402

D

D =PP3V3_S3_ENET 6 41 42

42 41 6

LAYOUT NOTE: PLACE C4110-11 AT U4101

=PP1V2_S3_ENET

=PP3V3_S3_ENET

42 41

PP3V3_S0

 0 2  W  F  5  L  6  2  0  %  1   0  1  5   /  F  4  4  1  M  R 1

 F  F  U  T  S  O  N

 1 2  F  W  5  6  L  2  0  %   0  1  1  5  F  4  4   /  M  1  R 1

 1 2     K  W  F  0  6  L  2      7  %  1  0   1  .  5   /  F  4  4  M      4  1  R 1

     8      8      4      9      3      3      5      4      4      3      3      1  7 2      7      6      5      4      3      2      1      0     D     D     D     D     D     D     D     D     D     D     D     D     D     D     D     D     V     V     V     V     V     V     V     V

ENET_LOM_DIS_L VMAIN_AVLBL

10

LOM_DISABLE*

12

VAUX_AVLBL

47 NC 11 9

NC

     3      2

     1      5      0      6      4      4  8 1      4     L     T     T _      O     D     D     V

     3     L     T     T _      O     D     D     V

     2     L     T     T _      O     D     D     V

     1     L     T     T _      O     D     D     V

    D     D     V     A

     0     L     T     T _      O     D     D     V

     7      2      1      2      8      2      9      5      5      5      3      2      2      1      6     L     D     D     V     A

     5     L     D     D     V     A

     4     L     D     D     V     A

     3     L     D     D     V     A

OMIT

VMAIN_AVLBL

QFN

OPTIONAL EXTERNAL LDO 42 42

OUT OUT

HSDACN

ENET_CTRL25 ENET_CTRL12 ENET_RSET

C

4

CTRL25

3

CTRL12

     0     L     D     D     V     A

PCI EXPRESS ANALOG

RSET

ENET_LED_ACT_L

59

LED_ACT*

ENET_LED_LINK10_100_L

60

ENET_LED_LINK1000_L

62

LED_LINK1000*

ENET_LED_LINK_L

63

LINK*

29

TSTPT

LED_LINK10/100*

LED

2 1

50

22 5

2

22 5

53

34 5

REFCLKN 56

34 5

PCIE_WAKE_L ENET_GATED_RST_L 53 23

42

 3 2      9  W  F  0  L  6  2  .  %   1  0  1      9  1  F   /  4  4  M      4  1  R 1

0.1UF

ENET_CLK100M_PCIE_P ENET_CLK100M_PCIE_N

5

10%

IN

 

20% CERM

10V 402

 

1

2

1

2

CERM 20%

402 10V

0.1UF

IN

22

PCIE_A_R2D_C_P

22

PCIE_A_R2D_C_N

IN

 5 2  F      9  W  0  2  6  L  .  %  0  1   1      9  1  4   /  F  4  M      4  1  R 1

IN

LAYOUT NOTE: PLACE C4112-13 AT U2100

 6 2      9  W  F  0  2  6  L  .  %  0  1   1  1      9   /  4  F  4  M      4  1  R 1

 4 2  F      9  W  0  L  6  2  .  %   1  0  1      9  1  F   /  4  4  M      4  1  R 1

C4113

OUT

402

ENET_C4107_2

OUT

C4112

0.1UF

C4111

REFCLKP 55

0.001UF

ENET_C4106_2

PCIE_A_D2R_N

IN

MDIP0 17

43

MDIN0 18

43

MDIP1 20

43

MDIN1 21

43

MDIP2 26

43

MDIN2 27

43

MDIP3 30

43

MDIN3 31

 2 2  W  F      5     K  %  6  2  L  0  1  0       7  1  1  F  4  .   /  4  1  M      4  R 1

46

43

ENET_VPD_CLK

VPD_CLK 38

TEST

TWSI

TESTMODE

TEST

SPI

VPD_DATA

41 42

ENET_PU_VDDO_TTL0

PU_VDDO_TTL1

43

ENET_PU_VDDO_TTL1

SPI_DI

35

SPI_DO

34

4.7K 4.7K

1   1  

 2  2

ENET_MDI_P<0> IO ENET_MDI_N<0> IO ENET_MDI_P<1> IO ENET_MDI_N<1> IO

C

ENET_MDI_P<2> IO ENET_MDI_N<2> IO ENET_MDI_P<3> IO ENET_MDI_N<3> IO

41

ENET_VPD_DATA

PU_VDDO_TTL0

41

R4130 R4131

=PP3V3_S3_ENET 6

 W  F  F  0 2  W  L  6  L  9 2  6        9  1      9  1  2  F  F  1   /  .  /  M  1  M  1 .  1  1      9      9  %  4  4      4      4  %  2  2  1  1  R 1  0  R 1  0  4  4

41 42

SPI_CLK 37 SPI_CS

MAIN CLK

C4107

2 CERM 50V

402

PCIE_A_D2R_P OUT

PCIE_A_R2D_P PCIE_A_R2D_N

54

1

10%

2 CERM 50V

CERM 402 20% 10V

49

TX_N

WAKE* 6

MEDIA

10V 402

1

PCIE_A_D2R_C_N

TX_P

PERST*

16

20% CERM

PCIE_A_D2R_C_P

     5      2     D     D     V

RX_N

88E8053

SWITCH_VAUX HSDACP

NC 25

     1     L     D     D     V     A

RX_P

U4101

SWITCH_VCC

NC 24

     2     L     D     D     V     A

     4      6

C4106

0.001UF

0.1UF

41 42 11 10 6

1

C4110

=PP2V5_S3_ENET 88 76 61 59 26

 F  8 2  W  6  L       9  1  1  F  .  /  1  M  1      9  4      4  %  2  1  R 1  0  4

 F  7 2  W  6  L       9  1  1  F  .  /  1  M  1      9  4      4  %  2  1  R 1  0  4

36

ENET_C4117_1

XTALI 15 ENET_XTALI XTALO 14 ENET_XTALO

THRML_PAD

1

     5      6

2

ENET_C4118_1 1

C4118

0.001UF

10% 50V 2 CERM 402

25.0000M 1

C4117

0.001UF

Y4101

10% 50V

2 CERM

402

SM-3-LF

1

1

402

C4116 27PF

C4115

5%

2 27PF 50V 5%

B

B

50V 2 CERM 402

CERM

42 41 6

1

=PP3V3_S3_ENET

C4140

 2  2     K  F      7  W  2  6  L  2  .  %  1   0  1      4  5  F  4  4   /  1  M  R 1

0.1UF 10%

2 16V X5R

402 8 3 2 1 7

42 41 6 42 41

=PP3V3_S3_ENET

A

C4126

1

0.1UF 10% 16V

2 X5R

402

0.1UF 10% 16V 402

6

ENET_VPD_DATA 41

ENET_VPD_CLK 41

4

C4127 1 C4128 1 C4129

2 X5R

5

VSS

=PP1V2_S3_ENET 1

1

VCC E2 OMIT NC1 U4102SDA NC0M24C08 SO8 SCL WC*

 3 2     K  W  F  2  6  L  2      7  %  1   0  1  .  5   /  F  4  4  M      4  1  R 1

0.1UF 10% 16V

2 X5R

402

0.1UF 10% 16V

2 X5R

402

1

C4130 0.1UF 10% 16V

1

C4131

0.001UF 10% 50V

2 X5R

2 CERM

402

402

1

C4132

0.001UF 10% 50V

2 CERM

402

1

C4133

0.001UF 10% 50V

1

C4134

0.001UF 10% 50V

2 CERM

2 CERM

402

 

C4135 0.1UF 10% 16V

2 X5R

1

C4136 0.1UF 10% 16V

2 X5R

402

402

1

1 C4137 C4138 0.001UF

0.1UF 10% 16V

2 X5R

402

10% 50V 2 CERM 402

1

C4139

ETHERNET CONTROLLER

0.001UF

10% 50V 2 CERM 402

SYNC_MASTER=ENET

SYNC_DATE=06/22/2005

NOTICE OF PROPRIETARY PROPERTY

402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051- 7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

41

1

110

A

 

8

6

7

5

4

2

3

1

D

D 41 6

L4200

=PP3V3_S3_ENET

FERR-330-OHM 1

2

Q4201_3

0805 6

1

C4200 10UF

10% 16V 2 CERM 1210

1

1

C4201 0.1UF

C4202 10UF

10% 16V 2 CERM 1210

10% 16V

2 X5R 402

1

C4203 4.7UF

20% 16V 2 CERM 1206-1

1

C4204 0.1UF

IN

EN NE E T_ R RS S T_ L

41

E NE T T_ _ GA T TE E D_ R RS S T_ L OUT

1

R4202 4.7K

10% 16V

5% 1/16W MF-LF 2 402

2 X5R 402

3

CRITICAL

Q4201 PBSS5540Z

1

SOT223 4 2 41

IN

ENET_CTRL25

PP2V5_S3_ENET 43 1

C4205 4.7UF

20% 10V 2 CERM 1210

1

C4206 0.1UF 10% 16V

MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

=PP2V5_S3_ENET

41

2 X5R 402

C

C

41

IN

6

ENET_CTRL12

TP_ENET_CTRL12 MAKE_BASE=TRUE

L4201

=PP1V2_S3_LAN

FERR-330-OHM 1

PP1V2_S3_ENET

2

MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

0805

B

1

C4209 4.7UF

20% 6.3V 2 CERM 603

1

C4210

B

0.1UF 2

10% 16V X5R 402

=PP1V2_S3_ENET

41

ETHERNET MISC

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF 42

1

110

 

8

6

7

3

4

5

2

1

R4300 1

0

2

5% 1/16W MF-LF 402

NOSTUFF

L4300

FERR-EMI-600-OHM 42

1

PP2V5_S3_ENET

2

PP2V5_ENET_CTAP

D

MIN_LINE_WIDTH=0.50mm MIN_NECK_WIDTH=0.38mm VOLTAGE=2.5V

SM

D

1

C4300

1

C4301

0.001UF

0.1UF

20% 50V 2 CERM 402

20% 10V 2 CERM 402

TABLE_5_HEAD

P AR T#

QTY

D E SC RI P TI ON

REFERENCE

DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

514-0366

1

FOXCONN AND DELTA   RJ45

JD600

CRITICAL

TABLE_ALT_HEAD

P AR T N UM BE R 6

ALTERNATE FOR PART NUMBER

B OM O PT IO N

REF DES   COMMENTS:

GND_CHASSIS_RJ45

C4304

1

0.001UF

10% 50V CERM 2 402

OMIT

JD600

RJ45-M50 F-ANG-TH PRIMARY

1CT:1CT

13 11

75 OHM

C 41

IO

41

IO

41

IO

ENET_MDI_P<0> ENET_MDI_N<0>

0 0

1

 

1

 

1 1

   

1

 

1

 

 2  2

R4350 R4351

  22  2  2  2  2

R4352 R4353 R4354 R4355 R4356 R4357

5

ENET_CTAP

6

ENET_CTAP

5

ENET_MDI_R_P<0>

1

MDI_0+

5

ENET_MDI_R_N<0>

2

MDI_0-

C

1CT:1CT SECONDARY 75 OHM

J1

3 41 41 41 41 41

IO IO IO IO IO

ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3>

0 0 0 0 0 0

1

 

1

 

5 5

ENET_MDI_R_P<1> ENET_MDI_R_N<1>

4

MDI_1+ MDI_1-

5

ENET_MDI_R_P<2>

7

MDI_2+

5

ENET_MDI_R_N<2>

8

MDI_2-

5

ENET_MDI_R_P<3>

9

MDI_3+

5

ENET_MDI_R_N<3>

10

MDI_3-

J2 J3 J4

1CT:1CT

J5 75 OHM

J6 J7 J8

1CT:1CT

12

RJ45 CABLE SIDE 75 OHM

RJ45 CHIP SIDE

S HI EL D

1 00 0P F, 2 00 0V

B

B 1

C4305

0.001UF

10% 50V 2 CERM 402

ETHERNET CONNECTOR

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

05 51 1-7 71 14 48

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF

43

1

110

 

8

6

7

2

3

4

5

1

NOSTUFF

R4411 0

1 1/16W

5%

2

MF-LF 402

L4409

600-OHM-300MA 46 45 44 6

1

=PP3V3_S5_FW

2

PP3V3_S5_FW_VDDA

45

0402 46 45 44 6

1

D

=PP3V3_S5_FW

C4410

 9  1  1

0.1UF

20% 10V 2 CERM 402

6

V D D  0

V D D 1

V D D 2

V D D  3

V V D D D D 4  5

V D D  6

V V V D D D D D D  7  8  9

D

 4  6  0  1  6  1  1  9

 1 9  6  7 3  9  5  2  2  3  1  1 1  2  3 4  4  5  7  8  9

P L L V D D

=PP3V3_S0_PCI

V D D 1  0

V D D A  0

V D D A 1

V D D A 2

C4401 27PF

44

85 PCI_VIOS 22

IO

22

IO

22

IO

22 22 22

22

IO

22

IO

22

IO IO

22 22 22

22 22

IO

PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12>

IO

PCI_AD<13>

IO

PCI_AD<14>

IO

22

22

PCI_AD<4>

IO

22

PCI_AD<2> PCI_AD<3>

IO

22

PCI_AD<1>

83 PCI_AD0 PCI_AD1 80 PCI_AD2 79 PCI_AD3

IO

IO

22

84

IO

IO

22

PCI_AD<0>

PCI_AD<15>

IO

PCI_AD<16>

IO

PCI_AD<17>

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22 22 22

IO

26 22

IO

26 22

IO

26 22

R4403

1

IO

2

0

26 22

OUT

22

B

26 22 26 22

34 67 60 58 23 5

TPBIAS0

114

FW_A_TPBIAS

IO

46 PCI_AD16 45 PCI_AD17

TPA0_P

113

46

FW_A_TPA_P

IO

TPA0_N

112

46

FW_A_TPA_N

TPB0_P

111

46

FW_A_TPB_P

IO

TPB0_N

110

46

FW_A_TPB_N

IO

TPBIAS1

29 PCI_AD26 28 PCI_AD27 25 PCI_AD28

109

FW_B_TPBIAS FW_B_TPA_P

46

FW_B_TPA_N

106

46

FW_B_TPB_P

46

FW_B_TPB_N

IO

FW_C_TPBIAS

IO

101

TPA2_P

100

46

FW_C_TPA_P

TPA2_N

99

46

FW_C_TPA_N

IO

TPB2_P

98

46

FW_C_TPB_P

IO

46

FW_C_TPB_N

PCI_CBE0*

LKON

90

PCI_CBE1* PCI_C_BE_L<2> 47 PCI_CBE2* PCI_C_BE_L<3> 33 PCI_CBE3*

NANDTREE

59 PCI_PAR 48 PCI_FRAME* 51 PCI_IRDY* 52 PCI_TRDY*

PCI_DEVSEL_L 53 PCI_DEVSEL* PCI_STOP_L 54 PCI_STOP* PCI_IDSEL

34

PCI_REQ1_L

17

TP_FW_CNA

6

TP_FW_NANDTREE

PC2

87

FW_PC2

CONTENDER

86

FW_CONTENDER

NU2

92

TP_FW_MPCIACT_L TP_FW_VAUX_PRES NC_FW_NU1

127

NC_FW_NU2

TEST0

10

IO

PCI_SERR_L

58 PCI_SERR*

TEST1

7

PCI_CLK_FW

20 PCI_CLK 13 CLKRUN*

PTEST

124

SE

126

SM

125

FW_CARDBUS_L

T1:

TP (?)

1

R4416 10K

3

CARDBUS*      S      S     V     L     L     P

 0  2  1

1

128 4

FW_TEST

FW_SM

9

TP_FW_ROM_AD

ROM_CLK

8

FW_ROM_CLK

1

10K

46

=PP3V3_S5_FW6

R4453 R4454 R4455

1

 

1

 

10K

1

 

 2

R4450

1

 

1

 

 2  2

R4451 R4452

1

 

44 45 46

2

 2  2  2

10K 10K 10K

10K 10K

FW_SE

ROM_AD

=PP12V_S5_FW_PHY

390K 2

R4409

FW_PC0 FW_PC1

PCI_REQ* 16 PCI_GNT* 57 PCI_PERR*

PCI_RST_FW_L 15 PCI_RST* INT_PIRQD_L 14 PCI_INTA* 18 PCI_PME/CSTSCHG*

1

88

NU1

R4414 1/16W 5% MF-LF 402

PC1

MPCIACT*

PCI_PME_FW_L

IO

89

IN

PM_CLKRUN_L

IO

PC0

VAUX_PRESENT

PCI_IDSEL

C

TP_FW_LKON

5

MF-LF 402

IO

TPB1_N

46

5%

1/16W

IO

TPBIAS2

TP_FW_LPS

PCI_TRDY_L

402

IO

105

91

PCI_IRDY_L

2 CERM

R4412

IO

46

LPS

IO

IO

46

107

FW_CPS

PCI_FRAME_L

FW_RESET_L

IO

108

94

PCI_PERR_L

OUT

46

TPA1_N

CNA

1 10V 20% 402

510K 2 1

CPS

PCI_PAR

MF-LF

TPA1_P TPB1_P

35 PCI_AD23 31 PCI_AD24 30 PCI_AD25

C ER M

0.1UF

44

97

IN

44

22

63 PCI_AD14 62 PCI_AD15

1%

2

5 0V 5 % 4 02

1

1/16W

1

FW_XTAL_XR

2.49K2

FW_R0

22 PCI_AD31

2

R4413 FW_R1

PCI_AD<31>

412

27PF

C4402

117

PCI_AD<30>

1

FW_XTAL_X0

 

FW_RESET_L 44

118

24 PCI_AD29 23 PCI_AD30

PCI_GNT1_L

IO

26 22

123

TPB2_N

PCI_AD<29>

CERM

C4412

HC49-USMD

2

1% 1/16W MF-LF 402

R0

PCI_C_BE_L<1> 60

IO

26 22

RESET*

44

FW_XTAL_X0 44

R1

PCI_C_BE_L<0> 73

IO

26 22

PCI_AD<28>

122

TQFP

65 PCI_AD12 64 PCI_AD13

IO

IO

22

PCI_AD<25> PCI_AD<26> PCI_AD<27>

XO

R4410

FW_XTAL_XI 44

68 PCI_AD10 67 PCI_AD11

IO

IO

22

PCI_AD<24>

U4400 FW32306

121

70 PCI_AD8 69 PCI_AD9

40 PCI_AD20 39 PCI_AD21 36 PCI_AD22

PCI_AD<23>

XI

75 PCI_AD6 74 PCI_AD7

42 PCI_AD18 41 PCI_AD19

PCI_AD<22>

2

50V 5% 402

Y4400 24.576M

OMIT

78 PCI_AD4 76 PCI_AD5

PCI_AD<20> PCI_AD<21>

CRITICAL 1

PCI_AD<18>

PCI_AD<19>

C

1

FW_XTAL_XI

B

2

10K

R4402      0      1      2      3      0      1      2      3      4      5      6      7      8      9      1      1      1      1      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S      S     V     V     V     V     V     V     V     V     V     V     V     V     V     V

 2  2  1  7  2  8  4  0  6  1  6  1  7  1  1  2  2  3  3  4  5  5  6  6  7  7  8

     0      1      2      3     A     A     A     A      S      S      S      S      S      S      S      S     V     V     V     V

 2  3  5  5  0  0  1  9  1  1  1

5% 1/16W MF-LF 2 402

R4407 22

IN

PCI_RST_L

1

46 45 44 6

2

PCI_RST_FW_L

THESE POWER PLANES SHOULD BE MOSTLY ISOLATED

=PP3V3_S5_FW

???

CHECK YELLOW EDS

44

150

FW: FW323-06

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

0 51 51 -7 -7 14 14 8

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

OF

13

44   110

1

A

 

8

6

7

2

3

4

5

1

D

D

46 44 6

=PP3V3_S5_FW

1

C4515 10UF

20% 6.3V 2 CERM 805-1

44

1

C4508 0.1UF

20% 10V 2 CERM 402

1

C4509 0.1UF

20% 10V 2 CERM 402

1

C4510 0.1UF

20% 10V 2 CERM 402

1

C4520 0.1UF

20% 10V 2 CERM 402

1

C4521

1

0.1UF

C4500 0.01UF

20% 10V 2 CERM 402

20% 16V 2 CERM 402

1

C4501 0.01UF

20% 16V 2 CERM 402

1

C4502 0.01UF

20% 16V 2 CERM 402

1

C4522 0.01UF

20% 16V 2 CERM 402

1

C4523 0.01UF

20% 16V 2 CERM 402

PP3V3_S5_FW_VDDA

1

C4503 10UF

20% 6.3V 2 CERM 805-1

C

1

C4507 0.1UF

20% 10V 2 CERM 402

1

C4506 0.1UF

20% 10V 2 CERM 402

1

C4505 0.01UF

20% 16V 2 CERM 402

1

C4504 0.01UF

20% 16V 2 CERM 402

C

B

B

FW: DECAPS

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

0 51 51 -7 -7 14 14 8

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

OF

13

45   110

1

A

 

8

6

7 6

1

PP12V_FW MIN_LINE_WIDTH=0.8MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V MAKE_BASE=TRUE

FW_VP

2

MINISMD-LF

1

44

PPFW_PORT0_VP

1

50V CERM 2 402

Termination

DP4610 BAV99DW-X-F SOT-363

IO

44

IO

44

IO

44 44

IO IO

1206-LF

CRITICAL

FL4610 120-OHM

PORT 0 1394A

2

46 FW_PORT0_TPA_P

1

4

46

FW_PORT0_TPA_N

2

3

46

FW_PORT0_TPB_P

CRITICAL

C4650

1

10% 6.3V 2 CERM-X5R 402

R4651 R46601 56.2

R4661 56.2

1% 1/16W MF-LF 402 2

46

1% 1/16W MF-LF 2 402

FW_A_TPA_P FW_A_TPA_N FW_A_TPB_P FW_A_TPB_N

46

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

FW_PORT0_TPA_P FW_PORT0_TPA_N FW_PORT0_TPB_P FW_PORT0_TPB_N

FW_B_TPA_P

MAKE_BASE=TRUE

R4653 R46621

56.2

56.2

1% 1/16W MF-LF 402 2

FW_TPA_C<0>

5% 25V CERM 2 402

2

DP4611

BAV99DW-X-F

46 46

FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N

46

C4612

46

0.001UF 10%

46

6 1 1

46

(TPB-)

VP

2

VGND 7

3

C4613 1 0.001UF 10%

1 4

8

9

C

10

C4615 0.1UF

10% 50V 2 X7R 603-1

50V CERM 2 402

GND_CHASSIS_FIREWIRE 6

C4616

46

1

0.01uF

20% 16V CERM 2 402

"Snapback" & "Late VG" Protection PP3V3_FW_ESD

DP4620

R4664

DP4620

BAV99DW-X-F

4.99K

2

(TPB+)

TPI#

5

50V CERM 2 402

1 1

5% 25V CERM 2 402

(TPA-)

TPI

SOT-363

2

1% 1/16W MF-LF 2 402

220PF

1

BAV99DW-X-F

SOT-363

(TPA+)

TPO TPO#

DP4611

56.2

VOLTAGE=0V

1/16W MF-LF 402

3

R4663

1% 1/16W MF-LF 402 2

R4654 4.99K C4664 1%

220PF

FW_PORT0_TPB_FL_N

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

FW_TPA_C<1> 1

C4654 1

4

PPFW_PORT0_VP_FL

46

46

VOLTAGE=0V

FW_PORT0_TPB_FL_P

1

56.2

1% 1/16W MF-LF 2 402

3

PP3V3_FW_ESD

MAKE_BASE=TRUE

1

5

FW_VP MAX IS 33V

FW_PORT1_TPA_P MAKE_BASE=TRUE

6

FW_PORT0_TPA_FL_N

46

MAKE_BASE=TRUE

R46521

4

2

MAKE_BASE=TRUE

FW_B_TPA_N FW_B_TPB_P FW_B_TPB_N

FW_PORT0_TPA_FL_P

2012

SYM_VER-1

1

FW_PORT0_TPB_N

1394A-M50 F-ST-TH

FLE011 120-OHM CRITICAL

1

56.2

1% 1/16W MF-LF 2 402

JE000

C4660 0.33UF

1

1% 1/16W MF-LF 402 2

44

4

VOLTAGE=1.86V

56.2

IO

FERR-160-OHM

2012

R46501

44

L4610

3

SYM_VER-1

10% 6.3V 2 CERM-X5R 402

IO

50V CERM 2 402

1

5

0.001UF 10% 6

1

FW_B_TPBIAS FW_A_TPBIAS

0.33UF

44

C4611 1

Place close to FireWire PHY

1

IO

SOT-363

2

0.001UF 10%

44

D

"Snapback" & "Late VG" Protection PP3V3_FW_ESD

DP4610

C

46

C4609

BAV99DW-X-F

IO

PPFW_PORT1_VP

VOLTAGE=33V

10% 50V 2 X7R 603-1

POWER DETECT)

C4610

IO

PPFW_PORTS_VP

0.1UF

TO FW CDS PIN (CABLE

2

46

44

2

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.8MM MIN_NECK_WIDTH=0.25MM VOLTAGE=33V

SMC

5% 1/8W MF-LF 805

D

1

I443 =PP12V_S5_FW_PHY

R4657 0

0.75AMP-13.2V

MURS320XXG

0.0252

1

1

F4602

FW_VP MAX IS 33V

D4600

R4656 1% 1W MF 2512-1

44

1

CRITICAL

NOSTUFF

8 WATTS MAX 12 VOLTS

VOLTAGE=1.86V

2

3

4

5

=PP12V_S5_FW

C4620

1% 1/16W MF-LF 402

1

SOT-363

10% 50V CERM 2 402

BAV99DW-X-F

C4621 1

2

0.001UF

0.001UF 6

SOT-363

1

PPFW_PORT1_VP 46

5

10% 50V CERM 2 402

3 1

4

CRITICAL

FL4620

FERR-160-OHM

1206-LF

SYM_VER-1

B

FW_PORT1_TPA_P

1

46

FW_PORT1_TPA_N

2

PORT 1 1394A

L4620

120-OHM 2012

46

4

CRITICAL

B

CRITICAL

2

3rd TPA/TPB pair unused

JE001

3

1394A-M50 F-ST-TH

FLE021 120-OHM 2012

FW_PORT1_TPA_FL_P

6

FW_PORT1_TPA_FL_N

5

FW_PORT1_TPB_FL_P

4

FW_PORT1_TPB_FL_N

3

TPO

(TPA+)

TPO#

(TPA-)

TPI

(TPB+)

TPI#

(TPB-)

SYM_VER-1

44

44

44

44

44

IO

IO

IO

F W_ C_T PB IA S FW_C_TPA_P

T MAKE_BASE=TRUE P_F W_ C_ TP BI AS

46

MAKE_BASE=TRUE NO_TEST=TRUE

FW_C_TPA_N

FW_PORT1_TPB_P

1

2

46 FW_PORT1_TPB_N

TP_FW_C_TPA_N MAKE_BASE=TRUE

IO

FW_C_TPB_P

IO

FW_C_TPB_N

4

TP_FW_C_TPA_P 3

1

PPFW_PORT1_VP_FL

TP_FW_C_TPB_P MAKE_BASE=TRUE

46

MIN_LINE_WIDT H=0.6 mm MIN_NECK_WID TH=0.25 mm VOLTAGE=33V

PP3V3_FW_ESD

TP_FW_C_TPB_N

DP4621

DP4621

MAKE_BASE=TRUE

C4622

0.001UF

6 1

45 44 6

=PP3V3_S5_FW

1

2

1

PP3V3_FW_ESD_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 MIN_NECK_WIDTH=0.25

[ LATE VG NOTES ] CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR IT IS 2.2V INSTEAD OF 2.7V

PP3V3_FW_ESD

400-OHM-EMI

1% 1/16W MF-LF 402

10

C4626 1 20% 16V CERM 402

2

GND_CHASSIS_FIREWIRE 6

mm mm

2

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

SM-1  3

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CRITICAL D4690 SOT23

A VOLTAGE DROP TO 2.2V

BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V

DROP

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

BZX84C2V7-X-F

SIZE

APPLE COMPUTER INC.

051-7148 SHT NONE

6

5

4

3

2

REV.

DRAWING NUMBER

D SCALE

7

A

46

VOLTAGE=3.3V MIN_LINE_W IDTH=0.38 mm MIN_NECK_W IDTH=0.25 mm

 1

8

46

FIREWIRE CONNECTORS L4690

R4690 374

9

0.01uF

4

10% 50V CERM 2 402

R4690 VALUE WAS RECOMMENDED BY COLIN

A

8

0.1UF

3

C4623 1

0.001UF

1

VGND

C4625

10% 50V 2 X7R 603-1

5

10% 50V CERM 2 402

ESD Rail

1

SOT-363

SOT-363

2

2

7

BAV99DW-X-F

BAV99DW-X-F

VP

13 OF

46

1

110

 

8

6

7

2

3

4

5

CRITICAL

External USB Ports

1

=PP5V_S3_BNDI

L4710

1

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

0.1UF

2

C4710

C4713 1

20% 16V CERM  2 402

20% 16V CERM  2 402

0.01uF

IO

0.01uF

2

3

USB_PORT0_P CRITICAL

0

1

D4700

2

402

NOSTUFF

R4713

VDD

1

D-

2

D+

3

GND

4

 0

C4743

D

1

0.01uF

20% 16V CERM 2 402

GND_CHASSIS_BNDI

2

LAYOUT NOTE: PLACE C4743, C4797 & L4740 NEAR JE350 PIN 14 IN THE ORDER LISTED, AND NOT ON BOTH SIDES OF THE PIN.

 T  R  O  P

7

1

0

1

47

1

0.01uF

F-ST-TH 5 6

NOSTUFF

C4742

JE310

4

R4712

GND_BNDI

VOLTAGE=0V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

USB-M50

SYM_VER-1

1

USB_A_P

2

47 6

120-OHM 2012

USB_A_N

0

20% 16V CERM  2 402

USB_PORT0_N 22

R4746 805 1/8W MF-LF 5%

C4712 1

47

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

10UF

20% 10V 2 CERM 805-2

1

SB HAS INTERNAL 15K PULL-DOWNS

PP5V_S3_BNDI

2

C4797

20% 2 6.3V POLY B2

L4712 IO

1

740S0032

PP5V_USB2_PORT0_F VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CRITICAL

22

1

100UF

20% 10V CERM 2 402

D

FERR-250-OHM

PP5V_BNDI_LE340

MINISMD-LF

SM

C4752 1

2

SM

FERR-250-OHM PP5V_USB2_PORT0

L4740

F4701

0.75AMP-13.2V 6

1

PLACE C4742 CLOSED TO JE350.

3

402

2

GND_CHASSIS_USB

RCLAMP0502B SC-75

CRITICAL

C

2

=PP5V_S3_USB

6 2 NOSTUFF

DZ4700 POWERDI-123

1

DFLS140

20% 6.3V 2 CERM 805-1

1

C4700 10UF

1

6 47

IN1

OUT1 15

IN2

OUT2 14

C4796

OUT3 11

0.1UF

20% 10V 2 CERM 402

3 4 7

EN1* EN2* EN3*

OC1* OC2* OC3*

1

PP5V_USB2_PORT1 VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C4751

1

0.1UF

16

12

22 22

OUT OUT

SB HAS INTERNAL 15K PULL-DOWNS

22

20% 16V CERM 2 402

CRITICAL

5

L4722 120-OHM

IO

4

IO

USB_H_N

R4742

C4723 0.01uF

F-ST-TH 5 6

1

4

2

3

R4722

0

1

R4723

USB_A_OC_L

1

73

GND_AUDIO_MIC_CONN

2

73

1

D-

2

USB_PORT1_P

D+

3

GND

4

D4701

2

0

1

 1

22

 T  R  O  P

7

1 2

AUD_MIC_IN_N_CONN

3

47 6

GND_CHASSIS_BNDI

4

47 6

GND_CHASSIS_BNDI

0

IO

C

5 6 7

USB_IR_P

2

USB_IR_N

8

GND_BNDI

10

USB_CAMERA_P

11

USB_CAMERA_N

12

9

402

L4752

USB_D_P

47

CRITICAL

2

VDD USB_PORT1_N

402

NOSTUFF

USB_C_OC_L

1

USB-M50

NOSTUFF

USB_E_OC_L

AUD_MIC_IN_P_CONN

2

R4754

JE320

20% 16V CERM 2 402

SYM_VER-1

USB_C_P

73

402

1

2012

USB_C_N

M-RT-SM 15

NOSTUFF

0

1

JE350 53261-1498

3

SYM_VER-2

20% 2 6.3V POLY B2

0.01uF

IO

518S0324 CRITICAL

120-OHM 2012

1

C4722

22

FHB CONNECTOR

2

CRITICAL

1

22

OUT

USB_H_P

100UF

20% 10V CERM 2 402

13

C4720

IO

L4742 2

PP5V_USB2_PORT1_F VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

SM 1

SB HAS INTERNAL 15K PULL-DOWNS

22

22

2

0

402

L4720

FERR-250-OHM

NC 8 NC 9 NC 10 GNDA GNDB 1

1

VOLTAGE=0

SOI

6

R4743

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM

U4700

TPS2043B

120-OHM 2012

3

13

NC_JE350_13 SB HAS INTERNAL 15K PULL-DOWNS

NOSTUFF 1

47

4

14

PP5V_S3_BNDI

SYM_VER-2

22

IO

16

USB_D_N

R4755 1

3

0

2

402

402

2

GND_CHASSIS_USB

6 47

RCLAMP0502B SC-75

B

B

BLUETOOTH

L4730

FERR-250-OHM 1

PP5V_USB2_PORT2 VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

2

PP5V_USB2_PORT2_F

SM

C4750

1

0.1UF 20% 10V CERM 402

1

6

=PP3V3_S3_BT

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C4730

CRITICAL

1

100UF

2

20% 2 6.3V POLY B2

20% 10V 2 CERM 805-2

SB HAS INTERNAL 15K PULL-DOWNS 22

C4732 1 0.01uF

20% 16V CERM  2 402

CRITICAL

C4733 1

22

0.01uF

IO IO

C4799 10UF

1

C4798 0.1UF

20% 10V 2 CERM 402

F-ST-SM 2

1

4

3

USB_G_N

USB_BT_N

USB_G_P

USB_BT_P

6

5 MAKE_BASE=TRUE MAKE_BASE=TRUE

JE330

20% 16V CERM 2 402

J4700

QT800101-1210S-8F

7

8

9

10

TO M13D SLOT

USB-M50 F-ST-TH 5

L4732

6

120-OHM 2012

 2

SYM_VER-1

22

IO

1

USB_E_N

4

USB_PORT2_N

SB HAS INTERNAL 15K PULL-DOWNS 22

IO

2

USB_E_P

3

NOSTUFF

R4732

1

0

1

0

1

D-

2

D+

3

GND

4

D4702

2

7

1

402

NOSTUFF

R4733

A

USB_PORT2_P

VDD

 T  R  O  P

NOTE: STANDOFFS FOR J4700

USB Device Interfaces

SDF4700

STDOFF-4OD4.5H-1.35-TH

3

2

1

402

GND_CHASSIS_USB 6

47

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

SDF4701

RCLAMP0502B

STDOFF-4OD4.5H-1.35-TH

SC-75

A

NOTICE OF PROPRIETARY PROPERTY

2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

1

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

0 51 -7 14 8

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF

47

1

110

 

8

7

6

5

4

3

2

1

D

D

C

C

B

B

BLANK

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

48

1

OF

13 110

 

8

6

7

2

3

4

5

1

D

D

=PP1V5_S0_AIRPORT 1

C5304

1

0.1UF

C5305 0.1UF

20% 10V 2 CERM 402

20% 10V 2 CERM 402

1

C5306

1

6

C5312 10UF

0.1UF

20% 10V 2 CERM 402

20% 6.3V 2 CERM 805-1

=PP3V3_S0_AIRPORT CRITICAL

1

J5300

20% 10V 2 CERM 402

F-RT-SM

54

R5304

C5308 0.1UF

ASOB226-S80N-7F

1

C5307

1

C5309 0.1UF

0.1UF

20% 10V 2 CERM 402

20% 10V 2 CERM 402

1

C5310

1

0.1UF

6

C5311 10UF

20% 10V 2 CERM 402

20% 6.3V 2 CERM 805-1

0 41 23

OUT

PCIE_WAKE_L

1

2

AIRPORT_WAKE_L

1

2

3

33

OUT

6

34 34

IN IN

7

8

9

10

AIRPORT_CLK100M_PCIE_N

11

12

AIRPORT_CLK100M_PCIE_P

13

CK410_SRC_CLKREQ6_L

17

22 5

OUT OUT

22

IN IN

20 22

PCIE_B_D2R_N

23

24

PCIE_B_D2R_P

25

26

27

28

1

PCIE_B_R2D_C_N 1

2

2

0.1UF

0.1UF

0.1UF

20% 10V 2 CERM 402

1

59 83

C

C5314 10UF

20% 6.3V 2 CERM 805-1

18

21

PCIE_B_R2D_C_P

C5313

16 KEY

19

C5300 22

1

14

15

22 5

PP3V3_S3 6

4

5

C

6

AIRPORT_RST_L

R5302 R5303

IN

0 0

29

30

AIRPORT_CONN_CLK

PCIE_B_R2D_N

31

32

AIRPORT_CONN_DATA

PCIE_B_R2D_P

33

34

35

36

22

USB_B_N

37

38

22

USB_B_P

39

40

41

42

43

44

LAYOUT NOTE:

45

46

PLACE R5302-03 SUCH THAT STUB LENGTH IS

47

48

MINIMIZED IF THE RESISTORS ARE NOT STUFFED

49

50

51

52

C5301 PLACE CAPS < 250 MILS FROM U2100

1

2

1

2

=SMB_AIRPORT_CLK

IO

=SMB_AIRPORT_DATA

IO

27 27

SB HAS INTERNAL 15K PULL-DOWNS IO IO

53

B

B

NOTE: STANDOFFS FOR J5300

SDF5300

STDOFF-4OD5.6H-1.35-TH 1

SDF5301

STDOFF-4OD5.6H-1.35-TH 1

AIRPORT CONN

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

53

1

OF

13 110

A

 

8

22

22

D

6

7

22

22

22

22

22

22

22

22

IN IN

PCIE_C_R2D_C_N

TP_PCIE_C_R2D_C_N

PCIE_C_R2D_C_P

TP_PCIE_C_R2D_C_P

3

2

1

MAKE_BASE=TRUE

OUT

P CI E_ C_ D2 R_ N

T P_ PC IE _C _D 2R _N

P CI E_ C_ D2 R_ P

T P_ PC IE _C _D 2R _P

D

MAKE_BASE=TRUE MAKE_BASE=TRUE

IN

P CI CI E_ D_ D_ R2 D_ D_ C_ N

T P_ PC PC IE _D _D _R 2 2D D _C _N _N

IN

PCIE_D_R2D_C_P

TP_PCIE_D_R2D_C_P

MAKE_BASE=TRUE MAKE_BASE=TRUE

OUT OUT

IN

4

MAKE_BASE=TRUE

OUT

IN

5

PCIE_D_D2R_N

TP_PCIE_D_D2R_N

P CI E_ D_ D2 R_ P

T P_ PC IE _D _D 2R _P

MAKE_BASE=TRUE MAKE_BASE=TRUE

PCIE_E_R2D_C_N

TP_PCIE_E_R2D_C_N

P CI CI E_ E_ E_ R2 D_ D_ C_ P

T P_ PC PC IE _E _E _R 2 2D D _C _P _P

MAKE_BASE=TRUE MAKE_BASE=TRUE

C

C 22

22

22

22

22

22

OUT OUT

IN IN

PCIE_E_D2R_N

TP_PCIE_E_D2R_N

PCIE_E_D2R_P

TP_PCIE_E_D2R_P

MAKE_BASE=TRUE MAKE_BASE=TRUE

PCIE_F_R2D_C_N

TP_PCIE_F_R2D_C_N

PCIE_F_R2D_C_P

TP_PCIE_F_R2D_C_P

MAKE_BASE=TRUE

OUT

OUT

MAKE_BASE=TRUE

PCIE_F_D2R_N

TP_PCIE_F_D2R_N

PCIE_F_D2R_P

TP_PCIE_F_D2R_P

MAKE_BASE=TRUE MAKE_BASE=TRUE

B

B

PCIE UNUSED PORTS

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

 54

1

OF

13 110

A

 

8

6

7

2

3

4

5

UNUSED PINS HAVE THE FORMAT SMC_XXX WHERE XXX IS THE PORT NUMBER. THEY ARE SET BY SOFTWARE TO BE DRIVEN OUTPUTS ALWAYS SO THEY CAN BE LEFT NO-CONNECTED.

59 58 6

=PP3V3_S5_SMC

OMIT 23

OUT OUT

77 26

IN

76 23

OUT

23

OUT

75

D

IN

OUT

23

OUT

59

OUT OUT

67 60 21

IO

67 60 21

IO

67 60 21

IO

67 60 21

IO

67 60 21

IN

6

IN

34 67 60 23

IN OUT OUT

60

OUT

59

IO

59

OUT OUT OUT

60

OUT

59

C

OUT

60 59 5

OUT

60 59 5 59

IN IO

P60/KIN0*

L13

P11

SMC_H8S2116

P61/KIN1*

L14

P12

BGA (1 OF 4)

P62/KIN2*

L15

22

P63/KIN3*

K12

63 22

P64/KIN4*

K13

63 22

P65/KIN5*

B12

P10

C13 A15 B14

P13

SMC_P20 59 SMC_P21 59 SMC_P22 SMC_P23 59 SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN 59 SMC_P26 59 SMC_P27 59

59

U5800

PM_LAN_ENABLE SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD SMC_SB_NMI PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L PCI_CLK_SMC INT_SERIRQ

B15

 

P14

59 59

C14

P15

K14

63 22

D12

P16

P66/IRQ6*/KIN6* J12

59

C15

P17

P67/IRQ7*/KIN7* J13

59

D13

P20

P70/AN0

N12

76

D14

P21

P71/AN1

R13

76

D15

P22

P72/AN2

P13

59

E12

P23

P73/AN3

R14

E14

P24

P74/AN4

P14

76

E15

P25

P75/AN5

R15

76

E13 F14

P26

P76/AN6

59

N13

59

P15

59

D9

P30/LAD0

P80/PME*

C7

23

C9

P31/LAD1

P81/GA20

A7

59

A9

P32/LAD2

P82/CLKRUN*

B7

67 60 44 23 5

B9

P33/LAD3

P83/LPCPD*

D6

67 60 23

D8

P34/LFRAME*

P84/IRQ3*/TXD1 C6

59

C8

P35/LRESET*

P85/IRQ4*/RXD1 A6

59

A8

P36/LCLK

P86/IRQ5*/SCK1/SCL1 B6

59

D7

P37/SERIRQ

P90/IRQ2*

K4

59

P91/IRQ1*

J2

59

SMC_XDP_TMS_L SMC_SYS_LED_16B SMB_BSB_DATA SMC_TPM_PP SMC_XDP_TRST_L SMC_XDP_TCK SMC_SYS_LED SMC_SYS_KBDLED

A5

SMC_TX_L SMC_RX_L SMC_SMB_0_CLK

G1

B5 D5

P27

P77/AN7

P40/TMIO P41/TMO0

P92/IRQ0*

J1

59

P42/SDA1

P93/IRQ12*

J3

88 79 77 23 6

C3

P43/TMI1/EXSCK1

P94/IRQ13*

J4

77 23

B1

P44/TMO1

P95/IRQ14*

H2

23

C2

P45

P96/EXCL

H1

59

D3

P46/PWX0/PWM0

P97/IRQ15*/SDA0 G2

59

C1

P47/PWX1/PWM1

1

SMC_PM_G2_EN SMC_ADAPTER_EN SPI_ARB SPI_SCLK

P51

F2

P52/SCL0

C5802 22UF

OUT

IN

1

C5803

1

0.1UF

C5804 0.1UF

20% 10V 2 CERM 402

20% 6.3V 2 X5R 805

OUT

20% 10V 2 CERM 402

1

C5805

1

C5806 0.1UF

0.1UF

20% 10V 2 CERM 402

20% 10V 2 CERM 402

IN

SPI_SI SPI_SO

OUT

LAYOUT NOTE:

IN

SMC_PROCHOT_3_3_L SMC_CPU_INIT_3_3_L SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_FWIRE_ISENSE SMC_WAKE_SCI_L SMC_TPM_GPIO PM_CLKRUN_L PM_SUS_STAT_L SC_TX_L SC_RX_L SMB_BSB_CLK

PLACE C5807 NEAR PIN F1

IN

SMC_VCL IN IN IN IN

1

LAYOUT NOTE:

C5807 0.47UF

VCL IS INTERNAL RAIL

PLACE R5899 AND C5820 NEAR SMC PIN

10% 6.3V 2 CERM-X5R 402

N14,N15

IN IN IN 59 58 6

IN

PP3V3_AVREF_SMC

=PP3V3_S5_SMC

R5899

IN

1

OUT

4.7

2

5% 1/16W MF-LF 402

IO IN

IN

MIN_NECK_WIDTH=0.20 MM

1

C5820 0.1UF

 5      2      1  1      1      1     P     P  J     A     F

 4  5  1  1  N  N      C      C      C      C     V     V     A     A

85 76 59 58

 4  5  1  1  M  M

OMIT

BGA (3 OF 4)

60 59 IN 59

IN

59

10K

MD1

E2

MD2

K1

NMI

F4

ETRST*

L1

IN

IN

R5809

5% 1/16W MF-LF 2402

SMC_H8S2116

GND_SMC_AVSS

SMC_RST_L

E3

RES*

SMC_XTAL SMC_EXTAL

A2

XTAL

B2

EXTAL

=PP3V3_S5_SMC

1

U5800

IN

IN

59 58 6

    F     F     E     E     R     R     V     V     A     A

 C  C  C  C  L  C  C  C  C  C  V  V  V  V  V

IO IN

59

PP3V3_AVCC_SMC MIN_LINE_WIDTH=0.25 MM

20% 10V 2 CERM 402

OUT

SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_SUS_CLK SMC_SMB_0_DATA

D

IN

R5801

1

10K

5% 1/16W MF-LF 2402

SMC_MD1

60

KBC_MDE

60

SMC_NMI

IN

SMC_TRST_L

IN

IN IO

P50

G4

1

AVSS VSS      1      4      4  2  3  3  3      4      4      2     D     P     R  1  1  1  1     A     B     D  F  F  B  A

P12 R12

C

NOSTUFF

R5898 1R5803 1R5802

1

10K 5%

1/16W MF-LF 2402

0 5%

10K 5%

1/16W MF-LF 2402

1/16W MF-LF 2402

OMIT

21 60 22 26 23 5 67 59 59 14 23 10 59 23

23 23 59 76 59 59 59 59

B

65 65 66 59 65

OUT IN IN OUT IN IO IO OUT IN OUT IN OUT IN OUT IN IN

OUT OUT OUT OUT IN

65 IN 66 59

59 59 59

IN IN IN IN IN

59 IN 59 59 59 59

IN IN IN IN

SMC_RCIN_L BOOT_LPC_SPI_L PM_SYSRST_L SMC_TPM_RESET_L PM_EXTTS_L<0> PM_THRM_L SYS_ONEWIRE PM_BATLOW_L SMC_EXTSMI_L SMC_RUNTIME_SCI_L SMC_ODD_DETECT ISENSE_CAL_EN SMC_EXCARD_CP SMC_EXCARD_PWR_EN SMC_EXCARD_PWR_OC_L SMC_XDP_TDO_3_3_L

 

R3

PA0/KIN8*/PA2DC

P3

PA1/KIN9*/PA2DD

R2

PA2/KIN10*/PS2AC

N3

PA3/KIN11*/PS2AD

R1

PA4/KIN12*/PS2BC

N2

PA5/KIN13*/PS2BD

M4

PA6/KIN14*/PS2CC

N1

U5800

SMC_H8S2116 BGA (2 OF 4)

PA7/KIN15*/PS2CD

PE0

M3

PE1*/ETCK

M2

PE2*/ETDI

M1

60 59 5

PE3*/ETDO

L4

60 59 5

PE4*/ETMS

L2

60 59 5

PF0/IRQ8*/PWM2

M7

PF1/IRQ9*/PWM3

P6

59 60 59 5

PF2/IRQ10*/TMOY R6

59

PF3/IRQ11*/TMOX N6

59

PF4/PWM4

M6

59

PB2

PF5/PWM5

R5

59

A11

PB3

PF6/PWM6

P5

59

B11

PB4

PF7/PWM7

C11

PB5

A12

PB6

D11

PB7

B10

PB0/LSMI*

A10

PB1/LSCI

D10

N5

59

PG0/EXIRQ8*/TMIX P9

63 22

PG1/EXIRQ9*/TMIY R9

59

PG2/EXIRQ10*/SDA2 N9

59

SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH

G14

PC0/TIOCA0/WUE8*

PG3/EXIRQ11*/SCL2 P8

59

G15

PC1/TIOCB0/WUE9*

PG4/EXIRQ12*/EXSDAA R8

59

G13

PC2/TIOCC0/TCLKA/WUE10* PG5/EXIRQ13*/EXSCLA M8

59

G12

PC3/TIOCD0/TCLKB/WUE11* PG6/EXIRQ14*/EXSDAB P7

59

H14

PC4/TIOCA1/WUE12*

SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH

H15 H13

PC5/TIOCB1/TCLKC/WUE13* PC6/TIOCA2/WUE14*

H12

PC7/TIOCB2/TCLKD/WUE15*

SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_ISENSE SMC_MEM_ISENSE ALS_LEFT ALS_RIGHT

PG7/EXIRQ15*/EXSCLB R7

59

PH0/EXIRQ6*

E1

59

PH1/EXIRQ7*

F3

59

PH2/FWE

K2

59

M11

PD0/AN8

PH3/EXEXCL

C4

59

P11

PD1/AN9

PH4

D4

26 23

R11

PD2/AN10

PH5

B3

59

N11

PD3/AN11

P10

PD4/AN12

R10

PD5/AN13

N10

PD6/AN14

M10

PD7/AN15

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_PF0 59 SMC_PF1 59 SMC_LID SMC_CPU_RESET_3_3_L SMC_BATT_ISET SMC_BATT_VSET SMC_SYS_ISET SMC_SYS_VSET SPI_CE_L SMC_XDP_TCK_3_3 SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP SMC_FWE ALS_GAIN SMS_INT_L SMS_ONOFF_L

IN

XW5800

IN

SM

IN

1

OUT

2

GND_SMC_AVSS

58 59 76 85

IN

IN IN OUT OUT OUT OUT IO IN IO

B

IO IO IO IO IO OUT OUT IN OUT OUT OUT

OMIT

U5800 SMC_H8S2116 BGA (4 OF 4)

A

SMC

G3

NC0

NC12

F15

H3

NC1

NC13

A14

K3

NC2

NC14

C12

L3

NC3

NC15

C10

N4

NC4

NC16

C5

M5

NC5

NC17

A3

N7

NC6

NC18

B8

M12

NC7

NC19

E4

M13

NC8

NC20

H4

L12

NC9

NC21

M9

K15

NC10

NC22

N8

J14

NC11

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

58

1

OF

13 110

A

 

8 59 58 6

6

7

2

3

4

5

SMC RESET BUTTON

=PP3V3_S5_SMC

1

SMC I2C BUS PULLUPS (INCLUDING UNUSED ONES) PP3V3_S0

76 61 41 26 11 10 6 88

C5901

1

0.1uF

2

20% 10V

2

R5900

1

CRITICAL

1K

5% 1/16W MF-LF 2 402

VDD

CERM 402

83 59 53 6

U5900

RN5VD30A-F SOT23-5

5

SMC_MANUAL_RST_L

4

D

C5900

DEVELOPMENT

SW5900 SM-LF

60 58

NO-CONNECT UNUSED PINS 58

3

58

10% 16V CERM 2 402

2

58 58 58 58 58

3

59 58 6

SMC_P20

NC_SMC_P20

SMC_P21 SMC_P22 SMC_P23

NC_SMC_P21 MAKE_BASE=TRUE NC_SMC_P22 MAKE_BASE=TRUE NC_SMC_P23

MAKE_BASE=TRUE

58 58 58 58 58

=PP3V3_S5_SMC

DEBUG TESTPOINTS ON SELECTED INPUTS/OUTPUTS 58

SMC_SYS_KBDLED

TP_SMC_SYS_KBDLED

58

SMC_PF0

TP_SMC_PF0

S MC _P M_ G2 _E N SMC_ADAPTER_EN

T P_ PM _G 2_ EN TP_SMC_ADAPTER_EN

58

ALS_LEFT

TP_ALS_LEFT

58

ALS_RIGHT

TP_ALS_RIGHT

MAKE_BASE=TRUE

SMC_P26 SMC_P27 SMC_BATT_ISET

NC_SMC_P26 MAKE_BASE=TRUE NC_SMC_P27 MAKE_BASE=TRUE NC_SMC_BATT_ISET

SMC_BATT_VSET SMC_SYS_ISET SMC_SYS_VSET

MAKE_BASE=TRUE NC_SMC_BATT_VSET NC_SMC_SYS_ISET MAKE_BASE=TRUE NC_SMC_SYS_VSET

58 58

MAKE_BASE=TRUE

4

AMBIENT LIGHT SENSOR CONNECTOR CRITICAL (REF DES PRESERVED FOR PLACEMENT PURPOSE) J2901 I2C ADDR:72(1001000)

1

 

 

2

R5903

SMB_B_S0_CLK

58 59

1

 

 

2

R5904

SMB_B_S0_DATA

58 59

2.2K

1

 

 

2

R5905

SMB_A_S3_CLK

58 59

2.2K

1

 

 

2

R5906

SMB_A_S3_DATA

58 59

2

R5910

SMB_BSB_CLK

58

2

R5911

SMB_BSB_DATA

58

SMC ALIASES, PULLUPS, AND TESTPOINTS

SMC_RST_L OUT

GND

1

0.01UF

SPST

1

OUT 1

CD NC

5

2.2K 2.2K

PP3V3_S3

58

SMC_PF1

MAKE_BASE=TRUE

1

 

10K

1

 

 

MAKE_BASE=TRUE

 FUNC_TEST=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

FUNC_TEST=TRUE

MAKE_BASE=TRUE

 FUNC_TEST=TRUE

MAKE_BASE=TRUE

 FUNC_TEST=TRUE

10K

1

 

 

2

R5912

10K

1

 

 

2

R5913

10K 10K

1

 

MAKE_BASE=TRUE

1

 

   

2

SMC_SMB_0_CLK

2

FUNC_TEST=TRUE

58

SMC_SMB_0_DATA

R5914 R5915

D

TP_SMC_SMB_0_CLK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_SMC_PF1

10K

 

58

TP_SMC_SMB_0_DATA

SMB_BSA_CLK

58

SMB_BSA_DATA

58

FUNC_TEST=TRUE

MAKE_BASE=TRUE

SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN 58SMC_ANALOG_ID 58 ALS_GAIN

NC_SMC_BATT_TRICKLE_EN_L MAKE_BASE=TRUE NC_SMC_BATT_CHG_EN MAKE_BASE=TRUE NC_SMC_ANALOG_ID MAKE_BASE=TRUE NC_ALS_GAIN

PULLUPS FOR SYSTEM STATE PINS SMC_PB7

59

TP_SMC_PB7 MAKE_BASE=TRUE

10K

 FUNC_TEST=TRUE

1

 

 

2

R5916

SMC_LID

58

MAKE_BASE=TRUE

PULLDOWNS FOR SYSTEM STATE PINS SMC_CASE_OPEN 10K 1     2 R5917

SMC 3.3V -> CPU 1.05V SHIFTER

53398-0476

58

F-ST-SM 5

PP3V3_S3

83 59 53 6

1

I2C_ALS_SDA I2C_ALS_SCL

59 59

2

59 7

CPU_PROCHOT_L

58

3

59

6 4

58

Q5901

D

58

SMC_PROCHOT

2

G

67 58

TP_SMC_EXCARD_PWR_EN  FUNC_TEST=TRUE MAKE_BASE=TRUE TP_SMC_PB7   FUNC_TEST=TRUE

SMC_FAN_3_TACH SMC_FAN_3_CTL

TP_SMC_FAN_3_TACH TP_SMC_FAN_3_CTL

ALIAS SENSORS INTO SMC I2C BUSSES 59 58

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

FUNC_TEST=TRUE

59 58

IO IO

SMB_B_S0_CLK SMB_B_S0_DATA

MAKE_BASE=TRUE MAKE_BASE=TRUE

 FUNC_TEST=TRUE

66

=I2C_HD_TEMP_SCL =I2C_HD_TEMP_SDA

66

=I2C_ODD_TEMP_SCL

66

=I2C_ODD_TEMP_SDA

10

=SMB_THRM_CLK

10

=SMB_THRM_DATA

66

10K

2

WIRE-OR DIMM OVERTEMP TO SMC

(REF DES PRESERVED FOR PLACEMENT PURPOSE) 21 14 7

J2903

29 28

PM_THRMTRIP_L

DIMM_OVERTEMP_L

SMC PULL-UPS

PM_EXTTS_L<0>

14 58

MAKE_BASE=TRUE

53398-0276

Q5901

D

59 58 6

58

GPUVCORE_IOUT

SMC_GPU_ISENSE

MAKE_BASE=TRUE

85

59 58

2N7002DW-X-F

SMC_THRMTRIP

58

SOT-363

5 58

1

G

2

=PP3V3_S5_SMC 5% 1/16W MF-LF 402

SENSE GPU REGULATOR OUTPUT CURRENT

3

M-ST-SM 3

POWER_BUTTON_L

R58271

SMC_TPM_RESET_L

SMC_EXCARD_PWR_EN SMC_PB7

1

POWER BUTTON HEADER

5

PP3V3_TPM_3VSB

67

SOT-363

S

518S0328

C

TPM RESET PULLUP

2N7002DW-X-F

6

58

S

58 58

4

SMC_ODD_DETECT

R5808 R5829

SMC_EXCARD_CP SMC_EXCARD_PWR_OC_L

R5830 R5831

SMC_ONOFF_L

   

1 1 1 1

2

10K 10K

2 2

10K 10K

2

59 58 59 58

IO IO

SMB_A_S3_CLK SMB_A_S3_DATA

 

IO IO

59

C

IO IO IO

I2C_ALS_SCL I2C_ALS_SDA

59

MAKE_BASE=TRUE

IO

IO

SMB_GPU_NB_THRM_CLK SMB_GPU_NB_THRM_DATA

61 61

IO

MAKE_BASE=TRUE

IO IO

NOT_DEVELOPMENT_SMC

WIRE SMC TO SB PINS

4

R5907

518S0327

SYS POWER BUTTON

GENERATE 0.48V MID-VREF SMC_ONOFF_L

2

58

58

R5930

C5902

1

20% 10V 20% 10V

2

58

6.2K

0.1uF

2

CERM 402

P0V48_SMC_LSREF

59

2

1K

C6704

C5800 1

SMC_XTAL

2

CERM 5% 50V 402

1

UNUSED_SMC_SENSE

MAKE_BASE=TRUE

OMIT

 

SMC_EXTAL 58

2

1

 

2

59 58

SC_TX_L

0

1

 

2

58

SMC_TPM_GPIO

R5995

CRITICAL

 

  1 0 5% SMC_TPM_PP1/16W

TPM_XTALO 67

DESIGNATOR(S)

1

0

SMC_TPM_PP

1

0

2

TIE ANALOG SENSOR OPAMP GROUNDS TO SMC GROUND

SMC_TX_L SMC_RX_L SYS_ONEWIRE SMC_BS_ALRT_L SMC_TMS SMC_TDO

58

SMC_TDI SMC_TCK SMC_BC_ACOK

58

SMC_FWE

60 58 5

1

10K 10K 10K 100K 10K 10K 10K 10K 10K 10K 10K 10K

2

 

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

PCB: RUN A TRACE FROM EACH ANALOG OPAMP PSEUDO-DIFFERENTIALLY NEXT TO THIS GND TRACE AND TIE INTO DIGITAL GND VERY CLOSE TO SMC’S XW5800. PLACE XW5900 NEAR XW5800.

XW5900 SM

GND_NEXT_TO_SMC

1

2

R5922

SMC_RX_L

5 58 59 60

DEVELOPMENT_SMC

R5923

SMC_TX_L

B

SENSE GPU VCORE

5 58 59 60

R5919 2

R5920

88

TPM_GPIO1

4.53K2 1

PP1V0R1V2_S0_GPU

2

R5921

TPM_GPIO2

SMC_GPU_VSENSE

1% 1/16W MF-LF 402

67

SMC_TPM_GPIO2

1

58

C5919 0.22UF

20% 6.3V 2 X5R 402

67

MF-LF 402

GND_SMC_AVSS

TPM_PP

58 59 76 85

67

5% 1/16W MF-LF 402

TABLE_5_HEAD

REFERENCE

R5924

SMC_TPM_GPIO1

32.768K

SM-LF

402 50V 5% C ERM

D E SC R IP TI O N

60 58 5 60 58 5

R5833 R5815 R5817 R5818 R5819 R5821 R5822 R5823 R5824 R5825 R5826 R5828

SC_TX_L SMS_ONOFF_L

5% 1/16W MF-LF 402

SELECT TPM GPIO

10K

2

DEVELOPMENT_SMC

1  

58

QTY

2

0

 Y6700

2

58 60 58 5

59

5% 1/16W MF-LF

SC_RX_L

 4

15PF

CERM 5% 50V 402

 

1

 1

C6705

2

22PF

P A RT #

10K

UNUSED_SMC_SENSE

59 58

CRITICAL

58

MAKE_BASE=TRUE

TPM_XTALI 67

2

5% 50V CERM 402

20.000M Y5800 SM-3

C5801 1

1

58

60 59 58 5

SMC_FWIRE_ISENSE

15PF

22PF

58

MAKE_BASE=TRUE

PULLDOWN UNUSED ANALOG SENSE PINS ON PORT 7.

SC_RX_L

1

NOT_DEVELOPMENT_SMC

59 58

60 59 58 5

58

59

LAYOUT NOTE: PLACE CAPACITORS BETWEEN CRYSTAL AND SMC/TPM

B

23

MAKE_BASE=TRUE

NC_SMS_X_AXIS MAKE_BASE=TRUE NC_SMS_Y_AXIS

58

58

5% 1/16W MF-LF 2 402

TPM CRYSTAL

21 60

SUS_CLK_SB

MAKE_BASE=TRUE

SMC_SUS_CLK SMS_X_AXIS SMS_Y_AXIS

NC_SMS_Z_AXIS MAKE_BASE=TRUE NC_SMC_NB_ISENSE MAKE_BASE=TRUE NC_SMC_MEM_ISENSE MAKE_BASE=TRUE UNUSED_SMC_SENSE 59

58

R5931

4

59 58

FWH_INIT_L

SMS_Z_AXIS SMC_NB_ISENSE SMC_MEM_ISENSE SMC_BATT_ISENSE

58

5% 1/16W MF-LF 402

1

SMC CRYSTAL

SMC_CPU_INIT_3_3_L

NC OR PULLDOWN UNUSED ANALOG SENSE PINS

=PP3V3_S0_FAN 1

DEVELOPMENT

3

OUT 65 59 6

66

5% 1/16W MF-LF 402

SPST

1

1K

1

SW5901 SM-LF

58

R5832

BOM OPTION TABLE_5_ITEM

197S0 165

1

XTAL,20.00,80PPM,HC49,SMD,LF

80 79 77 76 66 65 26 11 6 5 66 65 59 6

Y5800

PP3V3_S5

83 81

=PP3V3_S0_FAN 1

2

1 1

R5932

20% 10V 20% 10V CERM 402

V+

A

2

LM393A

6

CPU_PROCHOT_L

5

GND 4

LM393A

V+

SOI-1-LF

U5999 3

5% 1/16W MF-LF 402

PRECISION 3.3V AVREF FOR SMC

=PP3V3_S5_SMC 83 81 80 79 6 5

PP5V_S5

58

1

R5942 10K Q5910 5%

2

SMC_PROCHOT_3_3_L 58

1/16W MF-LF 402

NTR4101P

R5933

1

1K

1K

1

10K

5% 1/16W MF-LF 402

2 402

58

2N7002

1

2

G

SOT23-LF

S

NOSTUFF

59 58 6

GND

CRITICAL

3

REF3133

C5943 1UF

2

P AR T N UM BE R

ALTERNATE FOR PART NUMBER

B OM O PT IO N

1

TABLE_ALT_ITEM

3 5 3 S1 3 81

3 5 3 S1 2 78

U5940

DONE IN M50/M51

IN

TI   GND

TURN ON 3.3V VREF ONLY AFTER SMC 3.3V RAIL AND AVCC RAIL IS UP.

10UF

20% 6.3V CERM 2 805-1

7

6

5

4

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

MIN_NECK_WI DTH=0.2 MM V OLTAGE=3.3V

1

C5941

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

0.01uF

20% 16V 2 CERM 402

SIZE

GND_SMC_AVSS MIN_LINE_WI DTH=0.4 MM MIN_NECK_WI DTH=0.2 MM VOLTAGE=0V

8

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

PP3V3_AVREF_SMC 58 2

C5940 C5942 1

10% 6.3V 2 CERM-X5R 402

A

NOTICE OF PROPRIETARY PROPERTY

MIN_LINE_WI DTH=0.4 MM

OUT

3

0.47UF

REF DES   COMMENTS:

PCB: ENSURE FSB_CPURST_L FANS OUT FROM U1200 AND MINIMIZE ROUTE LENGTH TO U5999.

1

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDT=0.2 MM

2

5% 1/16W MF-LF 402

SOT23-3

SMC_REF_IN 1

0

1

U5940

TABLE_ALT_HEAD

4

=PP3V3_S5_SMC

D

10% 2 6.3V CERM 402

1

SMC & TPM SUPPORT

R5940

S G

Q5911

D

R5941

SMC_XDP_TDO_3_3_L 58

2

5% 1/16W MF-LF 402

SMC_CPU_RESET_3_3_L

3

  2

SOT-23

MIN_LINE_WID TH=0.4 MM MIN_NECK_WID TH=0.2 MM

SMC_REF_GATE1

R5935

1

5% 1/16W MF-LF

8 2

SMC_XDP_TCK_3_3

2

SMC_REF_GATE2 1

SOI-1-LF 7

U5999 59 7

1K

5% 1/16W MF-LF 402

1K

8

P0V48_SMC_LSREF

59 58 6

R5934

C5903

0.1uF

59

CRIT ICAL

CPU 1.05V -> SMC 3.3V SHIFTER

3

APPLE COMPUTER INC.

051-7148

SCALE

58 59 76 85

SHT NONE

2

REV.

DRAWING NUMBER

D

13

OF 59

1

110

 

8

6

7

6

1

=PP3V3_S5_DEBUG DEVELOPMENT

DEVELOPMENT 1

C6000 1UF

10% 6.3V 2 CERM 402

D

6

2

3

4

5

1

C6001 0.1UF

20% 10V 2 CERM 402

D

=PP5V_S0_DEBUG DEVELOPMENT 1

C6002 1UF

10% 6.3V 2 CERM 402

DEVELOPMENT 1

C6003 0.1UF

20% 10V 2 CERM 402

DEVELOPMENT

J6000

F-ST-5047 SM1

67 58 21 67 58 21

67 58 21 67 58 44 23 5 58 22

C

LPC_AD<0> LPC_AD<1> LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L 59 58 5

6

SMC_TMS

DEBUG_RST_L SMC_TRST_L SMC_TDO 58 SMC_MD1 SMC_TX_L 5 58 58 5

59 58 5

59

PP5V_S3 PLACE C5951 NEXT TO Q5952

NOSTUFF 1

1

R5955

B

4.7K

R5951

C5951

2.2K 5% 1/16W MF-LF 402

5% 1/16W MF-LF

2 402

2

SOT23-LF

S

R5957

2

0

1/16W MF-LF 5% 402 1 2

SMC_SYS_LED_16B

1

0

 

5% 1/16W MF-LF 402

2

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L

21 59 34

21 58 67 21 58 67

23 58 67 23 58 67

C

5 58 59 5 58 59

58 59 58 5 58 59

SV_SET_UP 23

6 83

B

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

Q5952

2N3906 SOT23-LF

3

5% 1/16W MF-LF 402

SYS_LED_C MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

SYS_LED_CTL_D

3

Q5950

D

R5990 58

10

LPC_AD<2> LPC_AD<3>

1% 1/16W MF-LF

1

2

R5991 SMC_SYS_LED

9

FWH_INIT_L PCI_CLK_PORT80

2 402

2

SYS_LED_CTL_B

4.7K

58

8

36 2

NOSTUFF

Q5951 2N7002

G

6

SYS_LED_CTL_C 3 D

1

4

7

R5952

SYS_LED_BRT_D

NOSTUFF

2

5

1 1

1UF

10% 6.3V CERM 402

1 3

2N7002 Q5950_1 1

G

NOSTUFF 1

R5950

SOT23-LF

S 2

1

5% 1/16W MF-LF 2 402

CRITICAL

LED5950

WHITE-740MCD

4.7K

3X2MM-SM1

2

LPC+ CONN

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

0 51 51 -7 -7 14 14 8

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

OF

13

60   110

1

A

 

8

7

6

3

4

5

2

1

D

D

R6102 1

0

2

ATI_TDIODE_N

91

ATI_TDIODE_P

91

5% 1/16W MF-LF 402

R6101 1

0

2

5% 1/16W MF-LF 402

C

C

R6100 U6100_VCC

47

1

2

PP3V3_S0

6 10 11 26 41 59 76 88

5% 1/16W MF-LF 402

 1

VCC

U6100

MAX6695AUB UMAX

TSENSE_GPU_DXP 1

C6100

2 DXP1

SMBDATA

9

SMB_GPU_NB_THRM_DATA

3 DXN 4 DXP2

SMBCLK

7

SMB_GPU_NB_THRM_CLK

ALERT*

8

OT1*

5

OT2*

10

59

59

0.001UF 2

NOSTUFF

20% 50V CERM 402

TSENSE_NB_GPU_DXN

GND

CRITICAL

J3

1

SM-2MT-BLK-LF

CRITICAL

C6101

 6

0.001UF

3

20% 50V 2 CERM 402

1

TSENSE_NB_DXP

2

I2C ADDR:30(0011000) 4

B

B

GPU+NB THERMAL

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

61

1

OF

13 110

A

 

8

6

7

2

3

4

5

1

D

D 6

=PP3V3_S5_ROM 1

R63021

R63011

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 402 2

3.3K

C6312 0.1UF 20%

3.3K

R63991

2 CERM 10V

8

10K

5% 1/16W MF-LF 402 2

402

OMIT

VDD

U6301 16MBIT

R6307 58 22

58 22

SPI_SCLK

1

47

SPI_SCLK_R

2

C6309 33PF 5% 50V

2 CERM

402

1

C6308

SPI_HOLD_L

R63091 10K

5% 1/16W MF-LF 402 2

33PF

5% 50V 2 CERM 402

1

SPI_WP_L

NOSTUFF 1

R6306

SOI

SI

SCK

5

SPI_SI_R

SST25VF016B

5% 1/16W MF-LF 402

SPI_CE_L

6

3 7

CE* WP* HOLD*

SO

2

SPI_SO_R

1

47

5% 1/16W MF-LF 402

VSS R6309 NOT NEEDED SINCE SPI ROM

1

47

2

1

C6301 33PF

4

5% 50V

IS SHARED WITH SB AND SMC

2

5% 1/16W MF-LF 402

R6303

2 CERM

402

1

SPI_SI

22 58

SPI_SO

22 58

C6311 33PF 5% 50V

2 CERM

402

C

C R6306-07 SHOULD BE PLACED LESS THAN 2.54MM FROM U2100 R6303 SHOULD BE PLACED LESS THAN 2.54MM FROM U6301

B

B

SPI BOOTROM SYNC_MASTER=MASTER

A

SYNC_DATE=5/23/05

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

63

1

110

A

 

8

6

7

2

3

4

5

1

FAN 0 66 65 6

=PP12V_S0_FAN

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

R6502

1

1.5K

R6506

1

5% 1/4W MF-LF 2 1206

10K

5% 1/16W MF-LF 2 402

D

NOSTUFF

R65031

1

1.5K

20% 25V 2 CERM 603

R6505

F0_VOLTAGE8R5

C6500 0.1UF

5% 1/8W MF-LF 8052

3.9K

5

D

M38: ODD FAN

F0_GATESLOWDN

Q6500

4

5% 1/8W MF-LF 805

NTHS5443T1 1206A-03-LF CRITICAL  1 2 3

1 58

IN

SMC_FAN_0_CTL

FAN_RPM0

Q6502

D

2N7002

1

G

J6500 53261-0498

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

R6512 1.0K

66 65 59 6

D6502 SMB

R6504

NOSTUFF 1

2

0

2

1

FAN_0_OUT MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM

5% 1/8W MF-LF 805

MMBD914XXG

1

47K

CRITICAL

C6504

1

MOTOR CONTROL

2

TACH

3

GND

4

12V DC

120UF

2

20% 2 16V ELEC 6.3X11-TH-LF1

6

518S0193

5% 1/16W MF-LF 2 402

R6599 SMC_FAN_0_TACH

1

5% 1/8W MF-LF 805

10K

OUT

0

1

SOT23

1

58

FAN_0_PWR

R6515

D6500 1

R6500

MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM

2

B130LBT01XF

3

5% 1/8W MF-LF 2 805

=PP3V3_S0_FAN

M-RT-SM 5

NOSTUFF

F0_RCFEEDBK 1

SOT23-LF

S

C6501 0.47UF

10% 16V 2 X7R 805

3 CRITICAL

 6 7 8

2

FAN_TACH0

5% 1/16W MF-LF 402

C

NOTE:

C

ADDED TO PROTECT SMC

FAN 1 66 65 6

=PP12V_S0_FAN

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

R6511

1

10K

R6510

1

5% 1/16W MF-LF 2 402

1.5K

5% 1/4W MF-LF 2 1206

NOSTUFF

R65071 R6509

F1_VOLTAGE8R5

3.9K

IN

SMC_FAN_1_CTL

0.1UF

10% 16V 2 X7R 805

Q6505 2N7002

1

G

F1_RCFEEDBK

SOT23-LF MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

S

NOSTUFF

R6513

1 2

1.0K

5% 1/8W MF-LF 2805

R6501

1

10K

CRITICAL

C6503

B

J6501

0.47UF

=PP3V3_S0_FAN

M38: HD FAN

1206A-03-LF

3 CRITICAL D

Q6503

4

NTHS5443T1

FAN_RPM1

66 65 59 6

5

F1_GATESLOWDN

1 58

C6502

20% 25V 2 CERM 603

5% 1/8W MF-LF 805 2

5% 1/8W MF-LF 805

B

1

1.5K

 1 2 3

 6 7 8

0

5% 1/8W MF-LF 805

M-RT-SM

D6503 SMB

R6508 1

53261-0598

NOSTUFF

2

1

FAN_1_OUT MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

3

D6501 MMBD914XXG

1

R6514 0

5% 1/8W MF-LF 805

5% 1/16W MF-LF 2 402

FAN_1_PWR

B130LBT01XF

1

SOT23

2

6 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

2

CRITICAL 1

C6505

1

MOTOR CONTROL

2

TACH

3

GND

4

12V DC

5

120UF

20% 2 16V ELEC 6.3X11-TH-LF1

7

518S0326

R6598 58

OUT

SMC_FAN_1_TACH

1

47K

2

FAN_TACH1

5% 1/16W MF-LF 402

Fan 0, 1 & System Temp

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

SCALE

7

6

5

4

3

2

051-7148 13 65 11 110 0 SHT

NONE

8

REV.

DRAWING NUMBER

D

OF

1

 

8

6

7

2

3

4

5

1

FAN 2 65 6

=PP12V_S0_FAN

D

D

80 79 77 76 65 59 26 11 6 5 PP3V3_S5 83 81

1

R6605

1

R6604

10K

R66011

1

5% 1/8W MF-LF 805 2

2

1.5K

1.5K

5% 1/16W MF-LF 402

5% 1/4W MF-LF 2 1206

2

NOSTUFF

C6600 0.1UF 20% 25V

CERM 603

5

R6603 F2_VOLTAGE8R5

3.9K

F2_GATESLOWDN

58

IN

SMC_FAN_2_CTL

FAN_RPM2

NTHS5443T1

Q6600

CRITICAL 1

10% 16V 2 X7R 805

Q6602

D

2N7002

1

G

F2_RCFEEDBK MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

SOT23-LF

S

NOSTUFF

1

R6606

2

1.0K

65 59 6

J6600

C6601 0.47UF

3

M38: CPU FAN M39: HD FAN

1206A-03-LF

4

5% 1/8W MF-LF 805

=PP3V3_S0_FAN 2

5% 1/8W MF-LF 805

 1 2  3

D6601 SMB

R6602 1

0

5% 1/8W MF-LF 805

1

FAN_2_OUT

2

53398-0476

NOSTUFF

 6  7  8

F-ST-SM 5

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

2

FAN_2_PWR

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM 1

D6600 1

CRITICAL

B130LBT01XF

3

220UF

R6607

MMBD914XXG SOT23

1

0

C6602

20% 2 16V ELEC SM-LF

2

R6600 10K

MOTOR CONTROL

2

TACH

3

GND

4

12V DC

6

5% 1/8W MF-LF 805

1

1

518S0328

5% 1/16W MF-LF

C

C

2 402 FAN_TACH2

R6697 58

OUT

SMC_FAN_2_TACH

1

47K

2

5% 1/16W MF-LF 402

HD TEMP SENSOR 6

ODD TEMP SENSOR

=PP3V3_S0_HD_TSENS 6

B

17_INCH_LCD

CPU_HS_ZH608

2 20% 16V

17_INCH_LCD

J6601

0.01UF

66 9

=PP3V3_S0_ODD_TSENS

CRITICAL

C6650 CERM 402

66 9

CPU_HS_ZH608

=I2C_HD_TEMP_SDA

2

59

=I2C_HD_TEMP_SCL

3 4

I2C ADDR:0X92(1001001)

0.1UF

20% 10V CERM 2 402

59

=I2C_ODD_TEMP_SDA

2

59

=I2C_ODD_TEMP_SCL

3

I2C ADDR:0X90(1001000)

2

1 CERM 402

C6655

1

0.1UF

20% 10V CERM 2 402

6

17_INCH_LCD

518S0193

C6653

0.01UF 20% 16V

M-RT-SM 5

4

6

C6651 CPU_HS_ZH608

53261-0498

1

1

C6654 1

17_INCH_LCD

66 9

2

20%   CERM 402 16V

1 59

J6602

0.01UF

M-RT-SM 5

B

CRITICAL

C6652

53261-0498

1

518S0193

0.01UF

66 9

CPU_HS_ZH608

2

1

20% 16V

CERM 402

Fan 2 & HD Temp

A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

66

1

OF

13 110

 

8

6

7

2

3

4

5

1

D

D

67 6

=PP3V3_S0_TPM

1

C6700 0.1UF

10% 16V 2 X5R 402

1

C6701 0.1UF

10% 16V 2 X5R 402

1

NOSTUFF

C6702

R6705

60 58 21 60 58 21 60 58 21

=PP3V3_S0_TPM

60 58 21

NOSTUFF

34

1

R6700

IO

26

LPC_AD<1>

23

LAD1

TPM

LPC_AD<2>

20

LAD2

TSSOP

LPC_AD<3>

17

LAD3

IN

PCI_CLK_TPM

IN

LPC_FRAME_L

60 58 23 60 58 23 60 58 44 23 5

59

IN IO IO

LAD0

21

LCLK

22

LFRAME*

16

5% 1/16W MF-LF 2 402

PLACE WHERE ACCESSIBLE

U6700

LPC_AD<0>

IO

0

LAYOUT NOTE:

C

60 58 21

IO

IO

2

3V0

10

3V1

19

VDD VDD

3V2

R6704

24 5

VNC

3

59

VSB

NC

VBAT

LRESET*

28

LPCPD*

INT_SERIRQ

27

SERRIRQ

PM_CLKRUN_L

15

CLKRUN/GPIO*

12

59

TPM_GPIO1

59

TPM_GPIO2

NC

1

PP/GPIO

6

GPIO_EXPRESS_00

1

GPIO/SM_DAT

2

NC GPIO/SM_CLK

(INT PD)

2

PP

TPM_XTALI

13

XTALI/32K_IN

59

TPM_XTALO

14

XTALO

10% 16V 2 X5R 402

R6702

5% 1/16W MF-LF 402

0

2

=PP3V3_S3_TPM

6

5% 1/8W MF-LF 805

C

BASE ADDR = 0X4E/4F

GPIO

59

C6703

10K

7

GPIO2

1

NC

CLKRUN*

TPM_PP

1

PP3V3_TPM_3VSB VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

NC

0.1UF

NC

PM_SUS_STAT_L

ON SPEC,

1/8W (R6704/R6705) IS USED FOR NOW

5% 1/8W MF-LF 805

VDD

3VSB

SINCE CURRENT OF VSB IS NOT YET

0

OMIT

67 6

NOTE:

1

0.1UF

10% 16V 2 X5R 402

LAYOUT NOTE: TESTBI/BADD/GPIO TESTBI/BADD TESTI

9 8

TPM_BADD

PLACE R6702-03 WHERE ACCESSIBLE NOSTUFF 1

GND      0      1      2      3     D     D     D     D     N     N     N     N      G      G      G      G

R6703

10K

 4      1      8      5      1      1      2

2

5% 1/16W MF-LF 402

BASE ADDR = 0X2E/2F

R6798 6

IN

TPM_LRESET_L

1

0

2

5% 1/16W MF-LF 402

TPM_RST_L NOSTUFF

B

B

R6799 59 58

IN

SMC_TPM_RESET_L

1

0

2

5% 1/16W MF-LF 402

TPM

A

SYNC_MASTER=N/A

SYNC_DATE=N/A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

67

1

OF

13 110

A

 

8

6

7

2

3

4

5

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=4.5V

AUDIO CODEC

PP4V5_AUDIO_ANALOG

APPLE P/N 353S1458 FERR-120-OHM-1.5A

VOLTAGE=3.3V 74 73 72 68 6

=PP3V3_S0_AUDIO

1

68 74

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

L6801

D

1

D

PPV_3V3_AUDIO_CODEC

2 0402-LF

C6800 1

1

20% 6.3V X5R 603

21 21 21

IN IN IN

C6801 1000PF

10UF

10% 25V 2 X7R 402

2

1

C6835 1000PF

ACZ_BITCLK ACZ_SYNC ACZ_SDATAOUT

R6807 21

OUT

ACZ_SDATAIN<0>

22

1

BIT_CLK SYNC

2

SDATA_OUT 10

5% 1/16W MF-LF 402 68 72 74

72 72

ACZ_SDATAIN_CHIP

     1     E     R      O      C _     D     D     V     D

     3     E     R      O      C _     D     D     V     D

GPIO2

74 74

C

STAC92204XR

SENSE_B

AUD_BI_PORT_C_L AUD_BI_PORT_C_R

PORT-C_L

CRITICAL

GND_AUDIO_CODEC

AUD_SPDIF_OUT_CHIP

1

22

68 72 73 74

AUD_SPDIF_OUT 73

2

5% 1/16W MF-LF 402

AUD_SPDIF_IN 73 AUD_SENSE_A 74

PORT-D_L_HP PORT-D_R_HP

AUD_BI_PORT_F_L AUD_BI_PORT_F_R

PORT-F_L_HP

LO

12

AUD_SENSE_B AUD_BI_PORT_A_L AUD_BI_PORT_A_R

PORT-A_R_HP

10

PORT-C_R

PORT-F_R_HP

15

MIC1

74 74

74 74

NC_AUD_VREF_PORT_A NC NC_AUD_BI_PORT_E_L NC NC_AUD_BI_PORT_E_R NC

VREFOUT-A

13

74

PORT-E_L PORT-E_R

CD-L CD-G10

AUD_VREF_PORT_B AUD_BI_PORT_B_L AUD_BI_PORT_B_R

VREFOUT-B

MIC2

CD-R

PORT-B_L PORT-B_R

74 68 74

C

68

VOLUME_UP

BEEP

VOLUME_DOWN

VREFOUT-C

PC_BEEP

VREFOUT-D

10

NC_AUD_VREF_PORT_C NC NC_AUD_VREF_PORT_D NC AUD_VREF_FILT AUD_ANALOG_FILT_1 AUD_ANALOG_FILT_2 AUD_BYPASS

VREF_FILT RESET*

ACZ_RST_L

AFILT1 AFILT2

1

R6800 100K

2

5% 1/16W MF-LF 402

1

CAP2

C6821 0.1UF

     3      2      S      S      S      S     V     V     D     D

10% 16V 2 X5R 402

AUD_NC_40 AUD_NC_43

NC1

     1      3      S      S      S      S     V     V     A     A

NC2

1

1000PF

OMIT

1

C6812

10% 25V 2 X7R 402

XW6801 SM 74 73 72 68

10% 25V 2 X7R 402

PORT-A_L_HP

HP

11

IN

C6836 1000PF

20% 16V 2 ELEC 6.3X5.5-SM

SPDIF-OUT

GPIO1

NCNC_VOL_UP NCNC_VOL_DOWN

21

1

100UF

GPIO3/SPDIFIN SENSE_A

GPIO0

BAL_IN_L BAL_IN_COM BAL_IN_R

C6803 1

R6808

14 74

10% 25V 2 X7R 402

1000PF

LQFP

AUD_GPIO_2 AUD_GPIO_0 AUD_GPIO_1

NCNC_AUD_BI_PORT_D_L NCNC_AUD_BI_PORT_D_R

1

20% 16V 2 ELEC 6.3X5.5-SM

     1     D     D      2     D     D     V     V     A     A

U6800

SDATA_IN 10

C6830

C6802 1 100UF

10% 25V 2 X7R 402

C6806 820PF

5% 50V 2 CERM 805

1

C6813

1

10% 25V 2 X7R 402

C6805 1

C6807 1

C6810 1

20% 6.3V  2 TANT SMA-LF

5% 50V CERM 2 805

20% 6.3V 2 TANT SMA-LF

20% 6.3V  2 TANT SMA-LF

820PF

C6833 1000PF

1000PF

10% 25V 2 X7R 402

C6804 1 10UF

2

1

10UF

10UF

GND_AUDIO_CODEC MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM VOLTAGE=0V

B

74 68

AUD_BI_PORT_B_L

AUD_BI_PORT_B_R

B

68

MIC INPUT TO BOTH L&R 68

AUD_GPIO_2

 

1

R6815

4.5V POWER SUPPLY FOR CODEC APN: 353S1455

10K

5% 1/16W MF-LF 2 402

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

L6800

FERR-120-OHM-1.5A

6

1

=PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

VR6800

MAX1819EBL33-T UCSP

2

5V_REG_IN

A1

IN

A3

SHDN*

0402-LF

 

=PP3V3_S0_AUDIO

1

1K

1% 1/16W MF-LF 402

2

A

126S0091

126S0092

B OM O PT IO N

R6810 78.7K

POK A2  3  C

C6822

2 NOSTUFF

10UF

C6823 0.1UF

DZ6800 POWERDI-123 DFLS140

1

2

VREG_FB

REF DES   COMMENTS:

74 73 72 68

1% 1/16W MF-LF 402

1

68 74

C6825 15PF

5% 50V 2 CERM 402

1

C6826 10UF

20% 6.3V 2 X5R 603

NC_VREG_POKNC

1

10% 16V X5R 2 402

TABLE_ALT_HEAD

ALTERNATE FOR PART NUMBER

PP4V5_AUDIO_ANALOG

NO STUFF 1

GND

AUD_4V5_SHDN_L 1

20% 6.3V 2 X5R 603

P AR T N UM BE R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=4.5V

SET C2

R6802 74 73 72 68 6

OUT C1

CRITICAL

1

R6811 29.4K

2

GND_AUDIO_CODEC

1% 1/16W MF-LF 402

AUDIO: CODEC SYNC_MASTER=FINO-SO

SYNC_DATE=04/28/2005

TABLE_ALT_ITEM

 

C6802,C6803

NOTICE OF PROPRIETARY PROPERTY

FACTORY SHORTAGE TABLE_ALT_ITEM

126S0091

126S0092

C7403,C7404

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

FACTORY SHORTAGE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF

68

1

110

A

 

8

6

7

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V

D

6

=PP12V_S0_AUDIO_SPKRAMP

1

1

SPEAKER AMP

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V

L7200

FERR-250-OHM

2

3

4

5

APPLE P/N 353S0680

PP12V_AUD_SPKRAMP_PLANE

2

D

SM-1

C7217 1

C7200 1

20% 16V 2 ELEC 6.3X8-SM

20% 16V 2 ELEC 6.3X8-SM

L7205

AUD_BI_PORT_C_L

1

1

100PF

1

10K

1% 1/16W MF-LF 2 402

0.47UF 1

0603

L7207

C7206

1K-OHM-100MA

0.47UF

AUDSAMPINRP

2

1

0603

1

C

2

 

5% 50V 2 CERM 402

L7208

AUD_BI_PORT_C_R

1

C7207

AUDSAMPINRN

0603

10K

1

1

R7212 10K

 2

5% 1/16W MF-LF 402

100

2

17 G1 18 G2

AUD_SAMP_FS1 AUD_SAMP_FS2

19 FS1 20 FS2

AUD_SAMP_SHDN_L 11 NC

1

5

C7221

G

SOT-363

S

R7216

G

MIN_NECK_WIDTH=0.15MM

C7203 10UF

10% 16V 2 CERM 1210

1

C7223 10UF

10% 16V 2 CERM 1210

72 74

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7201

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

180-OHM-1.5A

AUDSAMPOUTLP

1

AUD_SPKR_OUTL_P

2

73

0603-LF

CHOLD 7

OUTL- 29 OUTL- 30

U7200

C1+ 6

C1- 5

AUDSAMPCPN

AUD_SPKR_OUTL_N

2

73

0603-LF

C7208 0.1UF

10% 50V 2 X7R 603-1

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

OUTR- 25 OUTR- 26

8 NC

1

AUDSAMPCPP

OUTR+ 27 OUTR+ 28

SHDN*

180-OHM-1.5A

AUDSAMPOUTLN

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

QFN-LF

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7202

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM 1

MAX9714

THM AGND PAD      3      1

     3      3

 1

PGND

AUDSAMPOURTP

 2

     3      2

SS 12

C NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7203

180-OHM-1.5A 1

SPKRAMP_MUTE

0

1

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

     4      2

AUDSAMPOUTRN

R7217

AUD_SPKR_OUTR_P

2

73

180-OHM-1.5A 1

5% 50V 2 CERM 402

73

SPKRAMP_SS

2

1

C7210 1000PF

1 1

AUD_SPKR_OUTR_N

2 0603-LF

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

1

100PF

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7204

5% 1/16W MF-LF 402

SOT-363

S

0.1UF

20% 16V 2 CERM 603

1

GND_AUDIO_SPKRAMP_PLANE

 D  L  O  H  C _  4  1  7  9  X  A  M _  D  U  A

OUTL+ 31 OUTL+ 32

AUD_MAX9714_VREG MIN_LINE_WIDTH=0.2MM 14 REG

2N7002DW-X-F

2

 

4

C7219

0603-LF

NOSTUFF

1

Q7200

D

2N7002DW-X-F

AUD_DEBOUNCE

 1

AUD_SAMP_G1 AUD_SAMP_G2

0

Q7200

D

1% 1/16W MF-LF 402

15 INR-

2

6

3

R7213 AUD_GPIO_0

AUD_SAMP_INR_N

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 402

68

1 10% 16V X7R 805

PP3V3_INTERCON

2

16 INR+

72

R7215 =PP3V3_S0_AUDIO

10 INL+

72

0.47UF

2

AUD_SAMP_INL_P

72

VDD

9 INL-

AUD_SAMP_INR_P

72

10% 16V X7R 805

C7216 100PF

1K-OHM-100MA

     1      2      2      2

 3  4

AUD_SAMP_INL_N

2 10% 16V X7R 805

GND_AUDIO_CODEC

1

R7214

C7205

AUDSAMPINLP

2

74 6 68 72 73

1

5% 50V 2 CERM 402

L7206

1K-OHM-100MA

74 73 72 68 6

 M  M  M  M  3  2  .  .  0  0  =  =  H  H  T  T  D  D  I  I  W  W __  E  K  N  C  I  E  L  N __  N  N  I  I  M  M

2 10% 16V X7R 805

C7215

1

10% 35V 2 X7R 805

2

=PP3V3_S0_AUDIO

0.47UF

AUDSAMPINLN 1

68

20% 16V CERM 603

C7202 1UF

0.1UF

10% 16V CERM 2 1210

C7204

2 0603

74 73 72 68

1

GND_AUDIO_SPKRAMP_PLANE

1K-OHM-100MA 68

C7218 1

1

10UF

220UF

220UF

74 72

C7201

10% 25V 2 X7R 402

C7209

1

C7211 1000PF

10% 25V 2 X7R 402

1

C7212 1000PF

10% 25V 2 X7R 402

1

C7213 1000PF

10% 25V 2 X7R 402

0.47UF

C7214

10% 16V 2 X7R 805

1UF

10% 25V 2 X5R 603

NOSTUFF

R7219 1

B

74 73 72 68

0

XC7200 50R28

2

5% 1/16W MF-LF 402

GND_AUDIO_CODEC

 1

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

XW7201 SM

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

B

OMIT

1

GND_AUDIO_SPKRAMP_PLANE 72 GND_AUDIO_SPKRAMP_PLANE

2

GND_AUDIO_SPKRAMP

6 74

74

72 74

GAIN SETTINGS: +19DB MODULATION SETTING: LOW EMI GAIN AND SWITCHING FREQUENCY STUFF OPTIONS

74 73 72 68 6

=PP3V3_S0_AUDIO 8

7

6

5

1

2

3

4

RP7200 47K

5% 1/16W SM-LF

A

72 72 72 72

AUDIO: SPEAKER AMP SYNC_MASTER=FINO-SO

AUD_SAMP_FS2 AUD_SAMP_FS1 AUD_SAMP_G2 AUD_SAMP_G1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

NOSTUFF 1

R7218 0

5% 1/16W MF-LF 2 402

74 72

SYNC_DATE=04/28/2005

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

1

R7208 0

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5% 1/16W MF-LF 2 402

SIZE

APPLE COMPUTER INC.

GND_AUDIO_SPKRAMP_PLANE

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13

OF

72

1

110

A

 

8

6

7

2

3

4

5

SPEAKER CABLE CONNECTOR

COMBO IN JACK

APPLE P/N 518S0325

APPLE P/N 514-0341

L7302

180-OHM-1.5A

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_R_JACK

1

AUD_LI_R_EMI

1

MIN_NECK_WIDTH=0.2MM

AUD_LI_L_JACK

OPTI-AUD-JCK

D

0603-LF

L7301

MIN_NECK_WIDTH=0.2MM

VCC GND

LED

VOUT

AUD_LI_L_EMI

1

L7305

MIN_NECK_WIDTH=0.2MM

1

AUD_LI_DET_EMI

AUD_LI_GND_JACK 73

2

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

1

180-OHM-1.5A

MIN_NECK_WIDTH=0.3MM

AUD_LI_GND_EMI

2

1

0603-LF

2

1

5% 1/16W MF-LF 402

2

C7326

DZ7302

2

72

7

5% 1/16W MF-LF 402

DZ7300

1 1

AUD_SPDIF_GND_IN

AUD_SPDIF_IN 68

1

402

402

DZ7324

2

2

1

1

DZ7301 8V-100PF

8V-100PF

XW7300 SM

402

402

1

2

 2

180-OHM-1.5A

NET_SPACING_TYPE=AUDIO 74

AUD_MIC_IN_P

1

2

XW7307 SM

GND_CHASSIS_AUDIO_EXTERNAL_J

C

6

GND_CHASSIS_AUDIO_EXTERNAL

1

2

L7312

GND_CHASSIS_AUDIO_EXTERNAL_J73

1

AUD_MIC_IN_P_EMI

74

180-OHM-1.5A

AUD_MIC_IN_N

1

2

180-OHM-1.5A 1

AUD_MIC_IN_N_EMI

2

IN

AUD_MIC_IN_P_CONN

IN

AUD_MIC_IN_N_CONN

IN

C

NET_SPACING_TYPE=AUDIO NET_SPACING_TYPE=AUDIO NET_SPACING_TYPE=AUDIO

0603-LF 2

DZ7325

2

8V-100PF

DZ7326 8V-100PF

402

TO POWER SUPPLY PAGE 6 IN

GND_AUDIO_MIC_CONN 47

47

L7313

NET_SPACING_TYPE=AUDIO

0603-LF

6

2 0603-LF

L7310

74

TO FHB CONNECTOR PAGE 47

180-OHM-1.5A

NET_SPACING_TYPE=AUDIO

0603-LF

NET_SPACING_TYPE=AUDIO

68

6

9

39

L7309

74 73

AUD_SPKR_OUTL_N AUD_SPKR_OUTL_P

72 73 74

8V-100PF

8V-100PF

R7305  1      0

72

GND_AUDIO_CODEC 68

2

10% 6.3V 2 CERM 402

13

4

R7306

1UF

12

3

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

AUD_SPDIFIN_JACK

11

D

2

0603-LF

10 SHELL

1

5

8 9

72

AUD_LI_DET_H 74

L7307

MIN_LINE_WIDTH=0.5MM

180-OHM-1.5A

PP3V3_AUDIO_SPDIF_JACK

M-RT-SM 8

AUD_SPKR_OUTR_N AUD_SPKR_OUTR_P

0603-LF

L7303

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

6

J7301

53261-0798

74

72

180-OHM-1.5A

MIN_LINE_WIDTH=0.3MM

2 0603-LF

5

NET_SPACING_TYPE=AUDIO

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_L

2 0603-LF

1

AUD_LI_DET_JACK

3

7

MIN_NECK_WIDTH=0.2MM

180-OHM-1.5A

MIN_LINE_WIDTH=0.3MM

2

MIN_LINE_WIDTH=0.5MM 74

MIN_NECK_WIDTH=0.2MM

L7304

180-OHM-1.5A

MIN_LINE_WIDTH=0.3MM

2

F-5.5-DEG-TH 4

AUD_LI_R

0603-LF

1

WO-RIB-M50 1

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

2

0603-LF

L7300

180-OHM-1.5A

MIN_LINE_WIDTH=0.3MM

PROPERTIES FOR ALL SPKR NETS (OTHERS HIDDEN)

L7306

180-OHM-1.5A

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

2

CRITICAL

J7300

1

402

1 1

GND_CHASSIS_AUDIO_INTERNAL

AUD_SPDIF_OUT  1

R7308 100K 5%

 2

1/16W MF-LF 402

L7315

=PP3V3_S0_AUDIO

1

L7323

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

180-OHM-1.5A 74 72 68 6

1

L7316

AUD_LO_TYPE

1

B

73

APPLE P/N 514-0338

PP3V3_AUDIO_SPDIF_JACK

0603-LF

L7324

180-OHM-1.5A 74

2

LINE OUT JACK

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

180-OHM-1.5A

PP3V3_AUDIO_SPDIF_EMI

2 0603-LF

1

180-OHM-1.5A AUD_LO_TYPE_EMI

2

1

0603-LF

2 0603-LF

C7317 1UF

10% 6.3V 2 CERM 402

1

C7318

CRITICAL

10UF

J7303

20% 6.3V 2 CERM 805-1

OPTI-AUD-OUT-JCK-M50

B

F-ANG-TH 10

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

L7318

1 74

AUD_LO_L

180-OHM-1.5A

2

1

AUD_LO_L_EMI

0603-LF

1

74

1

AUD_LO_TIP_EMI

1

TYPE_DET

6 2 4

RING

1

GND_1

5

GND_2

AUD_LO_GND_JACK

2 0603-LF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

L7317

7 8

L7325

180-OHM-1.5A

AUD_LO_R

3

AUD_LO_L_JACK AUD_LO_TIP_JACK MIN_NECK_WIDTH=0.2MM AUD_LO_R_JACK MIN_NECK_WIDTH=0.2MM AUD_LO_R_JACK

TIP TIP_DET

180-OHM-1.5A

2 0603-LF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LO_TYPE_JACK MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

L7327

180-OHM-1.5A AUD_LO_TIP

2 0603-LF

L7319

74

11

L7326

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

180-OHM-1.5A

9

180-OHM-1.5A AUD_LO_R_EMI

2

1

0603-LF

2

VIN VCC

 D  E  L

GND

12

0603-LF

13

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM

L7880

L7381

180-OHM-1.5A 74 73 72 68

GND_AUDIO_CODEC

1

180-OHM-1.5A GND_AUDIO_CODEC_EMI1

2

1

0603-LF

A

AUD_SPDIF_GND_OUT

R73021

2

0

0603-LF

5% 1/16W MF-LF 402

AUDIO: CONNECTORS

2

SYNC_MASTER=AUDIO 2

2

DZ7380 8V-100PF 402

1

1 2

2

DZ7314 8V-100PF

8V-100PF

402

402 2

1

8V-100PF

2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

DZ7323 8V-100PF 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1 SIZE

1

1 74 73

SYNC_DATE=01/10/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

8V-100PF DZ7313 402

DZ7311 402

DZ7315

GND_CHASSIS_AUDIO_EXTERNAL_J

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

73

1

OF

13 110

A

 

8

6

7

PORT F (LI) PLUG DETECT JACK SENSE PULL UPS(PLACE NEXT TO CODEC)

74 68

2

3

4

5

AUDIO GROUND RETURNS

AUD_SENSE_B

PP4V5_AUDIO_ANALOG

74 73 72 68 6

D

AUD_PORT_F_DET_L

100K

5.11K

5% 1/16W MF-LF 2 402

1% 1/16W MF-LF 2 402

1% 1/16W MF-LF 2 402

R7404 AUD_SENSE_A 68

74

AUD_SENSE_B 68

74

73

AUD_LI_DET_H

47K

1

NOSTUFF

NC

R7442

3

5% 1/16W MF-LF 402

2

2N7002

AUDLINDETH 1

1

G

SOT23-LF

S

74

C7407

1

74

2

C7401

AUD_PORT_A_R1

C7408

10% 16V 2 X5R 402

NOSTUFF

AUD_PORT_A_L2 74

R7410

AUD_PORT_A_R2 74

NOSTUFF

72 6

GND_AUDIO_SPKRAMP

0

1

0

1

R7443

0.1UF

2 CERM 10V 402

0.1UF

0.1UF

10% 16V 2 X5R 402

D

2

5% 1/8W MF-LF 805

AUD_PORT_A_L1

20%

1

0

1

Q7401

D

PLACE NEAR L6800 GND_AUDIO_CODEC 68 72 73 74

2

5% 1/8W MF-LF 805

1% 1/16W MF-LF 2 402

R7420

R7422

R7421

5.11K

0

1

20.0K

1

1

1

R7405

=PP3V3_S0_AUDIO

R7440

TO POWER SUPPLY PAGE 6 GND_AUDIO 6

1 74 68

1

PLACE NEAR ENTRY TO SPEAKER AMP GROUND PLANE

2

5% 1/8W MF-LF 805

2

5% 1/8W MF-LF 805

NOSTUFF

GND_AUDIO_CODEC

74 73 72 68

R7412

GND_AUDIO_CODEC

74 73

GND_CHASSIS_AUDIO_EXTERNAL_J

0

1

68 72 73 74

74 68

PLACE AT J7303

2

5% 1/8W MF-LF 805

PP4V5_AUDIO_ANALOG CRITICAL

USED PORT PORT PORT PORT

PORTS A HP/LI B MIC IN, VREF 80% C BI SPEAKERS F LI/LO

UNUSED PORTS PORT E SPDIF OUT DELEGATE PORT D

C2 VCC

PLACE ACROSS GROUND SPLIT

U7400

68

 

AUD_GPIO_1 1

R7437

1% 1/16W MF-LF 2 402

C1

SHDN*

74

AUD_PORT_A_L1

B1 INL

74

AUD_PORT_A_R1

B3 INR

10K

NOSTUFF

MAX9890

UCSP1

R7411

CEXT C3

U7400_CEXT

OUTL A1

AUD_PORT_A_L2 74

OUTR A3

AUD_PORT_A_R2 74

72

0.1UF

 D  N  G

10% 16V 2 X7R-CERM 402

68

AUD_BI_PORT_F_L

1

AUD_BI_PORT_F_R

1

4.7

2

AUD_PORT_F_L1

1

2

10% 16V TANT SMA-LF

AUD_LI_L

73

AUD_LI_R

73

1

2

74 68

AUD_SENSE_B

74 68

AUD_SENSE_A

74

AUD_PORT_A_R2

R7414 AUD_BI_PORT_A_L

68

AUD_BI_PORT_A_R

1

R7415 1

4.7

4.7

2

5% 1/8W MF-LF 805

2

AUD_PORT_A_L1 74 AUD_PORT_A_R1 74

5% 1/8W MF-LF 805

1

74 73 72 68

74

R7413 470K

AUD_LO_L

2

20% 16V ELEC 6.3X5.5-SM

73

2

C7404

R7430

AUD_LO_R

2

R74231

20% 16V ELEC 6.3X5.5-SM

22K

5% 1/16W MF-LF 402 2

R74181 22K

2

73

73

AUD_LO_TIP

39.2K

3

47K

1

R7424 22K

AUD_LO_DET2_1 1

5

G

Q7402

D

2N7002DW-X-F

2N7002DW-X-F

SOT-363

S

5

G

SOT-363

S

4

C7400

NC

AUD_PORT_E_DET_L 6

Q7402

D

2N7002DW-X-F

2

NC

3

Q7400

D

5% 1/16W MF-LF 402

1

1% 1/16W MF-LF 2 402

AUD_PORT_A_DET_L

5% 1/16W MF-LF 402

R7400

100UF 1

1

39.2K

1% 1/16W MF-LF 2 402

AUD_TYPE_DET_EN

1

5% 1/16W MF-LF 402

B

GND_CHASSIS_AUDIO_EXTERNAL_J 73

R7431

=PP3V3_S0_AUDIO

100UF

AUD_PORT_A_L2

2

1

74 73 72 68 6

C7403 74

1

3.3UF 10% 16V TANT SMA-LF

PORT A HP/LI

C

SM

GND_AUDIO_CODEC

PORT A/H (LO/DIG_OUT) PLUG DETECT (E TELLS H TO COME ON)

C7406

AUD_PORT_F_R1

2

5% 1/8W MF-LF 805

68

XW7440

74 73 72 68

3.3UF

5% 1/8W MF-LF 805

R7417 68

4.7

68 72 73 74

PLACE NEAR HEADPHONE PORT

74 73 72 68

C7405

R7416

GND_AUDIO_CODEC

2

5% 1/8W MF-LF 805

 C7424

GND_AUDIO_CODEC

PORT F LI/LO

0

1

1

     2     A

C

GND_AUDIO_SPKRAMP_PLANE

 

2

G

SOT-363

S 1

4

0.1UF

5% 1/16W MF-LF 2 402

20% 10V 2 CERM 402

1

R7419 22K

2

5% 1/16W MF-LF 402

74 73 72 68

GND_AUDIO_CODEC

74 73 72 68 6

=PP3V3_S0_AUDIO

B

R7407

GND_AUDIO_CODEC

1

100K 2

AUD_LO_DET1_INV

5% 1/16W MF-LF 402

74

AUD_LO_DET1_1

1

R7409 270K

UNUSED PORT TERMINATION

5% 1/16W MF-LF 2 402

1

C7415 0.1UF

10% 16V 2 X5R 402

1

6

73

AUD_LO_TYPE

47K

1

2 74

5% 1/16W MF-LF 402

0.1UF

1

G

SOT-363

S 1

C7402

20% 10V 2 CERM 402

0.1UF

74 73 72 68

10% 16V 2 X5R 402

GND_AUDIO_CODEC

MICROPHONE IMPEDANCE MATCHING CIRCUIT

68 72 73 74

R7435

AUD_MIC_INTERCON

R7427

A

73

NET_SPACING_TYPE=AUDIO

R7425

AUD_MIC_IN_P

1

C7418

1

73

7

6

2

10% 50V CERM  2 805

AUDIO: POWER SUPPLIES SYNC_MASTER=AUDIO

20% 16V 2 ELEC 6.3X8-SM

5% 1/16W MF-LF 402

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

68 72 73 74

2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

AUD_BI_PORT_B_L 68

10% 50V X7R 603-1

100K

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

XW7400 SM 1

4

SYNC_DATE=02/23/2006

NOTICE OF PROPRIETARY PROPERTY GND_AUDIO_CODEC

0.1UF

AUD_MIC_P1

R74261

AUD_MIC_IN_N

5

AUD_VREF_PORT_B 68

5% 1/16W MF-LF 402

C7419

5% 1/16W MF-LF 402 2

820PF

NET_SPACING_TYPE=AUDIO

330 5% 1/10W MF-LF 603

2.2K 2

220UF

2.2K

2

1

C7435 1

1

8

2

0.1UF

C7417

GND_AUDIO_CODEC

2N7002DW-X-F

AUD_LO_DET1_1 1

C7416

10% 16V 2 X5R 402

Q7400

D

R7408

BAL_IN_L 68 BAL_IN_R 68 BAL_IN_COM 68

2

APPLE COMPUTER INC. GND_AUDIO_CODEC 68

3

051-7148

SCALE 72 73 74

SHT NONE

2

REV.

DRAWING NUMBER

D

74

1

OF

13 110

A

 

8

6

7 97 88 6

1

10

5% 1/16W MF-LF 402

PP12V_S5_CPU_REG

1

1uF

R7520

=PP3V3_S0_IMVP

2

1

R7521 5%

1

20% 6.3V CERM 603

GND_IMVP6_SGND

DPRSTP*

PSI*

Operation Mode

0

1

1

2-Phase CCM

0

1

0

1-Phase CCM

1

0

1

1-Phase DCM

1

0

0

1-Phase DCM

0.1uF

402 X5R

R7596

IMVP6_NTC_R

8

CPU_VID<6> 1

8

CPU_VID<5>

CPU_VID<4> 1

8

CPU_VID<3>

8

0

CRITICAL

R7527

CPU_VID<2> 1

1

8

CPU_VID<1>

8

CPU_VID<0> 1

R7526

4.02K

402 1

2

0

IN

VIN

IMVP_VID<5>

0

1

IMVP_VID<3>

2

R7590

IMVP_VID<1>

37

IMVP_VID<0>

R7519 1

PM_DPRSLPVR

21 7

IN

2

C7510

7

77

IN IN

2

IMVP_PGD_IN

3

R75A0

26

499

C7505

1

FROM SMC

1/16W MF-LF 402 1% 2

58

0.01uF 16V 402 1

OUT IN

44

IMVP6_NTC

6

10% CERM 2

75

IMVP6_SOFT

7

75

IMVP6_RBIAS

4

IMVP6_UGATE1

LGATE1 PGND1 ISEN1

UGATE2 PHASE2 LGATE2

VR_ON

1

GND_IMVP6_SGND

147K

2

402 1% MF-LF 1/16W

R7508

75

VR_TT* ISEN2

1

R7509 1.82K

1% 1/16W MF-LF 2 402

1

470pF

10% 50V CERM 402

2

75

NO STUFF

75

R7513

IMVP6_VDIFF_RC 1

2

R7511

75

2.0K

75

1% 1/16W MF-LF 402

VSUM

SOFT

VO

RBIAS

IMVP6_VDIFF

13 VDIFF

IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW

12 FB2 11

VSEN

FB

10 COMP 9 VW

RTN

VSS

1.40K

75

GND_IMVP6_SGND

1

20% 25V X5R 603

20% 25V 2 X5R 603

IMVP6_UGATE2

75

IMVP6_PHASE2

30

75

1

50V CERM 402

2

R7514 180K

5% 1/16W MF-LF 2 402

  47PF C7507 5% 50V CERM 402

1

R7510

23

75

19

75

8

75

18 16 17

75

IMVP6_DFB

1

0.001uF

15

1% 1/16W MF-LF 402

1

4.32K

180pF

5% 2 50V CERM 402

    N     E      S 1 R7518     V C7531 _ 1K 1% 0.01uF      6 1/16W     P MF-LF 10%     V 402 16V     M 2 CERM 75     I 402 1

2

10% 50V CERM 402

C7529

75 75 75 75 75

IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1 IMVP6_FET_RC1 IMVP6_VSUM_R1 R7504_1

 

1

0.25 MM

0.25 MM

75

1.5 MM

0.25 MM

75

1.5 MM

0.25 MM

0.25 MM

0.25 MM

75

 

0.25 MM

0.25 MM

75

 

0.25 MM

0.25 MM

75

0.25 MM

0.25 MM

75

 

 

75

MEROM

NO STUFF

HAT2165H

0.033UF

0.33uF

10% 16V X5R 402

10% 6.3V CERM-X5R 402

1

2

R7531

1 4

1 2 3

 C7502

NO STUFF

1

10% 50V CERM 402

C7592

0.0022UF

0.0022UF 2

10% 50V CERM 402

NTC

1

2 1% MF-LF 1/16W 402

C7521

1

1

R7523 0

5% 1/16W MF-LF 2 402

1

R7522 0

IMVP6_PHASE2 IMVP6_BOOT2

 

IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2 IMVP6_FET_RC2 IMVP6_VSUM_R2 R7507_1

 

   

 

2

D7501

XW7501

R7502 1.0

1

1

5% 1/4W MF-LF 1206

1

2

     2     R _     M R7505 10K     U75 1% IMVP6_FET_RC2      S 1/16W     V MF-LF _ 402 1   C7511      6 4700PF     P 10%     V 50V 2     M 75     I1 CERM

B340LBXF

  SM

SM

R7506

603

3.65K

SMB

2

1% 1/10W MF-LF 603

75

R7507

1

1

1/16W 402 MF-LF 5% 2

1

100

7

6

NO STUFF 1

R7541

0.22uF

10% 6.3V 402 CERM-X5R

10K

1% 1/10W

MF-LF 2 603

(IMVP6_VSUM) (IMVP6_VO)

PPVCORE_CPU

5 6 75 76

R7528 NOSTUFF 1

2

100

*NEED TO CHANGE R7531 TO NTC

ERT-J1VR103J PANASONIC

LAYOUT NOTE: MIN_LINE_WIDTH MIN_NECK_WIDTH

CPU_VCCSENSE_P CPU_VCCSENSE_N

75

8 8

CPU_VCCSENSE_P & N ARE DIFF PAIRS ROUTE AS 18MIL WIDE, 7MIL SPACE

75 75 75 75

MIN_NECK_WIDTH

75

0.25 MM

0.25 MM

0.25 MM

0.25 MM

0.25 MM

0.25 MM

0.25 MM

0.25 MM

0.25 MM

75 75

75 75

IMVP6_OCSET

 

IMVP6_VSUM   GND_IMVP6_SGND   IMVP6_VO   IMVP6_DROOP IMVP6_DFB   IMVP6_SOFT   IMVP6_RBIAS   IMVP6_VDIFF   IMVP6_FB2   IMVP6_FB IMVP6_COMP IMVP6_VW

   

0 . 25 M M 0 . 25 M M 0.50 MM

0 . 20 M M 0 . 20 M M 0 . 20 M M

0 . 25 M M

0 . 20 M M

0.25   MM

0.20 MM

0 . 25 M M

0 . 20 M M

0 . 25 M M

0 . 20 M M

0 . 25 M M

0 . 20 M M

0 . 25 M M

0 . 20 M M

0 . 25 M M

0 . 20 M M

0.25   MM

0.20 MM

0 . 25 M M

0 . 20 M M

0 . 25 M M

0 . 25 M M

0.25   MM

0.25 MM

0 . 25 M M

0 . 25 M M

IMVP6 CPU VCore Regulator S YN YN C_ C_ MA MA ST ST ER ER =P =P OW OW ER ER

0.25 MM

0.25 MM

0.60 MM

0.25 MM

75

0.25 MM

0.25 MM

75

IMVP6_RTN IMVP6_VSEN

 

S YN YN C_ C_ DA DA TE TE =0 =0 7/ 7/ 08 08 /2 /2 00 00 5

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

   

5

B

2

C7504

APPLE COMPUTER INC.

4

3

051-7148

SCALE

2

REV.

DRAWING NUMBER

D

SHT NONE

8

 1 _  7  0  5  7  R

PLACE R7528-29 CLOSE TO CPU DECAPS

5% 1/16W MF-LF 2 402

0.25 MM

2

XW7502

(IMVP6_ISEN2)

2

ERT-J1VR103J

2

1

2

0603-LF

R7529 NOSTUFF 1

CRITICAL

L7501

0.36UH-30A-0.80MOHM

LFPAK

10KOHM-5% 1% MF-LF 1/16W 402

1210

5

HAT2165H

NO STUFF

IMVP6_VO_R

20% 16V

LFPAK

1 2 3

1

1

C7508

2 X7R

HAT2168H

2

1% 1/16W MF-LF 2 402

2

Q7572

2

2.61K

1

22UF

20% 16V

10K

1% 1/10W MF-LF 603

SM

Q7505

4

R7530

1

CRITICAL

C7533

20% 6.3V X5R 402

680UF

C

R7540

(IMVP6_PHASE2)

1 2 3

R7515

 C7534 1  C7528 2

5

LFPAK

(IMVP6_VO)

1% 1/16W MF-LF 2 402 1

Q7503

R7516

C7501 ELEC TH-MCZ

1% 1/16W MF-LF 2 402

11K

MIN_LINE_WIDTH

 

1

11.5K

1

2

MIN_NECK_WIDTH

 

C7503

0.22uF

CRITICAL

CRITICAL

2

2

2

10% 6.3V CERM-X5R 402

PP12V_S5_CPU_REG

LFPAK

1 2 3

75 75

1

CRITICAL

1

75

75

R75041

1

5% 1/16W MF-LF 402

R7501

C7516

2

R7517

    N     T     R _      6     P     V     M     I

NO STUFF

 1 _  4  0  5  7  R

1

2

HAT2168H

IMVP6 CPU VCORE REGULATOR 75

75

3.65K

Q7502 75 75

75

0.25 MM

75

75

     1     R 1 2 _     M     U R7500      S 10K     V 1% _ 1/16W      6 MF-LF 402     P     V     M     I

1% 1/10W MF-LF 2 603

0.01uF

SM

1.5 MM

B340LBXF SMB

CRITICAL

IMVP6_VSUM IMVP6_OCSET IMVP6_VO IMVP6_DROOP

10% 16V CERM 402

XW7500

 

10% 50V CERM 402

2

4

14

0.22UF

IMVP6_PHASE1 IMVP6_BOOT1

D7500

0.0022UF

10% 50V CERM 402

IMVP6_ISEN2

1

2

75

C7590

1

0.0022UF

5

2

1% 1/16W MF-LF 2 402

(IMVP6_COMP)

MIN_LINE_WIDTH

  C7500

4

2

1

4.42K

Note 1: C7532,C7533 = 27.4 Ohm For Validating CPU Only.

A

4700PF

5

0.01uF

  10% C7513 470PF

1

IMVP6_LGATE2 (GND)

10% 16V CERM 402

2

SM

10% 50V CERM 603

2

1

XW7503 1

  C7512

1 2 3

76 75

NO STUFF

470PF

1

1

NO STUFF

NO STUFF

6 75 76

SM

2

5% 1/4W MF-LF 1206

IMVP6_FET_RC1

0.22UF

2

C7532

10% 50V CERM 402

1

IMVP6_ISEN1

49 1

(IMVP6_VW)

IMVP6_COMP_RC

2

C7515

0.22UF

PPVCORE_CPU 5

XW7504

(IMVP6_ISEN1)

75

75

  C7514

2

4

4

R7503 1.0

IMVP6_LGATE1 (GND)

75

TPAD

21

(IMVP6_FB)

1

LFPAK

LFPAK

44A MAX CURRENT

2

HAT2165H

HAT2165H

IMVP6_PHASE1

24

25 NC

1% 1/16W MF-LF 2 402

B

C7527

2

27 28

1210

0.36UH-30A-0.80MOHM (IMVP6_PHASE1) 1 2 1

NTC

DFB

  C7506

75

33

29

DROOP

1

75

32

20% 16V

2 X7R

1210

SM

Q7504

PGND2

PGOOD

OCSET 75

34

X5R

C7597 22UF

20% 16V

PSI*

IMVP_VR_ON VR_PWRGOOD_DELAY

75

PHASE1

PGD_IN

VR_PWRGD_CK410_L

1 5

OUT

75

IMVP6_BOOT1 IMVP6_BOOT2

UGATE1 35

QFN

VID0

48 3V3 47 CLK_EN*

IMVP6_VR_TT

26 14 5

75

26 BOOT2

U7500

FROM 1.5V AND 1.05V VREGS

10% CERM 2

22UF

L7500

5

1 2 3 1

BOOT1 36

ISL6262

DPRSLPVR

CPU_PSI_L

0.01uF

16V 402 1

Q7501

5

31 PVCC

46 DPRSTP* 45

CPU_DPRSTP_L IMVP_DPRSLPVR

499

1/16W 1% MF-LF 402

22 VDD

OMIT

39 VID2 38 VID1

IMVP_VID<2>

2

470K

41 VID4 40 VID3

IMVP_VID<4>

R7591

0

43 VID6 42 VID5

IMVP_VID<6>

2

2

2 23 14

C

0

1

PLACE R7526 CLOSE TO CPU

1/16W 1% 402 MF-LF

20

R7593

1

2 X7R

CRITICAL

CRITICAL

1

2

10%

603

CRITICAL

C7598

1

2

R7592

1uF

25V

603 X5R 2

CRITICAL 1 2 3

1 2 3

2

R7594

1uF

25V 10%

LFPAK

R7595 0

2

1210

HAT2168H

4

2

1

8

LAYOUT NOTE:

0

20% 16V

D DPRSLPVR

10% 16V 2

LFPAK

4

 C7530

1/16W 402 MF-LF 75

4.7uF

2

 C7550 1 C7551

1

22UF 2 X7R

Q7570

5

HAT2168H

  C7535

PP3V3_S0_IMVP6_3V3

2

10

1

10% 16V X5R 402 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

10

Q7500

5

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

0.1uF

C7509

330UF

20% 2 16V ELEC SM-3

MEROM CRITICAL

CRITICAL

  C7596

1

C7517

1

CRITICAL

PPVIN_S5_IMVP6_VIN

2

C7518

20% 2 16V ELEC SM-3

PP12V_S5_CPU_REG

76 75

10% 25V X5R 603

2

5% 1/16W MF-LF 402

D

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

  C7526

 

1

330UF

PP5V_S0_IMVP6_VDD

2

R7512

6

1 CRITICAL

OMIT

OMIT 1

1

76 75

2

3

4

5

PP5V_S0

13 OF

75

1

110

A

 

8

6

7

5

2

3

4

1 SMC PWRGD PULLUP PP3V3_S5

PROCESSOR VCORE CURRENT SENSE

80 79 77 66 65 59 26 11 6 5 83 81

(USING 12V INPUT CURRENT TO DERIVE CPU CURRENT)

6

=PP12V_S5_CPU

1

2 TH-VERT-LF

1

R7623 10K

CRITICAL

L7502

R7599

1UH-20A-4.5MOHM

PP12V_S5_CPU_REG75

0.0252

PP12V_L7502

1

VOLTAGE=12V

1% 1W MF 2512-1

D

76

VOLTAGE=12V MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM

2

R7620

PCB:KEEP SHORTS NEXT TO U7501 PCB:PLACE D7599,R7597,C7599 BY SMC

6

PP3V3_S0 6

SYS_POWERFAIL_L

1

3 NOSTUFF

CRITICAL

XW7598 SM

4 VIN SOT23-5IOUT

3

1 NC

5

LOAD

CPU_DCIN_SENSE

1

1

C7599 0.22UF

20% 6.3V 2 X5R 402

1

464

2

10K

2

SMC_CPU_ISENSE

58

5% 1/16W MF-LF 402

SO SMC ADC SAMPLING WORKS WELL.

GND_SMC_AVSS

R7691

ADC IS 10BIT 0 TO 1023 0 TO 3.3V

1 58

1 MS TIME CONSTANT

1% 1/16W MF-LF 402

D

RSMRST_PWRGD 58

2

R7602 TO SMC

SOT23

SMC_DCIN_ISENSE

1% 1/16W MF-LF 402

1K

2

1

14.53K 2

R7598

 2

COUNT 0.00881 A/COUNT

BAS16

R7597

2 CPU_SENSE_I_R

1

GND

SCALE 2.73224 A/V

D7599

OMIT

U7501

0

5% 1/16W MF-LF 402

10 11 26 41 59 61 88

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM

ZXCT1010

1% 1/16W MF-LF 402

NOSTUFF

58 59 76 85

CPU_DCIN_SENSE_R

1% 1/16W MF-LF 402

PCB: PLACE D7599, C7599, R7597 WITHIN 1" OF SMC

(U5800)

PROCESSOR DCIN VOLTAGE SENSE (SCALING 12V INPUT VOLTAGE TO SMC)

76 75

PP12V_S5_CPU_REG 1

R7630

C

6.04K

PCB: PLACE R7632, C7633 WITHIN 1" OF

1% 1/16W MF-LF

SMC_PBUS_VSENSE_R

R7631 2.0K

SCALE

COUNT .0129 V/COUNT

4.53K2

SMC_PBUS_VSENSE

1

1% 1/16W MF-LF 402

1

4 V/V

C

PROCESSOR VCORE SENSE

SMC (U5800)

R7632

2 402

58

1

0.22UF C7633 20%

1% 1/16W MF-LF 2 402

6.3V 2 X5R 402

ADC IS 10BIT 0 TO 1023 0 TO 3.3V

GND_SMC_AVSS

PCB: PLACE R7612, C7612 WITHIN 1" OF

SMC (U5800)

58 59 76 85

R7612 75 6 5

PPVCORE_CPU

4.53K2

SMC_CPU_VSENSE

1

1% 1/16W MF-LF 402

1

58

C7612 0.22UF

20% 6.3V 2 X5R 402

Current Sense Calibration Circuit Switches in fixed load on power supplies

B

58

IN

GND_SMC_AVSS

B

ISENSE_CAL_EN

CPU SENSE CIRCUITRIES

R76401

A

SYNC_MASTER=(MASTER)

100K 5% 1/16W MF-LF 402

58 59 76 85

to calibrate current sense circuits

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY 2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

76

1

OF

13 110

A

 

8

6

7

6

2

3

4

5

1

2.5V S0 Regulator

=PP3V3_S0_2V5REG

2.5V S0

R7700 88 83 81 80 79 78 77 11 6 5

79 77 76 66 65 59 26 11 6 5

PP12V_S5 1 79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

PP3V3_S5

83 81 80

R7799

10K

2

1

1

R7793

10K

5% 1/16W MF-LF 402

2

PM_SLP_S3 78

81

PP1V05_S0_PGOOD

1

80

PP1V5_S0_PGOOD

2

80 81

6

5

R7701

MC74VHC1G08

59 26 11 6 5 PP3V3_S5 83 81 80 79 77 76 66 65 75 IMVP_PGD_IN

4

1

3

IN

2

  PM_SLP_S3_L

G

5

1

SOT-363

S

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

1

5% 1/16W MF-LF 2 402

2

C7711 1

NB=0.142A M56=0.745A TOTAL=0.887A

6

CRITICAL

L7700 2.2uH

SW 4

2V5REG_RT

1

SHDN/RT

2V5REG_MODE

2

SYNC/MODE VFB 9

PP2V5 S0_PGOOD

8

26 58

2V5REG_SW

ITH 10 PGOOD CRITICAL PGND

SGND

5

3

1

MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm

2V5REG_ITH

88 83 81 80 79 78 77 11 6 5

PP12V_S5

PP0V9_S0_PGOOD

1

77

PP2V5 S0_PGOOD

2

5

SOT23-5-LF 4

R7704

PM_PWROK

1

1

2 2

CONTINUOUS

1% 1/16W MF-LF 402

C7704

2

2

100pF

10% 50V CERM 402

5% 50V CERM 402

R7708 1% 1/16W MF-LF 402

1

C7709 22uF

2

20% 6.3V X5R 805

(R1) 2

XW7700 SM 1

5% 1/16W MF-LF 2 402

PM_SLP_S4 77

2

VOUT = VREF * (1 + R2 / R1) 79 83

0.784V MIN VREF = 0.800V TYP 0.816V MAX

3

Q7703

D

1

VOLTAGE=0V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

10K

5% 1/16W MF-LF 2 402

1

2

4.7K

2V5REG_SGND

R7798

10K

1% 1/16W MF-LF 402

(R2)

C7703

0.0033uF

1

R7794

2

R7705 324K

NOSTUFF 1

2

2V5REG_ITH_RC

1

10K 5% 1/16W MF-LF 402

3 79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

5% 50V CERM 402

1

R7707 10K

22pF

1/16W MF-LF 402

MC74VHC1G08

U7711

1

4.99K 1%

10V

79

1

C7706

R7706

D

6 11 88

2 SM1-LF

2V5REG_VFB

3

2

PP2V5_S0

MSOP-LF

77

ALL_SYS_PWRGD

POWER BUDGET

20% 6.3V X5R 603

LTC3411 2

SOT23-5-LF 4

2

7

MC74VHC1G08

U7712

2

0.1UF

C7700 10UF

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

SVIN PVIN U7700

10V

2N7002DW-X-F

88 79 58 23 6

5% 1/16W MF-LF 402

0.1UF

OUT

1

PP3V3_SO_2V5REG_R

10K

C7712

SOT23-5-LF

U7710

Q7703

D

47K

2 10V

5% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

R7710

0.1UF

NOSTUFF 1

D

1

C7710

1

10

2N7002DW-X-F

58 23

IN

PM_SLP_S4_L

5

G

C

SOT-363

S

C

4

1.2V S3 REGULATOR / 1.2V S0 FET 6

=PP3V3_S3_1V2REG

C7751 1

2

1

1

2

2

22uF

NOSTUFF

20% 6.3V X5R 805

R7757 1M 5% 1/16W MF-LF 402

C7752 22uF 20% 6.3V X5R 805

1.2V S0

     6      5      4      1      1      1

POWER BUDGET M56=2.100A YUKON=0.426A

VIN1

U7750

19

SYNC

1V2REG_VBIAS

17

VBIAS

2 3

1V2REG_ITH 1V2REG_RUNSS

1

1

R7754 71.5K

2

1% 1/16W MF-LF 402

1

C7798 1UF

10% 16V 2 X5R 603

RT

1V2REG_MODE

1V2REG_VFB

B

18

C7753

0.0033UF 10% 50V 2 CERM 402 1V2REG_ITH_RC

CRITICAL

VSENSE

C7754

BOOT

5

PH0

6

PH1

7

PH2

8

PH3

9

PH4

COMP

PWRGD SS/ENA PGND

1

0.047UF

SOP

20

     1      2      3      1      1      1

    D     N      G     A  1

TOTAL=2.526A

C7797

SN200505068 CONTINUOUS 1V2REG_RT

10

1V2REG_BOOT

1

2

10% 16V CERM 402

CRITICAL

L7750 1.0UH-3.48A 1V2REG_SW

4 1V2REG_PGOOD

1 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

1

1

R7750

187 1% 1/16W MF-LF 402 2

     1      2

100PF

5% 50V 2 CERM 402

C7750

R7753

1

10% 50V CERM 402

1% 1/16W MF-LF 402

1

B

6

C7756

22uF

22uF

20% 6.3V X5R 805

20% 6.3V X5R 805

2

1

R7752 10K

2 402

(R2)

0.0018UF

1K

2

C7755

1% 1/16W MF-LF

1V2REG_SW_FIL

1

2

PP1V2_S3

2 SM-LF

    L     M     R     H     T

2

 1  2  5  6

3

NOSTUFF

2N7002

83 79 77

PM_SLP_S4

1

G

1

SOT23-LF

S

VOUT = VREF * (1 + R2 / R1)

C7757 470pF

Q7799

D

2

10% 50V CERM 402

1

R7751

26.7K

0.882V MIN VREF = 0.891V TYP 0.900V MAX

1% 1/16W MF-LF 402

2

(R1)

2

 V

 D    F  1  6    L  0     4    P  7      O  4      S  7  3     T  I  Q  S

 3

 4

XW7750

2.5V & 1.2V GRAPHICS REGULATORS

SM

1V2REG_SGND

A

1

2

85

GPUVCORE_PGOOD

VOLTAGE=0V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

=PP1V2_S0_REG 1

88

SYNC_MASTER=(MASTER)

C7799

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

0.1UF

20% 10V 2 CERM 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

77

1

110

A

 

PAGE_BORDER=TRUE

8

6

7

2

3

4

5

1

TABLE_5_HEAD

P AR T#

QTY

D ES C RI PT I ON

REFERENCE

DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

114 S0514

1

5.11 OHM 0402 1% 1/16W LF

R 7840

D

D

C7802

1.8V S0 REGULATOR

1UF

1 88 83 81 80 79 77

11 6 5

PP12V_S5

10% 25V X5R 603

1V8REG_GPU_VCC5

C

2

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

R7800

10

1

1% 1/16W MF-LF 2 402

8.5A PEAK CURRENT DRAW 7.2A CONTINUOUS CURRENT DRAW

C7804

1

1UF

D 4

10% 6.3V 2 CERM 402

9

1V8REG_GPU_PVCC5

LOAD FROM POWER BUDGET

10

7

8

VCC12 VCC5

14

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

U7800

BOOT

15

PHASE

13

ISL6549

R7801 1

0

2

5% 1/16W MF-LF 402

1V8REG_GPU_LDO_FB

PM_SLP_S3

1

G

Q7802

QFN

4

LDO_FB

LGATE

16

2

4.7UF 20% 6.3V CERM 603

0

1 2 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 5% 1/16W MF-LF 402

1V8REG_GPU_BOOT

1V8REG_GPU_BOOT_R MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

Q7800

CASE369-LF

2

2

1

6

AGNDPGND 17

12

5

2

7.15K2

L7800 1.53UH

2

PP1V8_S0

SM

5.11

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

D 4

CRITICAL

Q7801

1V8REG_GPU_COMP_R 1 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C7811 820PF 2

CASE369-LF

S3

2

10% 10V CERM 402

NTD60N02R

1 G

C7814

0.068UF

1

1

1

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

10% 25V 2 X7R 402

330UF

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

1

88

C7806 10UF

20% 6.3V 2 CERM 805-1

1

R7812

C7813

22

5% 1/16W MF-LF 2 402 1

R7802 1.24K

2

1

XW7800 SM

953 1% 1/16W MF-LF 2 402

1V8REG_GPU_FB_R MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 2 402

1

C7809

B

0.01UF

10% 16V 2 CERM 402

(R2)

R7803

1

1V8REG_GPU_GND VOLTAGE=0

C7817

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

5% 50V 2 CERM 1206

1500PF

1

1V8REG_GPU_SNUB

1000PF

C7810

C7807 330UF

1

1% 1/4W MF-LF 2 1206

1

10% 50V CERM 402

B

TOTAL=8.010A

CRITICAL 3

R7804

R7805 1% 1/16W MF-LF 402

2

M56=2.400A GDDR=3.320A IO=1.750A

20% 25V CERM

1V8REG_GPU_FB

1V8REG_GPU_COMP

1

1.5V S0 POWER BUDGET

S 3

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

THRML_PAD DGND

10% 16V 2 CERM 1210

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

11

C

C7800 10UF

20% 2 16V ELEC SM-LF

1V8REG_GPU_SWITCHNODE 603

FS_DIS COMP

R7892 C7803 1 39.2K 1% 1/16W MF-LF 402

C7805 0.1UF

R7840

1V8REG_GPU_LGATE FB

SOT23-LF

S

LDO_DR

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1V8REG_GPU_FS_DIS

2N7002

81 80 77

3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

3 D

1V8REG_GPU_LDO_DR

OMIT MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

680UF

CRITICAL

NTD60N02R

1 G

1V8REG_GPU_UGATE UGATE

PVCC5

C7801

(R1)

V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

VOUT=VREF*(1+R2/R1) 0.784V MIN VREF = 0.800V TYP 0.816V MAX

1.8V GDDR REGULATOR

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT

SCALE NONE

8

7

6

5

4

3

2

REV.

051-7148

D

TRUE

78

1

OF

13 110

A

 

8

6

7

C7992

2

3

4

5

1

1.8V S3 REGULATOR

1UF

1 88 83 81 80 78 77 11 6 5

D

PP12V_S5

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

R7905 10

1% 1/16W MF-LF 402

2

OMIT 1

C7900 1UF

10

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

1V8REG_DDR_LDO_DR

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

R7992 C7903 1 100K

5% 1/16W MF-LF 2 402

2N7002

83 77

PM_SLP_S4

1

G

SOT23-LF

S

LDO_DR

4

LDO_FB

16

FS_DIS

QFN

BOOT

15

PHASE

13

LGATE

4.7UF

20% 6.3V CERM 2 603

C7901

R7940 0

1 2 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 5% 1/16W MF-LF 402

1V8REG_DDR_BOOT

1V8REG_DDR_BOOT_R

COMP

1

THRML_PAD DGND

AGND PGND 17

6

12

5

NB=4.000A DRAM=6.000A CRITICAL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

20% 25V CERM

3

1V8REG_DDR_SWITCHNODE 603

2

R7902 5.11

PP1V8_S3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

D 4

0.047UF

CRITICAL

Q7901

NTD60N02R

1 G

C7908

R7904

CASE369-LF

S3

1V8REG_DDR_COMP_R 1

2 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 10% 16V CERM 1000PF 402 1 2

2

C7906

10% 25V 2 X7R 402

5 6

C7913

C7998

10UF

330UF

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

20% 6.3V CERM 1206

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

R7999

C7909

22

5% 50V 2 CERM 1206

1000PF

1

330UF

1000PF

C7902

C7912

1V8REG_DDR_SNUB

1 1

1 1

1% 1/4W MF-LF 1206

2

1

R7903

10% 25V X7R 402

C

1.53UH

1

1V8REG_DDR_FB MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1V8REG_DDR_COMP

1% 1/16W MF-LF 402

2

TOTAL=10.000A

L7900 SM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

4.02K2 1

1.8V S3 POWER BUDGET

2

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

11

2

10UF

10% 16V 2 CERM 1210

S3

0.1UF 1

C7910

C7911

CASE369-LF

G

1V8REG_DDR_LGATE FB

Q7902

14

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

PVCC5

U7900

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1V8REG_DDR_FS_DIS

3 D

UGATE

VCC5

NTD60N02R

1

1V8REG_DDR_UGATE

20% 2 16V ELEC SM-3

Q7900

8

VCC12

1

330UF

CRITICAL

D 4 7

ISL6549 3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1V8REG_DDR_LDO_FB

2

5% 1/16W MF-LF 402

1

10% 6.3V 2 CERM 402

9

1V8REG_DDR_PVCC5

0

D

10% 25V X5R 603

1V8REG_DDR_VCC5

R7991

2

1.24K

5% 1/16W MF-LF 402

1V8REG_DDR_FB_R MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 2 402

1

C

C7907 0.01UF

10% 16V 2 CERM 402

(R2)

1

2

1K R7901

XW7900

1% 1/16W MF-LF 2 402

SM

1

1V8REG_DDR_GND

VOUT=VREF*(1+R2/R1)

(R1)

VOLTAGE=0 V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

83 81 80 79 59 6 5

0.784V MIN VREF = 0.800V TYP 0.816V MAX

PP5V_S5

C7980

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

0.1UF 1   2

1

R7911 5.49K

2

1% 1/16W MF-LF 402

20% 10V CERM 402

3

1V6_REF 1.591V

4

PP1V8_S3

5

B

1

R7910 10K

2

1% 1/16W MF-LF 402

LM339A SOI-LF 2

V+

B

PP1V8_S3_PGOOD

U7910 GND

12 1

R7912 5.11K

2

83 81 80 79 59 6 5

1% 1/16W MF-LF 402

PP5V_S5

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

1

R7913

1

R7914

66 65 59 26 11 6 5 PP3V3_S5 83 81 80 79 77 76

330 PM_SLP_S3_L

MEMVTT_EN

31

2

5% 1/16W MF-LF 402

0V7_REF 0.723V

10

PP0V9_S0

11

3

PP1V8_S3

8

1V0_REF

9

DEVELOPMENT

V+

U7901 81 80

A

GREEN-3.6MCD 2.0X1.25MM-SM

LM339A SOI-LF 14

LM339A SOI-LF

U7910

DEVELOPMENT

LED7900

2 402 3

V+

LED_PP1V8_S3_P 1

1% 1/16W MF-LF

1% 1/16W MF-LF 2 402

R7906

88 77 58 23 6

10K

8.45K

1DEVELOPMENT

6

PLACE LED NEAR VREG

13

PP0V9_S0_PGOOD

77

GND

12 1

R7915

2

1.8V Vreg

2.37K

LED_PP1V8_S3_N

1% 1/16W MF-LF 2 402

GND

12

SYNC_DATE=04/12/2005

SYNC_MASTER=M23-PC

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

79

1

OF

13 110

A

 

8

6

7

C8002

2

3

4

5

1

1.5V S0 REGULATOR D

1UF

D

1 88 83 81 79 78 77 11 6 5

PP12V_S5

10% 25V X5R 603

1V5REG_PCIE_VCC5 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

R8005

1

C8006

9

1V5REG_PCIE_PVCC5

10

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

0

2

5% 1/16W MF-LF 402

Q8003

PM_SLP_S3

1

G

VCC5

1V5REG_PCIE_UGATE UGATE

1V5REG_PCIE_LDO_FB

4

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

LDO_DR

QFN

LDO_FB

BOOT

15

13

LGATE

16

0

1V5REG_PCIE_BOOT 1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 5% 1/16W MF-LF 402

2

1V5REG_PCIE_BOOT_R MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

4.7UF

2

1

THRML_PAD DGND 6

AGND PGND 17

5

12

C

C8000

1.5V S0 POWER BUDGET

TOTAL=8.010A CRITICAL 3

L8000 1.53UH

2

PP1V5_S0

SM 1

1

R8002 5.11

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

D 4

CRITICAL

Q8001

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C8011

R8004 4.22K2

C8015

10% 10UF 16V 2 CERM 1210

2

20% 25V CERM

1V5REG_PCIE_FB

1V5REG_PCIE_COMP

1

1

CPU=0.120A NB=6.000A SB=1.890A

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 402

2

1

10% 10UF 16V 2 CERM 1210

1V5REG_PCIE_SWITCHNODE603

11

2

C8014

20% 680UF 2 16V ELEC TH-MCZ

CASE369-LF

S 3

0.1UF

FS_DIS COMP

R8092 C8009 1 100K

2

C8010

CRITICAL

Q8000

NTD60N02R

1 G

1V5REG_PCIE_LGATE

1V5REG_PCIE_FS_DIS

20% 6.3V CERM 603

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

R8040

PHASE

FB

5% 1/16W MF-LF 402

14

PVCC5

U8000 3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

SOT23-LF

S

D 4

8

VCC12

ISL6549

1V5REG_PCIE_LDO_DR

2N7002

81 78 77

7

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

3 D

1

10% 1UF 6.3V 2 CERM 402

10 1% 1/16W MF-LF 2 402

R8001

2

NTD60N02R

1 G

0.047UF 1V5REG_PCIE_COMP_R 1

CASE369-LF

2

1

C8012

6 11

C8016 10UF

330UF

20% 6.3V 2 CERM 805-1

1V5REG_PCIE_SNUB

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 10% 16V CERM 1000PF 402 1 2

1

C8099

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

1% 1/4W MF-LF 1206

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

S3

2

1

C8001 330UF

1

1

R8099

C8004

22

1000PF

C8005

5% 1/16W MF-LF 2 402

5% 50V 2 CERM 1206

1000PF

10% 25V 2 X7R 402

C

1

R8003

10% 25V X7R 402

1V5REG_PCIE_FB_R

1K

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 2 402

1

C8003 0.01UF

10% 16V 2 CERM 402

(R2)

1

R8000

2

1.13K

XW8000 SM

1% 1/16W MF-LF 2 402

1

1V5REG_PCIE_GND

(R1)

VOLTAGE=0 V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

VOUT=VREF*(1+R2/R1) 0.784V MIN VREF = 0.800V TYP 0.816V MAX

83 81 79 59 6 5

PP5V_S5

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

1

R8010

1

R8011

10K

8.45K

1% 1/16W MF-LF 2 402

B 1V3_REF 1.300V

2

B

LM339A

6

V+

SOI-LF 1

U7910 7

PP1V5_S3

1% 1/16W MF-LF 402

3

PP1V5_S0_PGOOD

77

GND 12

1

R8012 5.49K

1% 1/16W MF-LF 2 402

66 65 59 26 11 6 5 PP3V3_S5 83 81 80 79 77 76

DEVELOPMENT 1

R8007 330

2

5% 1/16W MF-LF 402

LED_PP1V5_S0_P 1 3

A

PP1V8_S3

V+

81 79

7

GREEN-3.6MCD 2.0X1.25MM-SM

1.5V Vreg

PLACE LED NEAR VREG

SYNC_MASTER=FINO-PC

2

SOI-LF 1

SYNC_DATE=05/18/2005

NOTICE OF PROPRIETARY PROPERTY

LED_PP1V5_S0_N

U7901 1V0_REF

DEVELOPMENT

LED8000

DEVELOPMENT

LM339A

6

GND

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

12

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

80

1

OF

13 110

A

 

8

6

7

C8192

2

3

4

5

1

1.05V S0 REGULATOR D

1UF

D

1 88 83 80 79 78 77 11 6 5

PP12V_S5

10% 25V X5R 603

1V05REG_NB_VCC5 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

R8105

10 1% 1/16W MF-LF 2 402

1

C8100

1V05REG_NB_PVCC5

10

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

0

2

1V05REG_NB_LDO_DR

PM_SLP_S3

1

G

1V05REG_NB_FS_DIS

UGATE

R8192 C8103 1 100K

SOT23-LF

2

5% 1/16W MF-LF 402

4.7UF

20% 6.3V CERM 2 603

14

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

U8100 LDO_DR

4

LDO_FB

QFN

BOOT

15

PHASE

13

LGATE

0

1V05REG_NB_BOOT

1 2 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 5% 1/16W MF-LF 402

11

1

16

COMP

1

AGND PGND 17

5

1V05REG_NB_COMP

1

3.9K 2

2

C

CPU=2.500A NB=5.500A SB=0.874A

1.5UH

1

CRITICAL

D 4

Q8103 C8108

NTD60N02R

1 G

0.047UF

CASE369-LF

S3

2 1

C8106

1.05V S0 POWER BUDGET

TOTAL=8.874A

2

PP1V05_S0

IHLP

1

2

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

1% 1/4W MF-LF 1206

20% 6.3V 2 CERM 805-1

1

R8190

C8109

22

5% 1/16W MF-LF 2 402

5% 50V 2 CERM 1206

10% 25V 2 X7R 402

6 34

C8115 10UF

330UF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1000PF

1000PF

1

C8190

20% 2 2.5V-ESR9V POLY CASE-D2E-LF

1V05REG_NB_SNUB

1

C8102

1

C8114 330UF

5.11

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 10% 16V CERM 1000PF 402 1 2

C8198

10% 10UF 16V 2 CERM 1210

R8102

1V05REG_NB_COMP_R 1

5% 1/16W MF-LF 402

1

L8100

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

R8104

12

C8112

10% 10UF 16V 2 CERM 1210

CRITICAL

1V05REG_NB_FB

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

THRML_PAD

6

1

S3

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C8111

2

20% 25V CERM 1V05REG_NB_SWITCHNODE 603 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

FS_DIS

DGND

1

10% 10UF 16V 2 CERM 1210

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1V05REG_NB_LGATE 2

C8110

10% 10UF 16V 2 CERM 1210

CASE369-LF

0.1UF

1V05REG_NB_BOOT_R

CRITICAL

Q8102

NTD60N02R

1 G

C8101

R8140

PVCC5

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

Q8104

S

VCC5

1V05REG_NB_UGATE

FB

2N7002

80 78 77

D 4

8

VCC12

ISL6549

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

3 D

7

3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1V05REG_NB_LDO_FB

5% 1/16W MF-LF 402

1

10% 1UF 6.3V 2 CERM 402 9

R8191

2

C

1

R8103

10% 25V X7R 402

1.02K

1% 1/16W MF-LF 2 402

1V05REG_NB_FB_R MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 1

C8107 0.01UF

10% 16V 2 CERM 402

(R2)

1

R8101

2

3.24K

XW8100 SM

1% 1/16W MF-LF 2 402

1

1V05REG_NB_GND

(R1)

VOLTAGE=0 V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

VOUT=VREF*(1+R2/R1) 0.784V MIN VREF = 0.800V TYP 0.816V MAX

83 80 79 59 6 5

PP5V_S5 1

R8110 10K

2

1% 1/16W MF-LF 402

3

B

81 80 79

1V0_REF

8

PP1V05_S0

9

B

LM339A V+

SOI-LF 14

U7910

PP1V05_S0_PGOOD

77

GND

12

66 65 59 26 11 6 5 PP3V3_S5 83 81 80 79 77 76

DEVELOPMENT 1

DEVELOPMENT

C8199

R8107 330

0.1UF 1

2 2

20% 10V CERM 402

PP1V05_S0 3

V+

1

R8198

A

8.45K

2 81 80 79

SOI-LF 2

U7901 5

1% 1/16W MF-LF 402

1

DEVELOPMENT

LED8100

DEVELOPMENT

GREEN-3.6MCD

LM339A

4

79 77 76 66 65 59 26 11 6 5 PP3V3_S5 83 81 80

5% 1/16W MF-LF 402

LED_PP1V05_S0_P

2.0X1.25MM-SM

PLACE LED NEAR VREG

1.05V VREG

2

LED_PP1V05_S0_N SYNC_DATE=05/18/2005

SYNC_MASTER=M38-RT

GND

NOTICE OF PROPRIETARY PROPERTY

12

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

1V0_REF 0.867V 1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

R8199 3.01K

1% 1/16W MF-LF 2 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

OF

13

81   110

1

A

 

8

7

6

2

3

4

5

1

D

D

PP5V_S5 88 83 81 80 79 78 77 11 6 5

5 6 59 79 80 81

PP12V_S5

R83011

1

5% 1/16W MF-LF 402

C8399 1UF

3.6K

5

6

7

8

20% 10V 2 CERM 603

CRITICAL

Q8300 IRF7413PBF

2

SO-8 4

GATE_5V_S3

6

CRITICAL

Q8303

D

1

R8303

2

G

SOT-363

S

1

2

3

47K

2N7002DW-X-F

C

2

5% 1/16W MF-LF 402

C PP5V_S3

6 60

1

PP3V3_S5

79 77

PM_SLP_S4

1 1

R8302

Q8302

D

2N7002DW-X-F

G

6

7

8

Q8301 IRF7413PBF SO-8 4

1

R8300

1

47K

SOT-363

S

5

20% 10V 2 CERM 603

GATE_3V3_S3 3 CRITICAL

C8398 1UF

3.6K

5% 1/16W MF-LF 2 402

5

5 6 11 26 59 65 66 76 77 79 80

81

79 78 77 11 6 5 PP12V_S5 88 83 81 80

2

5% 1/16W MF-LF 402

2

3

PP3V3_S3

6 53 59

4

B

B

5V & 3.3V Fets

A

S YN C C_ _M MA A ST E ER R =F I IN N O- P PC C

S YN C C_ _ DA T TE E =0 4 4/ / 12 / /2 20 00 05

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

83

1

OF

13 110

A

 

8

6

7

2

3

4

5

1

OMIT

U8400 M56P BGA

(1 OF 7) 13

13

13

13

D 13

IN

IN

IN

IN

IN

C8420

PEG_R2D_C_P<15>

C8421

PEG_R2D_C_N<15>

0.1uF 0.1uF

PEG_R2D_C_P<14>

C8422

0.1uF

PEG_R2D_C_N<14>

C8423

0.1uF

1

1

2

1

2

1

2

0.1uF

PEG_R2D_C_N<13>

C8425

0.1uF

1

2

PEG_R2D_C_P<12>

C8426

0.1uF

1

2

1

16V

X5R

402

10%

16V

X5R

402

1 0%

16V

X 5R

4 02

10%

16V

X5R

402

2 10%

13

13

13

13

13

13

13

13

IN

IN

IN

IN

IN

IN

IN

IN

13 IN

13

C

13

88

=PP1V2_S0_PCIE_GPU_VDDR

88

=PP1V2_S0_PCIE_GPU_PVDD

13

Add ferrite bead(s)?

OMIT

13

U8400 M56P

13

BGA

13

N23

W27

P23

W29

PCIE_PVDD_12 (1.2V)

Y26

C8402

1

C8401

10% 6.3V CERM 402

V23

1

2

2

N25

Y30

N26 N27

C8407

AA25

N28

1uF

AA26

N29

AA29

AL29

10% 6.3V CERM 402

2

20% 6.3V X5R 805

13

10% 6.3V CERM 402

C8406

1

1

1

IN

IN

IN

AL32

AB27

AM27

AB29

AM28

AC23

AM29

10% 6.3V CERM 402

2

2

20% 6.3V X5R 805

13

13

IN

IN

C8413

C8412

1

1uF

1uF 10% 6.3V CERM 402

1

10% 6.3V CERM 402

2

C8411

1

1

1uF 2

10% 6.3V CERM 402

13

C8410

IN

2

20% 6.3V X5R 805

13

AM31

AC26

 D  N  U  O  R  G

AC29 AC30 AD25 AD26

PCIE_PVSS

PCIE_VSS

AE27

P24 P25 P26

AF26 AF28 AF29

AG25

L8400

0.1uF

1

2

PEG_R2D_C_N<9>

C8433

0.1uF

1

2

C8434

PEG_R2D_C_P<8>

C8435

PEG_R2D_C_N<8>

C8436

PEG_R2D_C_P<7>

0.1uF 0.1uF

0.1uF

PEG_R2D_C_N<7>

C8437

0.1uF

PEG_R2D_C_P<6>

C8438

0.1uF

C8439

PEG_R2D_C_N<6>

0.1uF

1

1

1

PEG_R2D_C_P<5>

C8440

0.1uF

PEG_R2D_C_N<5>

C8441

0.1uF

C8442

PEG_R2D_C_P<4>

C8443

PEG_R2D_C_N<4>

C8444

PEG_R2D_C_P<3>

C8445

PEG_R2D_C_N<3>

0.1uF 0.1uF

0.1uF

2

0.1uF

2

1

2

1

IN

C8446

PEG_R2D_C_P<2>

0.1uF

1

0.1uF

1

2

0.1uF

1

2

IN

0402 13

IN

C8449

0.1uF

1

2

C8450

0.1uF

1

2

C8451

PEG_R2D_C_N<0>

0.1uF

1

402

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

0.1uF

1

2

C8456

0.1uF

1

2

10%

PEG_R2D_P<1>

AH30

PCIE_RX1P

PCIE_TX1P

AJ25

PEG_D2R_C_P<1>

PEG_R2D_N<1>

AG30

PCIE_RX1N

PCIE_TX1N

AH25

PEG_D2R_C_N<1>

C8457

0.1uF

C8458

0.1uF

X5R

402

10%

16V

X5R

402

PEG_R2D_P<2>

AG32

PCIE_RX2P

PCIE_TX2P

AH28

PEG_D2R_C_P<2>

PEG_R2D_N<2>

AF32

PCIE_RX2N

PCIE_TX2N

AG28

PEG_D2R_C_N<2>

AF31

PCIE_RX3P

PCIE_TX3P

AG27

PEG_D2R_C_P<3>

PEG_R2D_N<3>

AE31

PCIE_RX3N

PEG_R2D_P<4>

AE30

PCIE_RX4P

PEG_R2D_N<4>

AD30

PCIE_RX4N

PEG_R2D_P<5>

AD32

PCIE_RX5P

PEG_R2D_N<5>

AC32

PCIE_RX5N

 E  C  A  F  R  E  T  N  I  S  U  B  S  S  E  R  P  X  E   I  C  P

C8459

0.1uF

C8460

0.1uF

1

2

C8461

0.1uF

1

2

10%

16V

X5R

402

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

PCIE_TX3N

AF27

10%

PEG_D2R_C_N<3>

C8462

PCIE_TX4P

AF25

PEG_D2R_C_P<4>

PCIE_TX4N

AE25

PEG_D2R_C_N<4>

C8463

16V

X5R

402

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

10%

16V

X5R

402

IN

R23

C8464

PCIE_TX5P

AE28

PEG_D2R_C_P<5>

PCIE_TX5N

AD28

PEG_D2R_C_N<5>

C8465

IN

6

C8466

PCIE_VSS

PCIE_RX6P

PCIE_TX6P

AD27

PEG_D2R_C_P<6>

PEG_R2D_N<6>

AB31

PCIE_RX6N

PCIE_TX6N

AC27

PEG_D2R_C_N<6>

T27

AH27

T29

AH29

U24

AJ26

U26

AJ28

U28

AJ29

U29

AJ30

U30

AJ32

V24

AK26

V25

AK29

V26

AK30

V29

AK31

V31

AK32

W24

AL27

W26

1

0.1uF

1

AB30

PEG_R2D_N<7>

AA30

PCIE_RX7P PCIE_RX7N

PCIE_TX7P PCIE_TX7N

AC25

C8467

0.1uF

1

2

C8468

0.1uF

1

2

AB25

C8469

0.1uF

1

0.1uF

1

PEG_R2D_P<8>

AA32

PCIE_RX8P

PCIE_TX8P

AB28

PEG_D2R_C_P<8>

Y32

PCIE_RX8N

PCIE_TX8N

AA28

PEG_D2R_C_N<8>

PEG_R2D_P<9>

Y31

PCIE_RX9P

PCIE_TX9P

AA27

PEG_D2R_C_P<9>

PEG_R2D_N<9>

W31

PCIE_RX9N

PCIE_TX9N

Y27

PEG_D2R_C_N<9>

C8471

0.1uF

1

C8472

0.1uF

0.1uF

1

2

1

2

10%

10%

0.1uF

1

W30

PCIE_RX10P

PCIE_TX10P

Y25

PEG_D2R_C_P<10>

PEG_R2D_N<10>

V30

PCIE_RX10N

PCIE_TX10N

W25

PEG_D2R_C_N<10>

C8475

0.1uF

1

2

C8476

0.1uF

1

2

10%

10%

V32

PEG_R2D_N<11>

U32

PCIE_RX11P PCIE_RX11N

PCIE_TX11P PCIE_TX11N

W28

PEG_D2R_C_P<11>

V28

PEG_D2R_C_N<11>

C8477

0.1uF

1

1

U31

PCIE_RX12P

PCIE_TX12P

V27

PEG_D2R_C_P<12>

PEG_R2D_N<12>

T31

PCIE_RX12N

PCIE_TX12N

U27

PEG_D2R_C_N<12>

C8479

0.1uF

1

1

PEG_R2D_P<13>

T30

PCIE_RX13P

PCIE_TX13P

U25

PEG_D2R_C_P<13>

R30

PCIE_RX13N

PCIE_TX13N

T25

PEG_D2R_C_N<13>

PEG_R2D_P<14>

R32

PCIE_RX14P

PCIE_TX14P

T28

PEG_D2R_C_P<14>

C8481

0.1uF

1

P32

PCIE_RX14N

PCIE_TX14N

R28

PEG_D2R_C_N<14>

PEG_R2D_P<15>

P31

PCIE_RX15P

PCIE_TX15P

R27

PEG_D2R_C_P<15>

PEG_R2D_N<15>

N31

PCIE_RX15N

PCIE_TX15N

P27

PEG_D2R_C_N<15>

10%

C8482

0.1uF

1

2

C8483

0.1uF

1

2 10%

C8484

0.1uF

1

2

C8485

0.1uF

1

2

10%

10%

C8486

2

0.1uF

1

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

2

10%

PEG_R2D_N<14>

16V

2 10%

PEG_R2D_N<13>

402

2 10%

0.1uF

402

X5R

2 10%

PEG_R2D_P<12>

X5R

16V

2 10%

0.1uF

16V

2 10%

PEG_R2D_P<10>

402

2 10%

C8473

X5R

2 10%

PEG_R2D_N<8>

16V

2 10%

PEG_D2R_C_N<7>

402

2

10%

PEG_D2R_C_P<7>

402

X5R

2

10%

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

16V

X5R

402

2 10%

GPU_CLK100M_PCIE_P

AL28

PCIE_REFCLKP

=PPVIO_S0_PCIE

GPU_CLK100M_PCIE_N

AK28

PCIE_REFCLKN

1

IN

PEG_RESET_L

AG24

PERST*

PCIE_CALRP

AD24

GPU_PCIE_CALRP

AF24

PERST*_MASK

PCIE_CALRN

AE24

GPU_PCIE_CALRN

AA24

PCIE_TEST

PCIE_CALI

AB24

GPU_PCIE_CALI

NC

T26

AH26

0.1uF

X5R

16V

2

10%

AC31

T24

AG31

1

16V

13

PEG_D2R_P<15>

13

PEG_D2R_N<15>

13

PEG_D2R_P<14>

13

PEG_D2R_N<14>

13

PEG_D2R_P<13>

13

PEG_D2R_N<13>

13

PEG_D2R_P<12>

13

PEG_D2R_N<12>

13

PEG_D2R_P<11>

13

PEG_D2R_N<11>

13

PEG_D2R_P<10>

13

PEG_D2R_N<10>

13

PEG_D2R_P<9>

13

PEG_D2R_N<9>

13

PEG_D2R_P<8>

13

PEG_D2R_N<8>

13

PEG_D2R_P<7>

13

PEG_D2R_N<7>

13

PEG_D2R_P<6>

13

PEG_D2R_N<6>

13

PEG_D2R_P<5>

OUT

13

PEG_D2R_N<5>

OUT

13

PEG_D2R_P<4>

OUT

13

PEG_D2R_N<4>

13

PEG_D2R_P<3>

13

PEG_D2R_N<3>

13

PEG_D2R_P<2>

13

PEG_D2R_N<2>

13

PEG_D2R_P<1>

13

PEG_D2R_N<1>

13

PEG_D2R_P<0>

13

PEG_D2R_N<0>

OUT

OUT

OUT

D

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

C

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

B

OUT

OUT

OUT

OUT

OUT

88

R8495 2.0K

R26

R31

0.1uF

402

2

10%

R25

AG29

1

10%

R24

R29

0.1uF

402

X5R

2

10%

C8480

16V

1

10%

C8478

10%

0.1uF

X5R

16V

2

10%

PEG_R2D_P<6>

PEG_R2D_P<11>

10%

1

10%

C8474

10%

2

10%

C8470

16V

2

1

10%

PEG_R2D_P<7>

10%

1

16V

2

P30

AG26

AH24

C8455

10%

PEG_R2D_P<3>

2

C8447

PEG_R2D_C_P<0>

PEG_D2R_C_N<0>

2

C8448

PEG_R2D_C_N<1>

X5R

16V

2

PEG_R2D_C_P<1>

13

AJ27

2

PEG_R2D_C_N<2>

13 IN

16V

10%

2

13

IN

PCIE_TX0N

2

1

1

10%

2

2

1

PEG_D2R_C_P<0>

PCIE_RX0N

2

1

1

402

2

1

1

AK27

AH31

2

FERR-220-OHM

P29

 I  C  P

AF30

1

X5R

2

13 IN

P28

 S  S  E  R  P  X  E

AE29

1

N24 N30

 R  E  W  O  P

AD31

GND_GPU_PCIE_PVSS VOLTAGE=0V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

 &

AD29

W23

0.1uF

1

PCIE_TX0P

PEG_R2D_N<0>

2

22uF 2

AM30

AC24

0.1uF

1

16V

2

C8432

AL31

AB26

0.1uF

1

PCIE_RX0P

2

PEG_R2D_C_P<9>

22uF

1uF 2

13 IN

C8405

AL30

PCIE_VDDR_12 (1.2V)

AC28

A

IN

C8431

PEG_R2D_C_N<10>

0.1uF

1

2000mA

AA23

AE26

IN

C8430

PEG_R2D_C_P<10>

0.1uF

C8400

13

Y29

AA31

B

IN

C8429

PEG_R2D_C_N<11>

22uF

1uF

1uF

U23

1

Y28

AB23

IN

C8428

PEG_R2D_C_P<11>

100mA

(2 OF 7)

Y24

IN

C8427

PEG_R2D_C_N<12>

AJ31

2

C8424

PEG_R2D_C_P<13>

10%

PEG_R2D_P<0>

2

R8497

1

1

2

2

R8496 562

1.47K 1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

ATI M56 PCI-E SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

84

1

110

A

 

8

6

7

2

3

4

5

1

GPU VCore Current Sense GPUISENS_NTC 1

88

=PP5V_S0_GPUVCORE

88

=PPVIN_S0_GPUVCORE

R8596

GPU VCore Supply C8501

D

1

1

2.2UF 20% 6.3V CERM1 603

2

5% 1/16W MF-LF 402

1

C8530

1

2

2

0 5% 1/16W MF-LF 402

1

R8503 10K

33K

5% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

GPUVCORE_EN

77

GPUVCORE_PGOOD

C8507

2 1

C8506

1

10% 16V CERM 402

C

R8506

2 2

1% 1/16W MF-LF 402

1

FSET

4

EN

5

GPUVCORE_FB

14

BOOT

13

PHASE

15

R8588

GPUVCORE_UG

0

1

FCCM PGOOD

FB

8

VO

1

C8509_P1

2

10% 50V CERM 402

GPUISENS_NEG

1

GPUVCORE_ISEN

11

GPUVCORE_LG

PGND

10

1

2

1uF

1% 1/16W MF-LF 402

5

4

LMV2011MF

4.53K2

1

5

1% 1/16W MF-LF 402

HAT2165H

5

1

1

1

XW8500

2

SM 1

3

2 1

2

3

2

1

10% 50V CERM 402

R8594 and R8597

=PPVCORE_S0_GPU_REG

88

<Ra>

R8521 1 1% 1/16W MF-LF 402

C8599

1

1

OMIT

D8520

R8522

SMB

10% 25V X7R 402

2

1

20% 2.5V-ESR9V POLY CASE-D2E-LF

C8543

22uF 20% 6.3V X5R 805

C8542 330uF

20% 6.3V X5R 805

C8541 <Rb> 2

1

C8540 22uF

2 2

1000PF

5% 50V 2 CERM 1206

C8521

59 76

470pF

close to inductor

1% 1/4W MF-LF 1206

1000pF

1000pF

GND_GPUVCORE_SGND

2

NO STUFF 1

C8522 10% 25V X7R 402

2

3.01K

4

GND_SMC_AVSS 58

C8592

5.11

1

NO STUFF 2

0.22UF

2

1% 1/16W MF-LF 402

Keep C8590, R8590,

R8599_2

  Q8522

1M

GPUVCORE_IOUTOUT

C85A0

1

20% 6.3V 2 X5R 402

R8592 1

R8599

2

NO STUFF CRITICAL

17

GPUISENS_POS

1

LFPAK

4

THRML PAD

2

Q8521

2

Placement Note:

1.5UH IHLP

2

27.4K

59

1% 1/16W MF-LF 402

2

CRITICAL

L8520

CRITICAL

3.01K

R85A0

SOT23-5

1% 1/16W MF-LF 402

1

R8510 1

1

D

U8595

3

R8591

1

2

10% 6.3V CERM 402

CRITICAL

U8595_1

GPUISENS_RC

3

C8595

2

1

2

470PF

5% 1/16W MF-LF 402

2

R8590

HAT2165H

C8508

0

1uF

20% 16V X7R 1210

649

20% 6.3V X5R 402

GPUVCORE_PHASE

9

COMP

6

LFPAK

5% 1/16W MF-LF 402

GPUVCORE_BOOT

LG

ISEN

2

HAT2168H

0.22UF

LFPAK

R8505

2

2

1% 1/16W MF-LF 402

Q8520

C8509

NO STUFF 1

22uF

20% 16V X7R 1210

CRITICAL

UG

GPUVCORE_COMP_R

40.2K

0.01UF

5% 50V CERM 402

2

1

27.4K

1

2

1% 1/16W MF-LF 402

R8593

6.3V CERM 402

4

QFN

VIN

7

3

15PF

1% 1/16W MF-LF 402

VCC

U8500

16

R8508

20% 16V X7R 1210

1M

1

C8590

5

ISL6269 1

GPUVCORE_COMP

150K

2

PVCC

GPUVCORE_FCCM

1

2

10%

12

GPUVCORE_FSET

88

C8532

1

20% 6.3V CERM1  2 603

R8507

1

22uF

22uF

1

C8531

1

10% 50V CERM 402

R8598

1% 1/16W MF-LF 402

2

1

1K

1

0

2.2UF

R8504

2

R8502

PP5V_S0_GPUVCORE_VCC

C8502

470pF

2

R8594

NO STUFF

2

88

C8598

0603-LF 2

NO STUFF

C8500 2

=PP5V_S0_GPUISENS

R8597 10KOHM-5%

1

1uF 10% 16V X5R 603

1

1K 1% 1/16W MF-LF 402

88

CRITICAL

1

C

330uF 20% 2.5V-ESR9V 2 2.5V-ESR9V 2 POLY

2

CASE-D2E-LF

5.11K

B340LBXF

1% 1/16W MF-LF 402

1

2

2

Vout(low)

= 0.6V * (1 + Ra/Rb)

Vout(high) = 0.6V * (1 + Ra/Req) Req = Rb || Rc

B

B

Back-Bias Negative Supply

Back-Bias Positive Supply

=PNVOUT_S0_GPUBBN_REG 88

=PPVCORE_S0_GPU_BBP

=PPVOUT_S0_GPUBBP_LDO

88

88

GPU (M56) Core Supplies

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

85

1

110

A

 

8

6

7

2

3

4

5

1

Page Notes Power aliases required by this page: - =PP1V5_GPU_VDD15 - =PP1VR1V3_GPU_VCORE Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)

U8400 M56P BGA

D

88

D

(7 OF 7) OMIT

=PPBB_S0_GPU 100mA (Preliminary) K18

K15

M23

C8690

1

1

2

2

22uF 20% 6.3V X5R 805

C8691

1

0.1uF

1uF 10% 6.3V CERM 402

C8692

2

10% 16V X5R 402

V10

R10

BBP

BBN

AC14

AC17

=PNBB_S0_GPU  D  N  U  O  R  G

P19 R15

=PPVCORE_S0_GPU 14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI

R17

1

22uF 20% 6.3V X5R 805

C8601

1

1

22uF 2

20% 6.3V X5R 805

C8604

1

2

10% 6.3V CERM 402

1

1uF

1uF 2

C8605

2

C8606

1

1uF

10% 6.3V CERM 402

2

C8607

1

2

10% 6.3V CERM 402

1

2

10% 6.3V CERM 402

C8609

1

1uF

1uF

1uF

10% 6.3V CERM 402

C8608

2

10% 6.3V CERM 402

C8610 1uF

2

10% 6.3V CERM 402

T16 T17

U15

1

C8611

1

1uF 2

10% 6.3V CERM 402

C8612

1

1

10% 6.3V CERM 402

2

C8614

1

10% 6.3V CERM 402

2

10% 6.3V CERM 402

C8615

1

1uF

1uF

1uF

1uF 2

C8613

2

10% 6.3V CERM 402

2

C8616

V14

1uF

V15

10% 6.3V CERM 402

M8 M9 M24 M28 M32 N3

 E  R  O  C

T18

U17

M7

 R  E  W  O  P

R19

U16

M6

  /

R18

C8600

N7 N8 P1

VDDC (1.0V/1.2V)

 &

P5

 Y  R  O  M  E  M

V16 V18

P6 P7 P15 P17

W14

R8630

1

0

C

5% 1/10W MF-LF 603

2

R3

W15

R6

W19

R14

AC11

R16

AC12

T10

AD11

T15

PPVCORE_S0_GPU_VDDCI VOLTAGE=1.2V MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

K14

C8630 6.3V X5R 805

1

1

2

2

C8631

1

10% 1uF 6.3V CERM 402

C8632

1

10% 1uF 2

6.3V CERM 402

C8633

1

10% 1uF 2

6.3V CERM 402

2

C8634

P16

10% 1uF

T14

6.3V CERM 402

T23 U19

U1 U5 U6 U7

VDDCI (1.0V/1.2V)

U8

W10

U9

W17

U10

=PP1V8R2V0_S0_FB_GPU

U14

2.0A @ 500MHz 1.8V GDDR3

A3

U18

A9

C8650

1

22uF 20% 6.3V X5R 805

C8651

1

22uF 2

20% 6.3V X5R  2 805

C8652

1

C8653

22uF

22uF

20% 6.3V X5R 805

20% 6.3V X5R 805

2

1

2

1

2

1

C8655

2

C8656

C8657

C8658

C8659

V3

C8660

A12

K23

F18

V6

1uF

1uF

1uF

1uF

1uF

1uF

10% 6.3V CERM 402

10% 6.3V CERM 402

V17

2

10% 6.3V CERM 402

F19

2

10% 6.3V CERM 402

A2

2

10% 6.3V CERM 402

A15

2

10% 6.3V CERM 402

A18

A8

F21

V19

A21

A11

F22

A24

A13

F24

A30

A16

F27

1

C8663

1

1

C8665

1

C8666

C1

A19

F30

C32

A22

G13

F32

A25

G16

Y7

H13

A31

G19

AA4

H19

B1

G20

AA6

B32

G21

AC9

1

2

C8661

1

1uF

C8662

1

1uF

10% 6.3V CERM 402

2

10% 6.3V CERM 402

1

1uF 2

10% 6.3V CERM 402

C8664

1

1uF 2

10% 6.3V CERM 402

1

1uF 2

10% 6.3V CERM 402

1uF 2

10% 6.3V CERM 402

J1

B

C

T19

20% 22uF

88 87

88

P14 P18

91 88

Y23

1

C8667

1

1uF 2

C8668

1

1uF

10% 6.3V CERM 402

2

10% 6.3V CERM 402

C8669

1

1uF 2

C8670

1

1uF

10% 6.3V CERM 402

2

C8675

1

10% 6.3V CERM 402

2

1

1

1

C8676

1

C4

G22

AC10

C5

G25

AD6

J13

C6

H1

AD7

J18

C9

H5

AD8

J19

C10

H7

AD9

C15

H16

C18

H20

C20

H21

C21

H28

K19

C24

H32

K20

C27

J3

K21

D11

J6

AE8

K24

D30

J9

AE14

L23

E5

J12

AE15

C8683

L24

E8

J16

AE16

1uF

L32

C8677

1

C8678

1uF

1uF

1uF

1uF

1uF

10% 6.3V CERM 402

10% 6.3V CERM 402

10% 6.3V CERM 402

10% 6.3V CERM 402

10% 6.3V CERM 402

10% 6.3V CERM 402

2

C8679

1

C8680

2

1

2

10% 6.3V CERM 402

1

2

10% 6.3V CERM 402

C8682

2

1

1uF

1uF

1uF

10% 6.3V CERM 402

C8681

2

2

10% 6.3V CERM 402

2

Y6

J11

10% 6.3V CERM 402

1uF

1uF 2

C8674

Y5

J10

2

J32

C8673

Y1

1uF

1

10% 6.3V CERM 402

J20

1

W18

C8672

C8671 1uF

2

W16

VSS

10% 6.3V CERM 402

A

2

K11 K13

VSS VDDR1 (1.8V/2.0V)

B

AD10 AD13 AD14 AD15

VSS

AD16 AD17

E9

J21

AE17

M1

E12

J24

AF14

M10

E13

J28

AF16

N9

E16

J30

AG11

N10

E19

K10

AG16

P8

E25

K12

AG23

P9

E28

K16

AH10

P10

E30

K17

AH11

R1

E32

K27

AH16

R9

F3

K30

AJ10

V1

F6

L1

AK16

Y8

F10

L6

AL1

Y9

F13

L7

AL13

Y10

F15

L29

AA1

F16

M3

ATI M56 Core Power SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

AM2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

AM13

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

86

1

110

A

 

8

6

7

2

3

4

5

Page Notes

OMIT

U8400

U8400

Power aliases required by this page:

M56P

M56P

- =PP1V8R2V0_S0_FB_GPU

BGA

BGA

(3 OF 7)

Signal aliases required by this page: (NONE)

89 5 89

BOM options provided by this page:

89

(NONE)

89 89 89

D

89 89 89 5 89 89 89 89 89 89 89 89 5 89 89 89 89 89 89 89 89 5 89 89 89 89 89 89 89 89 5

C

89 89 89 89 89 89 89 89 5 89 89 89 89 89 89 89 89 5 89 89 89 89 89 89 89 89 5

88 87 86

89

=PP1V8R2V0_S0_FB_GPU

89

B

89

R8710

1

1

89

R8712

40.2

40.2

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

R8711

2

2

1

1

C8711

100 1% 1/16W MF-LF 402

1

2

89 89

R8713

1

100

0.1uF 10% 16V X5R 402

89

2 2

M31

DQA_0

MAA_0

D26

89

FB_A_MA<0>

FB_A_DQ<1>

M30

DQA_1

MAA_1

F28

89

FB_A_MA<1>

IO

FB_A_DQ<2>

L31

DQA_2

MAA_2

D28

89

FB_A_MA<2>

IO

FB_A_DQ<3>

L30

DQA_3

MAA_3

D25

FB_A_DQ<4>

H30

DQA_4

MAA_4

E24

89

FB_A_MA<4>

IO

FB_A_DQ<5>

G31

DQA_5

MAA_5

E26

89

FB_A_MA<5>

IO

FB_A_DQ<6>

G30

DQA_6

 A

MAA_6

D27

89

FB_A_MA<6>

FB_A_DQ<7>

F31

DQA_7

MAA_7

F25

89

FB_A_MA<7>

IO

FB_A_DQ<8>

M27

DQA_8

MAA_8

C26

89

FB_A_MA<8>

IO

FB_A_DQ<9>

M29

DQA_9

 E  C  A  F  R  E  T  N  I

MAA_9

B26

89

FB_A_MA<9>

MAA_10

D29

89

FB_A_MA<10>

MAA_11

B27

89

FB_A_MA<11>

MAA_12

E27

MAA_13 MAA_14

E29

89

B25

89

FB_A_BA<2> FB_A_BA<0>

MAA_15

C25

89

FB_A_BA<1>

IO

IO

IO

89 5

FB_A_DQ<10>

L28

DQA_10

FB_A_DQ<11>

L27

DQA_11

IO

FB_A_DQ<12>

J27

DQA_12

H29

IO

FB_A_DQ<13> FB_A_DQ<14>

G29

DQA_13 DQA_14

IO

FB_A_DQ<15>

G27

DQA_15

FB_A_DQ<16>

M26

DQA_16

IO

FB_A_DQ<17>

L26

DQA_17

DQMA_0*

H31

89

FB_A_DQM_L<0>

IO

FB_A_DQ<18>

M25

DQA_18

DQMA_1*

J29

89

FB_A_DQM_L<1>

FB_A_DQ<19>

L25

FB_A_DQ<20>

IO

IO

 Y  R  O  M  E  M

90 5 90

IO

90

IO

DQA_21

DQMA_4*

E21

FB_A_DQ<22>

H27

DQA_22

DQMA_5*

B15

89

FB_A_DQM_L<5>

FB_A_DQ<23>

H26

DQA_23

DQMA_6*

D14

89

FB_A_DQM_L<6>

IO

FB_A_DQ<24>

F26

DQA_24

DQMA_7*

J17

89

FB_A_DQM_L<7>

IO

FB_A_DQ<25>

G26

DQA_25

FB_A_DQ<26>

H25

DQA_26

QSA_0

J31

89 5

FB_A_RDQS<0>

IO

FB_A_DQ<27>

H24

DQA_27

K29

89 5

FB_A_RDQS<1>

IN

IO

FB_A_DQ<28>

 E QSA_1  B  O QSA_2  R  T QSA_3  S

K25

89 5

FB_A_RDQS<2>

IN

F23

89 5

FB_A_RDQS<3>

QSA_4

D20

89 5

FB_A_RDQS<4>

IN

B16

89 5

FB_A_RDQS<5>

IN

D16

89 5

FB_A_RDQS<6>

H15

89 5

FB_A_RDQS<7>

90

DQA_28 DQA_29

J23

DQA_30

J22

DQA_31

FB_A_DQ<32>

E23

DQA_32

 D  A QSA_5  E  R QSA_6

FB_A_DQ<33>

D22

DQA_33

QSA_7

FB_A_DQ<34>

D23

DQA_34

FB_A_DQ<35>

E22

DQA_35

QSA_0*

K31

89 5

FB_A_WDQS<0>

IO

FB_A_DQ<36>

E20

DQA_36

K28

89 5

FB_A_WDQS<1>

IO

FB_A_DQ<37>

 E QSA_1*  B  O QSA_2*  R  T QSA_3*  S

K26

89 5

G24

89 5

D21

89 5

FB_A_WDQS<4>

C16

89 5

FB_A_WDQS<5>

D15

89 5

FB_A_WDQS<6>

J15

89 5

FB_A_WDQS<7>

IO

FB_A_WDQS<2> FB_A_WDQS<3>

B18

DQA_41

FB_A_DQ<42>

C17

DQA_42

QSA_7*

FB_A_DQ<43>

B17

DQA_43

FB_A_DQ<44>

C14

DQA_44

CLKA0

D31

89 5

FB_A_CLK_P<0>

FB_A_DQ<45>

B14

DQA_45

CLKA0*

E31

89 5

FB_A_CLK_N<0>

FB_A_DQ<46>

C13

DQA_46

FB_A_DQ<47>

B29

89 5

FB_A_CS_L<0>

DQA_47

CSA0_0*

B13

FB_A_DQ<48>

DQA_48

CSA0_1*

C28

D17

FB_A_DQ<49>

E18

DQA_49

CKEA0

B30

89 5

FB_A_CKE<0>

FB_A_DQ<50>

E17

DQA_50

FB_A_DQ<51>

F17

DQA_51

FB_A_DQ<52>

E15

DQA_52

FB_A_DQ<53>

E14

DQA_53

FB_A_DQ<54>

F14

DQA_54

FB_A_DQ<55>

D13

DQA_55

FB_A_DQ<56>

H18

DQA_56

FB_A_DQ<57>

H17

IO

FB_A_DQ<58>

IO

FB_A_DQ<59>

IO

FB_A_DQ<60>

IO

FB_A_DQ<61>

G14

DQA_61

FB_A_DQ<62>

H14

DQA_62

FB_A_DQ<63>

J14

DQA_63

GPU_MVREFD0

C31

MVREFD_0

GPU_MVREFS0

C30

MVREFS_0

IO IO IO IO IO IO IO IO IO IO IO IO IO

IO IO

C8713

90

OUT

90

OUT

90

OUT

90

OUT

90

OUT

90 5

OUT

90

OUT

90

OUT

90

OUT

90

OUT

90

OUT

90 90 5

RASA0*

B28

89 5

FB_A_RAS_L<0>

CASA0*

C29

89 5

FB_A_CAS_L<0>

WEA0*

B31

89 5

FB_A_WE_L<0>

90 90

OUT

90 90

OUT

90

OUT

90

TP_FB_A_ODT<0> OUT

CLKA1

B20

89 5

FB_A_CLK_P<1>

G18

DQA_58

CLKA1*

C19

89 5

FB_A_CLK_N<1>

G17

DQA_59

G15

DQA_60

VSSRH0

90

OUT

DQA_57

A28

90 5

NC

F29

(1.8V/ VDDRH0  2.0V)

90

90

ODTA0

A27

90

90

DQA_40

IO

90

IN

B19

IO

90

IN

FB_A_DQ<41>

IO

90

IN

 E QSA_4*  T  I QSA_5*  R  W QSA_6*

IO

90

IN

H22

DQA_39

90 5

IO

H23

DQA_38

90

IO

FB_A_DQ<31>

DQA_37

90

IO

FB_A_DQ<30>

D18

90

IO

FB_A_DQ<29>

D19

90

IO

IO

F20

90

IO

IO

FB_A_DQ<40>

90

OUT

G28

FB_A_DQ<39>

90

OUT

FB_A_DQM_L<4>

FB_A_DQ<38>

90

OUT

FB_A_DQM_L<2>

IO

90

OUT

FB_A_DQM_L<3>

IO

90

OUT

89

IO

90

OUT

TP_FB_A_MA12

89

IO

90

OUT

89

IO

90 5

OUT

G23

IO

90

OUT

J26

IO

90

OUT

DQMA_3*

IO

90

OUT

DQMA_2*

IO

90

OUT

DQA_20

IO

90

OUT

DQA_19

IO

90

OUT

J25

IO

90

OUT

FB_A_DQ<21>

IO

90 5

OUT

FB_A_MA<3>

IO

IO

0.1uF

1% 1/16W MF-LF 402

(4 OF 7)

FB_A_DQ<0>

IO

90 90 5

CSA1_0*

B23

CSA1_1*

C23

89 5

FB_A_CS_L<1>

OUT

88 87 86

=PP1V8R2V0_S0_FB_GPU

90 90

OUT

NC

R8720

CKEA1

C22

89 5

FB_A_CKE<1>

RASA1*

B24

89 5

FB_A_RAS_L<1>

CASA1*

B22

89 5

FB_A_CAS_L<1>

WEA1*

B21

89 5

FB_A_WE_L<1>

ODTA1

D24

TP_FB_A_ODT<1>

90

OUT

OUT OUT

1

1

90

R8722

40.2

40.2

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

2

90 90 90

OUT

R8721

1

C8721

100 1% 1/16W MF-LF 402

1 1

10% 16V X5R 402

2

R8723

1

100

0.1uF

L8715 =PP1V8R2V0_S0_FB_GPU

88 87 86 2

0402

2 2

C8715

C8716 10% 6.3V CERM 402

G4

90

FB_B_MA<0>

C12

DQB_1

MAB_1

E6

90

FB_B_MA<1>

IO

FB_B_DQ<2>

B11

DQB_2

MAB_2

E4

90

FB_B_MA<2>

IO

FB_B_DQ<3>

C11

DQB_3

MAB_3

H4

FB_B_DQ<4>

C8

DQB_4

MAB_4

J5

90

FB_B_MA<4>

IO

FB_B_DQ<5>

B7

DQB_5

MAB_5

G5

90

FB_B_MA<5>

IO

FB_B_DQ<6>

C7

DQB_6

 B

MAB_6

F4

90

FB_B_MA<6>

FB_B_DQ<7>

B6

DQB_7

MAB_7

H6

90

FB_B_MA<7>

IO

FB_B_DQ<8>

F12

DQB_8

MAB_8

G3

90

FB_B_MA<8>

IO

FB_B_DQ<9>

D12

DQB_9

 E  C  A  F  R  E  T  N  I

MAB_9

G2

90

FB_B_MA<9>

MAB_10

D4

90

FB_B_MA<10>

MAB_11

F2

90

FB_B_MA<11>

MAB_12

F5

MAB_13 MAB_14

D5

90

H2

90

FB_B_BA<2> FB_B_BA<0>

MAB_15

H3

90

FB_B_BA<1>

IO

IO

IO

C8723

2

2

5% 1/16W MF-LF 402 1

1

10% 6.3V CERM 402

C8726

1

1uF

1uF 2

10% 6.3V CERM 402

2

2

OUT OUT OUT

FB_B_MA<3>

OUT OUT OUT

OUT OUT OUT

FB_B_DQ<10>

E11

DQB_10

FB_B_DQ<11>

F11

DQB_11

IO

FB_B_DQ<12>

F9

DQB_12

D8

IO

FB_B_DQ<13> FB_B_DQ<14>

D7

DQB_13 DQB_14

IO

FB_B_DQ<15>

F7

DQB_15

FB_B_DQ<16>

G12

DQB_16

IO

FB_B_DQ<17>

G11

DQB_17

DQMB_0*

B8

90

FB_B_DQM_L<0>

IO

IO

FB_B_DQ<18>

H12

DQB_18

DQMB_1*

D9

90

FB_B_DQM_L<1>

IO

FB_B_DQ<19>

H11

FB_B_DQ<20>

IO

IO

 Y  R  O  M  E  M

OUT OUT

TP_FB_B_MA12

OUT OUT OUT OUT

DQB_19

DQMB_2*

G9

90

FB_B_DQM_L<2>

H9

DQB_20

DQMB_3*

K7

90

FB_B_DQM_L<3>

FB_B_DQ<21>

E7

DQB_21

DQMB_4*

M5

90

FB_B_DQM_L<4>

FB_B_DQ<22>

F8

DQB_22

DQMB_5*

V2

90

FB_B_DQM_L<5>

FB_B_DQ<23>

G8

DQB_23

DQMB_6*

W4

90

FB_B_DQM_L<6>

IO

FB_B_DQ<24>

G6

DQB_24

DQMB_7*

T9

90

FB_B_DQM_L<7>

IO

FB_B_DQ<25>

G7

DQB_25

FB_B_DQ<26>

H8

DQB_26

QSB_0

B9

90 5

FB_B_RDQS<0>

IO

FB_B_DQ<27>

J8

DQB_27

D10

90 5

FB_B_RDQS<1>

IO

FB_B_DQ<28>

 E QSB_1  B  O QSB_2  R  T QSB_3  S

H10

90 5

FB_B_RDQS<2>

K6

90 5

FB_B_RDQS<3>

N4

90 5

FB_B_RDQS<4>

U2

90 5

FB_B_RDQS<5>

U4

90 5

FB_B_RDQS<6>

V8

90 5

FB_B_RDQS<7>

IO IO IO IO IO

IO

IO IO IO IO IO IO

OUT OUT

K8

DQB_28

FB_B_DQ<29>

L8

DQB_29

IO

FB_B_DQ<30>

K9

DQB_30

IO

FB_B_DQ<31>

L9

DQB_31

FB_B_DQ<32>

K5

DQB_32

 D  A QSB_5  E  R QSB_6

FB_B_DQ<33>

L4

DQB_33

QSB_7

FB_B_DQ<34>

K4

DQB_34

FB_B_DQ<35>

L5

DQB_35

QSB_0*

B10

90 5

FB_B_WDQS<0>

IO

FB_B_DQ<36>

N5

DQB_36

E10

90 5

FB_B_WDQS<1>

IN

IO

FB_B_DQ<37>

 E QSB_1*  B  O QSB_2*  R  T QSB_3*  S

G10

90 5

FB_B_WDQS<2>

IN

J7

90 5

FB_B_WDQS<3>

M4

90 5

FB_B_WDQS<4>

IN

U3

90 5

FB_B_WDQS<5>

IN

V4

90 5

FB_B_WDQS<6>

IO

IO IO IO IO

N6

DQB_37

FB_B_DQ<38>

P4

DQB_38

IO

FB_B_DQ<39>

R4

DQB_39

IO

FB_B_DQ<40>

IO

QSB_4

OUT OUT OUT OUT OUT

IN

IN

P2

DQB_40

FB_B_DQ<41>

R2

DQB_41

FB_B_DQ<42>

T3

DQB_42

QSB_7*

V9

90 5

FB_B_WDQS<7>

FB_B_DQ<43>

T2

DQB_43

FB_B_DQ<44>

W3

DQB_44

CLKB0

B4

90 5

FB_B_CLK_P<0>

FB_B_DQ<45>

W2

DQB_45

CLKB0*

B5

90 5

FB_B_CLK_N<0>

FB_B_DQ<46>

Y3

DQB_46

FB_B_DQ<47>

D2

90 5

FB_B_CS_L<0>

DQB_47

CSB0_0*

Y2

FB_B_DQ<48>

DQB_48

CSB0_1*

E3

T4

FB_B_DQ<49>

R5

DQB_49

CKEB0

C2

90 5

FB_B_CKE<0>

FB_B_DQ<50>

T5

DQB_50

FB_B_DQ<51>

E2

90 5

FB_B_RAS_L<0>

DQB_51

RASB0*

T6

FB_B_DQ<52>

V5

DQB_52

CASB0*

D3

90 5

FB_B_CAS_L<0>

FB_B_DQ<53>

W5

DQB_53

FB_B_DQ<54>

WEB0*

90 5

FB_B_WE_L<0>

DQB_54

B2

W6

FB_B_DQ<55>

Y4

DQB_55

ODTB0

D6

FB_B_DQ<56>

R8

DQB_56

FB_B_DQ<57>

T8

DQB_57

CLKB1

N2

90 5

FB_B_CLK_P<1>

IO

FB_B_DQ<58>

R7

DQB_58

CLKB1*

P3

90 5

FB_B_CLK_N<1>

IO

FB_B_DQ<59>

T7

DQB_59

FB_B_DQ<60>

K2

90 5

FB_B_CS_L<1>

V7

DQB_60

CSB1_0*

IO

W7

DQB_61

K3

IO

FB_B_DQ<61>

CSB1_1*

FB_B_DQ<62>

W8

DQB_62

CKEB1

L3

90 5

FB_B_CKE<1>

FB_B_DQ<63>

W9

DQB_63

GPU_MVREFD1

B3

MVREFD_1

GPU_MVREFS1

C3

MVREFS_1

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

IO IO

F1

(1.8V/ VDDRH1  2.0V)

E1

VSSRH1

GPU_TEST_MCLK

AA5

TEST_MCLK

GPU_TEST_YCLK

AA2

TEST_YCLK

GPU_MEMTEST

AA7

MEMTEST

IN IN

OUT OUT

OUT OUT OUT OUT

TP_FB_B_ODT<0>

OUT

OUT OUT

B

OUT

NC OUT

J2

90 5

FB_B_RAS_L<1>

L2

90 5

FB_B_CAS_L<1>

WEB1*

M2

90 5

FB_B_WE_L<1>

ODTB1

J4

DRAM_RST

OUT

NC

CASB1*

RASB1*

C

OUT

 E QSB_4*  T  I QSB_5*  R  W QSB_6*

IO

D

OUT

IO

IO

10% 16V X5R 402

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

C8725

2

90 5

AA3

1

88

1

OUT OUT OUT

TP_FB_B_ODT<1>

4.7K

FERR-220-OHM

1

1uF 2

MAB_0

FB_B_DQ<1>

IO

0.1uF

1% 1/16W MF-LF 402

0402 1

1uF 10% 6.3V CERM 402

=PP1V8R2V0_S0_FB_GPU

1

PP1V8R2V0_S0_GPU_VDDRH0 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

DQB_0

PP1V8R2V0_S0_GPU_VDDRH1

L8725

FERR-220-OHM 1

B12

OUT

R8731 87 86 88

FB_B_DQ<0>

OUT

10% 16V X5R 402

2

1

OMIT

FB_DRAM_RST

OUT

OUT

R8733 4.7K

2

2 1

R8730

R8732

4.7K

243

5% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

ATI M56 Frame Buffer I/F

A

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

87

1

110

A

 

8

 

7

6

 

 

5

 

4

M56 GPIOS

"S0" GPU RAILS

=PP3V3_S0_GPU_VDDR3 88

3

 

2

1

91

ONLY ON IN RUN

94 91 59

D

PP1V0R1V2_S0_GPU MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.125MM VOLTAGE=1.2V

=PPVCORE_S0_GPU_REG

85

=PPVCORE_S0_GPU

PP5V_S0_GPUVCORE_VCC

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.125MM VOLTAGE=5V

10 1 1 /1 0W

 

2

R8800 6 03 MF-LF

=PP5V_S0_GPUVCORE

85

5%

=PP1V2_S0_PCIE_GPU_VDDR

84

=PP1V2_S0_PCIE_GPU_PVDD

84

=PPVIO_S0_PCIE

76 61 59 41 26 11 10 6

91

=PPVOUT_S0_GPUBBP_LDO

85

=PNVOUT_S0_GPUBBN_REG =PNBB_S0_GPU

PP3V3_S0

 

10K1

 

2

1/16W

91

GPU_GPIO_2

1 10K 1/16W

91

GPU_GPIO_3

10K1

91

GPU_GPIO_4

D

R8802 402 MF-LF

5%

10K1

 

R8803

 

2 402 MF-LF 5%

NOSTUFF  

2

1 /1 6W

R8804 4 02 M F -L F 5%

NOSTUFF  

2

1/16W

R8805 402 MF-LF

5%

GPIO 4 = DEBUG SIGNALS OUT

86 91

GPU_GPIO_5

10K1

91

GPU_GPIO_6

10K1

 

 

2

1/16W

R8806 402 MF -LF

5%

85

86

=PP3V3_S0_GPUBBP =PP3V3_DDC_DVI

97

=PP3V3_S0_LCD

94

91

=PP3V3_S0_GPU_VDDR3 =PP3V3_S0_GPU

NOSTUFF  

2

1/16W

R8807 402 MF-LF

5%

GPU_GPIO_7

91

GPU_GPIO_10

91

TP_GPU_GPIO_7 MAKE_BASE=TRUE

=PP3V3_S0_GPUBBCTL

C

402 MF-L F 5%

NOSTUFF

77

=PP1V2_S0_GPU_VDDPLL

=PPBB_S0_GPU

PNBB_S0_GPU MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0

GPU_GPIO_1

84

=PP1V2_S0_REG

PPBB_S0_GPU MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.125MM VOLTAGE=1.2V

R8813

GPIO 1 = TRANSMITTER DE-EMPHASIS ENABLE INTERNAL PULL DOWN, ATI RECOMMENDS HIGH

GPUVCORE_VCC MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.125MM VOLTAGE=5V

PP1V2_GPU_IO_S0 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.125MM VOLTAGE=1.2V

1/16W

2

85

91

85

 

GPIO 0 = TRANSMITTER POWER SAVINGS ENABLE INTERNAL PULL DOWN, ATI RECOMMENDS HIGH

86 91

=PPVCORE_S0_GPU_BBP

 

10K1

GPU_GPIO_0

88 91

GPU_GPIO_8

10K1

402 MF-LF

91

GPU_GPIO_9

   2 R8809 10K1 NOSTUFF

91

GPU_GPIO_13

10K1

91

=PP2V5_S0_GPU_PVDD

91

=PP2V5_S0_GPU_VDD25

91 91

=PP2V5_S0_GPU_VDDC_CT

=PP1V8_S0_FB_VDD

1 /1 6W

4 02 M F- LF

NOSTUFF  

2

5%

R8812 402 MF-LF  5%

1/16W

 

10K 1

2 R8810

1/16W

402 MF-LF 5%

NOSTUFF  

10K1

2

1/16W

R8811 402 MF-LF

5%

93

GPIO 9,13,12,11 = ROM ID CFG INTERNAL PULL DOWN 0010 = 256 M APERATURE SIZE

89 90

=PP1V8R3V3_S0_GPU_VDDR4

ATI_FB_256M

91

=PP1V8R3V3_S0_GPU_VDDR5 =PP1V8_S0_FB_VDDQ

GPU_GPIO_11

91

=PP2V5_S0_GPU

PP1V8R2V0_S0_FB_GPU MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.125MM VOLTAGE=1.8V

GPU_GPIO_12

91

91

GPU_GPIO_24

 

10K1

2

1/16W

402 MF-LF

5%

TP_GPU_VGA_R MAKE_BASE=TRUE

GPU_VGA_R

93

TP_GPU_VGA_G MAKE_BASE=TRUE

GPU_VGA_G

93

TP_GPU_VGA_B MAKE_BASE=TRUE

GPU_VGA_B

86 87

GPU_VGA_HSYNC

93

TP_GPU_VGA_VSYNC MAKE_BASE=TRUE

GPU_VGA_VSYNC

93

TP_GPU_TV_Y MAKE_BASE=TRUE

GPU_TV_Y

93

TP_GPU_TV_COMP MAKE_BASE=TRUE

GPU_TV_COMP

93

GPU_TV_C

TP_GPU_DDC_B_DATA MAKE_BASE=TRUE

ATI_FB_HYNIX 91

GPU_GPIO_27

10K1

91

GPU_GPIO_28

10K1

91

GPU_GPIO_29

10K1

 

2

R8831   4 02 MF-LF

1 /1 6W

93

TP_GPU_VGA_HSYNC MAKE_BASE=TRUE

TP_GPU_DDC_B_CLK MAKE_BASE=TRUE

78

=PP1V8R2V0_S0_FB_GPU

91

TP_GPU_TV_C MAKE_BASE=TRUE

R8830

89 90

PP1V8_S0

GPU_GPIO_17

C

ATI_FB_256M

PP2V5_S0

TP_GPU_GPIO_17 MAKE_BASE=TRUE

5%

=PP3V3_S0_GPUBBN

77 11 6

91

2

=PP3V3_S0_GPU_CLOCKS =PP3V3_DDC_LCD 94 =PP3V3_GPU 94

GPU_GPIO_14

NOSTUFF   R8808

1/16W

NC_GPU_GPIO_10 MAKE_BASE=TRUE

6 91 93 97

TP_GPU_GPIO_14 MAKE_BASE=TRUE

93

GPU_DDC_B_CLK

93

GPU_DDC_B_DATA

93

5%

B

B 83 81 80 79 78 77 11 6 5

PP12V_S5

6

PP12V_S0

=PPVIN_S0_GPUVCORE

85

 

 

2

1/16W

R8832 402 MF-LF 5%

TMDS_PANEL =PP12V_GPU

94

1/16W

 

2

R8833 402 MF-LF

5%

 

2

GPU_VCORE_LOW MAKE_BASE=TRUE 97 75 6

PP5V_S0

GPU_GPIO_15

10K1

=PP5V_S0_GPUBBCTL

1/16W

=PP5V_S0_DVI_DDC

97

=PP5V_S0_GPUISENS

85

 

91

R8850 402 MF-LF

5%

GPIO 15 = SWITCH CORE VOLTAGE HIGH TO LOW EXTERNAL PULL DOWN RECOMMENDED

85

GPUVCORE_EN

87

33 1   1 / 16 W

 

2

R8801 4 02 M F- LF

FB_DRAM_RST MAKE_BASE=TRUE

5%

PM_SLP_S3_L 6

DRAM_RST

23 58 77 79

GPU MISC

5 89 90

A

A

8

 

7

6

 

5

 

4

 

3

 

2

 

1

 

8

6

7

2

3

4

5

90 89 88

IN

=PP1V8_S0_FB_VDD

90 89 88

C8900

1

1

22uF 20% 6.3V X5R 805

2

2

C8901

1

C8902

1

C8903

C8904

1

0.1uF

0.1uF

0.1uF

0.1uF

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

2

2

L8910 FERR-220-OHM 1

D

2

PP1V8_FB_A0_VDDA0

L8915

1

FERR-220-OHM

C8910

C8915

1

0.1uF

0.1uF 1

2

PP1V8_FB_A0_VDDA1 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

0402

2

10% 16V X5R 402

10% 16V X5R 402

2

U8900.J1

U8900.J12

Connect to designated pin, then GND 90 89 88

IN

=PP1V8_S0_FB_VDDQ

C8920

1

1

22uF 20% 6.3V X5R 805

2

2

C8921

1

C8922

1

C8923

1

C8924

1

C8925

1

C8926

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

R8930

1

2

R8932

2.37K

2.37K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

2

2

2

1

2

FB_A0_VREF0 FB_A0_VREF1

R8940

F12

VDD3

M1

VDD4

M12

VDD5

V2

VDD6

V11

VDD7

OMIT

U8900 FBGA

(2 OF 2)

VDDA0

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

IN

=PP1V8_S0_FB_VDD

Power aliases required by this page:

VSS0

A3

VSS1

A10

VSS2

G1

VSS3

G12

VSS4

L1

VSS5

L12

VSS6

V3

VSS7

V10

FERR-220-OHM

J1

1

VSSA0

C8950 22uF 20% 6.3V X5R 805

2

0402

J12 B1

L8965

VSSQ1

B4

FERR-220-OHM

VDDQ2

VSSQ2

B9

VDDQ3

VSSQ3

B12

VDDQ4

VSSQ4

D1

VDDQ0 VDDQ1

C1 C4 C9 C12

VDDQ5

VSSQ5

D4

E1

VDDQ6

VSSQ6

D9

E4

VDDQ7

VSSQ7

D12

E9

VDDQ8

VSSQ8

G2

E12

VDDQ9

VSSQ9

G11

VDDQ10

VSSQ10

L2

J9

VDDQ11

VSSQ11

L11

N1

VDDQ12

VSSQ12

P1

N4

VDDQ13

VSSQ13

N9

VDDQ14

N12

1

89 87 89 87 89 87 5 89 87 89 87 89 87 89 87 89 87 89 87 89 87 89 87 87 5 87 5 87 5 87 5 87 5 87 5 87 5

90 89 88 5

87 5 87 5 87 5 87 5

87 5 87 5 87 5 87 5

89 87 89 87 89 87

R8933

5.49K

5.49K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

R8942

2

1

C8931

2

0.1uF

0.1uF

0.1uF

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

IN

C8970

1

1

C8971

1

C8972

1

1

60.4

121

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

A4

IN

FB_A_MA<5>

H2

A5

IN

FB_A_MA<6>

IN IN IN IN

K3

FB_A_MA<10>

K11

FB_A_MA<11>

L9

FB_A_CKE<0>

H9

FB_A_CLK_P<0>

J11

FB_A_CLK_N<0>

VSSQ2

B9

VDDQ3

VSSQ3

B12

C9

VDDQ4

VSSQ4

D1

C12

VDDQ5

VSSQ5

D4

E1

VDDQ6

VSSQ6

D9

E4

VDDQ7

VSSQ7

D12

E9

VDDQ8

VSSQ8

G2

E12

VDDQ9

VSSQ9

G11

P4 P9 P12

VDDQ16

VSSQ16

T1

R1

VDDQ16

VSSQ16

T1

R4

VDDQ17

VSSQ17

T4

R8980

R4

VDDQ17

VSSQ17

T4

R9

VDDQ18

VSSQ18

T9

2.37K

2.37K

R9

VDDQ18

VSSQ18

T9

R12

VDDQ19

VSSQ19

T12

VDDQ19

VSSQ19

T12

VDDQ20

1% 1/16W MF-LF 402

R12

V1

1% 1/16W MF-LF 402

V1

VDDQ20

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

1

2

R8982

2

H1

VREF0

H12

VREF1

2

2

2

1

2

VDDQ21

FB_A1_VREF0

V12

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

FB_A1_VREF1

R8981

10% 16V X5R 402

E10

87

FB_A_DQM_L<3>

DM2

N10

87

FB_A_DQM_L<2>

DM3

N3

87

FB_A_DQM_L<1>

A6

 H  G  I  H  F  M

A10

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

IN IN IN

B2

87

FB_A_DQ<2>

B3

87

FB_A_DQ<4>

DQ2

C2

87

FB_A_DQ<3>

IO

DQ3

C3

87

FB_A_DQ<7>

IO

DQ4

E2

87

FB_A_DQ<1>

IO

DQ5

F3

87

FB_A_DQ<5> FB_A_DQ<0>

DQ6

F2

A11

DQ7

G3

87

FB_A_DQ<6>

CKE

DQ8

B11

87

FB_A_DQ<28>

DQ9

B10

87

FB_A_DQ<30>

C11

87

FB_A_DQ<29> FB_A_DQ<27>

87 5

FB_A_WE_L<0>

H4

WE*

DQ12

E11

87

FB_A_DQ<31>

FB_A_CAS_L<0>

F9

CAS*

DQ13

F10

87

FB_A_DQ<25>

FB_A_RAS_L<0>

H10

RAS*

DQ14

F11

87

FB_A_DQ<26>

IO IO

IO

1

1

R8983

5.49K

5.49K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

R8992

2

1

1

1

IO IO IO IO IO IO IO IO

A4

ZQ

DQ15

G10

FB_A0_MF

A9

MF

DQ16

M11

87

FB_A_DQ<21>

FB_A0_SEN

V4

SEN

DQ17

L10

87

FB_A_DQ<23>

DRAM_RST

V9

RESET

DQ18

N11

87

FB_A_DQ<19>

FB_A_RDQS<0>

DQ19

M10

87

FB_A_DQ<20>

D3

DQ20

R11

DQ21

R10

DQ22

T11

87

FB_A_DQ<18>

DQ23

T10

87

FB_A_DQ<17>

IO IO

FB_A_RDQS<3>

D10

FB_A_RDQS<2>

P10

FB_A_RDQS<1>

P3

RDQS0 RDQS1 RDQS2 RDQS3

87

FB_A_DQ<24>

FB_A_DQ<22> 87 5

FB_A_DQ<16>

FB_A_WDQS<0>

D2

WDQS0

DQ24

M2

87

FB_A_DQ<13>

FB_A_WDQS<3>

D11

WDQS1

DQ25

L3

87

FB_A_DQ<14>

FB_A_WDQS<2>

P11

WDQS2

DQ26

N2

87

FB_A_DQ<12>

FB_A_WDQS<1>

P2

WDQS3

DQ27

M3

87

FB_A_DQ<15>

DQ28

R2

87

FB_A_DQ<11>

DQ29

R3

FB_A_BA<0>

G9

FB_A_BA<1>

G4

FB_A_BA<2>

2

H3

TP_U8900_J2

J2

TP_U8900_J3

J3

BA0  H  G  I BA1  H  F BA2  M

DQ30 DQ31

T2 T3

87 5 87 87

FB_A_DQ<8>

FB_A_DQ<10> FB_A_DQ<9>

89 87 89 87 89 87 5

89 87 89 87 89 87 89 87 89 87 89 87

R8991

1

2

Signal aliases required by this page: (NONE)

D

VDDQ21

H1

VREF0

H12

VREF1

C

C8983 0.1uF

10% 16V X5R 402

2

10% 16V X5R 402

2

1

R8996

2 1

R8993 121

60.4

5% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

1

2

R8995

1K

2

1

0.1uF

R8994

2

C8981

1

R8997 121

2

CRITICAL

1% 1/16W MF-LF 402

FB_A_MA<0>

K9

A0

OMIT

89 87 87 5 87 5 87 5 87 5 87 5 87 5 87 5

FB_A_DQM_L<4>

U8950

DM0

E3

FB_A_MA<1>

H11

A1

FBGA

DM1

E10

FB_A_MA<2>

K10

A2

(1 OF 2)

DM2

N10

87

FB_A_DQM_L<6>

FB_A_MA<3>

M9

A3

DM3

N3

87

FB_A_DQM_L<5>

IN

FB_A_MA<4>

K4

A4

FB_A_MA<5>

87

FB_A_DQ<36>

A5

B2

H2

DQ0

IO

IN

DQ1

B3

87

FB_A_DQ<34>

IN

FB_A_MA<6>

DQ2

C2

87

FB_A_DQ<37>

IO

DQ3

C3

87

FB_A_DQ<33>

IO

DQ4

E2

87

FB_A_DQ<35>

IO

DQ5

F3

87

FB_A_DQ<38>

IN IN IN IN IN

K3

A6

 H  G  I  H  F  M

IN

FB_A_MA<7>

L4

A7

IN

FB_A_MA<8>

K2

A8/AP

FB_A_MA<9>

M4

A9

IN IN

FB_A_MA<10>

IN

FB_A_MA<11>

K11

A10

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

IN IN IN IN IN IN IN

L9

FB_A_CKE<1>

H9

FB_A_CLK_P<1>

J11

FB_A_CLK_N<1>

87 87

FB_A_DQM_L<7>

FB_A_DQ<32>

DQ6

F2

A11

DQ7

G3

87

FB_A_DQ<39>

CKE

DQ8

B11

87

FB_A_DQ<61>

CK

DQ9

B10

87

FB_A_DQ<59>

C11

87

FB_A_DQ<60> FB_A_DQ<58> FB_A_DQ<57>

IO

FB_A0_ZQ

87 5

89 87

89 87

DQ1

CK

 H  G  I  H  F  M

IN

DQ0

C10

2

VDDQ2

C4

R1

DQ11

2

C1

P1

CS*

R8949

B4

VSSQ15

F4

100

B1

VSSQ1

VDDQ15

87

1

VSSQ0

VDDQ1

N12

DQ10

1

J12

VDDQ0

P12

CK*

243

VSSA1

A1 A12

VSSQ15

J10

1% 1/16W MF-LF 402

J1

VDDQ15

FB_A_CS_L<0>

R8948

VSSA0

L11

DM1

A9

IN

(NONE)

V10

VSSQ14

FBGA

A7

IN

V3

VSS7

VDDQ14

(1 OF 2)

A8/AP

IN

VDDA1

BOM options provided by this page:

VSS6

N9

A2

M4

OUT

K12

L12

P9

A1

K2

OUT

VDDA0

VSS5

VSSQ14

FB_A_DQM_L<0>

L4

OUT

K1

L1

L2

87

FB_A_MA<9>

OUT

VDD7

VSS4

VSSQ13

E3

FB_A_MA<8>

IN

VDD6

G12

VDDQ13

DM0

FB_A_MA<7>

IN

V2 V11

VSS3

N4

10% 16V X5R 402

C8933

OMIT

IN

IN

VDD5

- =PP1V8_S0_FB_VDDQ

G1

P4

U8900

IN

IN

M12

- =PP1V8_S0_FB_VDD

A10

VSS2

VSSQ12

2

K4

IN

VDD4

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

A3

VSS1

VDDQ12

1

FB_A_MA<4>

IN

M1

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

VSS0

N1

2

2

CRITICAL

A3

IN

VDD3

FBGA

VSSQ11

R8947

121

5% 1/16W MF-LF 402

M9

IN

F12

OMIT

U8950 (2 OF 2)

VDDQ11

2

1K

K10

IN

VDD2

J9

20% 6.3V X5R 805

1% 1/16W MF-LF 402

H11

IN

VDD1

VSSQ10

0.1uF

60.4

FB_A_MA<3>

IN

C8976

0.1uF

121

2

1

0.1uF

1% 1/16W MF-LF 402

2

C8975

0.1uF

121

R8945

1

0.1uF

1% 1/16W MF-LF 402

1

C8974

0.1uF

121

2

U8900.J12

VDD0

F1

VDDQ10

R8990

FB_A_MA<2>

IN

1

1% 1/16W MF-LF 402

R8943

10% 16V X5R 402

2

A2 A11

J4

22uF

1

FB_A_MA<1>

IN

C8973

1% 1/16W MF-LF 402

1

0.1uF

10% 16V X5R 402

=PP1V8_S0_FB_VDDQ

60.4

2

C8965

1

U8900.J1

121

A0

IN

2

1% 1/16W MF-LF 402

R8941

2

C8960

PP1V8_FB_A1_VDDA1 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

121

2

2

1

1% 1/16W MF-LF 402

K9

IN

2

PP1V8_FB_A1_VDDA0

2

0402

2

R8946

C8954

1

0.1uF 1

0.1uF

FB_A_MA<0>

IN

1

0.1uF

1

C8953

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM 1

1

R8944

1

0.1uF

121

2 89 87

1

C8952

Connect to designated pin, then GND 90 89 88

J4

2

1

VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

VSSQ0

VDDA1

A1 A12

2

C8951

L8960

VSSA1

K12

1

1

1% 1/16W MF-LF 402

1

A

VDD2

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

R8931

B

VDD1

V12

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

C

VDD0

F1

K1

VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

0402

A2 A11

1

Page Notes

CRITICAL

CRITICAL

87 5

J10

CK*

DQ10

FB_A_CS_L<1>

F4

CS*

DQ11

C10

87

FB_A_WE_L<1>

H4

WE*

DQ12

E11

87

FB_A_CAS_L<1>

F9

CAS*

DQ13

F10

FB_A_RAS_L<1>

H10

RAS*

DQ14

F11

87

FB_A_DQ<62>

 H  G  I  H  F  M

87 5

FB_A_DQ<56>

IN IN IN

IO IO IO IO IO IO IO IO IO IO

FB_A1_ZQ

A4

ZQ

DQ15

G10

87

FB_A_DQ<63>

IO

FB_A1_MF

A9

MF

DQ16

M11

87

FB_A_DQ<50>

IO

IO

FB_A1_SEN

V4

SEN

DQ17

L10

87

FB_A_DQ<49>

IO

DRAM_RST

V9

RESET

DQ18

N11

87

FB_A_DQ<53>

FB_A_RDQS<4>

DQ19

M10

87

FB_A_DQ<51>

D3

DQ20

R11

DQ21

R10

87

FB_A_DQ<55>

DQ22

T11

87

FB_A_DQ<52>

DQ23

T10

87

FB_A_DQ<54>

IO

IO IO IO IO IO

IO IO IO IO IO IO

90 89 88 5

87 5 87 5 87 5 87 5

87 5 87 5 87 5 87 5

89 87 89 87 89 87

IN OUT OUT OUT OUT IN IN IN IN IN IN IN

FB_A_RDQS<7>

D10

FB_A_RDQS<6>

P10

FB_A_RDQS<5>

P3

RDQS0 RDQS1 RDQS2 RDQS3

FB_A_DQ<48>

FB_A_WDQS<4>

D2

WDQS0

DQ24

M2

FB_A_WDQS<7>

D11

WDQS1

DQ25

L3

87

FB_A_DQ<42>

FB_A_WDQS<6>

P11

WDQS2

DQ26

N2

87

FB_A_DQ<41>

FB_A_WDQS<5>

P2

WDQS3

DQ27

M3

87

FB_A_DQ<43>

DQ28

R2

87

FB_A_DQ<47>

DQ29

R3

87

FB_A_DQ<45>

DQ30

T2

87

FB_A_DQ<46>

DQ31

T3

87

FB_A_DQ<44>

FB_A_BA<0>

G9

FB_A_BA<1>

G4

FB_A_BA<2>

H3

BA0  H  G  I BA1  H  F BA2  M

IO

RFU1 RFU2

R8998

1

1

R8999 100

243 1% 1/16W MF-LF 402

5% 1/16W MF-LF 402

87 5

2

2

TP_U8950_J2

J2

TP_U8950_J3

J3

87 5

FB_A_DQ<40>

B

IO

IO

IO IO IO IO IO IO IO

GDDR3 Frame Buffer A

IO IO

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

IO IO

NOTICE OF PROPRIETARY PROPERTY

IO

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

IO IO

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

RFU1 RFU2

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5% 1/16W MF-LF 402

SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

89

1

110

A

 

8

6

7

2

3

4

5

90 89 88

IN

=PP1V8_S0_FB_VDD

90 89 88

C9000

1

1

22uF 20% 6.3V X5R 805

2

2

C9001

1

C9002

1

C9003

C9004

1

0.1uF

0.1uF

0.1uF

0.1uF

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

2

2

L9010 FERR-220-OHM 1

D

2

PP1V8_FB_B0_VDDA0

L9015

1

FERR-220-OHM

C9010

C9015

1

0.1uF

0.1uF 1

2

PP1V8_FB_B0_VDDA1 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

0402

2

10% 16V X5R 402

10% 16V X5R 402

2

U9000.J1

U9000.J12

Connect to designated pin, then GND 90 89 88

IN

=PP1V8_S0_FB_VDDQ

C9020

1

1

22uF 20% 6.3V X5R 805

2

2

C9021

1

C9022

1

C9023

1

C9024

1

C9025

1

C9026

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

R9030

1

2

R9032

2.37K

2.37K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

2

2

2

1

2

FB_B0_VREF0 FB_B0_VREF1

R9040

F12

VDD3

M1

VDD4

M12

VDD5

V2

VDD6

V11

VDD7

OMIT

U9000 FBGA

(2 OF 2)

VDDA0

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

IN

=PP1V8_S0_FB_VDD

Power aliases required by this page:

VSS0

A3

VSS1

A10

VSS2

G1

VSS3

G12

VSS4

L1

VSS5

L12

VSS6

V3

VSS7

V10

FERR-220-OHM

J1

1

VSSA0

C9050 22uF 20% 6.3V X5R 805

2

0402

J12 B1

L9065

VSSQ1

B4

FERR-220-OHM

VDDQ2

VSSQ2

B9

VDDQ3

VSSQ3

B12

VDDQ4

VSSQ4

D1

VDDQ0 VDDQ1

C1 C4 C9 C12

VDDQ5

VSSQ5

D4

E1

VDDQ6

VSSQ6

D9

E4

VDDQ7

VSSQ7

D12

E9

VDDQ8

VSSQ8

G2

E12

VDDQ9

VSSQ9

G11

VDDQ10

VSSQ10

L2

J9

VDDQ11

VSSQ11

L11

N1

VDDQ12

VSSQ12

P1

N4

VDDQ13

VSSQ13

N9

VDDQ14

N12

1

90 87 90 87 90 87 5 90 87 90 87 90 87 90 87 90 87 90 87 90 87 90 87 87 5 87 5 87 5 87 5 87 5 87 5 87 5

90 89 88 5

87 5 87 5 87 5 87 5

87 5 87 5 87 5 87 5

90 87 90 87 90 87

R9033

5.49K

5.49K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

R9042

2

1

C9031

2

0.1uF

0.1uF

0.1uF

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

IN

C9070

1

1

C9071

1

C9072

1

1

60.4

121

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

A4

IN

FB_B_MA<5>

H2

A5

IN

FB_B_MA<6>

IN IN IN IN IN IN

K3

K11 L9

FB_B_CKE<0>

H9

FB_B_CLK_P<0>

J11

FB_B_CLK_N<0>

VSSQ2

B9

VDDQ3

VSSQ3

B12

C9

VDDQ4

VSSQ4

D1

C12

VDDQ5

VSSQ5

D4

E1

VDDQ6

VSSQ6

D9

E4

VDDQ7

VSSQ7

D12

E9

VDDQ8

VSSQ8

G2

E12

VDDQ9

VSSQ9

G11

P4 P9 P12

VDDQ16

VSSQ16

T1

R1

VDDQ16

VSSQ16

T1

R4

VDDQ17

VSSQ17

T4

R9080

R4

VDDQ17

VSSQ17

T4

R9

VDDQ18

VSSQ18

T9

2.37K

2.37K

R9

VDDQ18

VSSQ18

T9

R12

VDDQ19

VSSQ19

T12

VDDQ19

VSSQ19

T12

VDDQ20

1% 1/16W MF-LF 402

R12

V1

1% 1/16W MF-LF 402

V1

VDDQ20

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

1

2

R9082

2

H1

VREF0

H12

VREF1

2

2

2

1

2

VDDQ21

FB_B1_VREF0

V12

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

FB_B1_VREF1

R9081

10% 16V X5R 402

FB_B_DQM_L<0>

E10 N10

87

FB_B_DQM_L<2>

N3

87

FB_B_DQM_L<1>

A6

 H  G  I  H  F  M

A10

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

87 87

FB_B_DQM_L<3>

DQ0

B2

87

FB_B_DQ<2>

DQ1

B3

87

FB_B_DQ<4>

DQ2

C2

DQ3

C3

DQ4

E2

DQ5

F3

IN IN IN IO IO IO

87

FB_B_DQ<7>

IO

87

FB_B_DQ<1>

IO

87

FB_B_DQ<5> FB_B_DQ<0>

DQ6

F2

A11

DQ7

G3

87

FB_B_DQ<6>

CKE

DQ8

B11

87

FB_B_DQ<28>

DQ9

B10

87

FB_B_DQ<30>

C11

87

FB_B_DQ<29> FB_B_DQ<27>

87 5

FB_B_WE_L<0>

H4

WE*

DQ12

E11

87

FB_B_DQ<31>

FB_B_CAS_L<0>

F9

CAS*

DQ13

F10

87

FB_B_DQ<25>

FB_B_RAS_L<0>

H10

RAS*

DQ14

F11

87

FB_B_DQ<26> FB_B_DQ<24>

IO

1

1

R9083

5.49K

5.49K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

R9092

2

1

1

1

IO IO IO IO IO IO IO IO

Signal aliases required by this page: (NONE)

D

VDDQ21

H1

VREF0

H12

0.1uF

VREF1

2

C

1

R9096

FB_B_DQ<11>

DQ29

R3

FB_B_BA<0>

G9

FB_B_BA<1>

G4

FB_B_BA<2>

H3

TP_U9000_J2

J2

TP_U9000_J3

J3

BA0  H  G  I BA1  H  F BA2  M

DQ30 DQ31

T2 T3

87 5 87 87

FB_B_DQ<8>

FB_B_DQ<10> FB_B_DQ<9>

90 87 87 5 87 5

87

FB_B_DQ<39>

IN

FB_B_MA<10>

IN

FB_B_MA<11>

87 5 87 5 87 5 87 5 87 5

IN

K11

IN IN IN IN IN IN

L9

FB_B_CKE<1>

H9

FB_B_CLK_P<1>

J11

A10

FB_B_CLK_N<1>

FB_B_DQ<32>

DQ6

F2

A11

DQ7

G3

CKE

DQ8

B11

87

FB_B_DQ<61>

CK

DQ9

B10

87

FB_B_DQ<59>

C11

87

FB_B_DQ<60> FB_B_DQ<58> FB_B_DQ<57>

87 5

J10

CK*

DQ10

FB_B_CS_L<1>

F4

CS*

DQ11

C10

87

FB_B_WE_L<1>

H4

WE*

DQ12

E11

87

FB_B_CAS_L<1>

F9

CAS*

DQ13

F10

FB_B_RAS_L<1>

H10

RAS*

DQ14

F11

87

FB_B_DQ<62>

 H  G  I  H  F  M

87 5

FB_B_DQ<56>

IO IO IO IO IO IO IO IO IO

T11

87

FB_B_DQ<52>

DQ23

T10

87

FB_B_DQ<53>

IO

87

FB_B_DQ<45>

IO

IO

IO IO IO IO IO

IO IO IO IO IO IO

90 89 88 5

87 5 87 5 87 5 87 5

87 5 87 5 87 5 87 5

90 87 90 87 90 87

IN OUT OUT OUT OUT IN IN IN IN IN IN IN

FB_B_RDQS<7>

D10

FB_B_RDQS<6>

P10

FB_B_RDQS<5>

P3

RDQS0 RDQS1 RDQS2 RDQS3

FB_B_DQ<48>

FB_B_WDQS<4>

D2

WDQS0

DQ24

M2

FB_B_WDQS<7>

D11

WDQS1

DQ25

L3

FB_B_WDQS<6>

P11

WDQS2

DQ26

N2

87

FB_B_DQ<43>

FB_B_WDQS<5>

P2

WDQS3

DQ27

M3

87

FB_B_DQ<41>

DQ28

R2

87

FB_B_DQ<47>

DQ29

R3

87

FB_B_DQ<42>

DQ30

T2

87

FB_B_DQ<46>

DQ31

T3

87

FB_B_DQ<44>

FB_B_BA<0>

G9

FB_B_BA<1>

G4

FB_B_BA<2>

H3

BA0  H  G  I BA1  H  F BA2  M

IO

RFU1 RFU2

R9098

1

1

1% 1/16W MF-LF 402

R9099 100

243

5% 1/16W MF-LF 402

87 5

2

2

TP_U9050_J2

J2

TP_U9050_J3

J3

87 5

FB_B_DQ<40>

B

IO

DQ22

IO

87

IO

FB_B_DQ<38>

A9

FB_B_DQ<55>

IO

R2

IO

FB_B_DQ<35>

87

A8/AP

M4

87

FB_B_DQ<17>

DQ28

FB_B_DQ<33>

87

F3

A7

K2

FB_B_MA<9>

R10

87

FB_B_DQ<15>

87

E2

DQ5

L4

FB_B_MA<8>

IN

DQ21

T10

87

C3

DQ4

FB_B_MA<7>

IN

IO

DQ23

M3

DQ3

IN

R11

FB_B_DQ<18>

DQ27

IO

DQ20

87

WDQS3

FB_B_DQ<37>

IO

T11

P2

87

FB_B_DQ<54>

DQ22

FB_B_WDQS<1>

C2

A6

87

R10

FB_B_DQ<12>

DQ2

K3

M10

DQ21

87

IN

IN

IO

DQ19

R11

N2

FB_B_DQ<34>

D3

DQ20

DQ26

87

FB_B_RDQS<4>

FB_B_DQ<20>

WDQS2

IO

B3

FB_B_DQ<49>

87

P11

FB_B_DQ<36>

DQ1

87

M10

FB_B_WDQS<2>

DQ0

87

A5

B2

H2

FB_B_MA<6>

N11

DQ19

FB_B_DQ<14>

FB_B_MA<5>

IN

DQ18

D3

87

A4

IN

IN

 H  G  I  H  F  M

IN

RESET

FB_B_RDQS<0>

L3

K4

FB_B_DQM_L<7>

V9

FB_B_DQ<19>

DQ25

IN

FB_B_MA<4>

IN

FB_B_DQM_L<4>

DRAM_RST

87

WDQS1

FB_B_DQM_L<5>

FB_B_DQ<50>

N11

D11

FB_B_DQM_L<6>

87

87

DQ18

FB_B_WDQS<3>

87

N3

L10

RESET

FB_B_DQ<13>

87

N10

DM3

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

DQ17

V9

87

E10

DM2

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

SEN

DRAM_RST

M2

DM1

(1 OF 2)

A3

V4

FB_B_DQ<23>

DQ24

87

FBGA

A2

M9

FB_B1_SEN

87

WDQS0

E3

A1

K10

FB_B_MA<3>

IO

L10

D2

DM0

H11

FB_B_MA<2>

IN

FB_B_DQ<51>

DQ17

FB_B_WDQS<0>

U9050

FB_B_MA<1>

IN

87

SEN

RDQS3

A0

M11

V4

P3

OMIT

K9

DQ16

FB_B0_SEN

FB_B_RDQS<1>

CRITICAL

1% 1/16W MF-LF 402

FB_B_MA<0>

IN

MF

FB_B_DQ<21>

RDQS2

R9097 121

2

A9

87

P10

1

FB_B1_MF

M11

FB_B_RDQS<2>

1% 1/16W MF-LF 402

IO

DQ16

FB_B_DQ<16>

90 87

60.4

1% 1/16W MF-LF 402

2

2

R9095

121

5% 1/16W MF-LF 402

FB_B_DQ<63>

MF

87 5

90 87 90 87

1

1

87

A9

RDQS1

90 87

10% 16V X5R 402

G10

FB_B0_MF

D10

90 87

2

DQ15

G10

FB_B_DQ<22>

90 87

2

R9093

1K

2

10% 16V X5R 402

ZQ

DQ15

87

90 87

1

0.1uF

2

R9094

2

C9083

A4

ZQ

RDQS0

90 87

90 87 5

R9091

1

FB_B1_ZQ

A4

FB_B_RDQS<3>

2

C9081

IO

FB_B0_ZQ

87 5

90 87

90 87

FB_B_DQ<3>

CK

 H  G  I  H  F  M

IN

87

C10

2

VDDQ2

C4

R1

DQ11

2

C1

P1

CS*

R9049

B4

VSSQ15

F4

100

B1

VSSQ1

VDDQ15

87

1

VSSQ0

VDDQ1

N12

DQ10

1

J12

VDDQ0

P12

CK*

243

VSSA1

A1 A12

VSSQ15

J10

1% 1/16W MF-LF 402

J1

VDDQ15

FB_B_CS_L<0>

R9048

VSSA0

L11

DM3

A9

IN

(NONE)

V10

VSSQ14

DM2

A7

OUT

V3

VSS7

VDDQ14

DM1

A8/AP

OUT

VDDA1

BOM options provided by this page:

VSS6

N9

FBGA

M4

OUT

K12

L12

P9

(1 OF 2)

K2

OUT

VDDA0

VSS5

VSSQ14

A2

L4

IN

K1

L1

L2

A1

FB_B_MA<9>

IN

VDD7

VSS4

VSSQ13

E3

FB_B_MA<8>

IN

VDD6

G12

VDDQ13

DM0

FB_B_MA<7>

IN

V2 V11

VSS3

N4

10% 16V X5R 402

C9033

OMIT

IN

IN

VDD5

- =PP1V8_S0_FB_VDDQ

G1

P4

U9000

IN

IN

M12

- =PP1V8_S0_FB_VDD

A10

VSS2

VSSQ12

2

K4

IN

VDD4

     0      2      C     B         C      Q      4      2      3      2      5     J      4     K

A3

VSS1

VDDQ12

1

FB_B_MA<4>

FB_B_MA<11>

M1

 Z  H  M  0  0  5   3  R  D  D  G   2  3  X  M  6  1

VSS0

N1

2

2

CRITICAL

A3

FB_B_MA<10>

VDD3

FBGA

VSSQ11

R9047

121

5% 1/16W MF-LF 402

M9

IN

F12

OMIT

U9050 (2 OF 2)

VDDQ11

2

1K

K10

IN

VDD2

J9

20% 6.3V X5R 805

1% 1/16W MF-LF 402

H11

IN

VDD1

VSSQ10

0.1uF

60.4

FB_B_MA<3>

IN

C9076

0.1uF

121

2

1

0.1uF

1% 1/16W MF-LF 402

2

C9075

0.1uF

121

R9045

1

0.1uF

1% 1/16W MF-LF 402

1

C9074

0.1uF

121

2

U 90 00 .J 12

VDD0

F1

VDDQ10

R9090

FB_B_MA<2>

IN

1

1% 1/16W MF-LF 402

R9043

10% 16V X5R 402

2

A2 A11

J4

22uF

1

FB_B_MA<1>

IN

C9073

1% 1/16W MF-LF 402

1

0.1uF

10% 16V X5R 402

=PP1V8_S0_FB_VDDQ

60.4

2

C9065

1

U 90 00 .J 1

121

A0

IN

2

1% 1/16W MF-LF 402

R9041

2

C9060

PP1V8_FB_B1_VDDA1 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

121

2

2

1

1% 1/16W MF-LF 402

K9

IN

2

PP1V8_FB_B1_VDDA0

2

0402

2

R9046

C9054

1

0.1uF 1

0.1uF

FB_B_MA<0>

IN

1

0.1uF

1

C9053

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM 1

1

R9044

1

0.1uF

121

2 90 87

1

C9052

Connect to designated pin, then GND 90 89 88

J4

2

1

VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

VSSQ0

VDDA1

A1 A12

2

C9051

L9060

VSSA1

K12

1

1

1% 1/16W MF-LF 402

1

A

VDD2

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

R9031

B

VDD1

V12

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

C

VDD0

F1

K1

VOLTAGE=1.8V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

0402

A2 A11

1

Page Notes

CRITICAL

CRITICAL

IO

IO IO IO IO IO

GDDR3 Frame Buffer B

IO IO

S YN C C_ _M MA A ST E ER R =( M MA A ST E ER R)

IO IO

S YN C C_ _ DA T TE E =( M MA A ST E ER R)

NOTICE OF PROPRIETARY PROPERTY

IO

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

IO IO

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

RFU1 RFU2

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5% 1/16W MF-LF 402

SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

90

1

110

A

 

8

6

7

2

3

4

5

1

Page Notes Power aliases required by this page: - =PP3V3_GPU_GPIOS - =PP2V5_PVDD - =PP1V8_GPU_LVDS_PLL 97 93 88 6

Signal aliases required by this page:

1

U8400

  external TMDS transmitters

BGA

  external TMDS transmitters

(6 OF 7)

BOM options provided by this page:

95

GPU_GPIO_18

AE13

GPIO_18

(NONE)

95

GPU_GPIO_19

AF13

GPIO_19

95

GPU_GPIO_20

AF9

95

GPU_GPIO_21

AG7

88

AC8

ATI_VREFG

GPIO_20

GPIO_0

AD4

GPU_GPIO_0

88 94

GPIO_21

GPIO_1

AD2

GPU_GPIO_1

88

GPIO_2

AD1

GPU_GPIO_2

88

GPIO_3

AD3

GPU_GPIO_3

88

GPIO_4

AC1

GPU_GPIO_4

88

GPIO_5

AC2

GPU_GPIO_22

AE10

GPU_GPIO_23

AE9

GPIO_23

88

GPU_GPIO_24

AF7

GPIO_24

95

GPU_GPIO_25

AF8

2

VREFG

95

95

GPIO_22

GPIO_25

95

GPU_GPIO_26

AH6

GPIO_26

88

GPU_GPIO_27

AF10

GPIO_27

88

GPU_GPIO_28

AG10

GPIO_28

88

GPU_GPIO_29

AH9

GPIO_29

95

GPU_GPIO_30

AJ8

GPIO_30

95

GPU_GPIO_31

AH8

GPIO_31

95

GPU_GPIO_32

AG9

GPIO_32

95

GPU_GPIO_33

AH7

GPIO_33

95

GPU_GPIO_34

AG8

GPIO_34

 O   /  I  E  S  O  P  R  U  P

1

22uF 20% 6.3V X5R 805

C9101

1

1uF 2

2

C9102

1

1uF

10% 6.3V CERM 402

2

10% 6.3V CERM 402

2

GPU_GPIO_7

88

AC6

GPU_GPIO_8

88

GPIO_9

AC5

GPU_GPIO_9

88

GPIO_10

AC4

GPU_GPIO_10

88

GPIO_11

AB3

GPU_GPIO_11

88

GPIO_12

AB4

GPU_GPIO_12

88

GPIO_13

AB5

GPU_GPIO_13

88

GPIO_14

AD5

GPU_GPIO_14

88

GPIO_15

AB8

GPU_GPIO_15

88

AA9

GPIO_16

AA8

GPU_GPIO_16

92

AB9

GPIO_17

AB7

GPU_GPIO_17

88

GENERICA

AK22

GPU_GENERICA

95

GENERICB

AF23

GPU_GENERICB

95

GENERICC

AE23

GPU_GENERICC

95

GENERICD

AD23

GPU_GENERICD

PANEL DIGON CONTROL VARY_BL

AE11

GPU_DIGON

6 94

GPU_VARY_BL

94

 L  A  R  E  N  E  G

AB10

1uF

AC19 AC20

VDDR3 (3.3V)

AD18 AD19

1

C9191

1

D R9191 499

0.1uF 10% 16V X5R 402

1% 1/16W MF-LF 402

2 2

1% 1/16W MF-LF 402

88

AB2

C9103 10% 6.3V CERM 402

GPU_GPIO_6

AC3

GPIO_8

Typically <50mA

1

GPU_GPIO_5

GPIO_6 GPIO_7_BLON

=PP3V3_S0_GPU_VDDR3

C9100

R9190 499

M56P

- =I2C_GPU_TMDS_SCL - I2C clock line for

D

=PP3V3_S0_GPU

OMIT

- =I2C_GPU_TMDS_SDA - I2C data line for

88

AD20

C

88

=PP2V5_S0_GPU_VDD25 70mA total for VDD25

K22

AD12

C

L10

C9110

1

1

2

2

20% 6.3V X5R 805

88

1

1uF

22uF

WHY ARE THESE SEPARATE?

C9111 10% 6.3V CERM 402

2

C9112

AA10

0.1uF

AC13

10% 16V X5R 402

NC0

AB6

NC

AC16

NC_DVOVMODE_0

AK4

NC

AC18

NC_DVOVMODE_1

AL4

NC

DVPCLK

AG1

VDD25 (2.5V)

ATI_DVPCLK

95

DVPCNTL_0

AF2

ATI_DVPCNTL<0>

95

C9117

DVPCNTL_1

AF1

ATI_DVPCNTL<1>

1uF

DVPCNTL_2

AF3

ATI_DVPCNTL<2>

95

 S  D  M  T

DVPDATA_0

AG2

ATI_DVPDATA<0>

95

DVPDATA_1

AG3

ATI_DVPDATA<1>

95

DVPDATA_2

AH2

ATI_DVPDATA<2>

95

 L  A  N  R  E  T  X  E

DVPDATA_3

AH3

ATI_DVPDATA<3>

95

DVPDATA_4

AJ2

ATI_DVPDATA<4>

95

DVPDATA_5

AJ1

ATI_DVPDATA<5>

95

DVPDATA_6

AK2

ATI_DVPDATA<6>

95

DVPDATA_7

AK1

ATI_DVPDATA<7>

95

AJ5

  /

DVPDATA_8

AK3

ATI_DVPDATA<8>

95

AK5

 T  S  O  H

DVPDATA_9

AL2

ATI_DVPDATA<9>

95

DVPDATA_10

AL3

ATI_DVPDATA<10>

95

DVPDATA_11

AM3

ATI_DVPDATA<11>

95

DVPDATA_12

AE6

ATI_DVPDATA<12>

95

DVPDATA_13

AF4

ATI_DVPDATA<13>

95

DVPDATA_14

AF5

ATI_DVPDATA<14>

95

DVPDATA_15

AG4

ATI_DVPDATA<15>

95

DVPDATA_16

AJ3

DVPDATA_17

AH4

DVPDATA_18

AJ4

ATI_DVPDATA<18>

95

DVPDATA_19

AG5

ATI_DVPDATA<19>

95

DVPDATA_20

AH5

ATI_DVPDATA<20>

95

DVPDATA_21

AF6

ATI_DVPDATA<21>

95

DVPDATA_22

AE7

ATI_DVPDATA<22>

DVPDATA_23

AG6

ATI_DVPDATA<23>

95

DPLUS

AG12

ATI_TDIODE_P

61

DMINUS

AH12

ATI_TDIODE_N

61

ROMCS*

AC7

TP_ATI_ROMCS_L

TESTEN

AG22

=PP2V5_S0_GPU_VDDC_CT Add ferrite bead

C9115

1

1

2

2

L9120 =PP1V8R3V3_S0_GPU_VDDR4

88

VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.12 MM

C9120

1

1

22uF 20% 6.3V X5R 805

L9125

B

=PP1V8R3V3_S0_GPU_VDDR5

2

2

2

C9122

1uF

0.1uF

10% 6.3V CERM 402

10% 16V X5R 402

2

VDDR4 (1.8V/3.3V)

 P  I  V

AE2 AE3

C9125 20% 6.3V X5R 805

L9130

AL5

1

1

2

2

C9126

C9127

AE4

1uF

0.1uF

10% 6.3V CERM 402

10% 16V X5R 402

AE5

1

2

VDDR5 (1.8V/3.3V)

FERR-220-OHM

=PP1V2_S0_GPU_VDDPLL

1

2

PP1V2_S0_GPU_VDDPLL

20mA

AC15

VOLTAGE=1.2V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

0402

C9130

1

1

2

2

20% 6.3V X5R 805

C9131

1

1uF

22uF

10% 6.3V CERM 402

C9132 1uF

2

10% 6.3V CERM 402

L9135 88

1

AM5

22uF

88

C9121

PP1V8R3V3_S0_GPU_VDDR5_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.12 MM

0402

10% 6.3V CERM 402

Typically <50mA

FERR-220-OHM 1

2

PP1V8R3V3_S0_GPU_VDDR4_F

2 0402

88

10% 6.3V CERM 402

Typically <50mA

FERR-220-OHM 1

1

1uF

22uF 20% 6.3V X5R 805

C9116

VDDPLL (1.2V)

(PP2V5_S0_GPU_PVDD_F)

AJ14

PVDD

(GND_GPU_PVSS)

AH14

PVSS

(PP1V0R1V2_S0_GPU_MPVDD)

A6

MPVDD

(GND_GPU_MPVSS)

A5

MPVSS

(2.5V)

(2.5V)

GPU_XTALIN

AL26

XTALIN

GPU_XTALOUT

AM26

XTALOUT

 & THERMAL DIODE  L  L  P ROM

AG14

PLLTEST

TEST

FERR-220-OHM

=PP2V5_S0_GPU_PVDD

1

2

PP2V5_S0_GPU_PVDD_F

92

100mA

VOLTAGE=2.5V MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.12 MM

0402

C9135

1

1

2

2

20% 6.3V X5R 805

C9136

1

1uF

22uF

10% 6.3V CERM 402

C9137

 L  A  T  X

TP_U8400_AG14

ATI_DVPDATA<16> ATI_DVPDATA<17>

10% 16V X5R 402

A

2 0402

PPVCORE_S0_GPU_MPVDD

95

95

R9195 1K

2 1

95

ATI_TESTEN 1

FERR-220-OHM

=PPVCORE_S0_GPU

B

0.1uF 2

L9140 88 86

95

5% 1/16W MF-LF 402

ATI M56 GPIO/DVO/Misc

20mA

VOLTAGE=1.2V MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM

SYNC_MASTER=(MASTER)

C9140

1

1

C9141

1

22uF

1uF

0.1uF

20% 6.3V X5R 805

10% 6.3V CERM 402

10% 16V X5R 402

2

2

2

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

C9142

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

91

1

110

A

 

8

6

7

3

4

5

2

1

Page Notes Power aliases required by this page: - =PP3V3_GPU_CLOCKS

- =PP3V3_GPU_PWRSEQ

- =PPVIN_GPU_LVDDR_LDO

- =PP2V5_GPU_PWRSEQ

- =PP2V5_GPU_LVDDR_LDO

- =PP1V8_GPU_PWRSEQ - =PP1V5_GPU_PWRSEQ

Signal aliases required by this page: (NONE) BOM options provided by this page:

D

- GPU_SS

- GPU_LVDDR_2V8

D

I28 34

 

CK410_27M_SPREAD

GPU_GPIO_16

91

MAKE_BASE=TRUE

C

C R9250

1

287

34

CK410_27M_NONSPREAD

1% 1/16W MF-LF 402

I26

2

GPU_CLK27M

GPU_XTALIN

91

1

R9202 162 1% 1/16W MF-LF 402

2

B

B

GPU CLOCKS

A

SYNC_MASTER=BOZEMAN

SYNC_DATE=05/21/2005

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

92

1

110

A

 

8

6

7

2

3

4

5

1

Page Notes Power aliases required by this page: - =PP2V5_S0_GPU - =PP1V8R2V5_S0_GPU_LVDDR Signal aliases required by this page: (NONE)

TERMINATION FOR TMDS USAGE OF LVDS PINS

BOM options provided by this page:

PLACE CLOSE TO GPU (U8400)

(NONE)

D

94 93

D

LVDS_L_CLK_P TMDS_PANEL

R93701 100

5% 1/16W MF-LF 402 2 94 93

LVDS_L_CLK_N

94 93

LVDS_L_DATA_P<0> TMDS_PANEL

R93711 100

5% 1/16W MF-LF 402

L9300 88

Sum of peak currents on this page:

FERR-220-OHM

=PP2V5_S0_GPU

1

605mA

2

PP2V5_S0_GPU_TPVDD MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=2.5V

0402

OMIT

20mA peak

U8400 C9300

1

1

2

2

20% 6.3V X5R 805

1

10% 6.3V CERM 402

2

2

PP2V5_S0_GPU_TXVDDR

1

1

20% 6.3V X5R 805

L9310

C9306

1

1uF

22uF

1

2

2

2

10% 6.3V CERM 402

2

TMDS_CLK_N

TX0P

AL10

97

TMDS_DATA_P<0>

TX0M

AK10

97

TMDS_DATA_N<0>

TX1P

AM11

97

TMDS_DATA_P<1>

TX1M

AL11

97

TMDS_DATA_N<1>

TX2P

AM12

97

TMDS_DATA_P<2>

TX2M

AL12

97

TMDS_DATA_N<2>

OUT

TX3P

AJ9

95

TMDS_DATA_P<3>

OUT

TX3M

AK9

95

TMDS_DATA_N<3>

TX4P

AJ11

95

TMDS_DATA_P<4>

TX4M

AK11

95

TMDS_DATA_N<4>

TX5P

AJ12

95

TMDS_DATA_P<5>

TX5M

AK12

95

TMDS_DATA_N<5> GPU_VGA_R GPU_VGA_G

AM6

PP2V5_S0_GPU_AVDD

AL7

1

1

C9311

1

1uF 2

2

10% 6.3V CERM 402

C9312 0.1uF

2

AL25

10% 16V X5R 402

AM25

AK25

0402

20mA peak 1

C9317

22uF

1uF

0.1uF

20% 6.3V X5R 805

10% 6.3V CERM 402

10% 16V X5R 402

2

2

2

AVSS

AK23

AVSSQ

AM23

VDD1DI (2.5V)

AL23

C9316

AVDD (2.5V)

L9320

130mA peak

93

ATI_RSET

AL22

1

2

C9320

PP2V5_S0_GPU_A2VDD MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.125 MM VOLTAGE=2.5V

0402

VSS1DI

1

1

2

2

1

1uF

22uF 20% 6.3V X5R 805

C9321 10% 6.3V CERM 402

2

C9322

AL16

0.1uF

AM16

10% 16V X5R 402

A2VDD (2.5V)

AL17 AM17

C9325

1

0402

20mA peak 1

22uF 20% 6.3V X5R  2 805

B

NC

2

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.12 MM VOLTAGE=2.5V

2

C9326

1

C9327

1uF

0.1uF

10% 6.3V CERM 402

10% 16V X5R 402

2

L9330

93

1

2

PP2V5_S0_GPU_LPVDD

ATI_R2SET

C9330 20% 6.3V X5R 805

1

1

L9345

C9331

1

1uF

1

2

0402

A2VSS

AL14

NC_A2VDDQ

AK13

A2VSSQ

AJ16

VDD2DI (2.5V)

AJ17

VSS2DI

AK14

R2SET

AE19

LPVDD (2.5V)

AE18

LPVSS

AM24

88

B

AL24

88

GPU_VGA_B

 C  A  D

HSYNC

AJ23

88

GPU_VGA_HSYNC

VSYNC

AJ22

88

GPU_VGA_VSYNC

OUT

R2

AK15

97

GPU_R2

OUT

G2

OUT

 )  2  T  R  C   /  V  T  (  2  C  A  D

OUT OUT

AM15

97

GPU_G2

B2

AL15

97

GPU_B2

H2SYNC

AF15

97

GPU_H2SYNC

V2SYNC

AG15

97

GPU_V2SYNC

Y

AJ15

88

GPU_TV_Y

C

AJ13

88

GPU_TV_C

COMP

AH15

88

GPU_TV_COMP

TXCLK_UP

OUT OUT OUT

Composite/S-Video

VGA

Component

OUT

Y

G

Y

OUT

C

R

Pr

OUT

Comp

B

Pb

94

LVDS_U_CLK_P

94

LVDS_U_CLK_N

94

LVDS_U_DATA_P<0>

2

2

10% 6.3V CERM 402

2

TXOUT_U0N

AH18

94

LVDS_U_DATA_N<0>

TXOUT_U1P TXOUT_U1N

AK20 AJ20

94 94

LVDS_U_DATA_P<1> LVDS_U_DATA_N<1>

TXOUT_U2P

AG20

94

LVDS_U_DATA_P<2>

TXOUT_U2N

AH20

94

LVDS_U_DATA_N<2>

AE22

TXOUT_U3P

AH21

94

LVDS_U_DATA_P<3>

C9347

AF19

TXOUT_U3N

AG21

94

LVDS_U_DATA_N<3>

AF20

TXCLK_LP

AM18

94 93

LVDS_L_CLK_P

TXCLK_LN

AL18

94 93

LVDS_L_CLK_N

TXOUT_L0P

AL19

94 93

LVDS_L_DATA_P<0>

TXOUT_L0N

AK19

94 93

LVDS_L_DATA_N<0>

TXOUT_L1P

AM20

94 93

LVDS_L_DATA_P<1>

TXOUT_L1N

AL20

94 93

TXOUT_L2P

AM21

94 93

LVDS_L_DATA_P<2>

TXOUT_L2N

AL21

94 93

LVDS_L_DATA_N<2>

TXOUT_L3P

AJ18

TXOUT_L3N

AK18

DDC1CLK

AH23

97

GPU_DDC_A_CLK

DDC1DATA

AH22

97

GPU_DDC_A_DATA

IO

DDC2CLK

AG13

88

GPU_DDC_B_CLK

IO

DDC2DATA

AH13

88

GPU_DDC_B_DATA

AF12

94 93

GPU_DDC_C_CLK

AE12

94 93

GPU_DDC_C_DATA

10% 6.3V CERM 402

AC22 AD21 AD22 AE20

PP2V5_S0_GPU_LVDDR MIN_LINE_WIDTH=0.35 MM MIN_NECK_WIDTH=0.125 MM VOLTAGE=2.5V

200mA peak

C9340

1

C9345

AE21

1

1

C9341

1

C9342

1

C9346

1

22uF

22uF

1uF

0.1uF

0.1uF

0.1uF

20% 6.3V X5R 805

20% 6.3V X5R 805

10% 6.3V CERM 402

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

R9351

2

2

2

2

97

715

2

OUT

AG18

2

LVDDR (2.5V)

 S  D  V  L

AF17 AF18

LVSSR

AK17

1% 1/16W MF-LF 402

OUT

AK21

AC21

AJ19

499

OUT

G

AH19

2

OUT

AK24

AH17

1

IN

GPU_HPD

AF11

HPD1

 N  O  I  T  R  A  O  C  T  I  I  F  N  I  O  T  M  N  E  D  I

DDC3CLK DDC3DATA

94 94

B

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

=PP3V3_S0_GPU

97 91 88 6

OUT OUT

R9390 5% 1/16W MF-LF 402

OUT OUT

LVDS_L_DATA_N<1>

1

R9391

4.7K

OUT

OUT OUT

94 93

GPU_DDC_C_CLK

94 93

GPU_DDC_C_DATA

1

4.7K 5% 1/16W MF-LF 402

2

2

OUT

LVDS_L_DATA_P<3>

OUT

LVDS_L_DATA_N<3>

OUT

ATI M56 Video Interfaces

IO

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

IO

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

IO IO

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

1% 1/16W MF-LF 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148 SHT NONE

7

6

5

4

3

2

REV.

DRAWING NUMBER

D SCALE

8

C

2

LVDS_L_DATA_N<2>

OUT

AJ21

1uF

AG19

R9350

100

5% 1/16W MF-LF 402 94 93

OUT

R

AG17

1

R93731

OUT

 )  T  R  C  (

AF22

93

2

TMDS_PANEL

OUT

88

AF21

ATI_R2SET

LVDS_L_DATA_P<2>

OUT

TXCLK_UN

C9332

FERR-220-OHM

93

94 93

OUT

TXOUT_U0P

20mA peak

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.12 MM VOLTAGE=2.5V

22uF

ATI_RSET

OUT

LVDS_L_DATA_N<1>

FERR-220-OHM

0402

A

OUT

94 93

RSET

FERR-220-OHM 1

OUT

FERR-220-OHM

L9325 PP2V5_S0_GPU_VDD2DI

5% 1/16W MF-LF 402

OUT

AJ24

2

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.12 MM VOLTAGE=2.5V

1

TXVSSR

 D  E  T  A  R  G  E  T  N  I

AM7

C9310 20% 6.3V X5R 805

1

TXVDDR (2.5V)

AK7

65mA peak

22uF

C9315

 S  D  M  T

AJ7

L9315 PP2V5_S0_GPU_VDD1DI

TMDS_CLK_P

97

AL6

FERR-220-OHM 1

97

AL9

AK8

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.12 MM VOLTAGE=2.5V

0402

AM9

TXCM

0.1uF 10% 16V X5R 402

100

TXCP

TPVSS

C9307

FERR-220-OHM

C

R93721

TPVDD (2.5V)

AL8 AJ6

2

TMDS_PANEL

AM8

AK6

C9305

LVDS_L_DATA_P<1>

BGA

150mA peak

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.12 MM VOLTAGE=2.5V

0402

94 93

(5 OF 7)

10% 6.3V CERM 402

FERR-220-OHM 1

LVDS_L_DATA_N<0>

M56P

C9302 1uF

1uF

22uF

L9305

C9301

94 93

13 OF

93

1

110

A

 

8

6

7

2

3

4

5

1

INVERTER INTERFACE

D

D

LCD (LVDS) INTERFACE NOSTUFF

R9491 94 88

0

1

=PP12V_GPU

2

5% 1/8W MF-LF 805

R9490 88

=PP3V3_S0_LCD

0

1

NOSTUFF

R9400

0.1UF

1

1

10% 50V X7R 603-1

NOSTUFF

R9401

2

1

29.4K

LCD_PWREN_L_RC

2

94 88

C9450 L9400

4 6

1

PP3V3_LCD_SW VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

5 2

TSOP-LF

3 D

Q9400

NOSTUFF

1

R9470

100K 5% 1/16W MF-LF 402

C9420

0.001uF

10UF

20% 50V CERM 402

10% 16V CERM 1210

2

3

LCD_PWM

4

PANEL_ID

1

518S0331 2

C

Q9401 2N7002

G

1

M-ST-SM

2 94 94

C9401

87437-0443-BLK 1

PP3V3R12V_LCD_CONN

94

1

1

2 SM

SI3443DV

GPU_DIGON

J9401

10% 35V X7R  2 805

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

FERR-250-OHM

3

LCD_PWREN_L

91 6

CRITICAL

1

1UF

NOSTUFF

1% 1/16W MF-LF 402

C

=PP12V_GPU

2

100K 5% 1/16W MF-LF 402

2

5% 1/8W MF-LF 805

C9400

NOSTUFF

94 88

=PP3V3_DDC_LCD

SOT23-LF

S 2

R9410

1

1

R9411

100K pull-ups are for

100K

100K

no-panel case (development)

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

Panel has 2K pull-ups 2

94 93

GPU_DDC_C_CLK

94 93

GPU_DDC_C_DATA

2

2

C9410

1

0.001uF 20% 50V CERM 402

R9450

2 91 88

GPU_GPIO_0

47

1

PANEL_ID

2

94

5% 1/16W MF-LF 402

88

=PP3V3_GPU

C9470

1

0.1UF

20% 10V 2 CERM 402

6

91

2

5% 1/16W MF-LF 2 402

LVDS_U_DATA_N<1>

3

93

LVDS_U_DATA_N<2>

5

93

LVDS_U_CLK_P

93

10K

2

LCD_PWM

94

5% 1/16W MF-LF 4022

NOSTUFF

0

B

2

MF-LF 402

2

LVDS_U_DATA_P<0> 93

4

LVDS_U_DATA_P<1> 93

6

LVDS_U_DATA_P<2> 93

7

8

9

10

LVDS_U_DATA_P<3>

11

12

93

LVDS_L_DATA_P<0>

13

14

93

LVDS_L_DATA_N<1>

15

16

17

18

93

LVDS_L_DATA_P<2>

19

20

93

LVDS_L_CLK_P

21

22

93

LVDS_L_DATA_P<3>

23

24

94 93

GPU_DDC_C_CLK

25

26

GPU_DDC_C_DATA

94 88

=PP3V3_DDC_LCD

27

28

PP3V3R12V_LCD_CONN

94

PP3V3R12V_LCD_CONN

29

30

PP3V3R12V_LCD_CONN

94

94

47

5% 1/16W MF-LF 402

R9474

1

5% 1/16W

J9402 53307-3072 F-ST-SM 93

1

LCD_PWM_R

R9473 1

CRITICAL

1

4

3 MC74VHC1G08 SOT23-5-LF

10K

1

LVDS_U_DATA_N<0>

R9475

U9470

R9472

STDOFF-3MMOD4.6MMH-1.35-TH

93

5

1

NOSTUFF 1

SDF9400

B

GPU_PWM_RST_L

GPU_VARY_BL

GATE TO PREVENT LEAKAGE ONTO PWM MIGHT BE ABLE TO BYPASS IF

SMC DRIVES SIGNAL

LVDS_U_CLK_N 93 LVDS_U_DATA_N<3> 93 LVDS_L_DATA_N<0>

93

LVDS_L_DATA_P<1> 93 LVDS_L_DATA_N<2> 93 LVDS_L_CLK_N 93 LVDS_L_DATA_N<3>

93

93 94

Internal Display Conns

A

SYNC_DATE=04/27/2005

SYNC_MASTER=BOZEMAN

SDF9401

STDOFF-3MMOD4.6MMH-1.35-TH

NOTICE OF PROPRIETARY PROPERTY

1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

94

1

110

A

 

8

D

C

B

6

7

TP_TMDS_DATA_P<3> MAKE_BASE=TRUE

TMDS_DATA_P<3>

93

TP_TMDS_DATA_N<3> MAKE_BASE=TRUE

TMDS_DATA_N<3>

93

TP_TMDS_DATA_P<4> MAKE_BASE=TRUE

TMDS_DATA_P<4>

93

TP_TMDS_DATA_N<4> MAKE_BASE=TRUE

TMDS_DATA_N<4>

93

TP_TMDS_DATA_P<5> MAKE_BASE=TRUE

TMDS_DATA_P<5>

93

TP_TMDS_DATA_N<5> MAKE_BASE=TRUE

TMDS_DATA_N<5>

93

4

5

ATI_DVPDATA<23>

91

TP_GPU_GPIO<34> MAKE_BASE=TRUE

GPU_GPIO_34

TP_ATI_DVPDATA<22> MAKE_BASE=TRUE

ATI_DVPDATA<22>

91

TP_GPU_GPIO<33> MAKE_BASE=TRUE

GPU_GPIO_33

91

TP_ATI_DVPDATA<21> MAKE_BASE=TRUE

ATI_DVPDATA<21>

91

TP_GPU_GPIO<32> MAKE_BASE=TRUE

GPU_GPIO_32

91

TP_ATI_DVPDATA<20> MAKE_BASE=TRUE

ATI_DVPDATA<20>

91

TP_GPU_GPIO<31> MAKE_BASE=TRUE

GPU_GPIO_31

91

TP_ATI_DVPDATA<19> MAKE_BASE=TRUE

ATI_DVPDATA<19>

91

TP_GPU_GPIO<30> MAKE_BASE=TRUE NO_TEST=TRUE

GPU_GPIO_30

91

TP_ATI_DVPDATA<18> MAKE_BASE=TRUE

ATI_DVPDATA<18>

91

TP_ATI_DVPDATA<17> MAKE_BASE=TRUE

ATI_DVPDATA<17>

91

TP_ATI_DVPDATA<16> MAKE_BASE=TRUE

ATI_DVPDATA<16>

91

TP_ATI_DVPDATA<15> MAKE_BASE=TRUE

ATI_DVPDATA<15>

91

TP_GPU_GPIO<26> MAKE_BASE=TRUE

GPU_GPIO_26

91

TP_ATI_DVPDATA<14> MAKE_BASE=TRUE

ATI_DVPDATA<14>

91

TP_GPU_GPIO<25> MAKE_BASE=TRUE

GPU_GPIO_25

91

TP_ATI_DVPDATA<13> MAKE_BASE=TRUE

ATI_DVPDATA<13>

91

TP_ATI_DVPDATA<12> MAKE_BASE=TRUE

ATI_DVPDATA<12>

91

TP_GPU_GPIO<23> MAKE_BASE=TRUE

GPU_GPIO_23

91

TP_ATI_DVPDATA<11> MAKE_BASE=TRUE

ATI_DVPDATA<11>

91

TP_GPU_GPIO<22> MAKE_BASE=TRUE

GPU_GPIO_22

91

TP_ATI_DVPDATA<10> MAKE_BASE=TRUE

ATI_DVPDATA<10>

91

TP_GPU_GPIO<21> MAKE_BASE=TRUE

GPU_GPIO_21

91

TP_ATI_DVPDATA<9> MAKE_BASE=TRUE

ATI_DVPDATA<9>

91

TP_GPU_GPIO<20> MAKE_BASE=TRUE

GPU_GPIO_20

91

TP_ATI_DVPDATA<8> MAKE_BASE=TRUE

ATI_DVPDATA<8>

91

TP_GPU_GPIO<19> MAKE_BASE=TRUE

GPU_GPIO_19

91

TP_ATI_DVPDATA<7> MAKE_BASE=TRUE

ATI_DVPDATA<7>

91

TP_GPU_GPIO<18> MAKE_BASE=TRUE

GPU_GPIO_18

91

TP_ATI_DVPDATA<6> MAKE_BASE=TRUE

ATI_DVPDATA<6>

91

TP_GPU_GENERICA MAKE_BASE=TRUE

GPU_GENERICA

91

TP_ATI_DVPDATA<5> MAKE_BASE=TRUE

ATI_DVPDATA<5>

91

TP_GPU_GENERICB MAKE_BASE=TRUE

GPU_GENERICB

91

TP_ATI_DVPDATA<4> MAKE_BASE=TRUE

ATI_DVPDATA<4>

91

TP_GPU_GENERICC MAKE_BASE=TRUE

GPU_GENERICC

91

TP_ATI_DVPDATA<3> MAKE_BASE=TRUE

ATI_DVPDATA<3>

91

TP_ATI_DVPDATA<2> MAKE_BASE=TRUE

ATI_DVPDATA<2>

91

TP_ATI_DVPDATA<1> MAKE_BASE=TRUE

ATI_DVPDATA<1>

91

TP_ATI_DVPDATA<0> MAKE_BASE=TRUE

ATI_DVPDATA<0>

91

ATI_DVPCLK

91

TP_ATI_DVPCNTL<0> MAKE_BASE=TRUE

ATI_DVPCNTL<0>

91

TP_ATI_DVPCNTL<1> MAKE_BASE=TRUE

ATI_DVPCNTL<1>

91

TP_ATI_DVPCNTL<2> MAKE_BASE=TRUE

ATI_DVPCNTL<2>

91

2

1

D

TP_ATI_DVPDATA<23> MAKE_BASE=TRUE

TP_ATI_DVPCLK MAKE_BASE=TRUE

3

91

C

B

M56 TPS A

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

.

REV.

DRAWING NUMBER

D

95

1

OF

13 110

 

8

6

7 PLACE FILTER CLOSE

PLACE LEFT SIDE

CRITICAL

CRITICAL L9700

R97011

1

182

1% 1/16W MF-LF 402

88

SYM_VER-1

4

2012H

TMDS_CONN_DN<0> 97 DIFFERENTIAL_PAIR=TMDS_CONN_D0

SM-LF

PP5V_S0_DDC

ALTERNATE FOR PART NUMBER 740S0028

400-OHM-EMI PP5V_S0_DDC_FUSE

1

VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

2

3

REF DES   COMMENTS:

F9710

FUSE

SM-1

88 75 6

2

B OM O PT IO N

VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

90-OHM-300MA

2

PP5V_S0

3V LEVEL SHIFTERS

TMDS_CONN_DP<0>

97 DIFFERENTIAL_PAIR=TMDS_CONN_D0

NO_TEST=TRUE

DIFFERENTIAL_PAIR=TMDS_DATA_0

D

0.5AMP-13.2V 2 =PP5V_S0_DVI_DDC 1

P AR T N UM BE R

740S0044

TABLE_ALT_ITEM

L9710

F9710

93 TMDS_DATA_N<0> DIFFERENTIAL_PAIR=TMDS_DATA_0

88

R9710

L9701

1

1/16W MF-LF 402

4

MINI-DVI 1

D

3

2

NO_TEST=TRUE

TMDS_DATA_P<1>

R9707

SYM_VER-1

1

182

1% 1/16W MF-LF 402

CRITICAL

L9702

4

2012H

97

DVI_DDC_CLK_UF

26

2

97

DVI_DDC_DATA_UF

18

10

28

4

97

VGA_B

20

12

VGA_HSYNC

29

5

97

TMDS_CONN_DN<2>

2

3

27

3

19

11

NO_TEST=TRUE

30

6 14

97

VGA_G

22

97

VGA_VSYNC

31

93 TMDS_CLK_N DIFFERENTIAL_PAIR=TMDS_CLK

97

VGA_R

8

24

16

L9703

1% 1/16W MF-LF 402 2

97

TMDS_CONN_DP<1>

97

TMDS_CONN_DN<1>

97

TMDS_CONN_DP<0>

1

1

2

97

2

D

S 4

TMDS_CONN_DN<0>

97

2

TMDS_CONN_CLKP 97

2N7002DW-X-F 100

97

2

G

SOT-363

2 6 D DVI_DDC_DATA

C9713 5% 50V CERM 402

2

3

R97171

5% 1/16W MF-LF 402

S 1

GPU_DDC_A_DATA

93

R9714

DVI_HPD_UF

1

20K

GPU_HPD

2

5% 1/16W MF-LF 402

 4  3

C9710 GND_CHASSIS_VGA

4

93

10K 2

5% 1/16W MF-LF 402

TMDS_CONN_CLKN 97

SYM_VER-1

1

GPU_DDC_A_CLK

R9721

R9713 1

5% 1/16W MF-LF 402

1

Q9711

5% 50V CERM 402

1

G 2

DVI_DDC_CLK3

5% 1/16W MF-LF 402

C9711

DVI_DDC_DATA_UF

97

5

SOT-363

100pF

CRITICAL

165-OHM SM-LF

TMDS_CK_TERM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM NO_TEST=TRUE

5% 50V CERM 2 402

TMDS_CONN_DN<2>

DVI_DDC_CLK_UF

100

10K

Q9711 2N7002DW-X-F

R9711

1

1

1

20% 50V CERM 603

TMDS_CONN_CLKN 97 DIFFERENTIAL_PAIR=TMDS_CONN_CLK

C9714 100pF

0.01uF

6

2

2

2

5% 50V CERM 402

5% 1/16W MF-LF 402

93

D9700

R9722

CASE425

100K  3  3

90.9

22PF

2

100pF

7

32

R97161

1

2

R9720

5% 1/16W MF-LF 402

15

TMDS_DATA_P<2>

C9700

97

13

TMDS_CONN_DP<2> 97 DIFFERENTIAL_PAIR=TMDS_CONN_D2

DIFFERENTIAL_PAIR=TMDS_DATA_2

97

TMDS_CONN_DP<2>

1

4.7K

9

97 DIFFERENTIAL_PAIR=TMDS_CONN_D2

90-OHM-300MA

2

1

DVI_HPD_UF

93 TMDS_DATA_N<2> DIFFERENTIAL_PAIR=TMDS_DATA_2

1

25

97

17

TMDS_CONN_DP<1> 97 DIFFERENTIAL_PAIR=TMDS_CONN_D1

DIFFERENTIAL_PAIR=TMDS_DATA_1

R9712

F-ST-SM4

TMDS_CONN_DN<1> 97 DIFFERENTIAL_PAIR=TMDS_CONN_D1

90-OHM-300MA

2

5% 1/16W MF-LF 402

J9710

CRITICAL SYM_VER-1 2012H

182 R9706 1%

C

1

4.7K

93 TMDS_DATA_N<1> DIFFERENTIAL_PAIR=TMDS_DATA_1

93

=PP3V3_DDC_DVI

TMDS_DATA_P<0> 1

93

1

TABLE_ALT_HEAD

(55mA requirement per DVI spec)

AS POSSIBLE

93

DVI INTERFACE

DVI DDC CURRENT LIMIT

TO TMDS CONNECTOR

AS CLOSE TO GPU (U8400)

2

3

4

5

2

1

MMSZ4681XXG

C

TMDS_CONN_CLKP

97 DIFFERENTIAL_PAIR=TMDS_CONN_CLK

NO_TEST=TRUE

90.9 1% 1/16W MF-LF 402

2

93 TMDS_CLK_P DIFFERENTIAL_PAIR=TMDS_CLK

97 93 91 88 6

=PP3V3_S0_GPU 1

C9750 0.1UF

20% 10V 2 CERM 402

VGA SYNC BUFFERS

B ANALOG FILTERING

5

PLACE CLOSE TO CONNECTOR

93

GPU_V2SYNC

1

R9750

SM-LF 4

2

FL9740 LCFILTER

GPU_VSYNC_BUF 1

33

2

VGA_VSYNC

97

5% 1/16W MF-LF 402

32 3

CRITICAL

B

U9750 74AHC1G32

SM-220MHZ-LF 93

GPU_B2

1 1

R9740

2

3

1

2

93

1% 1/16W MF-LF 402

FL9741 LCFILTER

97

1

VGA_G

97

C9740 3.3pF

CRITICAL

SM-220MHZ-LF

GPU_G2

VGA_B

4

75

2

0.25% 50V CERM 402

97 93 91 88 6

2

=PP3V3_S0_GPU

PLACE R9750 & R9751 CLOSE TO DVI CONNECTOR 1

3

1

R9741

1

75

2 93

FL9742 LCFILTER

1% 1/16W MF-LF 402 1

1

R9742

CRITICAL

2

0.25% 50V CERM 402

VGA_R

2

3

2

97

4

5 1

75

A

20% 10V 2 CERM 402

C9741 3.3pF

SM-220MHZ-LF

GPU_R2

C9742

93

3.3pF

1% 1/16W MF-LF 402

C9751 0.1UF

4

2

GPU_H2SYNC

U9751 74AHC1G32

1

SM-LF 4

0.25% 50V CERM 402

2

32 3

External Display Conns

R9751 1 GPU_HSYNC_BUF

33

2

VGA_HSYNC

SYNC_MASTER=BOZEMAN

SYNC_DATE=04/14/2005

97

NOTICE OF PROPRIETARY PROPERTY

5% 1/16W MF-LF 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

051-7148

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

DRAWING NUMBER

D

13 OF

97

1

110

A

 

8 Title:

 

7

Basenet Report

6

 

=SMB_AIRPORT_DATA

Design:

m38a

Date:

Jun 21 19:41:15 2006

SMB_CK410_DATA

- @m38a_lib.M38A

SMB_CK410_DATA

-

@m38a_lib.M38A

 

5 53B4

- @m38a_lib.M38A

27D6 33B6

=PP3V3_S0_SB_VCCLAN3_ 3 -

23D5 27B8 27D7

@m38a_lib.M38A

27D6 33B6

=PP3V3_S0_SB_VCC3_3_P CI -

27 C6

53B4

@m38a_lib.M38A

0V7_REF - @m38a_lib.M38A

79A3

=PP0V9_S0_MEM_TERM - @m38a_lib.M38A 6D4 30D4

=PP3V3_S0_SB_VCC3_3

1V0_REF

1V0_REF - @m38a_lib.M38A

79A5 80A5 81A5 81B3

PP0V9_S0 - @m38a_lib.M38A

@m38a_lib.M38A

1V2REG_BOOT

1V2REG_BOOT

- @m38a_lib.M38A

1V2REG_ITH - @m38a_lib.M38A

1V2REG_ITH_RC

1V2REG_ITH_RC

1V2REG_MODE

1V2REG_MODE

1V2REG_PGOOD

1V2REG_PGOOD

1V2REG_RT

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

1V2REG_RT - @m38a_lib.M38A

1V2REG_RUNSS

1V2REG_RUNSS

1V2REG_SGND

1V2REG_SGND

1V2REG_SW

1V2REG_SW - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

1V2REG_SW_FIL

1V2REG_SW_FIL

1V2REG_VBIAS

1V2REG_VBIAS

=PP1V2_S0_GPU_VDDPLL

=PP1V2_S0_REG

77B6

=PP1V2_S0_PCIE_GPU_P VDD -

- @m38a_lib.M38A - @m38a_lib.M38A

77B6

@m38a_lib.M38A

77A8

=PP1V2_S0_PCIE_GPU_V DDR -

77B5

@m38a_lib.M38A

77B4

PP1V2_GPU_IO_S0

77B6

=PPVIO_S0_PCIE

77B6

=PP1V2_S0_REG

=PP1V2_S0_PCIE_GPU_V DDR -

81C6 81C5

@m38a_lib.M38A =PP1V2_S0_PCIE_GPU_P VDD -

1V05REG_NB_COMP

1V05REG_NB_COMP

81C6

@m38a_lib.M38A

1V05REG_NB_COMP_R

1V05REG_NB_COMP_R 1V05REG_NB_FB

- @m38a_lib.M38A

- @m38a_lib.M38A

1V05REG_NB_FB_R

- @m38a_lib.M38A

1V05REG_NB_FS_DIS

1V05REG_NB_FS_DIS 1V05REG_NB_GND

1V05REG_NB_LDO_DR

1V05REG_NB_LDO_DR

- @m38a_lib.M38A

- @m38a_lib.M38A

1V05REG_NB_LDO_FB

1V05REG_NB_LDO_FB

1V05REG_NB_LGATE

1V05REG_NB_LGATE

1V05REG_NB_PVCC5

1V05REG_NB_PVCC5

- @m38a_lib.M38A - @m38a_lib.M38A

=PP1V2_S3_ENET

81C5 =PP1V2_S3_LAN

81C7 81B7

=PP1V8_S0_FB_VDD

81C7 81C7

1V05REG_NB_VCC5

1V5REG_PCIE_COMP_R

- @m38a_lib.M38A

1V5REG_PCIE_FB

1V5REG_PCIE_FB

1V5REG_PCIE_FB_R

1V5REG_PCIE_FB_R

1V5REG_PCIE_FS_DIS

1V5REG_PCIE_FS_DIS

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

1V5REG_PCIE_LDO_DR

- @m38a_lib.M38A

PP1V8R2V0_S0_FB_GPU

-

80C5

-

1V5REG_PCIE_SNUB

1V5REG_PCIE_SWITCHN ODE -

80C5

=PP1V8_S3_MEM

DE 1V5REG_PCIE_UGATE

@m38a_lib.M38A 1V5REG_PCIE_UGATE

80D6

PP1V8_S3 - @m38a_lib.M38A

1V5REG_PCIE_VCC5

1V5REG_PCIE_VCC5

- @m38a_lib.M38A

79B3 79D6

1V8REG_DDR_COMP

1V8REG_DDR_COMP_R

1V8REG_DDR_COMP_R 1V8REG_DDR_FB

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

1V8REG_DDR_FB_R

- @m38a_lib.M38A

1V8REG_DDR_FS_DIS 1V8REG_DDR_GND

1V8REG_DDR_LDO_DR

1V8REG_DDR_LDO_DR

=PPVCORE_S0_GPU

88C6

PP1V0R1V2_S0_GPU

86B8 87A5 87A8 87B5 87B8

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

88C6

=PP3V3_S0_GPU

- @m38a_lib.M38A

=PP3V3_S0_FAN

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

=PP2V5_S0_NB_VCCA_3G BG =PP2V5_S0_GPU

PP2V5_S0 - @m38a_lib.M38A

- @m38a_lib.M38A

=PP2V5_S0_GPU_VDD25 @m38a_lib.M38A

79C7

=PP2V5_S0_GPU_VDDC_C T -

79C7

@m38a_lib.M38A

-

=PPVCORE_S0_GPU_REG

78B2 88B6

=PP3V3_S0_AIRPORT

88B8

=PP3V3_S0_2V5REG

-

@m38a_lib.M38A

- @m38a_lib.M38A

=PP3V3_S3_1V2REG

88B6 91B7

- @m38a_lib.M38A

PP3V3_S3 - @m38a_lib.M38A

86B8 87A5 87A8 87B5 87B8

=PP3V3_S3_BT - @m38a_lib.M38A =PP3V3_S3_TPM

- @m38a_lib.M38A

=PP3V3_S3_ENET

- @m38a_lib.M38A

=PP3V3_S3_ENET

- @m38a_lib.M38A

88B6 93C8

PP3V3_S5 - @m38a_lib.M38A

78C6

1V8REG_GPU_BOOT_R

1V8REG_GPU_BOOT_R

1V8REG_GPU_COMP

1V8REG_GPU_COMP

1V8REG_GPU_COMP_R

1V8REG_GPU_COMP_R

1V8REG_GPU_FB

1V8REG_GPU_FB

1V8REG_GPU_FB_R

1V8REG_GPU_FB_R

1V8REG_GPU_FS_DIS

1V8REG_GPU_FS_DIS

1V8REG_GPU_GND

1V8REG_GPU_GND

1V8REG_GPU_LDO_DR

1V8REG_GPU_LDO_DR

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

1V8REG_GPU_LDO_FB

1V8REG_GPU_LDO_FB

1V8REG_GPU_LGATE

1V8REG_GPU_LGATE

1V8REG_GPU_PVCC5

1V8REG_GPU_PVCC5

- @m38a_lib.M38A - @m38a_lib.M38A

2V5REG_ITH - @m38a_lib.M38A 2V5REG_ITH_RC

2V5REG_MODE

2V5REG_MODE

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

2V5REG_RT

2V5REG_RT - @m38a_lib.M38A

2V5REG_SGND

2V5REG_SGND

2V5REG_SW

2V5REG_SW - @m38a_lib.M38A

2V5REG_VFB

2V5REG_VFB - @m38a_lib.M38A

5V_REG_IN

5V_REG_IN - @m38a_lib.M38A

=I2C_HD_TEMP_SCL

=I2C_HD_TEMP_SCL

- @m38a_lib.M38A

=I2C_ODD_TEMP_SCL =SMB_THRM_CLK SMB_B_S0_CLK

@m38a_lib.M38A =PP3V3_S5_SB_VCCSUS3_ 3_USB -

41D5 41D6 42C4

@m38a_lib.M38A

42C4 43D8

=PP3V3_S5_SB_VCCSUS3_ 3 -

6A4 14C7 14D6 19C7 20A4

@m38a_lib.M38A

=PP2V5_S3_ENET =PP3V3_S0_NB

- @m38a_lib.M38A -

@m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

SMB_GPU_NB_THRM_CLK

-

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

20B4 20B4

=PP3V3_S5_SB_PM

- @m38a_lib.M38A

88C6 97D2

=PP3V3_S5_SB_USB

78B3

=PP3V3_DDC_LCD

- @m38a_lib.M38A

88C6 94A7 94C7

=PP3V3_S5_SB - @m38a_lib.M38A

78B7

=PP3V3_GPU - @m38a_lib.M38A

88C6 94B3

78B7

PP3V3_S0 - @m38a_lib.M38A

6B6 6D8 10D2 11B8 26B7

78C7 78B7

=SMB_THRM_CLK

- @m38a_lib.M38A

=I2C_ODD_TEMP_SCL =I2C_HD_TEMP_SDA

=I2C_HD_TEMP_SDA =I2C_ODD_TEMP_SDA

A

=SMB_THRM_DATA SMB_B_S0_DATA

-

@m38a_lib.M38A

- @m38a_lib.M38A -

@m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

SMB_GPU_NB_THRM_DAT A -

- @m38a_lib.M38A

@m38a_lib.M38A

7 8C6

-

- @m38a_lib.M38A

=PP3V3_S0_2V5REG

- @m38a_lib.M38A

=PP3V3_S0_AIRPORT

77D2

=PP3V3_S0_PCI

77D2

=PP3V3_S0_AUDIO

-

@m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

77D3

SMB_B_S0_DATA

- @m38a_lib.M38A

=SMB_THRM_DATA

- @m38a_lib.M38A

SMB_CK410_CLK

-

@m38a_lib.M38A

- @m38a_lib.M38A

=SMB_AIRPORT_CLK

- @m38a_lib.M38A

- @m38a_lib.M38A

SMB_CLK - @m38a_lib.M38A SMB_CK410_CLK

- @m38a_lib.M38A

=SMB_AIRPORT_CLK =I2C_MEM_SDA

=I2C_MEM_SDA

6A4

68A5 68D7

=PP3V3_S5_SB_VCCSUS3_ 3 72A6 72C8

@m38a_lib.M38A =PP3V3_S0_SB_VCC3_3

-

- @m38a_lib.M38A

- @m38a_lib.M38A

58B5 59C2 59D1 10C3 59C1 5 9C1

=PP3V3_S0_NB_VCC_HV

-

- @m38a_lib.M38A

ATI_DVPDATA<7>

ATI_DVPDATA<7>

- @m38a_lib.M38A

6D1 11B5 23D1

ATI_DVPDATA<8>

ATI_DVPDATA<8>

- @m38a_lib.M38A

6D1 22D8

ATI_DVPDATA<9>

ATI_DVPDATA<9>

- @m38a_lib.M38A

6D1 23A7 23B3 23B7 23D4

ATI_DVPDATA<10>

ATI_DVPDATA<10>

- @m38a_lib.M38A

91B3 95B6

23D8 25C8 26D8

ATI_DVPDATA<11>

ATI_DVPDATA<11>

- @m38a_lib.M38A

91B3 95B6

5D2 6A8 6C8 6D2 6D8 6D8

ATI_DVPDATA<12>

ATI_DVPDATA<12>

- @m38a_lib.M38A

91B3 95B6

11D8 26C1 26C4 26C4 59A8

ATI_DVPDATA<13>

ATI_DVPDATA<13>

- @m38a_lib.M38A

91B3 95C6

ATI_DVPDATA<14> ATI_DVPDATA<15> ATI_DVPDATA<16>

ATI_DVPDATA<14> ATI_DVPDATA<15> ATI_DVPDATA<16>

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

ATI_DVPDATA<17>

ATI_DVPDATA<17>

- @m38a_lib.M38A

91B3 95C6

ATI_DVPDATA<18>

ATI_DVPDATA<18>

- @m38a_lib.M38A

91B3 95C6

ATI_DVPDATA<19>

- @m38a_lib.M38A

ATI_DVPDATA<20> ATI_DVPDATA<21>

ATI_DVPDATA<21>

- @m38a_lib.M38A

91B3 95C6

6D1 24A5 24B3 25B6 25D1

ATI_DVPDATA<22>

ATI_DVPDATA<22>

- @m38a_lib.M38A

91A3 95C6

ATI_DVPDATA<23>

- @m38a_lib.M38A

91A3 95C6

ATI_DVPDATA<20>

- @m38a_lib.M38A

91B3 95C6

91A3

23D8 25C8 26D8

AUDLINDETH

AUDLINDETH - @m38a_lib.M38A

74D5

6D1 63D4

AUDSAMPCPN

AUDSAMPCPN - @m38a_lib.M38A

72C4

6D1 44A6 44B2 44D5 44D7

AUDSAMPCPP

AUDSAMPCPP - @m38a_lib.M38A

72C4

45D6 46A8

AUDSAMPINLN

AUDSAMPINLN

- @m38a_lib.M38A

72D6

6A4 68A5

AUDSAMPINLP

AUDSAMPINLP

- @m38a_lib.M38A

6A5

AUDSAMPINRN

AUDSAMPINRN

- @m38a_lib.M38A

6A4 60D4

AUDSAMPINRP

AUDSAMPINRP

- @m38a_lib.M38A

88A6 97D6

AUDSAMPOURTP

AUDSAMPOURTP

- @m38a_lib.M38A

72C4

AUDSAMPOUTLN

AUDSAMPOUTLN

- @m38a_lib.M38A

72C4

6B4 59A8 59B7 65B7 65C7

=PP5V_S0_AUDIO

PP5V_S0_AUDIO

6B4 38D3

=PP5V_S0_DEBUG

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

=PP5V_S0_DEBUG

- @m38a_lib.M38A

61C5 91A3 61C5 91A3

72C6 72C6 72C6

6B4 26D4

=PP5V_S0_DVI_DDC

6B4 26D1

=PP5V_S0_GPUISENS

6B4 24C3 25B3

PP5V_S0 - @m38a_lib.M38A

6A6 6D8 75D7 88B8 97D3

AUDSAMPOUTLP

AUDSAMPOUTLP

- @m38a_lib.M38A

72C4

=PP5V_S0_SB - @m38a_lib.M38A

6A4 25D8

AUDSAMPOUTRN

AUDSAMPOUTRN

- @m38a_lib.M38A

72C4

6B4 24B3 25A3

=PP5V_S0_PATA

6B4 24B5 24B5 25B8 25C6 6B4 17C6 19A8 19C7

- @m38a_lib.M38A

6B4 21C3 21D3 23B3 23D5 6A4 24D3 25D3

@m38a_lib.M38A

- @m38a_lib.M38A

85D 2

88A6

6A4 38C4 38D3 6A6 6D8 75D7 88B8 97D3

=PP5V_S0_SB - @m38a_lib.M38A

6A4 25D8

=PP5V_S0_PATA

6A4 38C4 38D3

- @m38a_lib.M38A

=PP5V_S0_GPUISENS =PP5V_S0_DVI_DDC =PP5V_S0_GPUVCORE

-

PP5V_S0 - @m38a_lib.M38A

=PP5V_S0_GPUBBCTL

=PP3V3_S0_SB_GPIO - @m38a_lib.M38A

-

@m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

=PP5V_S0_GPUVCORE

- @m38a_lib.M38A

85D 2

88A6

AUD_4V5_SHDN_L

AUD_4V5_SHDN_L

AUD_ANALOG_FILT_1

AUD_ANALOG_FILT_1

- @m38a_lib.M38A

68C4

AUD_ANALOG_FILT_2

AUD_ANALOG_FILT_2

- @m38a_lib.M38A

68C4

AUD_BI_PORT_A_L

AUD_BI_PORT_A_L

AUD_BI_PORT_A_R

88B6

AUD_BI_PORT_B_L

88A6 97D6 85D7 88D6

=PP5V_S0_MEMVTT

6C3 31C6

AUD_BI_PORT_A_R AUD_BI_PORT_B_L AUD_BI_PORT_B_R

88D6

GPUVCORE_VCC - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

AUD_BI_PORT_C_L

- @m38a_lib.M38A

68C7 72D8

AUD_BI_PORT_C_R

- @m38a_lib.M38A

68C7 72C8

=PP3V3_S0_SB

PP3V3_S0 - @m38a_lib.M38A

6B6 6D8 10D2 11B8 26B7 88C8

=PP5V_S3_USB - @m38a_lib.M38A

6C3 47C8

AUD_DEBOUNCE

AUD_DEBOUNCE

=PPSPD_S0_MEM

6A4 28A7 29A3 29A7

PP5V_S3 - @m38a_lib.M38A

6C4 60B6 83C3

AUD_GPIO_0

AUD_GPIO_0 - @m38a_lib.M38A

6B4 22B5 25D8 27C6

=PP5V_S0_MEMVTT

- @m38a_lib.M38A

PP5V_S3 - @m38a_lib.M38A

26C6 41D8 59D3 61C3 76D6

=PP5V_S3_BNDI

- @m38a_lib.M38A

6C4 60B6 83C3 6C3 47D3

68C1 74B8 68B2 68C1 74A3 68B1 68C1

AUD_BI_PORT_C_L

27D6 33B6

AUD_BI_PORT_F_L

AUD_BI_PORT_F_L

- @m38a_lib.M38A

68C1 74C8

AUD_BI_PORT_F_R

AUD_BI_PORT_F_R

- @m38a_lib.M38A

68C1 74C8

AUD_BYPASS

AUD_BYPASS - @m38a_lib.M38A - @m38a_lib.M38A

A

68A5

68C1 74B8

AUD_BI_PORT_C_R

23D5 27B8 27D7

- @m38a_lib.M38A

91B3 95C6

6D1 24B3 25D1

91D3

@m38a_lib.M38A - @m38a_lib.M38A

91B3 95C6 91B3 95C6 91B3 95C6

81A5 83C3 6D1 58C2 58D3 58D4 59A4

ATI_DVPDATA<19>

B

91B3 95B6

ATI_VREFG - @m38a_lib.M38A

=PP3V3_S0_SB_VCCLAN3 _3 -

27D6 33B6

91B3 95B6

ATI_VREFG

27D6 28A6 29A6

27D6 28A6 29A6

91B3 95B6

6D1 23A7 23B3 23B7 23D4

27D6 53B4

27D6 53B4

91B3 95B6

93A8 93B5

@m38a_lib.M38A

66B4

ATI_DVPDATA<6>

ATI_TESTEN - @m38a_lib.M38A

33D8 34D4

@m38a_lib.M38A =PP3V3_S0_SB_VCC3_3_ PCI -

91B3 95B6

ATI_DVPDATA<6>

6D1 24A5 24B3 25B6 25D1

ATI_TESTEN

=PP5V_S0_AUDIO

10C3 59C1

- @m38a_lib.M38A

93A8 93B5

=PP3V3_S0_HD_TSENS - @m38a_lib.M38A 6B4 66B5

58B5 59C2 59D1

ATI_DVPDATA<5>

- @m38a_lib.M38A

=PP3V3_S0_FAN

59C1 61C3

91B3 95B6

ATI_DVPDATA<5>

- @m38a_lib.M38A

58B5 59C2 59D1

66B4

91B3 95B6

- @m38a_lib.M38A

ATI_R2SET - @m38a_lib.M38A

59C1 61C3

5 9C1

91B3 95B6

- @m38a_lib.M38A

ATI_DVPDATA<4>

ATI_TDIODE_P

=PP3V3_S5_FW - @m38a_lib.M38A

=PP3V3_S0_SB_VCC3_3_ IDE -

91B3 95B6

- @m38a_lib.M38A

ATI_DVPDATA<3>

ATI_DVPDATA<4>

ATI_TDIODE_N

33C8 33D3

@m38a_lib.M38A

59C1 66B6

91B3 95B6

- @m38a_lib.M38A

ATI_DVPDATA<2>

ATI_DVPDATA<3>

ATI_RSET - @m38a_lib.M38A

=PP3V3_S5_ROM

- @m38a_lib.M38A

- @m38a_lib.M38A

ATI_DVPDATA<1>

ATI_DVPDATA<2>

ATI_TDIODE_P

6A4 66B4

- @m38a_lib.M38A

ATI_DVPDATA<0>

ATI_DVPDATA<1>

ATI_TDIODE_N

6A4

@m38a_lib.M38A

=PP3V3_S0_SB_PM

ATI_DVPDATA<0>

6D1 24C3

ATI_R2SET

=PP3V3_S5_SB - @m38a_lib.M38A

=PP3V3_S0_SB_PCI

45D6 46A8 6D1 22C6 27C6

6D1 24B3 25D1

ATI_DVPDATA<23>

6A4 24C3 25C4

66B4

91B3 95A6

ATI_RSET

=PP3V3_S0_SB_3V3_1V5 _VCCHDA -

10C3 59C1

91B3 95A6

- @m38a_lib.M38A

6D1 24C3

68A4

5 9C1

91C3 95A6

- @m38a_lib.M38A

ATI_DVPCNTL<2>

6D1 22D8

@m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

ATI_DVPCNTL<1>

6D1 22C6 27C6

6A4 67C7 67D4

=PP3V3_S0_PATA

95A8

ATI_DVPCNTL<0>

ATI_DVPCNTL<2>

6D1 11B5 23D1

- @m38a_lib.M38A

- @m38a_lib.M38A

58B5 59C2 59D1

59D3 59D3 91C3 95A6

- @m38a_lib.M38A

=PP3V3_S0_TPM

- @m38a_lib.M38A

- @m38a_lib.M38A

58A7 59D5 58A7 59D5

- @m38a_lib.M38A

77D2

-

- @m38a_lib.M38A

=PP3V3_S5_SB_IO

=PP3V3_S5_SB_3V3_1V5_ VCCSUSHDA -

=PP3V3_S0_ODD_TSENS

- @m38a_lib.M38A

TP_ALS_RIGHT

=PP3V3_S5_SB_PM

6A4 28A7 29A3 29A7

10C3 59C1

TP_ALS_LEFT

ALS_RIGHT - @m38a_lib.M38A ATI_DVPCLK - @m38a_lib.M38A

=PP3V3_S5_SB_USB

- @m38a_lib.M38A

66B4

ALS_LEFT - @m38a_lib.M38A

ALS_RIGHT ATI_DVPCLK

ATI_DVPCNTL<1>

@m38a_lib.M38A

=PPSPD_S0_MEM

59C1 66B6

ALS_LEFT

72D5 73B8 74B5 74C5 74D6 =PP3V3_S0_CK410

5 9C1

6B7 53C5 53C6 26D5 58D7 77D4

6A4 75D8

=PP3V3_S0_IMVP

77C2 77D2

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

ATI_DVPCNTL<0>

@m38a_lib.M38A

77D3

- @m38a_lib.M38A

- @m38a_lib.M38A

AIRPORT_WAKE_L

59A5 59C4 59D3 59D8

59A5 59C4 59D3 59D8 =PP3V3_S5_SB_VCCSUS3_ 3_USB -

53C2

@m38a_lib.M38A

=I2C_ODD_TEMP_SDA =I2C_MEM_SCL

- @m38a_lib.M38A

88C6 94C8

6A4 44D5

AIRPORT_RST_L

6D1 58C2 58D3 58D4 59A4

79A5 79B3 80A5 80B3 81A5

6A4 77D4 6A 4

34B4 34C2 53C6

5 3B5 53B5

6D1 44A6 44B2 44D5 44D7

77D5 77D6 77D6 77D8 79A3

88C6 88D3 91C6 =PP3V3_S5_SMC

78C7

AIRPORT_CONN_CLK - @m38a_lib.M38A AIRPORT_CONN_DATA - @m38a_lib.M38A

TP_ATI_DVPCLK

65B7 65D7 66D7 76D2 77C8

6A7 88C6 91D2 93A1 97A5 97B5

=PP3V3_S0_GPU_VDDR3

@m38a_lib.M38A

=I2C_MEM_SCL

PP3V3_S5 - @m38a_lib.M38A

66C7

- @m38a_lib.M38A

- @m38a_lib.M38A

88C8 =PP3V3_S0_GPU

78B3 78B5

@m38a_lib.M38A SMB_B_S0_CLK

- @m38a_lib.M38A

26C6 41D8 59D3 61C3 76D6

=PP3V3_S0_LCD

1V8REG_GPU_VCC5

2V5REG_ITH

- @m38a_lib.M38A

=PP3V3_S5_SB_3V3_1V5_ VCCSUSHDA 88B6 93C8

=PP3V3_DDC_DVI

@m38a_lib.M38A 1V8REG_GPU_UGATE

1V8REG_GPU_VCC5

- @m38a_lib.M38A

78B5

7 8C7

- @m38a_lib.M38A

1V8REG_GPU_UGATE

2V5REG_ITH_RC

=PP3V3_S5_SMC

=PP2V5_S0_GPU

78B5

7 8B6

1V8REG_GPU_SWITCHNO DE -

=PP3V3_S0_NB

5D2 6A8 6C8 6D2 6D8 6D8

79A5 79B3 80A5 80B3 81A5

=PP2V5_S0_GPU_PVDD - @m38a_lib.M38A 88B6 91A8

PP2V5_S3_ENET

78B6

- @m38a_lib.M38A

1V8REG_GPU_SNUB

1V8REG_GPU_SWITCHNOD E

78C5

- @m38a_lib.M38A

1V8REG_GPU_SNUB

=PP2V5_S3_ENET

AIRPORT_RST_L AIRPORT_WAKE_L

65B7 65D7 66D7 76D2 77C8

=PP3V3_S5_SB_IO

- @m38a_lib.M38A

AIRPORT_CLK100M_PCI E_P @m38a_lib.M38A

6D1 63D4 11D8 26C1 26C4 26C4 59A8

@m38a_lib.M38A -

21C7 68D7

59C5

88B6 91C6

1V8REG_GPU_BOOT

AIRPORT_CLK100M_PCIE

6B6 11B8 11C8 77D1 88C8

C

6 8C6 21C7 68D7

81A5 83C3

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

34B4 34C2 53C6

77D5 77D6 77D6 77D8 79A3

=PP2V5_S0_GPU_VDD25

ACZ_SDATAOUT

@m38a_lib.M38A

AIRPORT_CONN_CLK AIRPORT_CONN_DATA

6D3 41A5 41B3 41C3 41D6

ACZ_SDATAIN_CHIP

ACZ_SYNC - @m38a_lib.M38A AIRPORT_CLK100M_PCI E_N -

 _P

6C3 6D3 67C2

88B6 91C6

@m38a_lib.M38A

1V8REG_GPU_BOOT

ACZ_SDATAOUT ACZ_SYNC AIRPORT_CLK100M_PCIE  _N

58B5 59C6

=PP3V3_S5_FW - @m38a_lib.M38A

79D7

ACZ_SDATAIN_CHIP

6D3 67C2

NC_ALS_GAIN

6B6 11B8 11C8 77D1 88C8

79C3

6D3 47B2 6D3 41A5 41B3 41C3 41D6

ALL_SYS_PWRGD

88B6 91C6

79C5

21C7 68D7

ALS_GAIN - @m38a_lib.M38A

=PP2V5_S0_GPU_VDDC_C T -

7 9D6

21C7 68C7

- @m38a_lib.M38A

ALL_SYS_PWRGD

PP2V5_S0 - @m38a_lib.M38A

- @m38a_lib.M38A

21C7 68D7

ACZ_RST_L - @m38a_lib.M38A ACZ_SDATAIN<0>

ALS_GAIN

7 9D7

- @m38a_lib.M38A

5D2 6D6 75A4 75D1 76B3

ACZ_BITCLK - @m38a_lib.M38A

ACZ_SDATAIN<0>

6D3 47B2

7 9C6

- @m38a_lib.M38A

6D4 8B6 8D7 8D8 9B8

6D1 60D4

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

@m38a_lib.M38A

86D8 88D6 91A7

=PP3V3_S3_BT - @m38a_lib.M38A

- @m38a_lib.M38A

1V8REG_DDR_VCC5

85A8 88D6

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

=PP3V3_S5_DEBUG

88B6 91C6

=PP2V5_S0_GPU_PVDD - @m38a_lib.M38A 88B6 91A8

-

=PPVCORE_S0_GPU =PPVCORE_S0_CPU

ACZ_RST_L

41D8 42D8 =PP3V3_S5_DEBUG

85C1 88D6

ACZ_BITCLK

83B3

5C4 6D3 28B2 28C8 28D3

88C8 59B4 88D8 85A6 88C6

6D3 77C7

6C3

6D3 31C7

86D6 88C6

85C1 88D6

83B3

=PP3V3_S3_USB =PP3V3_S3_TPM

6B4 17D6 19A8 19C7

46D6 86D8 88D6 91A7

6A7 6D4 53C4 59C8 59D3

=PP3V3_S3_VGASYNC

- @m38a_lib.M38A

=PPVCORE_S0_CPU

PPVCORE_CPU

5C4 6D3 28B2 28C8 28D3

- @m38a_lib.M38A - @m38a_lib.M38A

44C2 46D5

59B4 88D8

@m38a_lib.M38A

28D6 29B2 29D3 29D6 5D2 6D4 79C2

1V8REG_DDR_LDO_FB

1V8REG_DDR_SNUB

=PPVCORE_S0_GPU_BBP

41D8 42D8

5D2 6D4 79C2

-

6C1 46D7

@m38a_lib.M38A

53C2

6A4 77D4

6A7 6D4 53C4 59C8 59D3

1V8REG_DDR_PVCC5

1V8REG_DDR_SWITCHNO DE -

6A4

PP3V3_S3 - @m38a_lib.M38A

1V8REG_DDR_LGATE

1V8REG_DDR_UGATE

- @m38a_lib.M38A

@m38a_lib.M38A

=PP3V3_S5_ROM

79C5

1V8REG_DDR_VCC5

=PPVOUT_S0_GPUBBP_L DO 72A6 72C8

@m38a_lib.M38A

79C7

- @m38a_lib.M38A

PP1V0R1V2_S0_GPU

68A5 68D7

6D3 31C7

79C5

1V8REG_DDR_UGATE

PPBB_S0_GPU

6A4

1V8REG_DDR_LGATE

E

@m38a_lib.M38A

97B5 66C7 - @m38a_lib.M38A

1V8REG_DDR_LDO_FB

1V8REG_DDR_SWITCHNOD

6A7 88C6 91D2 93A1 97A5

-

6B4 59A8 59B7 65B7 65C7

=PP3V3_S0_AUDIO

6D3 6D3 14C2 16B6 19B8

79C3

79C7

=PPVCORE_S0_GPU_REG

88B6 91B7

28D6 29B2 29D3 29D6

BG

- @m38a_lib.M38A

33D8 34D4

- @m38a_lib.M38A

=PP1V8_S0_MEMVTT =PP2V5_S0_NB_VCCA_3G

- @m38a_lib.M38A

33C8 33D3

- @m38a_lib.M38A

=PP1V8_S3_MEM

79D5 79C6

- @m38a_lib.M38A

6A4

=PP1V8_S0_MEMVTT

- @m38a_lib.M38A

- @m38a_lib.M38A

PP12V_FW - @m38a_lib.M38A

- @m38a_lib.M38A

1V8REG_DDR_PVCC5 1V8REG_DDR_SNUB

- @m38a_lib.M38A

-

=PP3V3_S0_CK410

=PP1V8_S3_MEM_NB

PP1V8_S3 - @m38a_lib.M38A

8 0D7

1V6_REF - @m38a_lib.M38A 1V8REG_DDR_BOOT

1V8REG_DDR_BOOT_R

1V8REG_DDR_FS_DIS

88C6

- @m38a_lib.M38A

88B6

1V5REG_PCIE_SWITCHNO

1V8REG_DDR_GND

- @m38a_lib.M38A

=PP3V3_S0_GPUBBN

=PP3V3_S3_1V2REG

1V5REG_PCIE_SNUB

1V8REG_DDR_COMP

=PPBB_S0_GPU

=PP3V3_S0_GPUBBP

19D7

8 0C3

=PP12V_S5_FW_PHY

=PPBB_S0_GPU

@m38a_lib.M38A

88C6 97D2

@m38a_lib.M38A =PP1V8_S3_MEM_NB

=PP12V_S5_FW_PHY

=PP3V3_S0_GPU_CLOCKS

6D3 42B8

- @m38a_lib.M38A

=PP1V8R2V0_S0_FB_GPU

80C7 80C7

1V8REG_DDR_BOOT_R

=PP3V3_S0_HD_TSENS - @m38a_lib.M38A 6B4 66B5

42B5

=PP3V3_DDC_DVI

80D7

1V8REG_DDR_FB_R

41A8 41D6 42B5

- @m38a_lib.M38A

6D4 77B3

88B6 91B7

80C6

1V8REG_DDR_FB

=PP12V_S5_FW

@m38a_lib.M38A

80B7

11D7 77C8 77D8 78C7 79D7 80D7 81D7 83C5 83C5 88B8 =PPVIN_S0_GPUVCORE - @m38a_lib.M38A 85D7 88B6

6A4 75D8

- @m38a_lib.M38A

=PP1V8R3V3_S0_GPU_VD DR5 -

- @m38a_lib.M38A

6C1 46D7 5D2 6C2 6D7 11A8 11C7

=PP3V3_S0_IMVP

88C6 94A7 94C7

- @m38a_lib.M38A

- @m38a_lib.M38A

84C8 88D6

88C6 94B3

1V5REG_PCIE_LDO_FB

1V8REG_DDR_BOOT

80D7 81D7 83C5 83C5 88B8 =PP12V_S5_FW

PP12V_S5 - @m38a_lib.M38A

6B4 88C6 94C8

- @m38a_lib.M38A

1V5REG_PCIE_PVCC5

- @m38a_lib.M38A

6B4 17C6 19A8 19C7

D

6C1 76D8 5D2 6C2 6D7 11A8 11C7

=PP3V3_S0_NB_PM - @m38a_lib.M38A =PP3V3_S0_LCD - @m38a_lib.M38A

=PP3V3_DDC_LCD

1V5REG_PCIE_LGATE

- @m38a_lib.M38A

-

=PP3V3_S0_NB_TVDAC - @m38a_lib.M38A 6B4 19C7

=PP3V3_GPU - @m38a_lib.M38A

1V5REG_PCIE_PVCC5

- @m38a_lib.M38A

11D7 77C8 77D8 78C7 79D7

88B6 89D5 89D8 90D5 90D8

1V5REG_PCIE_LGATE

=PP12V_S5_CPU

=PPVIN_S0_GPUVCORE - @m38a_lib.M38A 85D7 88B6

=PP1V8_S0_FB_VDDQ - @m38a_lib.M38A

=PP1V8R3V3_S0_GPU_VD DR4 -

80C7

=PP12V_S5_CPU

PP12V_S5 - @m38a_lib.M38A

@m38a_lib.M38A

@m38a_lib.M38A

8 0C3

6A5

6A4 44D5

=PP3V3_S0_NB_VCC_HV

@m38a_lib.M38A

80C5

6A4 65B6 65D7 66D6 6A4 72D8

@m38a_lib.M38A

72D5 73B8 74B5 74C5 74D6

PP1V8_S0 - @m38a_lib.M38A

80C5

6A4 65B6 65D7 66D6 6A6 6D8 88B8

6B4 38D3

@m38a_lib.M38A

@m38a_lib.M38A

81D7 8 0C6

6B4 22B5 25D8 27C6

6A4 66B4

88B6

1V5REG_PCIE_LDO_FB

1V6_REF

- @m38a_lib.M38A

8 1D6

8 0C6

- @m38a_lib.M38A

=PP12V_S0_AUDIO_SPK RAMP PP12V_S0_AUDIO_SPKR AMP -

-

77A3 88C6

78B2 88B6

- @m38a_lib.M38A

- @m38a_lib.M38A

84A2 88C6

88B6 91B7

- @m38a_lib.M38A

- @m38a_lib.M38A

=PP3V3_S0_PATA

88D8

@m38a_lib.M38A

- @m38a_lib.M38A

6D1 25C8

@m38a_lib.M38A

84C8 88D6

=PP1V8R3V3_S0_GPU_VD DR5 -

1V5REG_PCIE_COMP_R

1V5REG_PCIE_GND

=PP3V3_S0_SB - @m38a_lib.M38A

@m38a_lib.M38A

1V5REG_PCIE_BOOT_R

1V5REG_PCIE_LDO_DR

84C8 88D6

PP1V8_S0 - @m38a_lib.M38A

- @m38a_lib.M38A

1V5REG_PCIE_BOOT

AMP

=PP3V3_S0_GPUBBCTL - @m38a_lib.M38A 88C6

=PP1V8R3V3_S0_GPU_VD DR4 -

1V05REG_NB_UGATE

=PP12V_S0_AUDIO_SPKR

88B6 89D5 89D8 90D5 90D8

-

- @m38a_lib.M38A

=PP12V_S0_FAN

6B4 26D1

81C3

1V5REG_PCIE_COMP

6B4 26D4 6B4 21C3 21D3 23B3 23D5

84C8 88D6

- @m38a_lib.M38A

88B6 89D5 89D8 90D5 90D8

=PP1V8R2V0_S0_FB_GPU

6A6 6D8 88B8

6A4 24C3 25C4

81C5

1V5REG_PCIE_BOOT_R

- @m38a_lib.M38A

=PP1V8_S0_FB_VDD

- @m38a_lib.M38A

88B6 94C3 94D7

=PP12V_S0_FAN

@m38a_lib.M38A

8 1D7

- @m38a_lib.M38A

1V5REG_PCIE_COMP

1V5REG_PCIE_GND

- @m38a_lib.M38A

5D2 6D2 6D7 59A5 79B3

PP12V_S0 - @m38a_lib.M38A 6B4 24B5 24B5 25B8 25C6

PP1V2_S3 - @m38a_lib.M38A =PP1V8_S0_FB_VDDQ - @m38a_lib.M38A

@m38a_lib.M38A

1V05REG_NB_VCC5

- @m38a_lib.M38A

- @m38a_lib.M38A

6C3 47D3

PP5V_S5 - @m38a_lib.M38A =PP12V_GPU - @m38a_lib.M38A

=PP3V3_S0_SB_3V3_1V5_ VCCHDA -

8 1C6

1V05REG_NB_SWITCHNO DE -

1V5REG_PCIE_BOOT

- @m38a_lib.M38A

PP1V2_S3_ENET =PP1V2_S3_LAN

- @m38a_lib.M38A

=PP5V_S5_SB

=PP12V_GPU

=PP3V3_S0_SB_GPIO - @m38a_lib.M38A

- @m38a_lib.M38A

1V05REG_NB_SNUB

1V05REG_NB_SWITCHNOD 1V05REG_NB_UGATE

=PP1V2_S3_ENET

-

6B4 24C3 25B3

77A3 88C6

- @m38a_lib.M38A

1V05REG_NB_SNUB E

81C5 81C3

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

=PP5V_S3_BNDI

1

6C3 47C8

=PP5V_S5_SB 6B4 24B3 25A3

84A2 88C6

=PP3V3_S0_ODD_TSENS

80B3

1V05REG_NB_GND

88C6 91B8

=PP3V3_S0_PCI

1V3_REF - @m38a_lib.M38A

6A4 24D3 25D3

2

- @m38a_lib.M38A

PP12V_S0 - @m38a_lib.M38A

=PP3V3_S0_SB_PCI

=PPVIO_S0_PCIE

1V2REG_VFB - @m38a_lib.M38A

1V05REG_NB_FB_R

6D6 79A3

=PP3V3_S0_SB_PM

-

@m38a_lib.M38A

1V05REG_NB_BOOT - @m38a_lib.M38A 1V05REG_NB_BOOT_R - @m38a_lib.M38A - @m38a_lib.M38A

=PP3V3_S0_SB_VCC3_3_I DE -

=PP0V9_S0_MEM_TERM - @m38a_lib.M38A 6D4 30D4

77B5

1V05REG_NB_BOOT 1V05REG_NB_BOOT_R

- @m38a_lib.M38A

6D4 31B3

=PP1V2_S0_GPU_VDDPLL

77B6 77B6

1V3_REF

1V05REG_NB_FB

- @m38a_lib.M38A

77B5 77B6

-

=PP5V_S3_USB

79B3 80B3 81B3 83C3

@m38a_lib.M38A 0V7_REF

=PP0V9_S0_MEMVTT_LDO

 

3

6A4 67C7 67D4

@m38a_lib.M38A

Location([Zone][dir ])

=PP0V9_S0_MEMVTT_LDO

 

4 =PP3V3_S0_TPM

Synonyms

1V2REG_VFB

B

- @m38a_lib.M38A

=SMB_AIRPORT_DATA

27 C6

Base Signal

1V2REG_ITH

C

@m38a_lib.M38A

SMB_DATA - @m38a_lib.M38A

Base nets and synonyms for m38a_lib.M38A(@m38a_lib.m38a(sch_1))

D

-

68C4 72B7 68C7 72B8 100

8

 

7

6

 

5

 

4

 

3

 

2

 

1

 

8 AUD_GPIO_1 AUD_GPIO_2

AUD_GPIO_2 - @m38a_lib.M38A

AUD_LI_DET_EMI

AUD_LI_DET_EMI

AUD_LI_DET_H

AUD_LI_DET_H

AUD_LI_DET_JACK AUD_LI_GND_EMI

AUD_LI_GND_JACK

AUD_LI_GND_JACK

AUD_LI_L

AUD_LI_L - @m38a_lib.M38A

- @m38a_lib.M38A

6

 

 

4

CK410_SRC2_P

- @m38a_lib.M38A

33B4 34A6

DMI_N2S_N<3>

DMI_N2S_N<3> - @m38a_lib.M38A

68B7 68C7

 

3

2

14B4 22D2

FB_A_DQ<22>

FB_A_DQ<22>

- @m38a_lib.M38A

87C7 89A6 87C7 89A6

CK410_SRC3_N

CK410_SRC3_N

- @m38a_lib.M38A

33B4 34D3

DMI_N2S_P<0>

DMI_N2S_P<0> - @m38a_lib.M38A

5B8 14B4 22D2

FB_A_DQ<23>

FB_A_DQ<23>

- @m38a_lib.M38A

73D6

CK410_SRC3_P

CK410_SRC3_P

- @m38a_lib.M38A

33B4 34D3

DMI_N2S_P<1>

DMI_N2S_P<1> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<24>

FB_A_DQ<24>

- @m38a_lib.M38A

5A6 5D6 87C7 89A6

73D4 74D6

CK410_SRC4_N

CK410_SRC4_N

- @m38a_lib.M38A

33B4 34B6

DMI_N2S_P<2>

DMI_N2S_P<2> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<25>

FB_A_DQ<25>

- @m38a_lib.M38A

87C7 89A6

73D7

CK410_SRC4_P

CK410_SRC4_P

- @m38a_lib.M38A

33B4 34B6

DMI_N2S_P<3>

DMI_N2S_P<3> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<26>

FB_A_DQ<26>

- @m38a_lib.M38A

87C7 89A6

73D6

CK410_SRC5_N

CK410_SRC5_N

- @m38a_lib.M38A

33B4 34B6

DMI_S2N_N<0>

DMI_S2N_N<0> - @m38a_lib.M38A

5C7 14B4 22D2

FB_A_DQ<27>

FB_A_DQ<27>

- @m38a_lib.M38A

87C7 89B6

73D7

CK410_SRC5_P

CK410_SRC5_P

- @m38a_lib.M38A

33B4 34B6

DMI_S2N_N<1>

DMI_S2N_N<1> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<28>

FB_A_DQ<28>

- @m38a_lib.M38A

87C7 89B6

73D4 74C5

CK410_SRC6_N

73D6

CK410_SRC6_N

- @m38a_lib.M38A

33B4 34B6

DMI_S2N_N<2>

DMI_S2N_N<2> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<29>

FB_A_DQ<29>

- @m38a_lib.M38A

87C7 89B6

CK410_SRC6_P

CK410_SRC6_P

- @m38a_lib.M38A

33B4 34B6

DMI_S2N_N<3>

DMI_S2N_N<3> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<30>

FB_A_DQ<30>

- @m38a_lib.M38A

87C7 89B6

AUD_LI_L_JACK

73D7

CK410_SRC7_N

CK410_SRC7_N

- @m38a_lib.M38A

33B4 34D3

DMI_S2N_P<0>

DMI_S2N_P<0> - @m38a_lib.M38A

5C7 14B4 22D2

FB_A_DQ<31>

FB_A_DQ<31>

- @m38a_lib.M38A

87C7 89A6

AUD_LI_R - @m38a_lib.M38A

73D4 74C5

CK410_SRC7_P

CK410_SRC7_P

- @m38a_lib.M38A

33B4 34D3

DMI_S2N_P<1>

DMI_S2N_P<1> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<32>

FB_A_DQ<32>

- @m38a_lib.M38A

5A6 5D6 87C7 89B2

AUD_LI_R_EMI

AUD_LI_R_EMI

73D6

CK410_SRC8_N

CK410_SRC8_N

- @m38a_lib.M38A

33A4 34A6

DMI_S2N_P<2>

DMI_S2N_P<2> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<33>

FB_A_DQ<33>

- @m38a_lib.M38A

87C7 89B3

AUD_LI_R_JACK

AUD_LI_R_JACK

- @m38a_lib.M38A

73D7

CK410_SRC8_P

CK410_SRC8_P

- @m38a_lib.M38A

33A4 34A6

DMI_S2N_P<3>

DMI_S2N_P<3> - @m38a_lib.M38A

14B4 22D2

FB_A_DQ<34>

FB_A_DQ<34>

- @m38a_lib.M38A

87C7 89B3

AUD_LO_DET1_1

AUD_LO_DET1_1

- @m38a_lib.M38A

74A4 74B2

CK410_SRC_CLKREQ1_L

CK410_SRC_CLKREQ1_L

33B4 34D8

DVI_DDC_CLK

DVI_DDC_CLK - @m38a_lib.M38A

97D2

FB_A_DQ<35>

FB_A_DQ<35>

- @m38a_lib.M38A

87C7 89B3

AUD_LO_DET1_INV

AUD_LO_DET1_INV

DVI_DDC_CLK_UF

DVI_DDC_CLK_UF

97D3 97D5

FB_A_DQ<36>

FB_A_DQ<36>

- @m38a_lib.M38A

87C7 89B3

DVI_DDC_DATA

DVI_DDC_DATA - @m38a_lib.M38A

97C2

FB_A_DQ<37>

FB_A_DQ<37>

- @m38a_lib.M38A

87C7 89B3

DVI_DDC_DATA_UF

DVI_DDC_DATA_UF

97C3 97D5

FB_A_DQ<38>

FB_A_DQ<38>

- @m38a_lib.M38A

87C7 89B3

DVI_HPD_UF

DVI_HPD_UF - @m38a_lib.M38A

97C3 97D5

FB_A_DQ<39>

FB_A_DQ<39>

- @m38a_lib.M38A

87C7 89B3

ENET_C4106_2

ENET_C4106_2 - @m38a_lib.M38A

ENET_C4107_2

AUD_LI_L_EMI

AUD_LO_DET2_1

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

AUD_LO_DET2_1

- @m38a_lib.M38A

- @m38a_lib.M38A

AUD_LO_GND_JACK

AUD_LO_GND_JACK

AUD_LO_L

AUD_LO_L - @m38a_lib.M38A AUD_LO_L_EMI

- @m38a_lib.M38A

- @m38a_lib.M38A

74B3

-

@m38a_lib.M38A

74B4

CK410_SRC_CLKREQ3_L

CK410_SRC_CLKREQ3_L

CK410_SRC_CLKREQ6_L

CK410_SRC_CLKREQ6_L

73B4

-

33B4 34D8

-

33B4 53C6

@m38a_lib.M38A

73B8 74B5 73B7

@m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

41D2

FB_A_DQ<40>

FB_A_DQ<40>

- @m38a_lib.M38A

5A6 5D6 87C7 89A2

AUD_LO_L_JACK

AUD_LO_L_JACK

CK410_SRC_CLKREQ8_L

CK410_SRC_CLKREQ8_L

ENET_C4107_2 - @m38a_lib.M38A

41D2

FB_A_DQ<41>

FB_A_DQ<41>

- @m38a_lib.M38A

87C7 89A3

AUD_LO_R

AUD_LO_R - @m38a_lib.M38A

73A8 74B5

ENET_C4117_1

ENET_C4117_1 - @m38a_lib.M38A

41B2

FB_A_DQ<42>

FB_A_DQ<42>

- @m38a_lib.M38A

87C7 89A3

AUD_LO_R_EMI

AUD_LO_R_EMI

73A7

CK410_USB48_FSA

CK410_USB48_FSA

33A4 34C6

ENET_C4118_1

ENET_C4118_1 - @m38a_lib.M38A

41B2

FB_A_DQ<43>

FB_A_DQ<43>

- @m38a_lib.M38A

87C7 89A3

AUD_LO_R_JACK AUD_LO_TIP

AUD_LO_R_JACK - @m38a_lib.M38A AUD_LO_TIP - @m38a_lib.M38A

73B4 73B8 74B5

CK410_XTAL_IN CK410_XTAL_OUT

CK410_XTAL_IN - @m38a_lib.M38A CK410_XTAL_OUT - @m38a_lib.M38A

33C6 33C6

ENET_CLK100M_PCIE_N

ENET_CLK100M_PCIE_N @m38a_lib.M38A

-

5D5 34A4 34B2 41C5

FB_A_DQ<44> FB_A_DQ<45>

FB_A_DQ<44> FB_A_DQ<45>

- @m38a_lib.M38A - @m38a_lib.M38A

87B7 89A3 87B7 89A3

ENET_CLK100M_PCIE_P

ENET_CLK100M_PCIE_P

-

5D5 34A4 34B2 41C5

FB_A_DQ<46>

- @m38a_lib.M38A - @m38a_lib.M38A

AUD_LO_TIP_EMI

AUD_LO_TIP_JACK

- @m38a_lib.M38A

AUD_LO_TIP_JACK

AUD_LO_TYPE

AUD_LO_TYPE

AUD_LO_TYPE_EMI

AUD_LO_TYPE_JACK

AUD_LO_TYPE_JACK

AUD_MAX9714_CHOLD

AUD_MAX9714_CHOLD

AUD_MAX9714_VREG

AUD_MAX9714_VREG

AUD_MIC_INTERCON

AUD_MIC_INTERCON AUD_MIC_IN_N

AUD_MIC_IN_P

AUD_MIC_IN_P_CONN

AUD_MIC_IN_P_CONN

AUD_MIC_IN_P_EMI

AUD_MIC_IN_P_EMI

AUD_MIC_P1

CLK_NB_OE_L

CLK_NB_OE_L - @m38a_lib.M38A

14B6 33B4

CPU_A20M_L

CPU_A20M_L - @m38a_lib.M38A

5C8 7C7 21C4

CPU_BSEL<0>

CPU_BSEL<0> - @m38a_lib.M38A

7B4 34B8

ENET_CTRL12

ENET_CTRL12 - @m38a_lib.M38A

CPU_BSEL<1>

CPU_BSEL<1> - @m38a_lib.M38A

7B4 34A8

CPU_BSEL<2>

CPU_BSEL<2> - @m38a_lib.M38A

7B4 34A8

ENET_CTRL25

ENET_CTRL25 - @m38a_lib.M38A

72C4

CPU_COMP<0>

CPU_COMP<0> - @m38a_lib.M38A

7B2

ENET_GATED_RST_L

ENET_GATED_RST_L

- @m38a_lib.M38A

7 2C5

CPU_COMP<1>

CPU_COMP<1> - @m38a_lib.M38A

7B2

- @m38a_lib.M38A

7 4A4

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

AUD_MIC_P1 - @m38a_lib.M38A

AUD_NC_40

7 3B4

CPU_COMP<2>

73C4 74A6

CPU_COMP<2> - @m38a_lib.M38A

ENET_LED_ACT_L

- @m38a_lib.M38A

CPU_DPSLP_L

CPU_DPSLP_L - @m38a_lib.M38A

7B3 21C4

ENET_LED_LINK_L

ENET_LED_LINK_L

CPU_FERR_L

CPU_FERR_L - @m38a_lib.M38A

7C7 21C2

ENET_LOM_DIS_L

ENET_LOM_DIS_L

73C2

7 3C3 74A4

CPU_GTLREF

- @m38a_lib.M38A

87B7 89A3

- @m38a_lib.M38A

87B7 89A3

FB_A_DQ<48>

- @m38a_lib.M38A

5A6 5D6 87B7 89A2

FB_A_DQ<49>

FB_A_DQ<49>

- @m38a_lib.M38A

87B7 89A3

FB_A_DQ<50>

FB_A_DQ<50>

- @m38a_lib.M38A

87B7 89A3

41C5 42D2

FB_A_DQ<51>

FB_A_DQ<51>

- @m38a_lib.M38A

87B7 89A3

6B7 42D3

FB_A_DQ<52>

FB_A_DQ<52>

- @m38a_lib.M38A

87B7 89A3

ENET_LED_LINK10_100_L

-

41C8

FB_A_DQ<53>

FB_A_DQ<53>

- @m38a_lib.M38A

87B7 89A3

41C8

FB_A_DQ<54>

FB_A_DQ<54>

- @m38a_lib.M38A

87B7 89A3

FB_A_DQ<55>

FB_A_DQ<55>

- @m38a_lib.M38A

87B7 89A3

FB_A_DQ<56>

FB_A_DQ<56>

- @m38a_lib.M38A

5A6 5D6 87B7 89A2

FB_A_DQ<57>

FB_A_DQ<57>

- @m38a_lib.M38A

87B7 89A3

41C8

FB_A_DQ<58>

FB_A_DQ<58>

- @m38a_lib.M38A

87B7 89B3

41C7

FB_A_DQ<59>

FB_A_DQ<59>

- @m38a_lib.M38A

87B7 89B3

FB_A_DQ<60>

- @m38a_lib.M38A

87B7 89B3

FB_A_DQ<61>

@m38a_lib.M38A

7B3 21C4 75C6

ENET_LED_LINK1000_L

-

41C8

@m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

CPU_GTLREF - @m38a_lib.M38A

5D4 7B4

ENET_MDI_N<0>

ENET_MDI_N<0>

- @m38a_lib.M38A

41C2 43C7

68C4

CPU_HS_ZH607

CPU_HS_ZH607

- @m38a_lib.M38A

9D4

ENET_MDI_N<1>

ENET_MDI_N<1>

- @m38a_lib.M38A

41C2 43C7

- @m38a_lib.M38A

87B7 89B3

68B4

CPU_HS_ZH608

CPU_HS_ZH608

- @m38a_lib.M38A

9D3 66A4 66A6 66B4 66B6

ENET_MDI_N<2>

ENET_MDI_N<2>

- @m38a_lib.M38A

41C2 43C7

FB_A_DQ<62>

- @m38a_lib.M38A

87B7 89A3

CPU_HS_ZH609

CPU_HS_ZH609

- @m38a_lib.M38A

9D3

ENET_MDI_N<3>

ENET_MDI_N<3>

- @m38a_lib.M38A

41C2 43B7

FB_A_DQ<63>

FB_A_DQ<63>

- @m38a_lib.M38A

87B7 89A3

CPU_HS_ZH610

CPU_HS_ZH610

- @m38a_lib.M38A

9D2

ENET_MDI_P<0>

ENET_MDI_P<0>

- @m38a_lib.M38A

41C2 43C7

FB_A_DQM_L<0>

FB_A_DQM_L<0>

- @m38a_lib.M38A

74B7 74C3 74D3

CPU_IGNNE_L

CPU_IGNNE_L - @m38a_lib.M38A

5C8 7C7 21C4

ENET_MDI_P<1>

ENET_MDI_P<1>

- @m38a_lib.M38A

41C2 43C7

FB_A_DQM_L<1>

FB_A_DQM_L<1>

- @m38a_lib.M38A

- @m38a_lib.M38A

74B7 74C4 74D4

CPU_INIT_L

CPU_INIT_L - @m38a_lib.M38A

5C8 7D6 21C4

ENET_MDI_P<2>

ENET_MDI_P<2>

- @m38a_lib.M38A

41C2 43C7

FB_A_DQM_L<2>

FB_A_DQM_L<2>

- @m38a_lib.M38A

87C5 89B6

- @m38a_lib.M38A

74B7 74C3 74D3

CPU_INTR

CPU_INTR - @m38a_lib.M38A

5C8 7C7 21C4

ENET_MDI_P<3>

ENET_MDI_P<3>

- @m38a_lib.M38A

41C2 43C7

FB_A_DQM_L<3>

FB_A_DQM_L<3>

- @m38a_lib.M38A

87C5 89B6

5C8 7C7 21C4

- @m38a_lib.M38A

74B7 74C4 74D4

AUD_PORT_A_L2

AUD_PORT_A_L2

- @m38a_lib.M38A

AUD_PORT_A_R1

AUD_PORT_A_R1

AUD_PORT_A_R2

AUD_PORT_A_R2

- @m38a_lib.M38A

AUD_PORT_E_DET_L

AUD_PORT_E_DET_L

- @m38a_lib.M38A

7 4B1

CPU_NMI

CPU_NMI - @m38a_lib.M38A

AUD_PORT_F_DET_L

AUD_PORT_F_DET_L

- @m38a_lib.M38A

7 4D4

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

AUD_SAMP_FS2

ENET_LED_LINK1000_L

47C2

AUD_PORT_A_L1

AUD_SAMP_FS2

L

CPU_DPRSTP_L

AUD_NC_43 - @m38a_lib.M38A

AUD_PORT_F_R1

ENET_LED_LINK10_100_

76D7

CPU_DCIN_SENSE_R

- @m38a_lib.M38A

- @m38a_lib.M38A

FB_A_DQ<47>

FB_A_DQ<48>

42B7 41C7 42C6

7 4B2

AUD_NC_40 - @m38a_lib.M38A

AUD_PORT_F_L1

ENET_LED_ACT_L

7B2

CPU_COMP<3> - @m38a_lib.M38A CPU_DCIN_SENSE

AUD_PORT_A_DET_L

AUD_SAMP_FS1

7B2

76C7

CPU_COMP<3>

- @m38a_lib.M38A

- @m38a_lib.M38A

ENET_RST_L - @m38a_lib.M38A

CPU_DCIN_SENSE

AUD_NC_43

AUD_SAMP_FS1

- @m38a_lib.M38A

CPU_DPRSTP_L

AUD_PORT_A_L1

AUD_PORT_F_R1

TP_ENET_CTRL12

CPU_DCIN_SENSE_R

73C2

FB_A_DQ<46>

FB_A_DQ<47> 41C7 42B8

@m38a_lib.M38A

73C4 74A6

47C2 7 3C3

AUD_PORT_A_DET_L

AUD_PORT_F_L1

33A4 34D8

73B7

- @m38a_lib.M38A

AUD_MIC_IN_N_CONN AUD_MIC_IN_N_EMI

AUD_MIC_IN_P

- @m38a_lib.M38A

73B8 74A5

- @m38a_lib.M38A

AUD_MIC_IN_N_EMI

-

@m38a_lib.M38A

73B7

- @m38a_lib.M38A

AUD_MIC_IN_N_CONN

73B4

73B4

- @m38a_lib.M38A

- @m38a_lib.M38A

AUD_LO_TYPE_EMI

AUD_MIC_IN_N

- @m38a_lib.M38A

AUD_SAMP_G1

AUD_SAMP_G1

AUD_SAMP_G2 AUD_SAMP_INL_N

AUD_SAMP_G2 - @m38a_lib.M38A AUD_SAMP_INL_N - @m38a_lib.M38A

- @m38a_lib.M38A

FB_A_DQ<60> FB_A_DQ<61> FB_A_DQ<62>

ENET_MDI_R_N<0>

ENET_MDI_R_N<0>

- @m38a_lib.M38A

5B4 43C6

CPU_PROCHOT_L

CPU_PROCHOT_L

7C6 59A8 59C7

ENET_MDI_R_N<1>

ENET_MDI_R_N<1>

- @m38a_lib.M38A

5B4 43C6

74C7

CPU_PSI_L

CPU_PSI_L - @m38a_lib.M38A

7A3 75C6

ENET_MDI_R_N<2>

ENET_MDI_R_N<2>

- @m38a_lib.M38A

5B4 43C6

FB_A_DQM_L<6>

FB_A_DQM_L<6>

- @m38a_lib.M38A

74C7

CPU_PWRGD

CPU_PWRGD - @m38a_lib.M38A

7B3 21C4

ENET_MDI_R_N<3>

ENET_MDI_R_N<3>

- @m38a_lib.M38A

5B4 43B6

FB_A_DQM_L<7>

FB_A_DQM_L<7>

- @m38a_lib.M38A

CPU_RCIN_L

CPU_RCIN_L - @m38a_lib.M38A

21C4

ENET_MDI_R_P<0>

ENET_MDI_R_P<0>

- @m38a_lib.M38A

5B4 43C6

FB_A_MA<0>

FB_A_MA<0> - @m38a_lib.M38A

87D5 89B5 89B8

5B4 43C6

FB_A_DQM_L<4> FB_A_DQM_L<5>

FB_A_DQM_L<4> FB_A_DQM_L<5>

- @m38a_lib.M38A - @m38a_lib.M38A

72A6 72C5

CPU_SENSE_I_R

76D7

ENET_MDI_R_P<1>

ENET_MDI_R_P<1>

- @m38a_lib.M38A

FB_A_MA<1>

FB_A_MA<1> - @m38a_lib.M38A

87D5 89B5 89B8

CPU_SMI_L

CPU_SMI_L - @m38a_lib.M38A

5C8 7C7 21C4

ENET_MDI_R_P<2>

ENET_MDI_R_P<2>

- @m38a_lib.M38A

5B4 43C6

FB_A_MA<2>

FB_A_MA<2> - @m38a_lib.M38A

87D5 89B5 89B8

72A6 72C5 72C5

CPU_STPCLK_L CPU_TEST1

CPU_STPCLK_L - @m38a_lib.M38A CPU_TEST1 - @m38a_lib.M38A

5C8 7C7 21C4 7B4

ENET_MDI_R_P<3> ENET_PU_VDDO_TTL0

ENET_MDI_R_P<3> - @m38a_lib.M38A ENET_PU_VDDO_TTL0 - @m38a_lib.M38A

5B4 43C6 41C5

FB_A_MA<3>

FB_A_MA<3> - @m38a_lib.M38A

5A6 5B6 5D6 87D5 89B5 89B8

- @m38a_lib.M38A

AUD_SAMP_INL_P

AUD_SAMP_INL_P

- @m38a_lib.M38A

72C5

CPU_TEST2

CPU_TEST2 - @m38a_lib.M38A

7B4

ENET_PU_VDDO_TTL1

ENET_PU_VDDO_TTL1

41C5

FB_A_MA<4>

FB_A_MA<4> - @m38a_lib.M38A

87D5 89B5 89B8

AUD_SAMP_INR_N

- @m38a_lib.M38A

72C5

CPU_THERMD_EXT_N

CPU_THERMD_EXT_N

- @m38a_lib.M38A

10B6

ENET_RSET

ENET_RSET - @m38a_lib.M38A

41C7

FB_A_MA<5>

FB_A_MA<5> - @m38a_lib.M38A

87D5 89B5 89B8

AUD_SAMP_INR_P

AUD_SAMP_INR_P

- @m38a_lib.M38A

72C5

CPU_THERMD_EXT_P

CPU_THERMD_EXT_P

- @m38a_lib.M38A

10B6

ENET_VPD_CLK

ENET_VPD_CLK - @m38a_lib.M38A

41A2 41C4

FB_A_MA<6>

FB_A_MA<6> - @m38a_lib.M38A

87D5 89B5 89B8

72C5

CPU_THERMD_N

CPU_THERMD_N

- @m38a_lib.M38A

7C6 10C6

ENET_VPD_DATA

ENET_VPD_DATA

41A2 41C4

FB_A_MA<7>

FB_A_MA<7> - @m38a_lib.M38A

87D5 89B5 89B8

68C1 74C5 74D7

CPU_THERMD_P

CPU_THERMD_P

- @m38a_lib.M38A

7C6 10C6

ENET_XTALI

ENET_XTALI - @m38a_lib.M38A

41B5

FB_A_MA<8>

FB_A_MA<8> - @m38a_lib.M38A

87D5 89B5 89B8

68C1 74C5 74D6 74D7

21C2

ENET_XTALO

ENET_XTALO - @m38a_lib.M38A

41B5

FB_A_MA<9>

FB_A_MA<9> - @m38a_lib.M38A

87D5 89B5 89B8

8B6 75A4

F0_GATESLOWDN

F0_GATESLOWDN

65D5

FB_A_MA<10>

FB_A_MA<10>

- @m38a_lib.M38A

87D5 89B5 89B8

- @m38a_lib.M38A

87D5 89B5 89B8

AUD_SAMP_SHDN_L

AUD_SENSE_A

- @m38a_lib.M38A

AUD_SENSE_A

- @m38a_lib.M38A

AUD_SENSE_B

AUD_SENSE_B

- @m38a_lib.M38A

CPU_THERMTRIP_R

CPU_THERMTRIP_R

AUD_SPDIFIN_JACK

AUD_SPDIFIN_JACK

- @m38a_lib.M38A

7 3D7

CPU_VCCSENSE_N

CPU_VCCSENSE_N

- @m38a_lib.M38A

AUD_SPDIF_GND_IN

AUD_SPDIF_GND_IN

- @m38a_lib.M38A

7 3C7

- @m38a_lib.M38A

AUD_SPDIF_GND_OUT

AUD_SPDIF_GND_OUT

AUD_SPDIF_IN

AUD_SPDIF_IN

AUD_SPDIF_OUT

AUD_SPDIF_OUT

AUD_SPDIF_OUT_CHIP

AUD_SPDIF_OUT_CHIP

AUD_SPKR_OUTL_N

AUD_SPKR_OUTL_N

- @m38a_lib.M38A

72C1 73D2

CPU_VID<4>

AUD_SPKR_OUTL_P

AUD_SPKR_OUTL_P

- @m38a_lib.M38A

72C1 73D2

CPU_VID<5>

AUD_SPKR_OUTR_N

AUD_SPKR_OUTR_N

- @m38a_lib.M38A

72C1 73D2

CPU_VID<6>

AUD_SPKR_OUTR_P

AUD_SPKR_OUTR_P

- @m38a_lib.M38A

72C1 73D2

CPU_XDP_CLK_N

AUD_TYPE_DET_EN

AUD_TYPE_DET_EN

- @m38a_lib.M38A

74B3

FSB_CLK_XDP_N

AUD_VREF_FILT

AUD_VREF_FILT

AUD_VREF_PORT_B

AUD_VREF_PORT_B

BAL_IN_COM

BAL_IN_COM - @m38a_lib.M38A

68C7 74A7

CRB_SV_DET

BAL_IN_L

BAL_IN_L - @m38a_lib.M38A

68C7 74A7

CRT_BLUE

BAL_IN_R

BAL_IN_R - @m38a_lib.M38A

68C7 74A7

BAT_1

BAT_1 - @m38a_lib.M38A

26C8

BAT_2

BAT_2 - @m38a_lib.M38A

26C8

CRT_BLUE_L - @m38a_lib.M38A

BEEP

BEEP - @m38a_lib.M38A

68C6

CRT_IREF - @m38a_lib.M38A

BIOS_REC

BIOS_REC - @m38a_lib.M38A

23A6 23C5

BOOT_LPC_SPI_L

BOOT_LPC_SPI_L

C8509_P1

C8509_P1 - @m38a_lib.M38A

CK410_27M_NONSPREAD

CK410_27M_NONSPREAD

CK410_27M_SPREAD

CK410_27M_SPREAD

CK410_CLK14P3M_TIMER

CK410_CLK14P3M_TIME R -

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A -

- @m38a_lib.M38A

- @m38a_lib.M38A

CK410_CPU0_P CK410_CPU1_N CK410_CPU1_P CK410_CPU2_ITP_SRC10  _N

CK410_CPU0_N

- @m38a_lib.M38A

CK410_CPU0_P

- @m38a_lib.M38A

CK410_CPU1_N

- @m38a_lib.M38A

CK410_CPU1_P

- @m38a_lib.M38A

CK410_CPU2_ITP_SRC1 0_N -

CPU_VCCSENSE_P

8B6 75A4

F0_RCFEEDBK

F0_RCFEEDBK - @m38a_lib.M38A

65C5

FB_A_MA<11>

FB_A_MA<11>

CPU_VID<0>

CPU_VID<0> - @m38a_lib.M38A

8B7 75C7

F0_VOLTAGE8R5

F0_VOLTAGE8R5

- @m38a_lib.M38A

65D6

FB_A_RAS_L<0>

FB_A_RAS_L<0>

- @m38a_lib.M38A

68C1 73D4

CPU_VID<1>

CPU_VID<1> - @m38a_lib.M38A

8B7 75C7

F1_GATESLOWDN

F1_GATESLOWDN

- @m38a_lib.M38A

65B5

FB_A_RAS_L<1>

FB_A_RAS_L<1>

- @m38a_lib.M38A

68D1 73B8

CPU_VID<2>

CPU_VID<2> - @m38a_lib.M38A

8B7 75C7

F1_RCFEEDBK

F1_RCFEEDBK - @m38a_lib.M38A

65B5

FB_A_RDQS<0>

FB_A_RDQS<0>

- @m38a_lib.M38A

5D6 87C5 89A8

CPU_VID<3>

CPU_VID<3> - @m38a_lib.M38A

8B7 75C7

F1_VOLTAGE8R5

F1_VOLTAGE8R5

- @m38a_lib.M38A

65B6

FB_A_RDQS<1>

FB_A_RDQS<1>

- @m38a_lib.M38A

5D6 87C5 89A8

CPU_VID<4> - @m38a_lib.M38A

8B7 75C7

F2_GATESLOWDN

F2_GATESLOWDN

- @m38a_lib.M38A

CPU_VID<5> - @m38a_lib.M38A

8B7 75C7

F2_RCFEEDBK

F2_RCFEEDBK - @m38a_lib.M38A

CPU_VID<6> - @m38a_lib.M38A

8B7 75D7

F2_VOLTAGE8R5

F2_VOLTAGE8R5

CPU_XDP_CLK_N

- @m38a_lib.M38A

11B3 34B3

FAN_0_OUT

FAN_0_OUT - @m38a_lib.M38A

- @m38a_lib.M38A

34B4 34C2

FAN_0_PWR

FAN_0_PWR - @m38a_lib.M38A

65C4

CPU_XDP_CLK_P

- @m38a_lib.M38A

11B3 34B3

FAN_1_OUT

FAN_1_OUT - @m38a_lib.M38A

FSB_CLK_XDP_P

- @m38a_lib.M38A

34B4 34C2

FAN_1_PWR

CRB_SV_DET - @m38a_lib.M38A

23B6 23C3

CRT_BLUE - @m38a_lib.M38A =PPVCORE_S0_NB

68D4

 _P

CK410_CPU2_ITP_SRC1 0_P -

66D4

FB_A_RDQS<2>

FB_A_RDQS<2>

- @m38a_lib.M38A

5D6 87C5 89A8

66C5

FB_A_RDQS<3>

FB_A_RDQS<3>

- @m38a_lib.M38A

5D6 87C5 89A8

66D5

FB_A_RDQS<4>

FB_A_RDQS<4>

- @m38a_lib.M38A

5D6 87C5 89A5

FB_A_RDQS<5>

FB_A_RDQS<5>

- @m38a_lib.M38A

5D6 87C5 89A5

FB_A_RDQS<6>

FB_A_RDQS<6>

- @m38a_lib.M38A

5D6 87C5 89A5

65B4

FB_A_RDQS<7>

FB_A_RDQS<7>

- @m38a_lib.M38A

5D6 87C5 89A5

FAN_1_PWR - @m38a_lib.M38A

65B3

FB_A_WDQS<0>

FB_A_WDQS<0>

- @m38a_lib.M38A

5B6 87C5 89A8

FAN_2_OUT

FAN_2_OUT - @m38a_lib.M38A

66C4

FB_A_WDQS<1>

FB_A_WDQS<1>

- @m38a_lib.M38A

5B6 87C5 89A8

13B5 19D4

FAN_2_PWR

FAN_2_PWR - @m38a_lib.M38A

66C3

FB_A_WDQS<2>

FB_A_WDQS<2>

- @m38a_lib.M38A

5B6 87C5 89A8

6D4 16C8 16D3 19B6 19D5

FAN_TACH0

FAN_TACH0 - @m38a_lib.M38A

65C7

FB_A_WDQS<3>

FB_A_WDQS<3>

- @m38a_lib.M38A

5B6 87C5 89A8

19D7

FAN_TACH1

FAN_TACH1 - @m38a_lib.M38A

65A7

FB_A_WDQS<4>

FB_A_WDQS<4>

- @m38a_lib.M38A

5A6 87C5 89A5

13B5 19D4

FAN_TACH2

FAN_TACH2 - @m38a_lib.M38A

66C7

FB_A_WDQS<5>

FB_A_WDQS<5>

- @m38a_lib.M38A

5A6 87C5 89A5

13B5 19D4

FB_A0_MF

FB_A0_MF - @m38a_lib.M38A

89A7

FB_A_WDQS<6>

FB_A_WDQS<6>

- @m38a_lib.M38A

5A6 87C5 89A5

CRT_GREEN_L - @m38a_lib.M38A

13B5 19D4

FB_A0_SEN

FB_A0_SEN - @m38a_lib.M38A

89A7

FB_A_WDQS<7>

FB_A_WDQS<7>

- @m38a_lib.M38A

5A6 87C5 89A5

22B3 58C7 60C4

CRT_GREEN - @m38a_lib.M38A

13B5 19D4

FB_A0_VREF0

FB_A0_VREF0 - @m38a_lib.M38A

89C7

FB_A_WE_L<0>

FB_A_WE_L<0>

- @m38a_lib.M38A

5B6 87B5 89A8

85C5

PP2V5_S0_NB_VCCA_CRT DAC -

17D6 19D4

FB_A0_VREF1

FB_A0_VREF1 - @m38a_lib.M38A

89C7

FB_A_WE_L<1>

FB_A_WE_L<1>

- @m38a_lib.M38A

5A6 87B5 89A5

FB_A0_ZQ

FB_A0_ZQ - @m38a_lib.M38A

89A7

FB_B0_MF

FB_B0_MF - @m38a_lib.M38A

90A7

FB_A1_MF

FB_B0_SEN - @m38a_lib.M38A

90A7

68C4

CPU_XDP_CLK_P

68C1 74A2

34A4 92C7

- @m38a_lib.M38A

@m38a_lib.M38A

34A4 92C5

13B5 19D4

FB_A1_MF - @m38a_lib.M38A

89A4

CRT_RED_L - @m38a_lib.M38A

13B5 19D4

FB_A1_SEN

FB_A1_SEN - @m38a_lib.M38A

89A4

FB_B0_VREF0

- @m38a_lib.M38A

PP1V05_S0 - @m38a_lib.M38A

6D6 34A8 34B8 34C7 81C2

FB_A1_VREF0

FB_A1_VREF0 - @m38a_lib.M38A

89C4

FB_B0_VREF1

FB_B0_VREF1

- @m38a_lib.M38A

5D4 6D4 7B5 7B7 7D5

FB_A1_VREF1

FB_A1_VREF1 - @m38a_lib.M38A

89C4

FB_B0_ZQ

FB_B0_ZQ - @m38a_lib.M38A

90A7

8C7 9C8 9C8 11B3 11C5

FB_A1_ZQ

FB_A1_ZQ - @m38a_lib.M38A

89A4

FB_B1_MF

FB_B1_MF - @m38a_lib.M38A

90A4

6D4 24D3 25D3

FB_A_BA<0>

FB_A_BA<0> - @m38a_lib.M38A

87D5 89A5 89A8

FB_B1_SEN

FB_B1_SEN - @m38a_lib.M38A

90A4

6D4 21C1 21C1 24C3 25C3

FB_A_BA<1>

FB_A_BA<1> - @m38a_lib.M38A

87D5 89A5 89A8

FB_A_BA<2> - @m38a_lib.M38A

87D5 89A5 89A8 5B6 87B5 89A8

33A4 34D6

=PP1V05_S0_CPU

- @m38a_lib.M38A

33C4 34B6

=PPVCORE_S0_SB

33C4 34B6

=PP1V05_S0_SB_CPU_IO

33C4 34B6

@m38a_lib.M38A

33C4 34B6

=PP1V05_S0_NB_VTT

33C4 34B6

=PP1V05_S0_FSB_NB - @m38a_lib.M38A

33C4 34B6

PREAD_P

- @m38a_lib.M38A @m38a_lib.M38A

CK410_FSA

CK410_FSA - @m38a_lib.M38A

CK410_FSB_TEST_MODE

CK410_FSB_TEST_MODE

CK410_FSC

CK410_FSC - @m38a_lib.M38A

-

- @m38a_lib.M38A

FB_B1_VREF1

- @m38a_lib.M38A

- @m38a_lib.M38A

FB_B1_ZQ

FB_B1_ZQ - @m38a_lib.M38A

90A4

FB_A_CAS_L<1>

- @m38a_lib.M38A

5A6 87B5 89A5

FB_B_BA<0>

FB_B_BA<0> - @m38a_lib.M38A

87D1 90A5 90A8

5B6 87B5 89B8

FB_B_BA<1>

FB_B_BA<1> - @m38a_lib.M38A

87D1 90A5 90A8

17D6 19D4

FB_A_CKE<1>

FB_A_CKE<1> - @m38a_lib.M38A

5A6 87B5 89B5

FB_B_BA<2>

FB_B_BA<2> - @m38a_lib.M38A

87D1 90A5 90A8

CK410_IREF

CK410_IREF - @m38a_lib.M38A

CK410_LVDS_N

CK410_LVDS_N

CK410_LVDS_P

CK410_LVDS_P

- @m38a_lib.M38A

TP_CK410_LVDS_N

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_CK410_LVDS_P

- @m38a_lib.M38A

FB_A_CLK_N<0>

- @m38a_lib.M38A

FB_A_CLK_N<1>

- @m38a_lib.M38A

FB_A_CLK_P<0>

- @m38a_lib.M38A

FB_A_CLK_P<1>

- @m38a_lib.M38A

6D6 34A8 34B8 34C7 81C2

FB_A_CLK_N<1>

CRT_RED_L - @m38a_lib.M38A

13B5 19D4

FB_A_CLK_P<0>

13B5 19D4

FB_A_CLK_P<1>

CRT_IREF - @m38a_lib.M38A

13B5 19D4

FB_A_CS_L<0>

FB_A_CS_L<0> - @m38a_lib.M38A

CRT_GREEN_L - @m38a_lib.M38A CRT_GREEN - @m38a_lib.M38A

5B6 87B5 89B8

FB_B_CAS_L<0>

5A6 87B5 89B5

FB_B_CAS_L<1>

5B6 87B5 89B8

FB_B_CKE<0>

FB_B_CAS_L<0> FB_B_CAS_L<1>

- @m38a_lib.M38A - @m38a_lib.M38A

90C4 90C4

5B5 87B1 90A8 5A5 87B1 90A5

FB_B_CKE<0>

- @m38a_lib.M38A

5B5 87B1 90B8

5A6 87B5 89B5

FB_B_CKE<1>

FB_B_CKE<1>

- @m38a_lib.M38A

5A5 87B1 90B5

5B6 87B5 89B8

FB_B_CLK_N<0>

FB_B_CLK_N<0>

- @m38a_lib.M38A

5B5 87B1 90B8

13B5 19D4

FB_A_CS_L<1>

FB_A_CS_L<1> - @m38a_lib.M38A

13B5 19D4

FB_A_DQ<0>

FB_A_DQ<0> - @m38a_lib.M38A

5B6 5D6 87D7 89B6

FB_B_CLK_P<0>

FB_B_CLK_P<0>

CRT_BLUE_L - @m38a_lib.M38A

13B5 19D4

FB_A_DQ<1>

FB_A_DQ<1> - @m38a_lib.M38A

87D7 89B6

FB_B_CLK_P<1>

FB_B_CLK_P<1>

34A8 34D4

=PPVCORE_S0_SB

- @m38a_lib.M38A

6D4 24D3 25D3

FB_A_DQ<2>

FB_A_DQ<2> - @m38a_lib.M38A

87D7 89B6

FB_B_CS_L<0>

FB_B_CS_L<0>

- @m38a_lib.M38A

33B6

=PPVCORE_S0_NB

- @m38a_lib.M38A

6D4 16C8 16D3 19B6 19D5

FB_A_DQ<3>

FB_A_DQ<3> - @m38a_lib.M38A

87D7 89B6

FB_B_CS_L<1>

FB_B_CS_L<1>

- @m38a_lib.M38A

19D7

FB_A_DQ<4>

FB_A_DQ<4> - @m38a_lib.M38A

87D7 89B6

FB_B_DQ<0>

FB_B_DQ<0> - @m38a_lib.M38A

5B5 5D6 87D3 90B6

FB_A_DQ<5>

FB_A_DQ<5> - @m38a_lib.M38A

87D7 89B6

FB_B_DQ<1>

FB_B_DQ<1> - @m38a_lib.M38A

87D3 90B6

FB_A_DQ<6>

FB_A_DQ<6> - @m38a_lib.M38A

87D7 89B6

FB_B_DQ<2>

FB_B_DQ<2> - @m38a_lib.M38A

87D3 90B6

FB_A_DQ<7>

FB_A_DQ<7> - @m38a_lib.M38A

87D7 89B6

FB_B_DQ<3>

FB_B_DQ<3> - @m38a_lib.M38A

87D3 90B6

33B4 34A6 34A4

=PP1V05_S0_SB_CPU_IO

33B4 34A6

@m38a_lib.M38A

34A4

=PP1V05_S0_NB_VTT

-

@m38a_lib.M38A

6D4 21C1 21C1 24C3 25C3 6D4

17D3

19B8 19D7

5A6 87B5 89B5

FB_B_CLK_N<1>

FB_B_CLK_N<1>

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

5A5 87B1 90B5 5B5 87B1 90B8 5A5 87B1 90B5 5B5 87B1 90B8 5A5 87B1 90B5

33B6 34C6

=PP1V05_S0_NB

FB_A_DQ<8> - @m38a_lib.M38A

5A6 5D6 87D7 89A6

FB_B_DQ<4>

FB_B_DQ<4> - @m38a_lib.M38A

87D3 90B6

- @m38a_lib.M38A

33B6 34C6

=PP1V05_S0_FSB_NB - @m38a_lib.M38A

5D4 6D4 12A7 12B7 12C2

FB_A_DQ<9>

FB_A_DQ<9> - @m38a_lib.M38A

87D7 89A6

FB_B_DQ<5>

FB_B_DQ<5> - @m38a_lib.M38A

87D3 90B6

CK410_PCI3_CLK

CK410_PCI3_CLK

- @m38a_lib.M38A

33B6 34C6

19D7

FB_A_DQ<10>

FB_A_DQ<10> - @m38a_lib.M38A

87D7 89A6

FB_B_DQ<6>

FB_B_DQ<6> - @m38a_lib.M38A

87D3 90B6

CK410_PCI4_CLK

CK410_PCI4_CLK

- @m38a_lib.M38A

33B6 34C6

=PP1V05_S0_CPU

5D4 6D4 7B5 7B7 7D5

FB_A_DQ<11>

FB_A_DQ<11> - @m38a_lib.M38A

87D7 89A6

FB_B_DQ<7>

FB_B_DQ<7> - @m38a_lib.M38A

87D3 90B6

CK410_PCI2_CLK

CK410_PCI2_CLK

CK410_PCI5_FCTSEL1 CK410_PCIF0_CLK

- @m38a_lib.M38A

FB_A_CLK_N<0>

PP1V05_S0 - @m38a_lib.M38A CRT_RED - @m38a_lib.M38A

@m38a_lib.M38A

CK410_PCI1_CLK

FB_B1_VREF0

FB_B1_VREF1

FB_A_CAS_L<0>

FB_A_CKE<0> - @m38a_lib.M38A

FB_A_CAS_L<0>

FB_B1_VREF0

90C7

FB_A_CKE<0>

19B8 19D7

CK410_PCI5_FCTSEL1 CK410_PCIF0_CLK

- @m38a_lib.M38A

- @m38a_lib.M38A

CK410_PCIF1_ITP_EN

CK410_PCIF1_ITP_EN

CK410_PD_VTT_PWRGD_L

CK410_PD_VTT_PWRGD_ L -

- @m38a_lib.M38A

CRT_DDC_CLK

CRT_DDC_CLK - @m38a_lib.M38A

CRT_DDC_DATA

CRT_DDC_DATA

33B8 34B6

TP_CRT_DDC_CLK

26A8 33A4

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_CRT_DDC_DATA - @m38a_lib.M38A

- @m38a_lib.M38A

33B6 34D6 33B8 34B6

@m38a_lib.M38A VR_PWRGD_CK410_L

- @m38a_lib.M38A

- @m38a_lib.M38A

6D4 19D7

FB_A_DQ<8>

7D5

8C7 9C8 9C8 11B3 11C5

FB_A_DQ<12>

FB_A_DQ<12> - @m38a_lib.M38A

87D7 89A6

FB_B_DQ<8>

FB_B_DQ<8> - @m38a_lib.M38A

5A5 5D6 87D3 90A6

13B5 19C4

FB_A_DQ<13>

FB_A_DQ<13> - @m38a_lib.M38A

87D7 89A6

FB_B_DQ<9>

FB_B_DQ<9> - @m38a_lib.M38A

87D3 90A6

19C5

FB_A_DQ<14>

FB_A_DQ<14> - @m38a_lib.M38A

87D7 89A6

FB_B_DQ<10>

FB_B_DQ<10>

- @m38a_lib.M38A

87D3 90A6

13B5 19C4

FB_A_DQ<15>

FB_A_DQ<15> - @m38a_lib.M38A

87D7 89A6

FB_B_DQ<11>

FB_B_DQ<11>

- @m38a_lib.M38A

87D3 90A6

FB_A_DQ<16>

FB_A_DQ<16> - @m38a_lib.M38A

5A6 5D6 87D7 89A6

FB_B_DQ<12>

FB_B_DQ<12>

- @m38a_lib.M38A

87D3 90A6

FB_B_DQ<13>

FB_B_DQ<13>

FB_B_DQ<14>

19C5

26A7 75C6

DEBUG_RST_L

DEBUG_RST_L - @m38a_lib.M38A

6B7 60C4

FB_A_DQ<17>

FB_A_DQ<17> - @m38a_lib.M38A

87D7 89A6

- @m38a_lib.M38A

87D3 90A6

33A4 34C6

DMI_IRCOMP_R

DMI_IRCOMP_R

- @m38a_lib.M38A

22C2

FB_A_DQ<18>

FB_A_DQ<18> - @m38a_lib.M38A

87C7 89A6

FB_B_DQ<14>

- @m38a_lib.M38A

87D3 90A6

33B4 34A6

DMI_N2S_N<0>

DMI_N2S_N<0>

- @m38a_lib.M38A

5B8 14B4 22D2

FB_A_DQ<19>

FB_A_DQ<19> - @m38a_lib.M38A

87C7 89A6

FB_B_DQ<15>

FB_B_DQ<15>

- @m38a_lib.M38A

87D3 90A6

DMI_N2S_N<1>

DMI_N2S_N<1>

- @m38a_lib.M38A

14B4 22D2

FB_A_DQ<20>

FB_A_DQ<20> - @m38a_lib.M38A

87C7 89A6

FB_B_DQ<16>

FB_B_DQ<16>

- @m38a_lib.M38A

5A5 5D6 87D3 90A6

DMI_N2S_N<2>

DMI_N2S_N<2>

- @m38a_lib.M38A

14B4 22D2

FB_A_DQ<21>

FB_A_DQ<21> - @m38a_lib.M38A

87C7 89A6

FB_B_DQ<17>

FB_B_DQ<17>

- @m38a_lib.M38A

87D3 90A6

CK410_REF1_FCTSEL0

CK410_REF1_FCTSEL0

CK410_SRC1_N

CK410_SRC1_N

- @m38a_lib.M38A

CK410_SRC1_P

CK410_SRC1_P

- @m38a_lib.M38A

33B4 34A6

CK410_SRC2_N

CK410_SRC2_N

- @m38a_lib.M38A

33B4 34A6

B

90C7

FB_A_CAS_L<1>

17D3

33A4 34A6

33C6 34A8

FB_B0_VREF0

19D7

33A4 34A6 34B8 34C4

FB_B0_SEN

5D4 6D4 12A7 12B7 12C2

6D4

@m38a_lib.M38A

CK410_DOT96_27M_NON SPREAD_P CK410_DOT96_27M_SPR EAD_N @m38a_lib.M38A

CK410_PCI1_CLK

7D5

FB_A_BA<2> -

PP2V5_S0_NB_VCCA_CRT DAC -

@m38a_lib.M38A

AD_N

- @m38a_lib.M38A

CRT_RED - @m38a_lib.M38A 91C3 92C3

@m38a_lib.M38A

CK410_DOT96_27M_NONS CK410_DOT96_27M_SPRE

5B6 87B5 89A8 5A6 87B5 89A5

65C4

@m38a_lib.M38A

CK410_CPU2_ITP_SRC10

- @m38a_lib.M38A

CPU_VCCSENSE_P

@m38a_lib.M38A CK410_CPU0_N

- @m38a_lib.M38A

73A3

@m38a_lib.M38A GPU_GPIO_16

- @m38a_lib.M38A

- @m38a_lib.M38A

C

87C5 89B3 87C5 89B3 87C5 89B3 87C5 89B3

72A6 72C5

CPU_SENSE_I_R

D

87D5 89B6

72A6 72C5

- @m38a_lib.M38A

1

87C5 89B6

AUD_SAMP_INR_N AUD_SAMP_SHDN_L

A

 

5

CK410_SRC2_P

AUD_LI_L_JACK

AUD_LO_TIP_EMI

B

- @m38a_lib.M38A - @m38a_lib.M38A

 

68C7 74C5

AUD_LI_R

AUD_LO_L_EMI

C

- @m38a_lib.M38A

- @m38a_lib.M38A

AUD_LI_DET_JACK AUD_LI_GND_EMI

AUD_LI_L_EMI

D

7 AUD_GPIO_1 - @m38a_lib.M38A

A

101

8

 

7

6

 

5

 

4

 

3

 

2

 

1

 

8

D

C

6

 

- @m38a_lib.M38A

87C3 90A6

FSB_BREQ0_L

FB_B_DQ<19>

FB_B_DQ<19>

- @m38a_lib.M38A

87C3 90A6

FSB_CLK_CPU_N

FB_B_DQ<20>

FB_B_DQ<20>

- @m38a_lib.M38A

87C3 90A6

FSB_CLK_CPU_P

FSB_CLK_CPU_P

FB_B_DQ<21>

FB_B_DQ<21>

- @m38a_lib.M38A

87C3 90A6

FSB_CLK_NB_N

FSB_CLK_NB_N

- @m38a_lib.M38A

5C7 12A6 34B4 34C2

FB_B_DQ<22>

FB_B_DQ<22>

- @m38a_lib.M38A

87C3 90A6

FSB_CLK_NB_P

FSB_CLK_NB_P

- @m38a_lib.M38A

5C7 12A6 34B4 34C2

FB_B_DQ<23>

FB_B_DQ<23>

- @m38a_lib.M38A

87C3 90A6

FSB_CPURST_L

FSB_CPURST_L

- @m38a_lib.M38A

5C8 7D6 11B5 12C4

FB_B_DQ<24>

FB_B_DQ<24>

- @m38a_lib.M38A

5A5 5C6 87C3 90A6

FSB_DBSY_L

FSB_DBSY_L - @m38a_lib.M38A

5C7 7D6 12B4

FB_B_DQ<25>

FB_B_DQ<25>

- @m38a_lib.M38A

87C3 90A6

FSB_DEFER_L

FSB_DEFER_L - @m38a_lib.M38A

7D6 12B4

FB_B_DQ<26>

FB_B_DQ<26>

- @m38a_lib.M38A

87C3 90A6

FSB_DINV_L<0>

FSB_DINV_L<0>

- @m38a_lib.M38A

5D7 5D8 7C4 12B4

FB_B_DQ<27>

FB_B_DQ<27>

- @m38a_lib.M38A

87C3 90B6

FSB_DINV_L<1>

FSB_DINV_L<1>

- @m38a_lib.M38A

FB_B_DQ<28>

FB_B_DQ<28>

- @m38a_lib.M38A

87C3 90B6

FSB_DINV_L<2>

FSB_DINV_L<2>

- @m38a_lib.M38A

FB_B_DQ<29>

FB_B_DQ<29>

- @m38a_lib.M38A

87C3 90B6

FSB_DINV_L<3>

FSB_DINV_L<3>

- @m38a_lib.M38A

FB_B_DQ<30>

FB_B_DQ<30>

- @m38a_lib.M38A

87C3 90B6

FSB_DPWR_L

FSB_DPWR_L - @m38a_lib.M38A

FB_B_DQ<31>

FB_B_DQ<31>

- @m38a_lib.M38A

87C3 90A6

FSB_DRDY_L

FSB_DRDY_L - @m38a_lib.M38A

7D6 12B4

FB_B_DQ<32>

FB_B_DQ<32>

- @m38a_lib.M38A

5A5 5C6 87C3 90B2

FSB_DSTBN_L<0>

FSB_DSTBN_L<0>

- @m38a_lib.M38A

FB_B_DQ<33>

FB_B_DQ<33>

- @m38a_lib.M38A

87C3 90B3

FSB_DSTBN_L<1>

FSB_DSTBN_L<1>

- @m38a_lib.M38A

FB_B_DQ<34>

FB_B_DQ<34>

- @m38a_lib.M38A

87C3 90B3

FSB_DSTBN_L<2>

FSB_DSTBN_L<2>

FB_B_DQ<35>

FB_B_DQ<35>

- @m38a_lib.M38A

87C3 90B3

FSB_DSTBN_L<3>

FSB_DSTBN_L<3>

FB_B_DQ<36>

FB_B_DQ<36>

- @m38a_lib.M38A

87C3 90B3

FSB_DSTBP_L<0>

FSB_DSTBP_L<0>

- @m38a_lib.M38A

FB_B_DQ<37>

FB_B_DQ<37>

- @m38a_lib.M38A

87C3 90B3

FSB_DSTBP_L<1>

FSB_DSTBP_L<1>

- @m38a_lib.M38A

FB_B_DQ<38>

FB_B_DQ<38>

- @m38a_lib.M38A

87C3 90B3

FSB_DSTBP_L<2>

FSB_DSTBP_L<2>

- @m38a_lib.M38A

FB_B_DQ<39>

FB_B_DQ<39>

- @m38a_lib.M38A

87C3 90B3

FSB_DSTBP_L<3>

FSB_DSTBP_L<3>

- @m38a_lib.M38A

FB_B_DQ<40> FB_B_DQ<41>

FB_B_DQ<40> FB_B_DQ<41>

- @m38a_lib.M38A - @m38a_lib.M38A

5A5 5C6 87C3 90A2 87C3 90A3

FSB_D_L<0> FSB_D_L<1>

FSB_D_L<0> - @m38a_lib.M38A FSB_D_L<1> - @m38a_lib.M38A

FB_B_DQ<42>

FB_B_DQ<42>

- @m38a_lib.M38A

87C3 90A3

FSB_D_L<2>

FSB_D_L<2> - @m38a_lib.M38A

FB_B_DQ<43>

FB_B_DQ<43>

- @m38a_lib.M38A

87C3 90A3

FSB_D_L<3>

FB_B_DQ<44>

FB_B_DQ<44>

- @m38a_lib.M38A

87B3 90A3

FB_B_DQ<45>

FB_B_DQ<45>

- @m38a_lib.M38A

87B3 90A3

FB_B_DQ<46>

FB_B_DQ<46>

- @m38a_lib.M38A

87B3 90A3

FB_B_DQ<47>

FB_B_DQ<47>

- @m38a_lib.M38A

FB_B_DQ<48>

FB_B_DQ<48>

FB_B_DQ<49>

FSB_BREQ0_L - @m38a_lib.M38A FSB_CLK_CPU_N

- @m38a_lib.M38A - @m38a_lib.M38A

 

5

5C7 7D6 12C4

FW_C_TPA_N

5C8 7C6 34B4 34C2

TP_FW_C_TPA_N

5C8 7C6 34B4 34C2

 

4 FW_C_TPA_N - @m38a_lib.M38A - @m38a_lib.M38A

46B7

GPU_GPIO_8

GPU_GPIO_8 - @m38a_lib.M38A

88C5 91D3

GPU_GPIO_9

GPU_GPIO_9 - @m38a_lib.M38A

88C5 91C3

GPU_GPIO_10

88C3 91C3

GPU_GPIO_11

GPU_GPIO_11

- @m38a_lib.M38A

88B5 91C3

44C3 46A8

GPU_GPIO_12

GPU_GPIO_12

- @m38a_lib.M38A

88C5 91C3

46A7

GPU_GPIO_13

GPU_GPIO_13

- @m38a_lib.M38A

88C5 91C3

44C3 46A8

GPU_GPIO_14

GPU_GPIO_14

- @m38a_lib.M38A

88C1 91C3

44C4 46B8

TP_FW_C_TPBIAS

46B7

FW_C_TPB_N - @m38a_lib.M38A TP_FW_C_TPB_N

FW_C_TPB_N

- @m38a_lib.M38A

- @m38a_lib.M38A

NC_GPU_GPIO_10

- @m38a_lib.M38A

88C5

FW_C_TPB_P

FW_C_TPB_P - @m38a_lib.M38A

5D7 5D8 7C2 12B4

FW_PC0

FW_PC0 - @m38a_lib.M38A

5D7 5D8 7B2 12B4

FW_PC1

FW_PC1 - @m38a_lib.M38A

5C7 7B3 12B4

FW_PC2

FW_PC2 - @m38a_lib.M38A

44B3

FW_PORT0_TPA_FL_N

FW_PORT0_TPA_FL_N

- @m38a_lib.M38A

46C2

5D7 5D8 7C4 12B4

FW_PORT0_TPA_FL_P

FW_PORT0_TPA_FL_P

- @m38a_lib.M38A

46C2

GPU_GPIO_18

GPU_GPIO_18

- @m38a_lib.M38A

91D5 95B4

5D7 5D8 7B4 12B4

FW_PORT0_TPB_FL_N

FW_PORT0_TPB_FL_N

- @m38a_lib.M38A

46C2

GPU_GPIO_19

GPU_GPIO_19

- @m38a_lib.M38A

91D5 95B4

- @m38a_lib.M38A

5D7 5D8 7C2 12B4

FW_PORT0_TPB_FL_P

FW_PORT0_TPB_FL_P

- @m38a_lib.M38A

46C2

GPU_GPIO_20

GPU_GPIO_20

- @m38a_lib.M38A

91D5 95B4

- @m38a_lib.M38A

5D7 5D8 7B2 12B4

FW_PORT1_TPA_FL_N

FW_PORT1_TPA_FL_N

- @m38a_lib.M38A

46B2

GPU_GPIO_21

GPU_GPIO_21

- @m38a_lib.M38A

91D5 95B4

FW_PORT1_TPA_FL_P

5D7 5D8 7B4 12B4

TP_FW_C_TPB_P

5D7 5D8 7C4 12B4

- @m38a_lib.M38A

46A7

TP_GPU_GPIO_14

44B3

GPU_GPIO_15

GPU_GPIO_15

GPU_GPIO_17

GPU_GPIO_17

44B3

- @m38a_lib.M38A

- @m38a_lib.M38A

GPU_VCORE_LOW

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_GPU_GPIO_17

- @m38a_lib.M38A

88C3 88B4 91C3 88B5 88C1 91C3 88C3

FW_PORT1_TPA_FL_P

- @m38a_lib.M38A

46B2

GPU_GPIO_22

GPU_GPIO_22

- @m38a_lib.M38A

91D5 95B4

FW_PORT1_TPB_FL_N

FW_PORT1_TPB_FL_N

- @m38a_lib.M38A

46B2

GPU_GPIO_23

GPU_GPIO_23

- @m38a_lib.M38A

91D5 95B4

5D7 5D8 7C2 12B4

FW_PORT1_TPB_FL_P

FW_PORT1_TPB_FL_P

- @m38a_lib.M38A

46B2

GPU_GPIO_24

GPU_GPIO_24

- @m38a_lib.M38A

88B5 91D5

5D7 5D8 7B2 12B4

FW_R0

FW_R0 - @m38a_lib.M38A

44C4

GPU_GPIO_25

GPU_GPIO_25

- @m38a_lib.M38A

91D5 95C4

FW_R1 FW_RESET_L

FW_R1 - @m38a_lib.M38A FW_RESET_L - @m38a_lib.M38A

44C4 44C2 44C3

GPU_GPIO_26 GPU_GPIO_27

GPU_GPIO_26 GPU_GPIO_27

- @m38a_lib.M38A - @m38a_lib.M38A

91D5 95C4 88B5 91D5

7C4 12D6

FW_ROM_CLK

FW_ROM_CLK - @m38a_lib.M38A

44B4

GPU_GPIO_28

GPU_GPIO_28

- @m38a_lib.M38A

88B5 91D5

FSB_D_L<3> - @m38a_lib.M38A

7C4 12D6

FW_SE

FW_SE - @m38a_lib.M38A

44B3

GPU_GPIO_29

GPU_GPIO_29

- @m38a_lib.M38A

88B5 91C5

FSB_D_L<4>

FSB_D_L<4> - @m38a_lib.M38A

7C4 12D6

FW_SM

FW_SM - @m38a_lib.M38A

44B3

GPU_GPIO_30

GPU_GPIO_30

- @m38a_lib.M38A

91C5 95C4

FSB_D_L<5>

FSB_D_L<5> - @m38a_lib.M38A

7C4 12D6

FW_TEST

FW_TEST - @m38a_lib.M38A

44B3

GPU_GPIO_31

GPU_GPIO_31

- @m38a_lib.M38A

91C5 95C4

FSB_D_L<6>

FSB_D_L<6> - @m38a_lib.M38A

7C4 12D6

FW_TPA_C<0>

FW_TPA_C<0> - @m38a_lib.M38A

46B8

GPU_GPIO_32

GPU_GPIO_32

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<7>

FSB_D_L<7> - @m38a_lib.M38A

7C4 12D6

FW_TPA_C<1>

FW_TPA_C<1> - @m38a_lib.M38A

46B7

GPU_GPIO_33

GPU_GPIO_33

- @m38a_lib.M38A

- @m38a_lib.M38A

5A5 5C6 87B3 90A2

FSB_D_L<8>

FSB_D_L<8> - @m38a_lib.M38A

7C4 12D6

FW_VP

FW_VP - @m38a_lib.M38A

46D4

GPU_GPIO_34

GPU_GPIO_34

- @m38a_lib.M38A

FB_B_DQ<49>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<9>

FSB_D_L<9> - @m38a_lib.M38A

7C4 12D6

FW_XTAL_X0

FW_XTAL_X0 - @m38a_lib.M38A

44D2 44D3

GPU_H2SYNC

GPU_H2SYNC - @m38a_lib.M38A

93B3 97A4

FB_B_DQ<50>

FB_B_DQ<50>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<10>

FSB_D_L<10> - @m38a_lib.M38A

7C4 12D6

FW_XTAL_XI

FW_XTAL_XI - @m38a_lib.M38A

44D2 44D3

GPU_HPD

GPU_HPD - @m38a_lib.M38A

93A5 97C1

FB_B_DQ<51>

FB_B_DQ<51>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<11>

FSB_D_L<11> - @m38a_lib.M38A

7C4 12D6

FW_XTAL_XR

FW_XTAL_XR - @m38a_lib.M38A

44D2

GPU_HSYNC_BUF

GPU_HSYNC_BUF

FB_B_DQ<52>

FB_B_DQ<52>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<12>

FSB_D_L<12> - @m38a_lib.M38A

7C4 12D6

GATE_3V3_S3

GATE_3V3_S3 - @m38a_lib.M38A

83B4

GPU_MEMTEST

GPU_MEMTEST

- @m38a_lib.M38A

87A3

FB_B_DQ<53>

FB_B_DQ<53>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<13>

FSB_D_L<13> - @m38a_lib.M38A

7C4 12C6

GATE_5V_S3

83C4

GPU_MVREFD0

GPU_MVREFD0

- @m38a_lib.M38A

87B7

FB_B_DQ<54>

FB_B_DQ<54>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<14>

FSB_D_L<14> - @m38a_lib.M38A

7C4 12C6

GND_AUDIO

GND_AUDIO - @m38a_lib.M38A

6C2 74D2

GPU_MVREFD1

GPU_MVREFD1

- @m38a_lib.M38A

87B3

FB_B_DQ<55>

FB_B_DQ<55>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<15>

FSB_D_L<15> - @m38a_lib.M38A

7C4 12C6

GND_AUDIO_CODEC

GND_AUDIO_CODEC

68A5 68B7 68D2 72B8 72C8

GPU_MVREFS0

GPU_MVREFS0

- @m38a_lib.M38A

87B7

FB_B_DQ<56>

FB_B_DQ<56>

- @m38a_lib.M38A

5A5 5C6 87B3 90A2

FSB_D_L<16>

FSB_D_L<16> - @m38a_lib.M38A

5D7 5D8 7C4 12C6

GPU_MVREFS1

- @m38a_lib.M38A

87B3

FB_B_DQ<57>

FB_B_DQ<57>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<17>

FSB_D_L<17> - @m38a_lib.M38A

7C4 12C6

FB_B_DQ<58>

FB_B_DQ<58>

- @m38a_lib.M38A

87B3 90B3

FSB_D_L<18>

FSB_D_L<18> - @m38a_lib.M38A

7B4 12C6

FB_B_DQ<59>

FB_B_DQ<59>

- @m38a_lib.M38A

87B3 90B3

FSB_D_L<19>

FSB_D_L<19> - @m38a_lib.M38A

7B4 12C6

GND_AUDIO_CODEC_EMI1

GND_AUDIO_CODEC_EMI1

FB_B_DQ<60>

FB_B_DQ<60>

- @m38a_lib.M38A

87B3 90B3

FSB_D_L<20>

FSB_D_L<20> - @m38a_lib.M38A

7B4 12C6

FB_B_DQ<61>

FB_B_DQ<61>

- @m38a_lib.M38A

87B3 90B3

FSB_D_L<21>

FSB_D_L<21> - @m38a_lib.M38A

7B4 12C6

GND_AUDIO_MIC_CONN

GND_AUDIO_MIC_CONN

GND_AUDIO_SPKRAMP

GND_AUDIO_SPKRAMP

5D7 5D8 7B4 12B4

GATE_5V_S3 - @m38a_lib.M38A - @m38a_lib.M38A

73A8 73D4 74A2 74A3 74A5 74A7 74B5 74B7 74C1 74C3 74C5 74C6 74D1 74D5 -

73A7

@m38a_lib.M38A - @m38a_lib.M38A

47C2 73C2

GPU_MVREFS1 GPU_PCIE_CALI GPU_PCIE_CALRN

- @m38a_lib.M38A

GPU_PCIE_CALI

- @m38a_lib.M38A

GPU_PCIE_CALRN

- @m38a_lib.M38A

GPU_PCIE_CALRP

GPU_PCIE_CALRP

GPU_PWM_RST_L

GPU_PWM_RST_L

- @m38a_lib.M38A

GPU_R2

GPU_R2 - @m38a_lib.M38A

- @m38a_lib.M38A

91C5 95C4 91C5 95C4

97A4

84A3 84A3 84A3 6C7 94B3 93B3 97A8

FB_B_DQ<62>

FB_B_DQ<62>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<22>

FSB_D_L<22> - @m38a_lib.M38A

7B4 12C6

GPU_TEST_MCLK

- @m38a_lib.M38A

FB_B_DQ<63>

- @m38a_lib.M38A

87B3 90A3

FSB_D_L<23>

FSB_D_L<23> - @m38a_lib.M38A

7B4 12C6

72A6 72B2 72B5 72D2 72D8

GPU_TEST_YCLK

GPU_TEST_YCLK

- @m38a_lib.M38A

FB_B_DQM_L<0>

FB_B_DQM_L<0>

- @m38a_lib.M38A

87D1 90B6

FSB_D_L<24>

FSB_D_L<24> - @m38a_lib.M38A

7B4 12C6

ANE

@m38a_lib.M38A

74C3

GPU_TV_C

GPU_TV_C - @m38a_lib.M38A

88B1 93B3

FB_B_DQM_L<1>

FB_B_DQM_L<1>

- @m38a_lib.M38A

87C1 90B6

FSB_D_L<25>

FSB_D_L<25> - @m38a_lib.M38A

7B4 12C6

GND_BNDI

GND_BNDI - @m38a_lib.M38A

47B2 47D1

TP_GPU_TV_C

- @m38a_lib.M38A

88B3

FB_B_DQM_L<2>

FB_B_DQM_L<2>

- @m38a_lib.M38A

87C1 90B6

FSB_D_L<26>

FSB_D_L<26> - @m38a_lib.M38A

7B4 12C6

GND_CHASSIS_AUDIO_EX

GND_CHASSIS_AUDIO_EXT ERNAL -

6B2 73C7

GPU_TV_COMP

GPU_TV_COMP

- @m38a_lib.M38A

FB_B_DQM_L<3>

FB_B_DQM_L<3>

- @m38a_lib.M38A

87C1 90B6

FSB_D_L<27>

FSB_D_L<27> - @m38a_lib.M38A

7B4 12C6

TERNAL

FB_B_DQM_L<4>

FB_B_DQM_L<4>

- @m38a_lib.M38A

87C1 90B3

FSB_D_L<28>

FSB_D_L<28> - @m38a_lib.M38A

7B4 12C6

GND_CHASSIS_IO_LEFT

6B2

GPU_TV_Y

GPU_TV_Y - @m38a_lib.M38A

FB_B_DQM_L<5>

FB_B_DQM_L<5>

- @m38a_lib.M38A

87C1 90B3

FB_B_DQM_L<6>

FB_B_DQM_L<6>

- @m38a_lib.M38A

GPU_V2SYNC

GPU_V2SYNC - @m38a_lib.M38A

93B3 97B4

FB_B_DQM_L<7> FB_B_MA<0>

FB_B_DQM_L<7> - @m38a_lib.M38A FB_B_MA<0> - @m38a_lib.M38A

GPU_VARY_BL GPU_VGA_B

GPU_VARY_BL - @m38a_lib.M38A GPU_VGA_B - @m38a_lib.M38A

91C3 94B4 88C1 93C3

FB_B_MA<1> - @m38a_lib.M38A

FSB_D_L<29>

FSB_D_L<29> - @m38a_lib.M38A

7B4 12C6

@m38a_lib.M38A

87C1 90B3

FSB_D_L<30>

FSB_D_L<30> - @m38a_lib.M38A

7B4 12C6

GND_CHASSIS_USB

FSB_D_L<31> FSB_D_L<32>

FSB_D_L<31> - @m38a_lib.M38A FSB_D_L<32> - @m38a_lib.M38A

7B4 12C6 7C2 12C6

GND_CHASSIS_IO_LEFT @m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<33>

FSB_D_L<33> - @m38a_lib.M38A

7C2 12C6

GND_CHASSIS_AUDIO_EX

87D1 90B5 90B8

FSB_D_L<34>

FSB_D_L<34> - @m38a_lib.M38A

7C2 12C6

TERNAL_J

FB_B_MA<3> - @m38a_lib.M38A

5A5 5B5 5C6 87D1 90B5

FSB_D_L<35>

FSB_D_L<35> - @m38a_lib.M38A

7C2 12C6

GND_CHASSIS_AUDIO_IN

90B8

FSB_D_L<36>

FSB_D_L<36> - @m38a_lib.M38A

7C2 12C6

TERNAL

FB_B_MA<4> - @m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<37>

FSB_D_L<37> - @m38a_lib.M38A

7C2 12C6

FB_B_MA<5>

FB_B_MA<5> - @m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<38>

FSB_D_L<38> - @m38a_lib.M38A

7C2 12C6

FB_B_MA<6> - @m38a_lib.M38A

87D1 90B5 90B8

FB_B_MA<7> - @m38a_lib.M38A

-

TP_GPU_TV_Y - @m38a_lib.M38A -

GND_CHASSIS_AUDIO_EXTERNAL_J

GND_CHASSIS_FIREWIRE

-

@m38a_lib.M38A

GND_CHASSIS_FIREWIRE

FSB_D_L<39>

FSB_D_L<39> - @m38a_lib.M38A

7C2 12B6

@m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<40>

FSB_D_L<40> - @m38a_lib.M38A

7C2 12B6

GND_CHASSIS_RJ45

FB_B_MA<8> - @m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<41>

FSB_D_L<41> - @m38a_lib.M38A

5D7 5D8 7C2 12B6

GND_CHASSIS_VGA

FB_B_MA<9> - @m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<42>

FSB_D_L<42> - @m38a_lib.M38A

7C2 12B6

GND_CHASSIS_RJ45

- @m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<43>

FSB_D_L<43> - @m38a_lib.M38A

7C2 12B6

GND_CHASSIS_IO_RIGHT

FB_B_MA<11>

FB_B_MA<11>

- @m38a_lib.M38A

87D1 90B5 90B8

FSB_D_L<44>

FSB_D_L<44> - @m38a_lib.M38A

7C2 12B6

FB_B_RAS_L<0>

FB_B_RAS_L<0>

5B5 87B1 90A8

FSB_D_L<45>

FSB_D_L<45> - @m38a_lib.M38A

7C2 12B6

GND_GPUVCORE_SGND

GND_GPUVCORE_SGND

-

- @m38a_lib.M38A -

FSB_D_L<46>

FSB_D_L<46> - @m38a_lib.M38A

7C2 12B6

GND_GPU_PCIE_PVSS

GND_GPU_PCIE_PVSS

5C6 87C1 90A8

FSB_D_L<47>

FSB_D_L<47> - @m38a_lib.M38A

7C2 12B6

GND_IMVP6_SGND

GND_IMVP6_SGND

- @m38a_lib.M38A

5C6 87C1 90A8

FSB_D_L<48>

FSB_D_L<48> - @m38a_lib.M38A

7C2 12B6

GND_NB_VSSA_LVDS

GND_NB_VSSA_LVDS

FB_B_RDQS<2>

- @m38a_lib.M38A

5C6 87C1 90A8

FSB_D_L<49>

FSB_D_L<49> - @m38a_lib.M38A

7C2 12B6

TP_GND_NB_VSSA_LVDS

FB_B_RDQS<3>

- @m38a_lib.M38A

5C6 87C1 90A8

FSB_D_L<50>

FSB_D_L<50> - @m38a_lib.M38A

7B2 12B6

@m38a_lib.M38A

FB_B_RDQS<4>

FB_B_RDQS<4>

- @m38a_lib.M38A

5C6 87C1 90A5

FSB_D_L<51>

FSB_D_L<51> - @m38a_lib.M38A

7B2 12B6

GND_NEXT_TO_SMC

GND_NEXT_TO_SMC

FB_B_RDQS<5>

FB_B_RDQS<5>

- @m38a_lib.M38A

5C6 87C1 90A5

FSB_D_L<52>

FSB_D_L<52> - @m38a_lib.M38A

7B2 12B6

GND_SMC_AVSS

GND_SMC_AVSS - @m38a_lib.M38A

FB_B_RDQS<6>

FB_B_RDQS<6>

- @m38a_lib.M38A

5C6 87C1 90A5

FSB_D_L<53>

FSB_D_L<53> - @m38a_lib.M38A

7B2 12B6

FB_B_RDQS<7>

FB_B_RDQS<7>

- @m38a_lib.M38A

5C6 87C1 90A5

FSB_D_L<54>

FSB_D_L<54> - @m38a_lib.M38A

7B2 12B6

GPUISENS_NEG

FB_B_WDQS<0>

FB_B_WDQS<0>

- @m38a_lib.M38A

5B5 87C1 90A8

FSB_D_L<55>

FSB_D_L<55> - @m38a_lib.M38A

7B2 12B6

GPUISENS_NTC

FB_B_WDQS<1>

FB_B_WDQS<1>

- @m38a_lib.M38A

5B5 87C1 90A8

FSB_D_L<56>

FSB_D_L<56> - @m38a_lib.M38A

7B2 12B6

GPUISENS_POS

FB_B_WDQS<2>

FB_B_WDQS<2>

- @m38a_lib.M38A

5B5 87C1 90A8

FSB_D_L<57>

FSB_D_L<57> - @m38a_lib.M38A

7B2 12B6

GPUISENS_RC

FB_B_WDQS<3>

FB_B_WDQS<3>

- @m38a_lib.M38A

5B5 87C1 90A8

FSB_D_L<58>

FSB_D_L<58> - @m38a_lib.M38A

7B2 12B6

GPUVCORE_BOOT

GPUVCORE_BOOT

- @m38a_lib.M38A

FB_B_WDQS<4>

FB_B_WDQS<4>

- @m38a_lib.M38A

5A5 87C1 90A5

FSB_D_L<59>

FSB_D_L<59> - @m38a_lib.M38A

5D7 5D8 7B2 12B6

GPUVCORE_COMP

GPUVCORE_COMP

- @m38a_lib.M38A

FB_B_WDQS<5>

FB_B_WDQS<5>

- @m38a_lib.M38A

5A5 87C1 90A5

FSB_D_L<60>

FSB_D_L<60> - @m38a_lib.M38A

7B2 12B6

GPUVCORE_COMP_R

GPUVCORE_COMP_R

5A5 87C1 90A5

FSB_D_L<61>

FSB_D_L<61> - @m38a_lib.M38A

7B2 12B6

5A5 87C1 90A5

FSB_D_L<62>

FSB_D_L<62> - @m38a_lib.M38A

5B5 87B1 90A8

FB_B_WDQS<6> FB_B_WDQS<7> FB_B_WE_L<0> FB_B_WE_L<1>

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

DRAM_RST - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A -

- @m38a_lib.M38A

TP_GPU_VGA_HSYNC

- @m38a_lib.M38A

GPU_VGA_R - @m38a_lib.M38A

6B2 43C6

- @m38a_lib.M38A

GPU_VGA_VSYNC

GPU_VGA_VSYNC

6B2 43C6

GPU_VSYNC_BUF

GPU_VSYNC_BUF

6B1

GPU_XTALOUT

GPU_XTALOUT

- @m38a_lib.M38A

I2C_ALS_SCL

I2C_ALS_SCL

- @m38a_lib.M38A

6B2 97C4

84B8

5A5 87B1 90A5

- @m38a_lib.M38A

FB_B_RDQS<1>

FB_DRAM_RST

GPU_VGA_HSYNC

47D2 GPU_VGA_R

- @m38a_lib.M38A

FB_B_RAS_L<1> FB_B_RDQS<0>

FB_B_RDQS<3>

FB_DRAM_RST

- @m38a_lib.M38A

GPU_VGA_G - @m38a_lib.M38A

GPU_VGA_HSYNC

TP_GPU_VGA_G

47C2 47C2

6B2 46A1 46C1

85C7

FB_B_RDQS<2>

FB_B_WE_L<1>

6A2

- @m38a_lib.M38A

FB_B_RDQS<1>

FB_B_WE_L<0>

TP_GPU_VGA_B GPU_VGA_G

6A2 73C4

- @m38a_lib.M38A

TP_GPU_VGA_VSYNC

@m38a_lib.M38A

FB_B_RDQS<0>

FB_B_WDQS<7>

73A8 73C5 73C8 74C1 74C3

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_GPU_VGA_R - @m38a_lib.M38A - @m38a_lib.M38A

FB_B_RAS_L<1>

FB_B_WDQS<6>

- @m38a_lib.M38A

-

@m38a_lib.M38A

FB_B_MA<10>

- @m38a_lib.M38A

47C4

@m38a_lib.M38A

GND_CHASSIS_BNDI

FB_B_MA<10>

FB_B_MA<8>

6B2 47A4 47B4 6B2

GND_CHASSIS_AUDIO_INT ERNAL -

FB_B_MA<9>

FB_B_MA<7>

GPU_TEST_MCLK

TP_GPU_TV_COMP

87C1 90B3 87D1 90B5 90B8

FB_B_MA<3>

FB_B_MA<6>

6C2 72B1 74D3

@m38a_lib.M38A

FB_B_MA<4>

FB_B_MA<2> - @m38a_lib.M38A

- @m38a_lib.M38A

GND_AUDIO_SPKRAMP_PLA NE -

SMB_A_S3_CLK I2C_ALS_SDA

75A4 75B6 75B8 75D7 17C6 19C2

I2C_ALS_SDA

- @m38a_lib.M38A - @m38a_lib.M38A

SMB_A_S3_DATA IDE_CSEL_PD

19C1

- @m38a_lib.M38A

- @m38a_lib.M38A

IDE_CSEL_PD

- @m38a_lib.M38A

- @m38a_lib.M38A

87A3 87A3

88B3 88B3

88C3 88C1 93C3 88C3 88B1 93B3 88B3 88C1 93C3 88C3 88B1 93B3 88B3 97B4 91A5 59C1 59C8 58B5 59C2 59D1 59C1 59C8 58B5 59C2 59D1 38C3

IDE_DASP_L

IDE_DASP_L - @m38a_lib.M38A IDE_DASP_L_DS

- @m38a_lib.M38A

59B2

IDE_IOCS16_PU

IDE_IOCS16_PU

- @m38a_lib.M38A

58B2 58C4 59A3 59B3 76B2

IDE_IRQ14

IDE_IRQ14 - @m38a_lib.M38A

21B6 38C4

76B6 76C5 85C1

IDE_PDA<0>

IDE_PDA<0> - @m38a_lib.M38A

21B5 38C3

GPUISENS_NEG - @m38a_lib.M38A

85D3

IDE_PDA<1>

IDE_PDA<1> - @m38a_lib.M38A

21B5 38C3

GPUISENS_NTC - @m38a_lib.M38A

85D3

IDE_PDA<2>

IDE_PDA<2> - @m38a_lib.M38A

21B5 38C1

GPUISENS_POS - @m38a_lib.M38A

85D3

IDE_PDCS1_L

IDE_PDCS1_L

- @m38a_lib.M38A

GPUISENS_RC - @m38a_lib.M38A

85D3

IDE_PDCS3_L

IDE_PDCS3_L

- @m38a_lib.M38A

85C5

IDE_PDD<0>

IDE_PDD<0> - @m38a_lib.M38A

21C5 38C3

85C7

IDE_PDD<1>

IDE_PDD<1> - @m38a_lib.M38A

21B5 38C3

85C7

IDE_PDD<2>

IDE_PDD<2> - @m38a_lib.M38A

21B5 38D3

85C8 88A8

IDE_PDD<3>

85C7

- @m38a_lib.M38A

38C3 38B3 38C1

21B5 38C1

GPUVCORE_EN

GPUVCORE_EN - @m38a_lib.M38A

IDE_PDD<3> - @m38a_lib.M38A

21B5 38D3

7B2 12B6

GPUVCORE_FB

GPUVCORE_FB - @m38a_lib.M38A

IDE_PDD<4>

IDE_PDD<4> - @m38a_lib.M38A

21B5 38D3

FSB_D_L<63>

FSB_D_L<63> - @m38a_lib.M38A

7B2 12B6

GPUVCORE_FCCM

GPUVCORE_FCCM

- @m38a_lib.M38A

85C7

IDE_PDD<5>

IDE_PDD<5> - @m38a_lib.M38A

21B5 38D3

5A5 87B1 90A5

FSB_HITM_L

FSB_HITM_L - @m38a_lib.M38A

5C7 7D6 12B4

GPUVCORE_FSET

GPUVCORE_FSET

- @m38a_lib.M38A

85C7

IDE_PDD<6>

IDE_PDD<6> - @m38a_lib.M38A

21B5 38D3

FSB_HIT_L

FSB_HIT_L - @m38a_lib.M38A

5C7 7D6 12B4

GPUVCORE_IOUT

GPUVCORE_IOUT

- @m38a_lib.M38A

59C5 85D1

IDE_PDD<7>

IDE_PDD<7> - @m38a_lib.M38A

21B5 38D3

5A5 5A6 5B5 5B6 88A6 89A5

FSB_IERR_L

FSB_IERR_L - @m38a_lib.M38A

7D6

58D5 59C6

IDE_PDD<8>

IDE_PDD<8> - @m38a_lib.M38A

21B5 38D1

89A8 90A5 90A8

FSB_LOCK_L

FSB_LOCK_L - @m38a_lib.M38A

5D7 5D8 7D6 12B4

GPUVCORE_ISEN

GPUVCORE_ISEN

85C5

IDE_PDD<9>

IDE_PDD<9> - @m38a_lib.M38A

5C8 21B5 38D1

- @m38a_lib.M38A - @m38a_lib.M38A

FSB_ADSTB_L<0>

FSB_ADSTB_L<0>

- @m38a_lib.M38A

5D7 5D8 7D7 12C4

FSB_REQ_L<0>

FSB_REQ_L<0>

- @m38a_lib.M38A

5C7 7D7 12B4

GPUVCORE_LG

GPUVCORE_LG - @m38a_lib.M38A

85C5

IDE_PDD<10>

IDE_PDD<10>

- @m38a_lib.M38A

21B5 38D1

FSB_ADSTB_L<1>

FSB_ADSTB_L<1>

- @m38a_lib.M38A

5D7 5D8 7C7 12C4

FSB_REQ_L<1>

FSB_REQ_L<1>

- @m38a_lib.M38A

5C7 7D7 12B4

GPUVCORE_PGOOD

GPUVCORE_PGOOD

- @m38a_lib.M38A

77A4 85C8

IDE_PDD<11>

IDE_PDD<11>

- @m38a_lib.M38A

21B5 38D1

FSB_ADS_L

FSB_ADS_L - @m38a_lib.M38A

7D6 12C4

FSB_REQ_L<2>

FSB_REQ_L<2>

- @m38a_lib.M38A

5C7 7D7 12A4

GPUVCORE_PHASE

GPUVCORE_PHASE

- @m38a_lib.M38A

85C5

IDE_PDD<12>

IDE_PDD<12>

- @m38a_lib.M38A

21B5 38D1

FSB_A_L<3>

FSB_A_L<3> - @m38a_lib.M38A

7D7 12D4

FSB_REQ_L<3>

FSB_REQ_L<3>

- @m38a_lib.M38A

5C7 7D7 12A4

GPUVCORE_UG

GPUVCORE_UG - @m38a_lib.M38A

85C5

IDE_PDD<13>

IDE_PDD<13>

- @m38a_lib.M38A

21B5 38D1

FSB_A_L<4>

FSB_A_L<4> - @m38a_lib.M38A

7D7 12D4

FSB_REQ_L<4>

FSB_REQ_L<4>

- @m38a_lib.M38A

5C7 7D7 12A4

GPU_B2

GPU_B2 - @m38a_lib.M38A

93B3 97B8

IDE_PDD<14>

- @m38a_lib.M38A

FSB_A_L<5>

FSB_A_L<5> - @m38a_lib.M38A

7D7 12D4

FSB_RS_L<0>

FSB_RS_L<0> - @m38a_lib.M38A

7D6 12A4

GPU_CLK27M

GPU_CLK27M - @m38a_lib.M38A

92C6

IDE_PDD<15>

- @m38a_lib.M38A

FSB_A_L<6>

FSB_A_L<6> - @m38a_lib.M38A

5D7 5D8 7D7 12D4

FSB_RS_L<1>

FSB_RS_L<1> - @m38a_lib.M38A

7D6 12A4

GPU_XTALIN - @m38a_lib.M38A

91A5 92C5

IDE_PDDACK_L

IDE_PDDACK_L

FSB_A_L<7>

FSB_A_L<7> - @m38a_lib.M38A

7D7 12D4

FSB_RS_L<2>

FSB_RS_L<2> - @m38a_lib.M38A

7D6 12A4

GPU_CLK100M_PCIE_N

GPU_CLK100M_PCIE_N

-

@m38a_lib.M38A

5C6 34A4

34B2 84A5

IDE_PDDREQ

IDE_PDDREQ - @m38a_lib.M38A

FSB_A_L<8>

FSB_A_L<8> - @m38a_lib.M38A

7D7 12D4

FSB_SLPCPU_L

FSB_SLPCPU_L

7A3 12A4

GPU_CLK100M_PCIE_P

GPU_CLK100M_PCIE_P

-

@m38a_lib.M38A

5C6 34A4

34B2 84A5

IDE_PDIORDY

IDE_PDIORDY

- @m38a_lib.M38A

FSB_A_L<9>

FSB_A_L<9> - @m38a_lib.M38A

7D7 12D4

FSB_TRDY_L

FSB_TRDY_L - @m38a_lib.M38A

7D6 12A4

GPU_DDC_A_CLK

GPU_DDC_A_CLK

FSB_A_L<10>

FSB_A_L<10>

- @m38a_lib.M38A

7D7 12D4

FWH_INIT_L

FWH_INIT_L - @m38a_lib.M38A

21C4 59C5 60C1

GPU_DDC_A_DATA

GPU_DDC_A_DATA

FSB_A_L<11>

FSB_A_L<11>

- @m38a_lib.M38A

7D7 12D4

GPU_DDC_B_CLK

GPU_DDC_B_CLK

FSB_A_L<12>

FSB_A_L<12>

- @m38a_lib.M38A

7D7 12D4

FWH_MFG_MODE

FWH_MFG_MODE

FSB_A_L<13>

FSB_A_L<13>

- @m38a_lib.M38A

7D7 12D4

FW_A_TPA_N

FW_A_TPA_N - @m38a_lib.M38A

FSB_A_L<14>

FSB_A_L<14>

- @m38a_lib.M38A

7D7 12D4

FSB_A_L<15>

FSB_A_L<15>

- @m38a_lib.M38A

7D7 12D4

FW_A_TPA_P

FW_A_TPA_P - @m38a_lib.M38A

FSB_A_L<16>

FSB_A_L<16>

- @m38a_lib.M38A

7D7 12C4

FSB_A_L<17>

FSB_A_L<17>

- @m38a_lib.M38A

7C7 12C4

FW_A_TPBIAS

FW_A_TPBIAS - @m38a_lib.M38A

44C4 46C8

GPU_DIGON

GPU_DIGON - @m38a_lib.M38A

6A7 91C3 94C8

IMVP6_DROOP

IMVP6_DROOP

FSB_A_L<18>

FSB_A_L<18>

- @m38a_lib.M38A

7C7 12C4

FW_A_TPB_N

FW_A_TPB_N - @m38a_lib.M38A

44C3 46C8

GPU_G2

GPU_G2 - @m38a_lib.M38A

93B3 97A8

IMVP6_FB

IMVP6_FB - @m38a_lib.M38A

75A4 75B6

FSB_A_L<19>

FSB_A_L<19>

- @m38a_lib.M38A

7C7 12C4

FW_PORT0_TPB_N

46C5 46C6

GPU_GENERICA

GPU_GENERICA - @m38a_lib.M38A

91C3 95B4

IMVP6_FB2

IMVP6_FB2 - @m38a_lib.M38A

75A4 75B6

FSB_A_L<20>

FSB_A_L<20>

- @m38a_lib.M38A

7C7 12C4

TP_GPU_GENERICA

95B6

IMVP6_FET_RC1

IMVP6_FET_RC1

- @m38a_lib.M38A

FSB_A_L<21>

FSB_A_L<21>

- @m38a_lib.M38A

7C7 12C4

GPU_GENERICB

GPU_GENERICB - @m38a_lib.M38A

91C3 95B4

IMVP6_FET_RC2

IMVP6_FET_RC2

- @m38a_lib.M38A

FSB_A_L<22>

FSB_A_L<22>

- @m38a_lib.M38A

7C7 12C4

TP_GPU_GENERICB

95B6

IMVP6_ISEN1

IMVP6_ISEN1

- @m38a_lib.M38A

75A8 75C5

FSB_A_L<23>

FSB_A_L<23>

- @m38a_lib.M38A

7C7 12C4

GPU_GENERICC

GPU_GENERICC - @m38a_lib.M38A

91C3 95B4

IMVP6_ISEN2

IMVP6_ISEN2

- @m38a_lib.M38A

75A6 75C5

FSB_A_L<24>

FSB_A_L<24>

- @m38a_lib.M38A

7C7 12C4

FW_B_TPA_P

FW_B_TPA_P - @m38a_lib.M38A

TP_GPU_GENERICC

95B6

IMVP6_LGATE1

FSB_A_L<25>

FSB_A_L<25>

- @m38a_lib.M38A

7C7 12C4

46B5 46C6

GPU_GENERICD

GPU_GENERICD - @m38a_lib.M38A

91C3

IMVP6_LGATE2

FSB_A_L<26>

FSB_A_L<26>

- @m38a_lib.M38A

7C7 12C4

FW_B_TPBIAS

FW_B_TPBIAS - @m38a_lib.M38A

44C4 46C8

GPU_GPIO_0

GPU_GPIO_0 - @m38a_lib.M38A

88D5 91D3 94C3

IMVP6_NTC

IMVP6_NTC - @m38a_lib.M38A

FSB_A_L<27>

FSB_A_L<27>

- @m38a_lib.M38A

5D7 5D8 7C7 12C4

FW_B_TPB_N

FW_B_TPB_N - @m38a_lib.M38A

44C3 46C8

GPU_GPIO_1

GPU_GPIO_1 - @m38a_lib.M38A

88D5 91D3

IMVP6_NTC_R

IMVP6_NTC_R

- @m38a_lib.M38A

FSB_A_L<28>

FSB_A_L<28>

- @m38a_lib.M38A

7C7 12C4

FW_PORT1_TPB_N

46B5 46C6

GPU_GPIO_2

GPU_GPIO_2 - @m38a_lib.M38A

88D5 91D3

IMVP6_OCSET

IMVP6_OCSET

- @m38a_lib.M38A

FSB_A_L<29>

FSB_A_L<29>

- @m38a_lib.M38A

7C7 12C4

FW_B_TPB_P - @m38a_lib.M38A

44C3 46C8

GPU_GPIO_3

GPU_GPIO_3 - @m38a_lib.M38A

88D5 91D3

IMVP6_PHASE1

IMVP6_PHASE1

- @m38a_lib.M38A

75A8 75C5

FSB_A_L<30>

FSB_A_L<30>

- @m38a_lib.M38A

7C7 12C4

FW_PORT1_TPB_P

46B5 46C6

GPU_GPIO_4

GPU_GPIO_4 - @m38a_lib.M38A

88C5 91D3

IMVP6_PHASE2

IMVP6_PHASE2

- @m38a_lib.M38A

75A6 75C5

- @m38a_lib.M38A

44B5

GPU_GPIO_5

GPU_GPIO_5 - @m38a_lib.M38A

88C5 91D3

44B3

GPU_GPIO_6

GPU_GPIO_6 - @m38a_lib.M38A

88C5 91D3

IMVP6_RTN

IMVP6_RTN - @m38a_lib.M38A

75A4 75B5

44C3

GPU_GPIO_7

GPU_GPIO_7 - @m38a_lib.M38A

88C3 91D3

IMVP6_SOFT

IMVP6_SOFT - @m38a_lib.M38A

75A4 75C6

- @m38a_lib.M38A

SMC_CPU_INIT_3_3_L - @m38a_lib.M38A 58D5 59C6 - @m38a_lib.M38A

FW_PORT0_TPA_N FW_PORT0_TPA_P

FW_A_TPB_P

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

FSB_A_L<31>

FSB_A_L<31>

7C7 12C4

FW_CARDBUS_L

FW_CARDBUS_L

- @m38a_lib.M38A

FSB_BNR_L

FSB_BNR_L - @m38a_lib.M38A

5C7 7D6 12C4

FW_CONTENDER

FW_CONTENDER

- @m38a_lib.M38A

FSB_BPRI_L

FSB_BPRI_L - @m38a_lib.M38A

7D6 12C4

FW_CPS

FW_CPS - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_GPU_DDC_B_DATA GPU_DDC_C_CLK

46C5 46C6

GPU_DDC_C_CLK

GPU_DDC_C_DATA

46C5 46C6

44C3 46C8

- @m38a_lib.M38A

- @m38a_lib.M38A

GPU_DDC_C_DATA

44C3 46C8

46B5 46C6

- @m38a_lib.M38A - @m38a_lib.M38A

GPU_DDC_B_DATA

46C5 46C6

44C3 46C8

- @m38a_lib.M38A

GPU_DDC_B_DATA

44C3 46C8

FW_PORT1_TPA_N

- @m38a_lib.M38A

TP_GPU_DDC_B_CLK

44C3 46C8

FW_B_TPA_N - @m38a_lib.M38A

FW_PORT1_TPA_P

FW_B_TPB_P

- @m38a_lib.M38A

FW_A_TPB_P - @m38a_lib.M38A FW_PORT0_TPB_P

FW_B_TPA_N

- @m38a_lib.M38A

23A6 23C5

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

IDE_PDD<14> IDE_PDD<15>

- @m38a_lib.M38A

21B5 38D1 21B5 38C1 21B6 38C1 21B6 38C4 5C8 21B6 38C4

93A3 97D1

IDE_PDIOR_L

IDE_PDIOR_L

- @m38a_lib.M38A

5C8 21B6 38C1

93A3 97C1

IDE_PDIOW_L

IDE_PDIOW_L

- @m38a_lib.M38A

21B6 38C3

88B1 93A3

IDE_RESET_L

IDE_RESET_L

- @m38a_lib.M38A

23C3 38D3 38D6

88B3

IMVP6_BOOT1

IMVP6_BOOT1

- @m38a_lib.M38A

75A8 75C5

IMVP6_BOOT2

IMVP6_BOOT2

- @m38a_lib.M38A

75A6 75C5

88B1 93A3 88B3

IMVP6_COMP

93A1 93A3 94A7 94C7 93A1 93A3 94A6 94C7

IMVP6_COMP_RC IMVP6_DFB

IMVP6_RBIAS

IMVP6_COMP - @m38a_lib.M38A IMVP6_COMP_RC

- @m38a_lib.M38A

IMVP6_DFB - @m38a_lib.M38A - @m38a_lib.M38A

IMVP6_LGATE1 IMVP6_LGATE2

IMVP6_RBIAS

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

B

21B5 38C3

87A1 88A8

SMC_GPU_ISENSE

C

88B1 93B3 88B1 93B3

IDE_DASP_L_DS - @m38a_lib.M38A

D

91C5 95C4

FB_B_DQ<63>

GND_AUDIO_SPKRAMP_PL

1

88C5

GPU_GPIO_10

FW_C_TPBIAS - @m38a_lib.M38A - @m38a_lib.M38A

2

- @m38a_lib.M38A

46B7

FW_C_TPA_P - @m38a_lib.M38A

FW_C_TPBIAS

- @m38a_lib.M38A

TP_GPU_GPIO_7

44C3 46B8

FW_C_TPA_P

TP_FW_C_TPA_P

 

3

44C3 46B8

5D7 5D8 7C4 12D6 7C4 12D6

FB_B_MA<1>

A

 

FB_B_DQ<18>

FB_B_MA<2>

B

7

FB_B_DQ<18>

75A4 75B6 75B7 75A4 75B5 75A4 75B4

A

75A8 75C2 75A6 75B2

75A8 75C5 75A6 75C5 75C7 75C7 75A4 75B5

75A4 75B6

102

8

 

7

6

 

5

 

4

 

3

 

2

 

1

 

8

7

  MEM_A_A<13>

I IMVP6_UGATE2 IMVP6_VDIFF

D

IMVP6_VDIFF

- @m38a_lib.M38A

 

3

2

MEM_B_DQ<1> - @m38a_lib.M38A

15D4 29D6

NB_CFG<14>

NB_CFG<14> - @m38a_lib.M38A

15D5 28B6

MEM_A_BS<0> - @m38a_lib.M38A

MEM_B_DQ<2>

MEM_B_DQ<2> - @m38a_lib.M38A

15D4 29D6

NB_CFG<15>

NB_CFG<15> - @m38a_lib.M38A

14C6

MEM_A_BS<2..0>

MEM_A_BS<2..0>

30C6

MEM_B_DQ<3>

MEM_B_DQ<3> - @m38a_lib.M38A

15D4 29D6

NB_CFG<16>

NB_CFG<16> - @m38a_lib.M38A

14C6 20C5

MEM_A_BS<1>

MEM_A_BS<1> - @m38a_lib.M38A

15D5 28B3

MEM_B_DQ<4>

MEM_B_DQ<4> - @m38a_lib.M38A

15D4 29D3

NB_CFG<17>

NB_CFG<17> - @m38a_lib.M38A

14C6

MEM_A_BS<2>

MEM_A_BS<2> - @m38a_lib.M38A

15D5 28C6

MEM_B_DQ<5>

MEM_B_DQ<5> - @m38a_lib.M38A

15D4 29D3

NB_CFG<18>

NB_CFG<18> - @m38a_lib.M38A

14C6 20B5

MEM_A_CAS_L

MEM_A_CAS_L - @m38a_lib.M38A

15D5 28B6 30B6

MEM_B_DQ<6>

MEM_B_DQ<6> - @m38a_lib.M38A

5A7 15D4 29D3

NB_CFG<19>

NB_CFG<19> - @m38a_lib.M38A

14C6 20B5

75C7

MEM_A_DM<0>

MEM_A_DM<0> - @m38a_lib.M38A

15D5 28D3

MEM_B_DQ<7>

MEM_B_DQ<7> - @m38a_lib.M38A

15D4 29D3

NB_CFG<20>

NB_CFG<20> - @m38a_lib.M38A

14B6 20A5

75A4 75B5

MEM_A_DM<1>

MEM_A_DM<1> - @m38a_lib.M38A

15D5 28D3

MEM_B_DQ<8>

MEM_B_DQ<8> - @m38a_lib.M38A

5A7 15C4 29D6

NB_CLK100M_GCLKIN_N

NB_CLK100M_GCLKIN_N

-

5C7 14C4 34B4 34C2

75A4 75C5

MEM_A_DM<2>

MEM_A_DM<2> - @m38a_lib.M38A

15D5 28C3

MEM_B_DQ<9>

MEM_B_DQ<9> - @m38a_lib.M38A

15C4 29D6

75A8 75C2

MEM_A_DM<3>

MEM_A_DM<3> - @m38a_lib.M38A

15C5 28C6

MEM_B_DQ<10>

MEM_B_DQ<10> - @m38a_lib.M38A

15C4 29D6

NB_CLK100M_GCLKIN_P

NB_CLK100M_GCLKIN_P

-

5C7 14C4 34B4 34C2

75A6 75B2

MEM_A_DM<4>

MEM_A_DM<4> - @m38a_lib.M38A

15C5 28B3

MEM_B_DQ<11>

MEM_B_DQ<11> - @m38a_lib.M38A

15C4 29D6

75A4 75B6

IMVP6_VR_TT

IMVP6_VR_TT

IMVP6_VSEN

IMVP6_VSEN - @m38a_lib.M38A

IMVP6_VSUM

IMVP6_VSUM - @m38a_lib.M38A

IMVP6_VSUM_R1

IMVP6_VSUM_R1

- @m38a_lib.M38A

IMVP6_VSUM_R2

IMVP6_VSUM_R2

- @m38a_lib.M38A

IMVP6_VW

IMVP6_VW - @m38a_lib.M38A

- @m38a_lib.M38A

@m38a_lib.M38A @m38a_lib.M38A

MEM_A_DM<5>

MEM_A_DM<5> - @m38a_lib.M38A

15C5 28A6

MEM_B_DQ<12>

MEM_B_DQ<12> - @m38a_lib.M38A

15C4 29D3

IMVP_DPRSLPVR

IMVP_DPRSLPVR

75C6

MEM_A_DM<6>

MEM_A_DM<6> - @m38a_lib.M38A

15C5 28A3

MEM_B_DQ<13>

MEM_B_DQ<13> - @m38a_lib.M38A

15C4 29D3

NB_FSB_XRCOMP

NB_FSB_XRCOMP

- @m38a_lib.M38A

IMVP_PGD_IN

IMVP_PGD_IN

- @m38a_lib.M38A

75C6 77D5

MEM_A_DM<7>

MEM_A_DM<7> - @m38a_lib.M38A

15C5 28A6

MEM_B_DQ<14>

MEM_B_DQ<14> - @m38a_lib.M38A

15C4 29D3

NB_FSB_XSCOMP

NB_FSB_XSCOMP

- @m38a_lib.M38A

IMVP_VID<0>

IMVP_VID<0>

- @m38a_lib.M38A

75C6

MEM_A_DQ<0>

MEM_A_DQ<0> - @m38a_lib.M38A

15D7 28D6

MEM_B_DQ<15>

MEM_B_DQ<15> - @m38a_lib.M38A

15C4 29D3

NB_FSB_XSWING

NB_FSB_XSWING

- @m38a_lib.M38A

12A6

IMVP_VID<1>

IMVP_VID<1>

- @m38a_lib.M38A

75C7

MEM_A_DQ<1>

MEM_A_DQ<1> - @m38a_lib.M38A

15D7 28D6

MEM_B_DQ<16>

MEM_B_DQ<16> - @m38a_lib.M38A

15C4 29C6

NB_FSB_YRCOMP

NB_FSB_YRCOMP

- @m38a_lib.M38A

12A6

IMVP_VID<2>

IMVP_VID<2>

- @m38a_lib.M38A

75C7

MEM_A_DQ<2>

MEM_A_DQ<2> - @m38a_lib.M38A

15D7 28D6

MEM_B_DQ<17>

MEM_B_DQ<17> - @m38a_lib.M38A

15C4 29C6

NB_FSB_YSCOMP

NB_FSB_YSCOMP

- @m38a_lib.M38A

12A6

IMVP_VID<3>

IMVP_VID<3>

- @m38a_lib.M38A

75C7

MEM_A_DQ<3>

MEM_A_DQ<3> - @m38a_lib.M38A

15D7 28D6

MEM_B_DQ<18>

MEM_B_DQ<18> - @m38a_lib.M38A

15C4 29C6

NB_FSB_YSWING

NB_FSB_YSWING

- @m38a_lib.M38A

12A6

75C7

MEM_A_DQ<4>

75C7

IMVP_VID<4>

- @m38a_lib.M38A

- @m38a_lib.M38A

NB_FSB_VREF

NB_FSB_VREF

- @m38a_lib.M38A

5D4 12C4 12A6 12A6

MEM_A_DQ<4> - @m38a_lib.M38A

15D7 28D3

MEM_B_DQ<19>

MEM_B_DQ<19> - @m38a_lib.M38A

15C4 29C6

NB_RST_IN_L

NB_RST_IN_L

MEM_A_DQ<5>

MEM_A_DQ<5> - @m38a_lib.M38A

15D7 28D3

MEM_B_DQ<20>

MEM_B_DQ<20> - @m38a_lib.M38A

15C4 29C3

NB_RST_IN_L_R

NB_RST_IN_L_R

75C7

MEM_A_DQ<6>

MEM_A_DQ<6> - @m38a_lib.M38A

15D7 28D3

MEM_B_DQ<21>

MEM_B_DQ<21> - @m38a_lib.M38A

15C4 29C3

NB_SB_SYNC_L

NB_SB_SYNC_L

IMVP_VR_ON

IMVP_VR_ON - @m38a_lib.M38A

58D7 75C6

MEM_A_DQ<7>

MEM_A_DQ<7> - @m38a_lib.M38A

5B7 15D7 28D3

MEM_B_DQ<22>

MEM_B_DQ<22> - @m38a_lib.M38A

15C4 29C3

NB_TV_DCONSEL0

NB_TV_DCONSEL0

- @m38a_lib.M38A

14D6

INT_PIRQA_L INT_PIRQB_L

INT_PIRQA_L INT_PIRQB_L

- @m38a_lib.M38A - @m38a_lib.M38A

22A7 26D2 22A7 26D2

MEM_A_DQ<8> MEM_A_DQ<9>

MEM_A_DQ<8> - @m38a_lib.M38A MEM_A_DQ<9> - @m38a_lib.M38A

15C7 28D6 15C7 28D6

MEM_B_DQ<23> MEM_B_DQ<24>

MEM_B_DQ<23> - @m38a_lib.M38A MEM_B_DQ<24> - @m38a_lib.M38A

5A7 15C4 29C3 15C4 29C6

NB_TV_DCONSEL1 NB_VCCSM_LF1

NB_TV_DCONSEL1 - @m38a_lib.M38A NB_VCCSM_LF1 - @m38a_lib.M38A

14C6 16B4

INT_PIRQC_L

INT_PIRQC_L

- @m38a_lib.M38A

22A7 26D2

MEM_A_DQ<10>

MEM_A_DQ<10>

NB_VCCSM_LF2

- @m38a_lib.M38A

16B4

INT_PIRQD_L

INT_PIRQD_L

- @m38a_lib.M38A

22A7 26D2 44B5

MEM_A_DQ<11>

NB_VCCSM_LF4

- @m38a_lib.M38A

16B8

23C8 58C7 60C1 67C6

NB_VCCSM_LF5

- @m38a_lib.M38A

16B8

IMVP_VID<5> IMVP_VID<6>

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

6B7 14B7 5C7 14B6

- @m38a_lib.M38A

15C7 28D6

MEM_B_DQ<25>

MEM_B_DQ<25> - @m38a_lib.M38A

5A7 15C4 29C6

MEM_A_DQ<11>

- @m38a_lib.M38A

15C7 28D6

MEM_B_DQ<26>

MEM_B_DQ<26> - @m38a_lib.M38A

15C4 29C6

INT_SERIRQ - @m38a_lib.M38A

MEM_A_DQ<12>

MEM_A_DQ<12>

- @m38a_lib.M38A

15C7 28D3

MEM_B_DQ<27>

MEM_B_DQ<27> - @m38a_lib.M38A

15C4 29C6

ISENSE_CAL_EN

ISENSE_CAL_EN

58B7 76A8

MEM_A_DQ<13>

MEM_A_DQ<13>

- @m38a_lib.M38A

15C7 28D3

MEM_B_DQ<28>

MEM_B_DQ<28> - @m38a_lib.M38A

15C4 29C3

NB_VTTLF_CAP1

NB_VTTLF_CAP1

- @m38a_lib.M38A

ITPRESET_L

ITPRESET_L - @m38a_lib.M38A

11B3

MEM_A_DQ<14>

MEM_A_DQ<14>

- @m38a_lib.M38A

5B7 15C7 28D3

MEM_B_DQ<29>

MEM_B_DQ<29> - @m38a_lib.M38A

15C4 29C3

NB_VTTLF_CAP2

NB_VTTLF_CAP2

- @m38a_lib.M38A

17A4

ITP_TDO

ITP_TDO - @m38a_lib.M38A

11B3

MEM_A_DQ<15>

MEM_A_DQ<15>

- @m38a_lib.M38A

15C7 28D3

MEM_B_DQ<30>

MEM_B_DQ<30> - @m38a_lib.M38A

15C4 29C3

NB_VTTLF_CAP3

NB_VTTLF_CAP3

- @m38a_lib.M38A

17B4

ITS_ALIVE

ITS_ALIVE - @m38a_lib.M38A

6A7

MEM_A_DQ<16>

MEM_A_DQ<16>

- @m38a_lib.M38A

5B7 15C7 28C6

MEM_B_DQ<31>

MEM_B_DQ<31> - @m38a_lib.M38A

15C4 29C3

NC_AUD_BI_PORT_D_L

NC_AUD_BI_PORT_D_L

- @m38a_lib.M38A

68C7

ITS_PLUGGED_IN

ITS_PLUGGED_IN

NB_VCCSM_LF4

17A4

6A7

MEM_A_DQ<17>

MEM_A_DQ<17>

- @m38a_lib.M38A

15C7 28C6

MEM_B_DQ<32>

MEM_B_DQ<32> - @m38a_lib.M38A

15C4 29B6

NC_AUD_BI_PORT_D_R

NC_AUD_BI_PORT_D_R

- @m38a_lib.M38A

68C7

KBC_MDE - @m38a_lib.M38A

58C2

MEM_A_DQ<18>

MEM_A_DQ<18>

- @m38a_lib.M38A

15C7 28C6

MEM_B_DQ<33>

MEM_B_DQ<33> - @m38a_lib.M38A

15C4 29B6

NC_AUD_BI_PORT_E_L

NC_AUD_BI_PORT_E_L

- @m38a_lib.M38A

68C1

LCD_PWM

LCD_PWM - @m38a_lib.M38A

94B1 94C3

MEM_A_DQ<19>

MEM_A_DQ<19>

- @m38a_lib.M38A

15C7 28C6

MEM_B_DQ<34>

MEM_B_DQ<34> - @m38a_lib.M38A

15B4 29B6

NC_AUD_BI_PORT_E_R

NC_AUD_BI_PORT_E_R

- @m38a_lib.M38A

LCD_PWM_R

LCD_PWM_R - @m38a_lib.M38A

94B2

MEM_A_DQ<20>

MEM_A_DQ<20>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<35>

MEM_B_DQ<35> - @m38a_lib.M38A

15B4 29B6

NC_AUD_VREF_PORT_A

NC_AUD_VREF_PORT_A

- @m38a_lib.M38A

LCD_PWREN_L

LCD_PWREN_L

94C8

MEM_A_DQ<21>

MEM_A_DQ<21>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<36>

MEM_B_DQ<36> - @m38a_lib.M38A

15B4 29B3

NC_AUD_VREF_PORT_C

NC_AUD_VREF_PORT_C

- @m38a_lib.M38A

LCD_PWREN_L_RC

LCD_PWREN_L_RC

94C7

MEM_A_DQ<22>

MEM_A_DQ<22>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<37>

MEM_B_DQ<37> - @m38a_lib.M38A

15B4 29B3

NC_AUD_VREF_PORT_D

NC_AUD_VREF_PORT_D

- @m38a_lib.M38A

LCD_SHOULD_ON

LCD_SHOULD_ON

6A6

MEM_A_DQ<23>

MEM_A_DQ<23>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<38>

MEM_B_DQ<38> - @m38a_lib.M38A

5A7 15B4 29B3

NC_FW_NU1

NC_FW_NU1 - @m38a_lib.M38A

44B3

LED_PP1V05_S0_N

LED_PP1V05_S0_N

- @m38a_lib.M38A

81A4

MEM_A_DQ<24>

MEM_A_DQ<24>

- @m38a_lib.M38A

15C7 28C6

MEM_B_DQ<39>

MEM_B_DQ<39> - @m38a_lib.M38A

15B4 29B3

NC_FW_NU2

NC_FW_NU2 - @m38a_lib.M38A

44B3

LED_PP1V05_S0_P

LED_PP1V05_S0_P

- @m38a_lib.M38A

81A4

MEM_A_DQ<25>

MEM_A_DQ<25>

- @m38a_lib.M38A

5B7 15C7 28C6

MEM_B_DQ<40>

MEM_B_DQ<40> - @m38a_lib.M38A

15B4 29B6

NC_JE350_13

NC_JE350_13

47B1

NC_SMC_P20

NC_SMC_P20 - @m38a_lib.M38A

59D5

SMC_P20 - @m38a_lib.M38A

58D7 59D6

NC_SMC_P21

NC_SMC_P21 - @m38a_lib.M38A

59D5

SMC_P21 - @m38a_lib.M38A

58D7 59D6

NC_SMC_P22

NC_SMC_P22 - @m38a_lib.M38A

59D5

SMC_P22 - @m38a_lib.M38A

58D7 59D6

KBC_MDE

LED_PP1V5_S0_N

- @m38a_lib.M38A

NB_VCCSM_LF2 NB_VCCSM_LF5

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

80A3

MEM_A_DQ<26>

MEM_A_DQ<26>

- @m38a_lib.M38A

15C7 28C6

MEM_B_DQ<41>

MEM_B_DQ<41> - @m38a_lib.M38A

15B4 29B6

80A4

MEM_A_DQ<27>

MEM_A_DQ<27>

- @m38a_lib.M38A

15C7 28C6

MEM_B_DQ<42>

MEM_B_DQ<42> - @m38a_lib.M38A

15B4 29A6

LED_PP1V8_S3_N

LED_PP1V8_S3_N

- @m38a_lib.M38A

79A4

MEM_A_DQ<28>

MEM_A_DQ<28>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<43>

MEM_B_DQ<43> - @m38a_lib.M38A

15B4 29A6

LED_PP1V8_S3_P

LED_PP1V8_S3_P

- @m38a_lib.M38A

79A4

MEM_A_DQ<29>

MEM_A_DQ<29>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<44>

MEM_B_DQ<44> - @m38a_lib.M38A

5A7 15B4 29B3

LPC_AD<0>

LED_PP1V5_S0_N

LPC_AD<0> - @m38a_lib.M38A

21D4 58D7 60C4 67C6

MEM_A_DQ<30>

MEM_A_DQ<30>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<45>

MEM_B_DQ<45> - @m38a_lib.M38A

15B4 29B3

LPC_AD<1>

LPC_AD<1> - @m38a_lib.M38A

21D4 58D7 60C4 67C6

MEM_A_DQ<31>

MEM_A_DQ<31>

- @m38a_lib.M38A

15C7 28C3

MEM_B_DQ<46>

MEM_B_DQ<46> - @m38a_lib.M38A

15B4 29A3

LPC_AD<2>

LPC_AD<2> - @m38a_lib.M38A

21D4 58C7 60C1 67C6

MEM_A_DQ<32>

MEM_A_DQ<32>

- @m38a_lib.M38A

15C7 28B6

MEM_B_DQ<47>

MEM_B_DQ<47> - @m38a_lib.M38A

15B4 29A3

LPC_AD<3>

LPC_AD<3> - @m38a_lib.M38A

21D4 58C7 60C1 67C6

MEM_A_DQ<33>

MEM_A_DQ<33>

- @m38a_lib.M38A

15C7 28B6

MEM_B_DQ<48>

MEM_B_DQ<48> - @m38a_lib.M38A

5A7 15B4 29A6

LPC_FRAME_L

LPC_FRAME_L

21C5 58C7 60C4 67C6

LVDS_A_CLK_N

LVDS_A_CLK_N

LED_PP1V5_S0_P

- @m38a_lib.M38A

LED_PP1V5_S0_P

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

TP_LVDS_A_CLK_N

- @m38a_lib.M38A

- @m38a_lib.M38A

MEM_A_DQ<34>

MEM_A_DQ<34>

- @m38a_lib.M38A

15B7 28B6

MEM_B_DQ<49>

MEM_B_DQ<49> - @m38a_lib.M38A

15B4 29A6

13D5 19D2

MEM_A_DQ<35>

MEM_A_DQ<35>

- @m38a_lib.M38A

15B7 28B6

MEM_B_DQ<50>

MEM_B_DQ<50> - @m38a_lib.M38A

15B4 29A6

19D1

MEM_A_DQ<36>

MEM_A_DQ<36>

- @m38a_lib.M38A

15B7 28B3

MEM_B_DQ<51>

MEM_B_DQ<51> - @m38a_lib.M38A

15B4 29A6

NC_SMC_P23

- @m38a_lib.M38A

68C1 68C1 68C1 68C1

NC_SMC_P23 - @m38a_lib.M38A

59D5

SMC_P23 - @m38a_lib.M38A

58D7 59D6

NC_SMC_P26

NC_SMC_P26 - @m38a_lib.M38A

59D5

SMC_P26 - @m38a_lib.M38A

58D7 59D6

NC_SMC_P27

NC_SMC_P27 - @m38a_lib.M38A

59D5

SMC_P27 - @m38a_lib.M38A

58D7 59D6

LVDS_A_CLK_P

LVDS_A_CLK_P

13C5 19D2

MEM_A_DQ<37>

MEM_A_DQ<37>

- @m38a_lib.M38A

15B7 28B3

MEM_B_DQ<52>

MEM_B_DQ<52> - @m38a_lib.M38A

15B4 29A3

19D1

MEM_A_DQ<38>

MEM_A_DQ<38>

- @m38a_lib.M38A

15B7 28B3

MEM_B_DQ<53>

MEM_B_DQ<53> - @m38a_lib.M38A

15B4 29A3

NC_VOL_DOWN

NC_VOL_DOWN

- @m38a_lib.M38A

68C7

LVDS_A_DATA_N<0> LVDS_A_DATA_N<1>

LVDS_A_DATA_N<0> LVDS_A_DATA_N<1>

- @m38a_lib.M38A - @m38a_lib.M38A

13C5 19D2 13C5 19D2

MEM_A_DQ<39> MEM_A_DQ<40>

MEM_A_DQ<39> MEM_A_DQ<40>

- @m38a_lib.M38A - @m38a_lib.M38A

5B7 15B7 28B3 15B7 28B6

MEM_B_DQ<54> MEM_B_DQ<55>

MEM_B_DQ<54> - @m38a_lib.M38A MEM_B_DQ<55> - @m38a_lib.M38A

15B4 29A3 15B4 29A3

NC_VOL_UP NC_VREG_POK

NC_VOL_UP - @m38a_lib.M38A NC_VREG_POK - @m38a_lib.M38A

68C7 68A3

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<2>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<41>

MEM_A_DQ<41>

- @m38a_lib.M38A

15B7 28B6

MEM_B_DQ<56>

MEM_B_DQ<56> - @m38a_lib.M38A

15B4 29A6

ODD_PWR_EN_L

ODD_PWR_EN_L

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<0>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<42>

MEM_A_DQ<42>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQ<57>

MEM_B_DQ<57> - @m38a_lib.M38A

15B4 29A6

13C5 19D2

MEM_A_DQ<43>

13C5 19D2

TP_LVDS_A_CLK_P

- @m38a_lib.M38A

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<2>

LVDS_BKLTCTL

LVDS_BKLTCTL

LVDS_BKLTEN

LVDS_BKLTEN

LVDS_B_CLK_N

LVDS_B_CLK_N

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

TP_LVDS_BKLTCTL

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_LVDS_BKLTEN

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_LVDS_B_CLK_N

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

26C2 59A8 59B7

MEM_A_DQ<43>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQ<58>

MEM_B_DQ<58> - @m38a_lib.M38A

15B4 29A6

P0V48_SMC_LSREF

P0V48_SMC_LSREF

MEM_A_DQ<44>

MEM_A_DQ<44>

- @m38a_lib.M38A

15B7 28B3

MEM_B_DQ<59>

MEM_B_DQ<59> - @m38a_lib.M38A

15B4 29A6

PANEL_ID

PANEL_ID - @m38a_lib.M38A

94C2 94C3

13D5 19C2

MEM_A_DQ<45>

MEM_A_DQ<45>

- @m38a_lib.M38A

15B7 28B3

MEM_B_DQ<60>

MEM_B_DQ<60> - @m38a_lib.M38A

15A4 29A3

PATA_PWR_EN_L

PATA_PWR_EN_L

23B3 23C3

19C1

MEM_A_DQ<46>

MEM_A_DQ<46>

- @m38a_lib.M38A

15B7 28A3

MEM_B_DQ<61>

MEM_B_DQ<61> - @m38a_lib.M38A

15A4 29A3

PCIE_A_D2R_C_N

PCIE_A_D2R_C_N

- @m38a_lib.M38A

13D5 19C2

MEM_A_DQ<47>

MEM_A_DQ<47>

- @m38a_lib.M38A

5B7 15B7 28A3

MEM_B_DQ<62>

MEM_B_DQ<62> - @m38a_lib.M38A

5A7 15A4 29A3

PCIE_A_D2R_C_P

PCIE_A_D2R_C_P

- @m38a_lib.M38A

- @m38a_lib.M38A

41D5 41D5

19C1

MEM_A_DQ<48>

MEM_A_DQ<48>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQ<63>

MEM_B_DQ<63> - @m38a_lib.M38A

15A4 29A3

PCIE_A_D2R_N

PCIE_A_D2R_N

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<49>

MEM_A_DQ<49>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQS_N<0>

MEM_B_DQS_N<0>

- @m38a_lib.M38A

5A7 15C2 29D6

PCIE_A_D2R_P

PCIE_A_D2R_P

- @m38a_lib.M38A

19D1

MEM_A_DQ<50>

MEM_A_DQ<50>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQS_N<1>

MEM_B_DQS_N<1>

- @m38a_lib.M38A

5A7 15C2 29D6

PCIE_A_R2D_C_N

PCIE_A_R2D_C_N

- @m38a_lib.M38A

22D4 41C3

13C5 19D2

MEM_A_DQ<51>

MEM_A_DQ<51>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQS_N<2>

MEM_B_DQS_N<2>

- @m38a_lib.M38A

5A7 15C2 29C6

PCIE_A_R2D_C_P

PCIE_A_R2D_C_P

- @m38a_lib.M38A

22D4 41C3

PCIE_A_R2D_N

5B8 22D4 41D4 5C8 22D4 41D4

LVDS_B_CLK_P

LVDS_B_CLK_P

19D1

MEM_A_DQ<52>

MEM_A_DQ<52>

- @m38a_lib.M38A

15B7 28A3

MEM_B_DQS_N<3>

MEM_B_DQS_N<3>

- @m38a_lib.M38A

5A7 15C2 29C3

PCIE_A_R2D_N

- @m38a_lib.M38A

LVDS_B_DATA_N<0>

LVDS_B_DATA_N<0>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<53>

MEM_A_DQ<53>

- @m38a_lib.M38A

15B7 28A3

MEM_B_DQS_N<4>

MEM_B_DQS_N<4>

- @m38a_lib.M38A

5A7 15C2 29B6

PCIE_A_R2D_P

PCIE_A_R2D_P

- @m38a_lib.M38A

LVDS_B_DATA_N<1>

LVDS_B_DATA_N<1>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<54>

MEM_A_DQ<54>

- @m38a_lib.M38A

5B7 15B7 28A3

MEM_B_DQS_N<5>

MEM_B_DQS_N<5>

- @m38a_lib.M38A

5A7 15C2 29B3

PCIE_B_D2R_N

PCIE_B_D2R_N

- @m38a_lib.M38A

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<2>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<55>

MEM_A_DQ<55>

- @m38a_lib.M38A

15B7 28A3

MEM_B_DQS_N<6>

MEM_B_DQS_N<6>

- @m38a_lib.M38A

5A7 15C2 29A6

PCIE_B_D2R_P

PCIE_B_D2R_P

- @m38a_lib.M38A

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<0>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<56>

MEM_A_DQ<56>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQS_N<7>

MEM_B_DQS_N<7>

- @m38a_lib.M38A

5A7 15C2 29A3

PCIE_B_R2D_C_N

PCIE_B_R2D_C_N

- @m38a_lib.M38A

22D4 53B7

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<1>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<57>

MEM_A_DQ<57>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQS_P<0>

MEM_B_DQS_P<0>

- @m38a_lib.M38A

5A7 15C2 29D6

PCIE_B_R2D_C_P

PCIE_B_R2D_C_P

- @m38a_lib.M38A

22D4 53B7

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<2>

- @m38a_lib.M38A

13C5 19D2

MEM_A_DQ<58>

MEM_A_DQ<58>

- @m38a_lib.M38A

15B7 28A6

MEM_B_DQS_P<1>

MEM_B_DQS_P<1>

- @m38a_lib.M38A

5A7 15C2 29D6

PCIE_B_R2D_N

PCIE_B_R2D_N

- @m38a_lib.M38A

LVDS_CLKCTLA

LVDS_CLKCTLA

13D5 19C2

MEM_A_DQ<59>

MEM_A_DQ<59>

- @m38a_lib.M38A

5B7 15B7 28A6

MEM_B_DQS_P<2>

MEM_B_DQS_P<2>

- @m38a_lib.M38A

5A7 15C2 29C6

PCIE_B_R2D_P

PCIE_B_R2D_P

- @m38a_lib.M38A

19C1

MEM_A_DQ<60>

MEM_A_DQ<60>

- @m38a_lib.M38A

15A7 28A3

MEM_B_DQS_P<3>

MEM_B_DQS_P<3>

- @m38a_lib.M38A

5A7 15C2 29C3

PCIE_C_D2R_N

PCIE_C_D2R_N

- @m38a_lib.M38A

LVDS_CLKCTLB

LVDS_CLKCTLB

13D5 19C2

MEM_A_DQ<61>

MEM_A_DQ<61>

- @m38a_lib.M38A

15A7 28A3

MEM_B_DQS_P<4>

MEM_B_DQS_P<4>

- @m38a_lib.M38A

5A7 15C2 29B6

19C1

MEM_A_DQ<62>

MEM_A_DQ<62>

- @m38a_lib.M38A

15A7 28A3

MEM_B_DQS_P<5>

MEM_B_DQS_P<5>

- @m38a_lib.M38A

5A7 15C2 29A3

- @m38a_lib.M38A

TP_LVDS_B_CLK_P

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_LVDS_CLKCTLA

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_LVDS_CLKCTLB LVDS_DDC_CLK

LVDS_DDC_CLK

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_LVDS_DDC_CLK

- @m38a_lib.M38A

- @m38a_lib.M38A

13D5 19C2

MEM_A_DQ<63>

MEM_A_DQ<63>

15A7 28A3

MEM_B_DQS_P<6>

MEM_B_DQS_P<6>

19C1

MEM_A_DQS_N<0>

MEM_A_DQS_N<0>

- @m38a_lib.M38A

5B7 15C5 28D6

MEM_B_DQS_P<7>

MEM_B_DQS_P<7>

13D5 19C2

MEM_A_DQS_N<1>

MEM_A_DQS_N<1>

- @m38a_lib.M38A

5B7 15C5 28D6

MEM_B_RAS_L

MEM_B_RAS_L - @m38a_lib.M38A

19C1

MEM_A_DQS_N<2>

MEM_A_DQS_N<2>

- @m38a_lib.M38A

5B7 15C5 28C6

MEM_B_SPD_SA1

MEM_B_SPD_SA1

MEM_A_DQS_N<3>

MEM_A_DQS_N<3>

- @m38a_lib.M38A

5B7 15C5 28C3

MEM_B_WE_L

MEM_B_WE_L - @m38a_lib.M38A

15B2 29B6 30A6

19C1

MEM_A_DQS_N<4>

MEM_A_DQS_N<4>

- @m38a_lib.M38A

5B7 15C5 28B6

MEM_CKE<0>

MEM_CKE<0> - @m38a_lib.M38A

14C4 28C6

93A3 93D2 94A6

LVDS_DDC_DATA

LVDS_DDC_DATA

LVDS_IBG

LVDS_IBG - @m38a_lib.M38A

13D5 19C2

TP_LVDS_IBG

TP_LVDS_DDC_DATA

LVDS_L_CLK_N

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

29A4

LVDS_L_CLK_N

- @m38a_lib.M38A

MEM_A_DQS_N<5>

MEM_A_DQS_N<5>

- @m38a_lib.M38A

5B7 15C5 28B3

MEM_CKE<3..0>

LVDS_L_CLK_P

- @m38a_lib.M38A

93A3 93D2 94A7

MEM_A_DQS_N<6>

MEM_A_DQS_N<6>

- @m38a_lib.M38A

5B7 15C5 28A6

MEM_CKE<1>

LVDS_L_DATA_N<0>

- @m38a_lib.M38A

93A3 93C2 94A6

MEM_A_DQS_N<7>

MEM_A_DQS_N<7>

- @m38a_lib.M38A

5B7 15C5 28A3

MEM_CKE<2>

LVDS_L_DATA_N<1>

- @m38a_lib.M38A

93A3 93C2 94A7

MEM_A_DQS_P<0>

MEM_A_DQS_P<0>

- @m38a_lib.M38A

5B7 15C5 28D6

MEM_CKE<3>

LVDS_L_DATA_N<2>

LVDS_L_DATA_N<2>

- @m38a_lib.M38A

93A3 93C2 94A6

MEM_A_DQS_P<1>

MEM_A_DQS_P<1>

- @m38a_lib.M38A

5B7 15C5 28D6

MEM_CLK_N<0>

LVDS_L_DATA_N<3>

LVDS_L_DATA_N<3>

- @m38a_lib.M38A

93A3 94A6

MEM_A_DQS_P<2>

MEM_A_DQS_P<2>

- @m38a_lib.M38A

5B7 15C5 28C6

MEM_CLK_N<1>

MEM_CLK_N<1> - @m38a_lib.M38A

14D4 28A3

LVDS_L_DATA_P<0>

LVDS_L_DATA_P<0>

- @m38a_lib.M38A

93A3 93D2 94A7

MEM_A_DQS_P<3>

MEM_A_DQS_P<3>

- @m38a_lib.M38A

5B7 15C5 28C3

MEM_CLK_N<2>

MEM_CLK_N<2> - @m38a_lib.M38A

14D4 29A3

LVDS_L_DATA_P<1>

LVDS_L_DATA_P<1>

- @m38a_lib.M38A

93A3 93C2 94A6

MEM_A_DQS_P<4>

MEM_A_DQS_P<4>

- @m38a_lib.M38A

5B7 15C5 28B6

MEM_CLK_N<3>

MEM_CLK_N<3> - @m38a_lib.M38A

14D4 29D3

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<2>

- @m38a_lib.M38A

93A3 93C2 94A7

MEM_A_DQS_P<5>

MEM_A_DQS_P<5>

- @m38a_lib.M38A

5B7 15C5 28A3

MEM_CLK_P<0>

MEM_CLK_P<0> - @m38a_lib.M38A

14D4 28D3

LVDS_L_DATA_P<3>

LVDS_L_DATA_P<3>

- @m38a_lib.M38A

93A3 94A7

MEM_A_DQS_P<6>

5B7 15C5 28A6

MEM_CLK_P<1>

MEM_CLK_P<1> - @m38a_lib.M38A

14D4 28A3

93B3 94B6

MEM_CLK_P<2> - @m38a_lib.M38A

14D4 29A3

14C4 28C3

MEM_CKE<2> - @m38a_lib.M38A

14C4 29C6

MEM_CKE<3> - @m38a_lib.M38A

14C4 29C3 14D4 28D3

MEM_A_DQS_P<6>

- @m38a_lib.M38A

LVDS_U_CLK_N

- @m38a_lib.M38A

MEM_A_DQS_P<7>

MEM_A_DQS_P<7>

- @m38a_lib.M38A

5B7 15C5 28A3

MEM_CLK_P<2>

LVDS_U_CLK_P

LVDS_U_CLK_P

- @m38a_lib.M38A

93B3 94A7

MEM_A_RAS_L

MEM_A_RAS_L - @m38a_lib.M38A

15B5 28B3 30B6

MEM_CLK_P<3>

MEM_CLK_P<3> - @m38a_lib.M38A

14D4 29D3

LVDS_U_DATA_N<0>

LVDS_U_DATA_N<0>

- @m38a_lib.M38A

93B3 94B7

MEM_A_WE_L

MEM_A_WE_L - @m38a_lib.M38A

15B5 28B6 30B6

MEM_CS_L<0>

MEM_CS_L<0> - @m38a_lib.M38A

14C4 28B3

LVDS_U_DATA_N<1>

LVDS_U_DATA_N<1>

- @m38a_lib.M38A

93B3 94B7

MEM_B_A<0>

MEM_B_A<0> - @m38a_lib.M38A

15C2 29B3 30B5

MEM_CS_L<3..0>

MEM_CS_L<3..0>

30D6

LVDS_U_DATA_N<2>

LVDS_U_DATA_N<2>

- @m38a_lib.M38A

93B3 94B7

MEM_B_A<1>

MEM_B_A<1> - @m38a_lib.M38A

15C2 29B6 30B5

MEM_CS_L<1>

MEM_CS_L<1> - @m38a_lib.M38A

LVDS_U_DATA_N<3>

LVDS_U_DATA_N<3>

- @m38a_lib.M38A

93B3 94A6

MEM_B_A<2>

MEM_B_A<2> - @m38a_lib.M38A

15C2 29B3 30B5

MEM_CS_L<2>

MEM_CS_L<2> - @m38a_lib.M38A

LVDS_U_DATA_P<0>

LVDS_U_DATA_P<0>

- @m38a_lib.M38A

93B3 94B6

MEM_B_A<3>

MEM_B_A<3> - @m38a_lib.M38A

15B2 29B6 30B5

MEM_CS_L<3>

MEM_CS_L<3> - @m38a_lib.M38A

14C4 29B6

LVDS_U_DATA_P<1>

LVDS_U_DATA_P<1>

- @m38a_lib.M38A

93B3 94B6

MEM_B_A<4>

MEM_B_A<4> - @m38a_lib.M38A

15B2 29B3 30B5

MEM_ODT<0>

MEM_ODT<0> - @m38a_lib.M38A

14C4 28B3

LVDS_U_DATA_P<2>

LVDS_U_DATA_P<2>

- @m38a_lib.M38A

93B3 94B6

MEM_B_A<5>

MEM_B_A<5> - @m38a_lib.M38A

15B2 29B6 30B5

MEM_ODT<3..0>

MEM_ODT<3..0>

LVDS_U_DATA_P<3>

- @m38a_lib.M38A

93B3 94A7

MEM_B_A<6>

MEM_B_A<6> - @m38a_lib.M38A

15B2 29C3 30B5

MEM_ODT<1>

MEM_ODT<1> - @m38a_lib.M38A

14C4 28B6

LVDS_VDDEN - @m38a_lib.M38A

13D5 19C2

MEM_B_A<7>

MEM_B_A<7> - @m38a_lib.M38A

15B2 29C3 30B5

MEM_ODT<2>

MEM_ODT<2> - @m38a_lib.M38A

14C4 29B3

TP_LVDS_VDDEN

19C1

MEM_B_A<8>

MEM_B_A<8> - @m38a_lib.M38A

15B2 29C6 30B5

MEM_ODT<3>

MEM_ODT<3> - @m38a_lib.M38A

14C4 29B6

13D5 19C2

MEM_B_A<9>

MEM_B_A<9> - @m38a_lib.M38A

15B2 29C6 30B5

MEM_RCOMP

MEM_RCOMP - @m38a_lib.M38A

14C4

- @m38a_lib.M38A - @m38a_lib.M38A

TP_PCIE_C_R2D_C_N

PCIE_D_D2R_N

TP_PCIE_D_D2R_N PCIE_D_D2R_P

PCIE_D_D2R_P

PCIE_D_R2D_C_N

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_D_D2R_P

- @m38a_lib.M38A - @m38a_lib.M38A

TP_PCIE_D_R2D_C_N PCIE_D_R2D_C_P PCIE_E_D2R_N

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_E_D2R_N PCIE_E_D2R_P

PCIE_E_D2R_P

PCIE_E_R2D_C_N

PCIE_E_R2D_C_N

PCIE_E_R2D_C_P

PCIE_E_R2D_C_P

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_E_D2R_P

- @m38a_lib.M38A - @m38a_lib.M38A

TP_PCIE_E_R2D_C_N

PCIE_F_D2R_N

PCIE_F_D2R_N

PCIE_F_D2R_P

PCIE_F_D2R_P

PCIE_F_R2D_C_N

PCIE_F_R2D_C_N

PCIE_F_R2D_C_P

PCIE_F_R2D_C_P

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_E_R2D_C_P

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_F_D2R_N

30D6

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_D_R2D_C_P PCIE_E_D2R_N

- @m38a_lib.M38A

- @m38a_lib.M38A

PCIE_D_R2D_C_N PCIE_D_R2D_C_P

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_C_R2D_C_P PCIE_D_D2R_N

14C4 29B3

LVDS_VDDEN

- @m38a_lib.M38A

PCIE_C_R2D_C_P

14C4 28B6

LVDS_U_DATA_P<3>

- @m38a_lib.M38A

PCIE_C_R2D_C_N

PCIE_C_R2D_C_P

30D6

MEM_CKE<1> - @m38a_lib.M38A

MEM_CLK_N<0> - @m38a_lib.M38A

- @m38a_lib.M38A

PCIE_C_R2D_C_N

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_C_D2R_P

5A7 15C2 29A3

LVDS_L_DATA_N<1>

- @m38a_lib.M38A

PCIE_C_D2R_P

5A7 15C2 29A6

LVDS_L_DATA_N<0>

MEM_CKE<3..0>

PCIE_C_D2R_P

15B2 29B3 30A6

LVDS_L_CLK_P

LVDS_U_CLK_N

TP_PCIE_C_D2R_N

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_PCIE_F_D2R_P

- @m38a_lib.M38A - @m38a_lib.M38A

TP_PCIE_F_R2D_C_N

- @m38a_lib.M38A

- @m38a_lib.M38A

41C5 41C5 5B8 22D4 53C7 5B8 22D4 53C7

53B6 53B6 22D4 54D8 54D6 22D4 54D8 54D6

22D4 54D8 54D6 22D4 54C8 54C6 22D4 54C8 54C6 22D4 54D8 54D6 22D4 54D8 54D6 22C4 54C8 54C6 22C4 54C8 54C6 22C4 54C8 54C6 22C4 54C8 54C6 22C4 54B8 54B6 22C4 54B8 54B6 22C4 54C8 54C6 22C4 54B8

LVDS_VREFH - @m38a_lib.M38A

19C1

MEM_B_A<10>

MEM_B_A<10> - @m38a_lib.M38A

15B2 29B6 30B5

MEM_RCOMP_L

MEM_RCOMP_L - @m38a_lib.M38A

14C4

PCIE_WAKE_L

PCIE_WAKE_L

LVDS_VREFL

LVDS_VREFL - @m38a_lib.M38A

13D5 19C2

MEM_B_A<11>

MEM_B_A<11> - @m38a_lib.M38A

15B2 29C3 30A5

MEM_VREF

MEM_VREF - @m38a_lib.M38A

5C4 28C7 28D6 29D6

PCI_AD<0>

PCI_AD<0> - @m38a_lib.M38A

22B7 44D5

TP_LVDS_VREFL

19C1

MEM_B_A<12>

MEM_B_A<12> - @m38a_lib.M38A

15B2 29C6 30A5

MEM_VREF_NB_0

MEM_VREF_NB_0

- @m38a_lib.M38A

5B7 14C4 19B6

PCI_AD<1>

PCI_AD<1> - @m38a_lib.M38A

22B7 44D5

15B2 29B3 30A5

MEM_VREF_NB_1

MEM_VREF_NB_1

- @m38a_lib.M38A

15D2 29B6

TP_LVDS_VREFH

MEMVTT_VREF

MEMVTT_VREF

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

31B4

MEM_B_A<13>

MEM_B_A<13> - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

54B6 23C8 41C4 53C7

5B7 14C4 19B7

PCI_AD<2>

PCI_AD<2> - @m38a_lib.M38A

22B7 44D5

15C5 28B3

MEM_B_BS<0>

MEM_B_BS<0> - @m38a_lib.M38A

NB_BSEL<0>

NB_BSEL<0> - @m38a_lib.M38A

14C6 34B8

PCI_AD<3>

PCI_AD<3> - @m38a_lib.M38A

22B7 44D5

30C6

MEM_B_BS<2..0>

MEM_B_BS<2..0>

30A6

NB_BSEL<1>

NB_BSEL<1> - @m38a_lib.M38A

14C6 34B8

PCI_AD<4>

PCI_AD<4> - @m38a_lib.M38A

22B7 44D5

15C5 28B6

MEM_B_BS<1>

MEM_B_BS<1> - @m38a_lib.M38A

15D2 29B3

NB_BSEL<2>

NB_BSEL<2> - @m38a_lib.M38A

14C6 34A8

PCI_AD<5>

PCI_AD<5> - @m38a_lib.M38A

22B7 44C5

15C5 28B3

MEM_B_BS<2>

MEM_B_BS<2> - @m38a_lib.M38A

15D2 29C6

NB_CFG<3>

NB_CFG<3> - @m38a_lib.M38A

14C6

PCI_AD<6>

PCI_AD<6> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<3> - @m38a_lib.M38A

15B5 28B6

MEM_B_CAS_L

MEM_B_CAS_L - @m38a_lib.M38A

15D2 29B6 30A6

NB_CFG<4>

NB_CFG<4> - @m38a_lib.M38A

14C6

PCI_AD<7> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<4> - @m38a_lib.M38A

15B5 28B3

MEM_B_DM<0>

MEM_B_DM<0> - @m38a_lib.M38A

15D2 29D3

NB_CFG<5>

NB_CFG<5> - @m38a_lib.M38A

14C6 20C7

PCI_AD<8>

PCI_AD<8> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<5> - @m38a_lib.M38A

15B5 28B6

MEM_B_DM<1>

MEM_B_DM<1> - @m38a_lib.M38A

15D2 29D3

NB_CFG<6>

NB_CFG<6> - @m38a_lib.M38A

14C6

PCI_AD<9>

PCI_AD<9> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<6> - @m38a_lib.M38A

15B5 28C3

MEM_B_DM<2>

MEM_B_DM<2> - @m38a_lib.M38A

15D2 29C3

NB_CFG<7>

NB_CFG<7> - @m38a_lib.M38A

14C6 20C7

PCI_AD<10>

PCI_AD<10> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<7> - @m38a_lib.M38A

15B5 28C3

MEM_B_DM<3>

MEM_B_DM<3> - @m38a_lib.M38A

15C2 29C6

NB_CFG<8>

NB_CFG<8> - @m38a_lib.M38A

14C6

PCI_AD<11>

PCI_AD<11> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<8>

MEM_A_A<8> - @m38a_lib.M38A

15B5 28C6

MEM_B_DM<4>

MEM_B_DM<4> - @m38a_lib.M38A

15C2 29B3

NB_CFG<9>

NB_CFG<9> - @m38a_lib.M38A

14C6 20B7

PCI_AD<12>

PCI_AD<12> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<9>

MEM_A_A<9> - @m38a_lib.M38A

15B5 28C6

MEM_B_DM<5>

MEM_B_DM<5> - @m38a_lib.M38A

15C2 29A6

NB_CFG<10>

NB_CFG<10> - @m38a_lib.M38A

14C6

PCI_AD<13>

PCI_AD<13> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<10>

MEM_A_A<10>

- @m38a_lib.M38A

15B5 28B6

MEM_B_DM<6>

MEM_B_DM<6> - @m38a_lib.M38A

15C2 29A3

NB_CFG<11>

NB_CFG<11> - @m38a_lib.M38A

14C6

PCI_AD<14>

PCI_AD<14> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<11>

MEM_A_A<11>

- @m38a_lib.M38A

15B5 28C3

MEM_B_DM<7>

MEM_B_DM<7> - @m38a_lib.M38A

15C2 29A6

NB_CFG<12>

NB_CFG<12> - @m38a_lib.M38A

14C6

PCI_AD<15>

PCI_AD<15> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<12>

MEM_A_A<12>

- @m38a_lib.M38A

15B5 28C6

MEM_B_DQ<0>

MEM_B_DQ<0> - @m38a_lib.M38A

15D4 29D6

NB_CFG<13>

NB_CFG<13> - @m38a_lib.M38A

14C6

PCI_AD<16>

PCI_AD<16> - @m38a_lib.M38A

22B7 44C5

MEM_A_A<0>

MEM_A_A<0> - @m38a_lib.M38A

MEM_A_A<13..0>

MEM_A_A<13..0>

MEM_A_A<1>

MEM_A_A<1> - @m38a_lib.M38A

MEM_A_A<2>

MEM_A_A<2> - @m38a_lib.M38A

MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>

8

- @m38a_lib.M38A

 

7

6

- @m38a_lib.M38A

 

5

 

4

PCI_AD<7>

 

3

 

B

22D4 54D8 54D6

LVDS_VREFH

TP_PCIE_F_R2D_C_P

C

22A6 26C3

SB_GPIO5 - @m38a_lib.M38A

- @m38a_lib.M38A

D

14B6 22A6

INT_SERIRQ

- @m38a_lib.M38A

1

14C6

MEM_A_BS<0>

75B4

IMVP_VID<5>

A

 

4

MEM_B_DQ<1>

75B7

IMVP6_VO_R - @m38a_lib.M38A

IMVP_VID<4>

B

 

5

15B5 28B3

75A4 75B6

IMVP6_VDIFF_RC

IMVP6_VO - @m38a_lib.M38A

IMVP6_VO_R

- @m38a_lib.M38A

 

75A4 75B4

IMVP6_VDIFF_RC IMVP6_VO

IMVP_VID<6>

C

- @m38a_lib.M38A

6 MEM_A_A<13> - @m38a_lib.M38A

2

A

 

1

 

8

D

 

5

PEG_R2D_C_P<1>

- @m38a_lib.M38A

13B3 84B5

PCI_AD<18>

PCI_AD<18> - @m38a_lib.M38A

22B7 44C5

PEG_R2D_C_P<2>

PEG_R2D_C_P<2>

- @m38a_lib.M38A

13B3 84B5

PCI_AD<19>

PCI_AD<19> - @m38a_lib.M38A

22A7 44C6

PEG_R2D_C_P<3>

PEG_R2D_C_P<3>

- @m38a_lib.M38A

13B3 84B5

PP2V5_S0_GPU_TPVDD

PP2V5_S0_GPU_TPVDD

PCI_AD<20>

PCI_AD<20> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<4>

PEG_R2D_C_P<4>

- @m38a_lib.M38A

13B3 84B5

PP2V5_S0_GPU_TXVDDR

PP2V5_S0_GPU_TXVDDR

PCI_AD<21>

PCI_AD<21> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<5>

PEG_R2D_C_P<5>

- @m38a_lib.M38A

13B3 84B5

PCI_AD<22>

PCI_AD<22> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<6>

PEG_R2D_C_P<6>

- @m38a_lib.M38A

13B3 84C5

PP2V5_S0_GPU_VDD1DI

PP2V5_S0_GPU_VDD1DI

PCI_AD<23>

PCI_AD<23> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<7>

PEG_R2D_C_P<7>

- @m38a_lib.M38A

13B3 84C5

PCI_AD<24>

PCI_AD<24> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<8>

PEG_R2D_C_P<8>

- @m38a_lib.M38A

13B3 84C5

PP2V5_S0_GPU_VDD2DI

PP2V5_S0_GPU_VDD2DI

PCI_AD<25>

PCI_AD<25> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<9>

PEG_R2D_C_P<9>

- @m38a_lib.M38A

13B3 84C5

PCI_AD<26>

PCI_AD<26> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<10>

PEG_R2D_C_P<10>

- @m38a_lib.M38A

13B3 84C5

PP3V3R12V_LCD_CONN

PP3V3R12V_LCD_CONN

PCI_AD<27>

PCI_AD<27> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<11>

PEG_R2D_C_P<11>

- @m38a_lib.M38A

13B3 84D5

PP3V3_AUDIO_SPDIF_EM

PP3V3_AUDIO_SPDIF_EMI

PCI_AD<28>

PCI_AD<28> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<12>

PEG_R2D_C_P<12>

- @m38a_lib.M38A

13A3 84D5

I

PCI_AD<29>

PCI_AD<29> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<13>

PEG_R2D_C_P<13>

- @m38a_lib.M38A

13A3 84D5

PP3V3_AUDIO_SPDIF_JA

PCI_AD<30>

PCI_AD<30> - @m38a_lib.M38A

22A7 44C5

PEG_R2D_C_P<14>

PEG_R2D_C_P<14>

- @m38a_lib.M38A

13A3 84D5

CK

- @m38a_lib.M38A

PP2V5_S0_GPU_PVDD_F

PP2V5_S0_GPU_PVDD_F

-

91A6

SB_INTVRMEN - @m38a_lib.M38A

93C7

-

93C8

-

93B8 @m38a_lib.M38A -

PEG_R2D_C_P<15>

PEG_R2D_C_P<15>

13A3 84D5

PP3V3_AVCC_SMC

PP3V3_AVCC_SMC

PEG_R2D_N<0>

PEG_R2D_N<0>

- @m38a_lib.M38A

84D4

PP3V3_AVREF_SMC

PP3V3_AVREF_SMC

PCI_CLK_PORT80

PCI_CLK_PORT80

34B4 60C1

PEG_R2D_N<1>

PEG_R2D_N<1>

- @m38a_lib.M38A

84D4

PP3V3_FW_ESD

PCI_CLK_SB

PCI_CLK_SB - @m38a_lib.M38A

5C8 22A6 34B4

PEG_R2D_N<2>

PEG_R2D_N<2>

- @m38a_lib.M38A

84D4

PP3V3_FW_ESD_F

- @m38a_lib.M38A

SMB_BSB_DATA

SMB_BSB_DATA

PP3V3_INTERCON

- @m38a_lib.M38A

72C7

SMB_LINK_ALERT_L

SMB_LINK_ALERT_L

94C6

SMC_ADAPTER_EN

SMC_ADAPTER_EN

SMC_ANALOG_ID

SMC_ANALOG_ID

SMC_BATT_CHG_EN

NC_SMC_ANALOG_ID - @m38a_lib.M38A SMC_BATT_CHG_EN - @m38a_lib.M38A

34C4 58C7

PEG_R2D_N<3>

PEG_R2D_N<3>

- @m38a_lib.M38A

84D4

PP3V3_INTERCON

34C4 67C6

PEG_R2D_N<4>

PEG_R2D_N<4>

- @m38a_lib.M38A

84C4

PP3V3_LCD_SW

22B6 44B5

PEG_R2D_N<5>

PEG_R2D_N<5>

- @m38a_lib.M38A

84C4

PP3V3_S0_CK410_VDD48

PP3V3_S0_CK410_VDD48

- @m38a_lib.M38A

22B6 44B5

PEG_R2D_N<6>

PEG_R2D_N<6>

- @m38a_lib.M38A

84C4

- @m38a_lib.M38A - @m38a_lib.M38A

22B6 44B5 22B6 44B5

PEG_R2D_N<7> PEG_R2D_N<8>

PEG_R2D_N<7> PEG_R2D_N<8>

- @m38a_lib.M38A - @m38a_lib.M38A

84C4 84C4

PP3V3_S0_CK410_VDDA

PP3V3_S0_CK410_VDDA @m38a_lib.M38A

PCI_DEVSEL_L

PCI_DEVSEL_L

22A6 26D2 44B5

PEG_R2D_N<9>

PEG_R2D_N<9>

- @m38a_lib.M38A

84C4

PP3V3_S0_CK410_VDD_C

PP3V3_S0_CK410_VDD_CP U_SRC -

PCI_FRAME_L

PCI_FRAME_L

PP3V3_LCD_SW - @m38a_lib.M38A

PEG_R2D_N<10>

- @m38a_lib.M38A

84B4

PU_SRC

PEG_R2D_N<11>

- @m38a_lib.M38A

84B4

PP3V3_S0_CK410_VDD_P

PEG_R2D_N<12>

- @m38a_lib.M38A

84B4

CI

PEG_R2D_N<13>

PEG_R2D_N<13>

- @m38a_lib.M38A

84B4

PP3V3_S0_CK410_VDD_R

33D5

-

33D6 SMC_BATT_ISENSE 33D5

PCI_LOCK_L - @m38a_lib.M38A

22A6 26D2

PEG_R2D_N<14>

PEG_R2D_N<14>

- @m38a_lib.M38A

84B4

EF

PCI_PAR - @m38a_lib.M38A

22A6 44B5

PEG_R2D_N<15>

PEG_R2D_N<15>

- @m38a_lib.M38A

84B4

PP3V3_S0_IMVP6_3V3

PP3V3_S0_IMVP6_3V3

PCI_PERR_L

PCI_PERR_L - @m38a_lib.M38A

22A6 26D2 44B5

PEG_R2D_P<0>

PEG_R2D_P<0>

- @m38a_lib.M38A

84D4

PP3V3_S5_FW_VDDA

PP3V3_S5_FW_VDDA

PCI_PME_FW_L

PCI_PME_FW_L

22B5 44B5

PEG_R2D_P<1>

PEG_R2D_P<1>

- @m38a_lib.M38A

84D4

PCI_REQ0_L

PCI_REQ0_L - @m38a_lib.M38A

22B6 26D2

PEG_R2D_P<2>

PEG_R2D_P<2>

- @m38a_lib.M38A

84D4

PCI_REQ1_L

PCI_REQ1_L - @m38a_lib.M38A

22B6 26D2 44B5

PEG_R2D_P<3>

PEG_R2D_P<3>

- @m38a_lib.M38A

84D4

PP3V3_TPM_3VSB

PP3V3_TPM_3VSB

PCI_REQ2_L

PCI_REQ2_L - @m38a_lib.M38A

22B6 26D2

PEG_R2D_P<4>

PEG_R2D_P<4>

- @m38a_lib.M38A

84D4

PP4V5_AUDIO_ANALOG

PP4V5_AUDIO_ANALOG

PCI_REQ3_L

PCI_REQ3_L - @m38a_lib.M38A

22B6 26D2

PEG_R2D_P<5>

PEG_R2D_P<5>

- @m38a_lib.M38A

84C4

PP5V_BNDI_LE340

PP5V_BNDI_LE340

33C5

@m38a_lib.M38A

PP3V3_S5_SB_RTC

PP3V3_S5_SB_RTC

PP3V3_SO_2V5REG_R

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

PP3V3_SO_2V5REG_R

- @m38a_lib.M38A

- @m38a_lib.M38A -

@m38a_lib.M38A

- @m38a_lib.M38A

PCI_RST_FW_L

PCI_RST_FW_L

44A7 44B5

PEG_R2D_P<6>

PEG_R2D_P<6>

- @m38a_lib.M38A

84C4

PP5V_S0_DDC

PCI_RST_L

PCI_RST_L - @m38a_lib.M38A

22A6 44A8

PEG_R2D_P<7>

PEG_R2D_P<7>

- @m38a_lib.M38A

84C4

PP5V_S0_DDC_FUSE

PP5V_S0_DDC_FUSE

PCI_SERR_L

PCI_SERR_L - @m38a_lib.M38A

22A6 26D2 44B5

PEG_R2D_P<8>

PEG_R2D_P<8>

- @m38a_lib.M38A

84C4

PP5V_S0_GPUVCORE_VCC

PP5V_S0_GPUVCORE_VCC

- @m38a_lib.M38A

84C4

PP5V_S0_DDC - @m38a_lib.M38A - @m38a_lib.M38A -

75D6

SMC_BATT_ISET

44D5 45C6

- @m38a_lib.M38A

- @m38a_lib.M38A

SMC_BATT_ISENSE

5D2 21D6 24B3 25A3 26D7

SMC_BATT_TRICKLE_EN_ L

- @m38a_lib.M38A

59B5

SMC_FWIRE_ISENSE

- @m38a_lib.M38A

58D5 59B6

- @m38a_lib.M38A - @m38a_lib.M38A

SMC_BATT_TRICKLE_EN _L -

97D4

SMC_BATT_VSET

- @m38a_lib.M38A

NC_SMC_BATT_VSET

- @m38a_lib.M38A

97D5

SMC_BC_ACOK

SMC_BC_ACOK

85D7 88D8

SMC_BS_ALRT_L

SMC_BS_ALRT_L

- @m38a_lib.M38A

SMC_CASE_OPEN

- @m38a_lib.M38A

- @m38a_lib.M38A

22A6 26D2 44B5

PEG_R2D_P<9>

PEG_R2D_P<9>

22A6 26D2 44B5

PEG_R2D_P<10>

PEG_R2D_P<10>

- @m38a_lib.M38A

84B4

PP5V_S0_IMVP6_VDD

13D3

PEG_R2D_P<11>

PEG_R2D_P<11>

- @m38a_lib.M38A

84B4

PP5V_S0_SB_V5REF

- @m38a_lib.M38A

84D3

PEG_R2D_P<12>

PEG_R2D_P<12>

- @m38a_lib.M38A

84B4

PP5V_S3_BNDI

PP5V_S3_BNDI - @m38a_lib.M38A

47B2 47D1

- @m38a_lib.M38A

84D3

PEG_R2D_P<13>

PEG_R2D_P<13>

- @m38a_lib.M38A

84B4

PP5V_S5_SB_V5REF_SUS

PP5V_S5_SB_V5REF_SUS

24D5 25C7

84D3

PEG_R2D_P<14>

47D6

SMC_EXCARD_CP

SMC_EXCARD_CP

47D4

SMC_EXCARD_PWR_EN

SMC_EXCARD_PWR_EN

PEG_D2R_C_N<2>

- @m38a_lib.M38A

SMC_CASE_OPEN 75D6 24D5 25D7

59B5 59B6

59D5 58D7 59D6 59D5

SMC_CPU_ISENSE

SMC_CPU_ISENSE

SMC_CPU_RESET_3_3_L

SMC_CPU_RESET_3_3_L

SMC_CPU_VSENSE

SMC_CPU_VSENSE

- @m38a_lib.M38A -

58B5 59D6 59D5 58C5 59B4 58C5 59B4 58C5 59C1 58D5 76D2 58B5 59A7

@m38a_lib.M38A - @m38a_lib.M38A

58D5 76B2

PEG_R2D_P<14>

- @m38a_lib.M38A

84D3

PEG_R2D_P<15>

PEG_R2D_P<15>

- @m38a_lib.M38A

84B4

PP5V_USB2_PORT0

PP5V_USB2_PORT0

84C3

PEG_RESET_L

PEG_RESET_L - @m38a_lib.M38A

6B7 84A5

PP5V_USB2_PORT0_F

PP5V_USB2_PORT0_F

PEG_D2R_C_N<5>

PEG_D2R_C_N<5>

- @m38a_lib.M38A

84C3

PLT_RST_L

PLT_RST_L - @m38a_lib.M38A

6C8 22A6

PP5V_USB2_PORT1

PP5V_USB2_PORT1

PEG_D2R_C_N<6>

PEG_D2R_C_N<6>

- @m38a_lib.M38A

84C3

PM_BATLOW_L

PM_BATLOW_L - @m38a_lib.M38A

23C1 58B7

PP5V_USB2_PORT1_F

PP5V_USB2_PORT1_F

PEG_D2R_C_N<7>

PEG_D2R_C_N<7>

- @m38a_lib.M38A

84C3

PM_BMBUSY_L

PM_BMBUSY_L - @m38a_lib.M38A

14B6 23C5

PP5V_USB2_PORT2

PP5V_USB2_PORT2

84C3

PM_CLKRUN_L

PM_CLKRUN_L - @m38a_lib.M38A

5B8 23C8 44B5 58C5 60C4

PP5V_USB2_PORT2_F

PP5V_USB2_PORT2_F

67C6

PP12V_AUD_SPKRAMP_PL

PP12V_AUD_SPKRAMP_PLA NE -

72D5

SMC_EXTAL

SMC_EXTAL - @m38a_lib.M38A

PM_DPRSLPVR PM_EXTTS_L<0>

PM_DPRSLPVR - @m38a_lib.M38A PM_EXTTS_L<0> - @m38a_lib.M38A

14B7 23C3 75C7 14B7 58B7 59C5

ANE PP12V_L7502

@m38a_lib.M38A PP12V_L7502 - @m38a_lib.M38A

76D7

SMC_EXTSMI_L SMC_FAN_0_CTL

SMC_EXTSMI_L - @m38a_lib.M38A SMC_FAN_0_CTL - @m38a_lib.M38A

23B8 58B7 58B7 65D8

DIMM_OVERTEMP_L

28C3 29C3 59C6

PP12V_S5_CPU_REG

PP12V_S5_CPU_REG

75C3 75D4 75D7 76C8 76D6

FAN_RPM0 - @m38a_lib.M38A

65D7

23C3 58D7

PPFW_PORT0_VP

PPFW_PORT0_VP

- @m38a_lib.M38A

46D2

SMC_FAN_0_TACH

SMC_FAN_0_TACH

PPFW_PORT1_VP

- @m38a_lib.M38A

46B2 46D1

SMC_FAN_1_CTL

SMC_FAN_1_CTL

PPFW_PORTS_VP

- @m38a_lib.M38A

PEG_D2R_C_N<3>

PEG_D2R_C_N<3>

PEG_D2R_C_N<4>

- @m38a_lib.M38A

PEG_D2R_C_N<4>

- @m38a_lib.M38A

PEG_D2R_C_N<8>

PEG_D2R_C_N<8>

- @m38a_lib.M38A

PEG_D2R_C_N<9>

PEG_D2R_C_N<9>

- @m38a_lib.M38A

PEG_D2R_C_N<10> PEG_D2R_C_N<11>

PEG_D2R_C_N<10> PEG_D2R_C_N<11>

- @m38a_lib.M38A - @m38a_lib.M38A

84B3 84B3

PEG_D2R_C_N<12>

PEG_D2R_C_N<12>

- @m38a_lib.M38A

84B3

PEG_D2R_C_N<13>

PEG_D2R_C_N<13>

- @m38a_lib.M38A

84B3

PM_LAN_ENABLE

PM_LAN_ENABLE

PEG_D2R_C_N<14>

PEG_D2R_C_N<14>

- @m38a_lib.M38A

84B3

PM_PWRBTN_L

PM_PWRBTN_L - @m38a_lib.M38A

- @m38a_lib.M38A

84B4

-

59B5 59B6

58B5 59D6

@m38a_lib.M38A SMC_BATT_VSET

PCI_TRDY_L - @m38a_lib.M38A

- @m38a_lib.M38A

59D5 58D5 59B6 59B5

PEG_D2R_C_N<0>

- @m38a_lib.M38A

58A7 59C6

58D5 59B6

NC_SMC_BATT_TRICKLE _EN_L 74C4 74D8

@m38a_lib.M38A

58D5 59D5 59D3

59C5 58D7 59D6

- @m38a_lib.M38A

PEG_D2R_C_N<1>

PP5V_S0_SB_V5REF

2 3D5

- @m38a_lib.M38A

SMC_BATT_ISET

84C3

- @m38a_lib.M38A

- @m38a_lib.M38A

@m38a_lib.M38A

23C3 58D7

SMC_DCIN_ISENSE - @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

SMC_DCIN_ISENSE

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

47C6

TP_SMC_EXCARD_PWR_E N -

47C5

@m38a_lib.M38A

47B6

SMC_EXCARD_PWR_OC_L

47B4

SMC_EXCARD_PWR_OC_L

-

58D5 76D5 59C5

59C3 58B7 59C4

@m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

58C3 59B8

58B7 65C8 58B7 65B8

PEG_D2R_C_N<15>

PEG_D2R_C_N<15>

84B3

PM_PWROK

PM_PWROK - @m38a_lib.M38A

77C5

FAN_RPM1 - @m38a_lib.M38A

65B7

PEG_D2R_C_P<0>

- @m38a_lib.M38A

84D3

PM_RI_L

PM_RI_L - @m38a_lib.M38A

23D5

PPFW_PORT0_VP_FL

PPFW_PORT0_VP_FL

- @m38a_lib.M38A

46C2

SMC_FAN_1_TACH

SMC_FAN_1_TACH

58B7 65A8

PEG_D2R_C_P<1>

PEG_D2R_C_P<1>

- @m38a_lib.M38A

84D3

PM_RSMRST_L

PM_RSMRST_L - @m38a_lib.M38A

23C1 58D7

PPFW_PORT1_VP_FL

PPFW_PORT1_VP_FL

- @m38a_lib.M38A

46B2

SMC_FAN_2_CTL

SMC_FAN_2_CTL

84D3

PM_SB_PWROK

PM_SB_PWROK - @m38a_lib.M38A

23C3 26D6

PPVCORE_S0_GPU_MPVDD

PPVCORE_S0_GPU_MPVDD

84D3

PM_SLP_S3

PM_SLP_S3 - @m38a_lib.M38A

77D7 78B8 80C8 81C8

84D3

PM_SLP_S3_L

PM_SLP_S3_L - @m38a_lib.M38A

6C8 23C3 58C5 77D8 79A7

PPVCORE_S0_GPU_VDDCI

PPVCORE_S0_GPU_VDDCI

MEMVTT_EN - @m38a_lib.M38A

31B5 79A6

PPVIN_S5_IMVP6_VIN

PPVIN_S5_IMVP6_VIN

PPV_3V3_AUDIO_CODEC

PPV_3V3_AUDIO_CODEC

PEG_D2R_C_P<2>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

- @m38a_lib.M38A

PEG_D2R_C_P<3>

- @m38a_lib.M38A

PEG_D2R_C_P<4>

- @m38a_lib.M38A

PEG_D2R_C_P<5>

PEG_D2R_C_P<5>

- @m38a_lib.M38A

84C3

PEG_D2R_C_P<6>

- @m38a_lib.M38A

84C3

PEG_D2R_C_P<7>

PEG_D2R_C_P<7>

- @m38a_lib.M38A

84C3

PM_SLP_S4

PM_SLP_S4 - @m38a_lib.M38A

77A8 77C7 79C8 83C6

84C3

46D3

-

91A6

-

86C7

- @m38a_lib.M38A - @m38a_lib.M38A

FAN_RPM2 - @m38a_lib.M38A

@m38a_lib.M38A

88A6

SMC_FAN_2_TACH

SMC_FAN_2_TACH

SMC_FAN_3_CTL

SMC_FAN_3_CTL

SMC_FAN_3_TACH

SMC_FAN_3_TACH

@m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

TP_SMC_FAN_3_CTL - @m38a_lib.M38A -

75D6 68D6

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_SMC_FAN_3_TACH

- @m38a_lib.M38A

PEG_D2R_C_P<8>

PEG_D2R_C_P<8>

- @m38a_lib.M38A

PM_SLP_S4_L

PM_SLP_S4_L - @m38a_lib.M38A

23C3 58C5 77C8

PEG_D2R_C_P<9>

PEG_D2R_C_P<9>

- @m38a_lib.M38A

84C3

PM_SLP_S5_L

PM_SLP_S5_L - @m38a_lib.M38A

23C3 58C5

Q4201_3

Q4201_3 - @m38a_lib.M38A

42D6

SMC_GPU_VSENSE

PEG_D2R_C_P<10>

PEG_D2R_C_P<10>

- @m38a_lib.M38A

84B3

PM_STPCPU_L

PM_STPCPU_L - @m38a_lib.M38A

23C8 33C4

Q5950_1

Q5950_1 - @m38a_lib.M38A

60A7

SMC_LID

PEG_D2R_C_P<11>

PEG_D2R_C_P<11>

- @m38a_lib.M38A

84B3

PM_STPPCI_L

PM_STPPCI_L - @m38a_lib.M38A

23C8 33C4

R6000_1

R6000_1 - @m38a_lib.M38A

60A6

SMC_LRESET_L

SMC_LRESET_L

PEG_D2R_C_P<12>

PEG_D2R_C_P<12>

- @m38a_lib.M38A

84B3

PM_SUS_STAT_L

PM_SUS_STAT_L

23C5 58C5 60C1 67C6

R6001_1

R6001_1 - @m38a_lib.M38A

60A6

SMC_MANUAL_RST_L

SMC_MANUAL_RST_L

PEG_D2R_C_P<13>

PEG_D2R_C_P<13>

- @m38a_lib.M38A

84B3

PM_SYSRST_L

PM_SYSRST_L - @m38a_lib.M38A

5B8 23C5 26C3 58B7

R6002_1

R6002_1 - @m38a_lib.M38A

60A6

SMC_MD1

SMC_MD1 - @m38a_lib.M38A

PEG_D2R_C_P<14>

PEG_D2R_C_P<14>

- @m38a_lib.M38A

84B3

PM_THRMTRIP_L

PM_THRMTRIP_L

SMC_MEM_ISENSE

SMC_MEM_ISENSE

PEG_D2R_C_P<15>

PEG_D2R_C_P<15>

- @m38a_lib.M38A

84B3

PM_THRM_L

PM_THRM_L - @m38a_lib.M38A

PEG_D2R_N<0>

PEG_D2R_N<0>

- @m38a_lib.M38A

13D3 84B1

POWER_BUTTON_L

POWER_BUTTON_L

- @m38a_lib.M38A

PEG_D2R_N<1>

PEG_D2R_N<1>

- @m38a_lib.M38A

13D3 84B1

PP0V9_S0_PGOOD

PP0V9_S0_PGOOD

- @m38a_lib.M38A

PEG_D2R_N<2>

PEG_D2R_N<2>

- @m38a_lib.M38A

13D3 84B1

PP1V2_S0_GPU_VDDPLL

PP1V2_S0_GPU_VDDPLL

PEG_D2R_N<3>

PEG_D2R_N<3>

- @m38a_lib.M38A

13D3 84B1

PEG_D2R_N<4>

PEG_D2R_N<4>

- @m38a_lib.M38A

13D3 84B1

PP1V05_S0_PGOOD

PP1V05_S0_PGOOD

PEG_D2R_N<5>

PEG_D2R_N<5>

- @m38a_lib.M38A

13D3 84B1

PP1V5_S0_NB_3GPLL_F

PP1V5_S0_NB_3GPLL_F

PEG_D2R_N<6>

PEG_D2R_N<6>

- @m38a_lib.M38A

13D3 84C1

PEG_D2R_N<7>

PEG_D2R_N<7>

- @m38a_lib.M38A

13D3 84C1

PP1V5_S0_NB_VCC3G

PP1V5_S0_NB_VCC3G

PP1V5_S0_NB_VCCA_3GP LL -

- @m38a_lib.M38A - @m38a_lib.M38A

-

- @m38a_lib.M38A

PEG_D2R_N<8>

PEG_D2R_N<8>

- @m38a_lib.M38A

13D3 84C1

PP1V5_S0_NB_VCCA_3GP

PEG_D2R_N<9>

- @m38a_lib.M38A

13D3 84C1

LL

PEG_D2R_N<10>

- @m38a_lib.M38A

13C3 84C1

PP1V5_S0_NB_VCCA_DPL

PEG_D2R_N<11>

PEG_D2R_N<11>

- @m38a_lib.M38A

13C3 84C1

LA

PEG_D2R_N<12>

PEG_D2R_N<12>

- @m38a_lib.M38A

13C3 84D1

PEG_D2R_N<13>

PEG_D2R_N<13>

- @m38a_lib.M38A

13C3 84D1

PP1V5_S0_NB_VCCA_DPL

PEG_D2R_N<14>

PEG_D2R_N<14>

- @m38a_lib.M38A

13C3 84D1

LB

PEG_D2R_N<15>

PEG_D2R_N<15>

- @m38a_lib.M38A

13C3 84D1

PEG_D2R_P<0>

PEG_D2R_P<0>

- @m38a_lib.M38A

13C3 84B1

PP1V5_S0_NB_VCCA_HPL

PEG_D2R_P<1>

PEG_D2R_P<1>

- @m38a_lib.M38A

13C3 84B1

L

PEG_D2R_P<2>

PEG_D2R_P<2>

- @m38a_lib.M38A

13C3 84B1

PP1V5_S0_NB_VCCA_MPL

PEG_D2R_P<3>

PEG_D2R_P<3>

- @m38a_lib.M38A

13C3 84B1

L

PEG_D2R_P<4>

PEG_D2R_P<4>

- @m38a_lib.M38A

13C3 84B1

PP1V5_S0_PGOOD

PP1V5_S0_PGOOD

-

PEG_D2R_P<5>

PEG_D2R_P<5>

- @m38a_lib.M38A

PEG_D2R_P<6>

PEG_D2R_P<6>

PEG_D2R_P<7>

PP1V5_S0_NB_VCCA_HPL L -

13C3 84B1

PP1V5_S0_SB_R

PP1V5_S0_SB_R

- @m38a_lib.M38A

13C3 84C1

PP1V5_S0_SB_VCC1_5_B

PP1V5_S0_SB_VCC1_5_B

- @m38a_lib.M38A

13C3 84C1

- @m38a_lib.M38A

13C3 84C1

PP1V5_S0_SB_VCCDMIPL

PP1V5_S0_SB_VCCDMIPL L -

PEG_D2R_P<9>

- @m38a_lib.M38A

13C3 84C1

L

PEG_D2R_P<10>

PEG_D2R_P<10>

- @m38a_lib.M38A

13C3 84C1

PP1V8R2V0_S0_GPU_VDD

PEG_D2R_P<11>

PEG_D2R_P<11>

- @m38a_lib.M38A

13C3 84D1

RH0

PEG_D2R_P<12>

- @m38a_lib.M38A

PEG_D2R_P<13>

13C3 84D1

PP1V8R2V0_S0_GPU_VDD

- @m38a_lib.M38A

13C3 84D1

RH1

PEG_D2R_P<14>

- @m38a_lib.M38A

13C3 84D1

PP1V8R3V3_S0_GPU_VDD

PEG_D2R_P<15>

PEG_D2R_P<15>

- @m38a_lib.M38A

13C3 84D1

R4_F

PEG_R2D_C_N<0>

13C3 84B5

PP1V8R3V3_S0_GPU_VDD

85C4

RSMRST_PWRGD - @m38a_lib.M38A

58D7 76D1

SMC_NMI

SMC_NMI - @m38a_lib.M38A

SATA_A_D2R_N - @m38a_lib.M38A

21B6 38A6

SMC_ODD_DETECT

SMC_ODD_DETECT

TP_SATA_A_D2R_N

38A5

SMC_ONOFF_L

SMC_ONOFF_L

SMC_PB7

SMC_PB7 - @m38a_lib.M38A TP_SMC_PB7 - @m38a_lib.M38A

59C3 59C3

SMC_PBUS_VSENSE

SMC_PBUS_VSENSE

58D5 76C6

38A5

SMC_PBUS_VSENSE_R

SMC_PBUS_VSENSE_R

21B6 38A6

SMC_PF0

SMC_PF0 - @m38a_lib.M38A TP_SMC_PF0 - @m38a_lib.M38A

59D3

SMC_PF1

SMC_PF1 - @m38a_lib.M38A

58B5 59D5

19A3

-

SATA_A_D2R_P

SATA_A_D2R_P - @m38a_lib.M38A

21B6 38A6

TP_SATA_A_D2R_P

38A5

SATA_A_R2D_C_N

SATA_A_R2D_C_N

SATA_A_R2D_C_P

SATA_A_R2D_C_P

TP_SATA_A_R2D_N

38B8

- @m38a_lib.M38A

38B8

17C6 19C4

SATA_C_D2R_N

SATA_C_D2R_N - @m38a_lib.M38A

21B6 38B6

21B6 38B6

SMC_RCIN_L

SMC_RCIN_L - @m38a_lib.M38A

- @m38a_lib.M38A

21B6 38B6

SMC_REF_GATE1

SMC_REF_GATE1

- @m38a_lib.M38A - @m38a_lib.M38A

SATA_C_R2D_N

SATA_C_R2D_N - @m38a_lib.M38A

38B8

SMC_REF_GATE2

SMC_REF_GATE2

SATA_C_R2D_P

SATA_C_R2D_P - @m38a_lib.M38A

38B8

SMC_REF_IN

SMC_REF_IN - @m38a_lib.M38A

25A7

SATA_RBIAS_N

SATA_RBIAS_N - @m38a_lib.M38A

21B6 38C7

SMC_RSTGATE_L

SATA_RBIAS_P - @m38a_lib.M38A

87B3 91B6 91B6

58D7

21B6 38C7

SMC_RST_L

SMC_RST_L - @m38a_lib.M38A

58C3 59D7 60C2

38C7

SMC_RUNTIME_SCI_L

SMC_RUNTIME_SCI_L

23C8

21B6 38C7

SMC_RX_L

SMC_RX_L - @m38a_lib.M38A

38C7

SMC_SB_NMI

SMC_SB_NMI - @m38a_lib.M38A

SB_A20GATE

SB_A20GATE - @m38a_lib.M38A

21C4

SMC_SMB_0_CLK

SMC_SMB_0_CLK

SB_ACZ_BITCLK

SB_ACZ_BITCLK

21C6

SB_ACZ_RST_L

SB_ACZ_RST_L - @m38a_lib.M38A

21C6

SB_ACZ_SDATAOUT

21C6

- @m38a_lib.M38A - @m38a_lib.M38A

SB_ACZ_SYNC

SB_ACZ_SYNC - @m38a_lib.M38A

21C6

SB_CLK14P3M_TIMER

SB_CLK14P3M_TIMER

- @m38a_lib.M38A

5B8 23D3 34D4

SB_CLK48M_USBCTLR

SB_CLK48M_USBCTLR

- @m38a_lib.M38A

5B8 23D3 34C4

PP1V8_FB_A0_VDDA0

- @m38a_lib.M38A

89D7

SB_CLK100M_DMI_P

PP1V8_FB_A0_VDDA1

- @m38a_lib.M38A

89D7

SB_CLK100M_SATA_N

SB_CLK100M_SATA_N

PP1V8_FB_A1_VDDA0

- @m38a_lib.M38A

89D4

SB_CLK100M_SATA_OE_L

SB_CLK100M_SATA_OE_L

PEG_R2D_C_N<5>

PEG_R2D_C_N<5>

- @m38a_lib.M38A

13B3 84B5

PP1V8_FB_A1_VDDA1

PP1V8_FB_A1_VDDA1

- @m38a_lib.M38A

89D4

PEG_R2D_C_N<6>

PEG_R2D_C_N<6>

- @m38a_lib.M38A

13B3 84C5

PP1V8_FB_B0_VDDA0

PP1V8_FB_B0_VDDA0

- @m38a_lib.M38A

90D7

SB_CLK100M_DMI_N

SB_CLK100M_DMI_N

- @m38a_lib.M38A

SB_CLK100M_DMI_P

- @m38a_lib.M38A - @m38a_lib.M38A -

SB_CLK100M_SATA_P

SMC_SMB_0_DATA SMC_SYS_ISET

SMC_SYS_KBDLED

- @m38a_lib.M38A

5B8 22C2 34A4 34C2 5B8 22C2 34A4 34C2

- @m38a_lib.M38A - @m38a_lib.M38A

TP_SMC_SYS_KBDLED SMC_SYS_LED

SMC_SYS_LED

5C8 21B6 34B4 34C2

SMC_SYS_LED_16B

SMC_SYS_LED_16B

23C3 33B4

SMC_SYS_VSET

SMC_SYS_VSET

5C8 21B6 34B4 34C2

SMC_TCK

- @m38a_lib.M38A

- @m38a_lib.M38A

NC_SMC_SYS_ISET

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

NC_SMC_SYS_VSET - @m38a_lib.M38A

- @m38a_lib.M38A

TP_SMC_SMB_0_DATA SMC_SYS_ISET SMC_SYS_KBDLED

@m38a_lib.M38A SB_CLK100M_SATA_P

- @m38a_lib.M38A

TP_SMC_SMB_0_CLK SMC_SMB_0_DATA

- @m38a_lib.M38A

- @m38a_lib.M38A

58B7

5D1 58C7 59B4 59B5 60C2 23C3 58D7 58C7 59D1 59D1 58C5 59D1 59D1 58B5 59D6 59D5 58C7 59D5 59D3 58C7 60A8 58B5 59D6 59D5

SMC_TCK - @m38a_lib.M38A

5D1 58C5 59B4 60C2

90D7

SB_CRT_TVOUT_MUX

SB_CRT_TVOUT_MUX

22B5

SMC_TDI

SMC_TDI - @m38a_lib.M38A

5D1 58B5 59B4 60C2

PP1V8_FB_B1_VDDA0

- @m38a_lib.M38A

90D4

SB_GPIO2

SB_GPIO2 - @m38a_lib.M38A

22A6 26C2

SMC_TDO

SMC_TDO - @m38a_lib.M38A

5D1 58B5 59B4 60C3

- @m38a_lib.M38A

90D4

SB_GPIO3

SB_GPIO3 - @m38a_lib.M38A

22A6 26C2

SMC_THRMTRIP

SMC_THRMTRIP

79B2

SB_GPIO4

SB_GPIO4 - @m38a_lib.M38A

22A6 26C2

SMC_TMS

SMC_TMS - @m38a_lib.M38A

77C6 77D3

SB_GPIO19

SB_GPIO19 - @m38a_lib.M38A

23D3

SMC_TPM_GPIO

SMC_TPM_GPIO

SB_GPIO21

SB_GPIO21 - @m38a_lib.M38A

23D3

SMC_TPM_PP

SMC_TPM_PP - @m38a_lib.M38A

58C7 59A6

SB_GPIO26

SB_GPIO26 - @m38a_lib.M38A

23C7

SMC_TPM_RESET_L

SMC_TPM_RESET_L

58B7 59C6 67B7

SB_GPIO29

SB_GPIO29 - @m38a_lib.M38A

22C4 22D8

SMC_TRST_L

SMC_TRST_L - @m38a_lib.M38A

SB_GPIO30

SB_GPIO30 - @m38a_lib.M38A

22C4 22D8

SMC_TX_L

SMC_TX_L - @m38a_lib.M38A

5D1 58C7 59B4 59B5 60C3

SB_GPIO31

SB_GPIO31 - @m38a_lib.M38A

22C4 22D8

SMC_VCL

SMC_VCL - @m38a_lib.M38A

58D3

PEG_R2D_C_N<8>

- @m38a_lib.M38A

PEG_R2D_C_N<9>

- @m38a_lib.M38A

PEG_R2D_C_N<10>

PEG_R2D_C_N<10>

- @m38a_lib.M38A

13B3 84C5

PP1V8_S3_PGOOD

PP1V8_S3_PGOOD

PEG_R2D_C_N<11>

PEG_R2D_C_N<11>

- @m38a_lib.M38A

13B3 84C5

PP2V5 S0_PGOOD

PP2V5 S0_PGOOD - @m38a_lib.M38A

PEG_R2D_C_N<12>

PEG_R2D_C_N<12>

- @m38a_lib.M38A

13B3 84D5

PP2V5_ENET_CTAP

PP2V5_ENET_CTAP

43D7

PEG_R2D_C_N<13>

PEG_R2D_C_N<13>

- @m38a_lib.M38A

13B3 84D5

PP2V5_S0_GPU_A2VDD

PP2V5_S0_GPU_A2VDD

PEG_R2D_C_N<14>

PEG_R2D_C_N<14>

- @m38a_lib.M38A

13B3 84D5

PP2V5_S0_GPU_AVDD

PP2V5_S0_GPU_AVDD

PEG_R2D_C_N<15>

PEG_R2D_C_N<15>

- @m38a_lib.M38A

13B3 84D5

PP2V5_S0_GPU_LPVDD

PP2V5_S0_GPU_LPVDD

- @m38a_lib.M38A

93B7

PEG_R2D_C_P<0>

PEG_R2D_C_P<0>

13B3 84B5

PP2V5_S0_GPU_LVDDR

PP2V5_S0_GPU_LVDDR

- @m38a_lib.M38A

93B7

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

93B7 93C7

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A - @m38a_lib.M38A

A

58C7 60A8

PP1V8_FB_B1_VDDA1

PEG_R2D_C_N<8> PEG_R2D_C_N<9>

- @m38a_lib.M38A

59A5 59A4 59A4

SATA_RBIAS - @m38a_lib.M38A

PP1V8_FB_A1_VDDA0

- @m38a_lib.M38A

- @m38a_lib.M38A

59A7

21C3 58C7

SATA_RBIAS_P - @m38a_lib.M38A

PP1V8_FB_A0_VDDA1

@m38a_lib.M38A

SMC_RSTGATE_L

58D5

SATA_RBIAS - @m38a_lib.M38A

SB_ACZ_SDATAOUT

PP1V8_FB_B0_VDDA1

- @m38a_lib.M38A

77D6 80B2

PP1V8_FB_A0_VDDA0

PP1V8_FB_B1_VDDA0

SMC_PROCHOT_3_3_L

23A3 23B3

- @m38a_lib.M38A

R5_F

PP1V8_FB_B0_VDDA1

SMC_PROCHOT_3_3_L

SATA_C_PWR_EN_L SATA_C_R2D_C_P

13C3 84B5

PP1V8_FB_B1_VDDA1

58B5 59C7

SATA_C_R2D_C_N

13B3 84B5

13B3 84C5

59D3

- @m38a_lib.M38A

SATA_C_R2D_C_P

13C3 84B5

13B3 84C5

- @m38a_lib.M38A

SATA_C_R2D_C_N

13B3 84B5

13B3 84C5

59D3

TP_PM_G2_EN

SATA_C_PWR_EN_L

@m38a_lib.M38A

58B5 59D5

SMC_PROCHOT

17C6 19C6

@m38a_lib.M38A

76C8

SMC_PROCHOT

23D2 38B5

87A7

59C5 59C5

58D5 59D5

- @m38a_lib.M38A

B

58B7 59C4 58C5 59B7 59C4

SMC_PM_G2_EN

21B6 38B6

- @m38a_lib.M38A

58C1 60C2

SMC_PM_G2_EN

SATA_C_DET_L - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

58A7 59B6 59B5

TP_SMC_PF1 - @m38a_lib.M38A

SATA_C_D2R_P - @m38a_lib.M38A

- @m38a_lib.M38A

PEG_R2D_C_N<7>

- @m38a_lib.M38A

SATA_C_DET_L

PEG_R2D_C_N<3>

PEG_R2D_C_N<7>

- @m38a_lib.M38A

- @m38a_lib.M38A

SATA_C_D2R_P

PEG_R2D_C_N<4>

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

19C5

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

SMC_NB_ISENSE

NC_SMC_NB_ISENSE

38A5

- @m38a_lib.M38A

SATA_C_D2R_C_P

@m38a_lib.M38A

PP1V8R3V3_S0_GPU_VDD R5_F -

- @m38a_lib.M38A

SATA_C_D2R_C_N

SATA_C_D2R_C_P

22C1 24D5 25B7

PP1V8R3V3_S0_GPU_VDD R4_F -

- @m38a_lib.M38A - @m38a_lib.M38A

TP_SATA_A_R2D_P

SMC_NB_ISENSE

21B6 38A6

SATA_C_D2R_C_N

24B5 25A6

PP1V8R2V0_S0_GPU_VDD RH1 -

- @m38a_lib.M38A - @m38a_lib.M38A

19C5

@m38a_lib.M38A PP1V8R2V0_S0_GPU_VDD RH0 -

- @m38a_lib.M38A

PEG_R2D_C_N<4>

PEG_R2D_C_N<2>

- @m38a_lib.M38A

75A6 75B1

R8599_2 - @m38a_lib.M38A

@m38a_lib.M38A

PEG_R2D_C_N<0>

PEG_R2D_C_N<1>

- @m38a_lib.M38A

58A7 59B6 59B5

R7507_1 - @m38a_lib.M38A

@m38a_lib.M38A

PEG_D2R_P<8>

6C7 58C7 58C1 60C3

SATA_A_D2R_N

17C6 19C6

- @m38a_lib.M38A

- @m38a_lib.M38A

58D5 59B3 58B5 59C1

RSMRST_PWRGD

@m38a_lib.M38A PP1V5_S0_NB_VCCA_MPL L -

- @m38a_lib.M38A

NC_SMC_MEM_ISENSE

58B5 59B4

5D1 59D8

R8599_2

17C6 19C4

- @m38a_lib.M38A

- @m38a_lib.M38A

58B7 59C5

R7507_1

@m38a_lib.M38A TP_NB_VCCA_DPLLB

- @m38a_lib.M38A

58B7 66C8

58B7 59C5 59C3

5D1 59C8

17D6 19A3

PP1V5_S0_NB_VCCA_DPL LB -

- @m38a_lib.M38A

SMC_LID - @m38a_lib.M38A

66C7

59C3

77D6 79A2

19A5

- @m38a_lib.M38A

SMC_FWE - @m38a_lib.M38A SMC_GPU_VSENSE

58B7 66C7

91B6

@m38a_lib.M38A

PEG_D2R_P<7>

PEG_R2D_C_N<1>

75A8 75C1

@m38a_lib.M38A

TP_NB_VCCA_DPLLA

PEG_D2R_P<8>

- @m38a_lib.M38A

60A5

R7504_1 - @m38a_lib.M38A

17D6

PP1V5_S0_NB_VCCA_DPL LA -

PEG_D2R_P<9>

PEG_D2R_P<14>

R6003_2 - @m38a_lib.M38A

R7504_1

@m38a_lib.M38A

PEG_D2R_N<10>

PEG_D2R_P<13>

R6003_2

77D6 81B2

- @m38a_lib.M38A

SMC_FWE

7C6 14B6 21C2 59C7

@m38a_lib.M38A

PEG_D2R_N<9>

PEG_D2R_P<12>

@m38a_lib.M38A

10D3 23C8 58B7

C

58B7 59C4 58B7

PEG_D2R_C_P<0>

PEG_D2R_C_P<6>

D

58C7 59D1

@m38a_lib.M38A

59C5 67C4 47D3

23C5

58C5 59D1

- @m38a_lib.M38A

PEG_COMP - @m38a_lib.M38A

PP5V_S0_IMVP6_VDD

@m38a_lib.M38A

14B6 19A2

58B5 59D1 58B5 59D1

UNUSED_SMC_SENSE

PCI_TRDY_L PEG_D2R_C_N<0>

-

14B6 19A2 19A1 19A1

SMC_FWIRE_ISENSE

PEG_COMP PEG_D2R_C_N<1>

- @m38a_lib.M38A

- @m38a_lib.M38A

NC_SMC_BATT_ISET

77D3 68A2 68D2

- @m38a_lib.M38A

UNUSED_SMC_SENSE

@m38a_lib.M38A

PCI_LOCK_L

- @m38a_lib.M38A

NC_SMC_BATT_CHG_EN

@m38a_lib.M38A

PP3V3_S0_CK410_VDD_RE F -

- @m38a_lib.M38A

TP_SMC_ADAPTER_EN

33C6

PP3V3_S0_CK410_VDD_PC I -

PCI_PAR

PCI_STOP_L - @m38a_lib.M38A

-

@m38a_lib.M38A

PEG_R2D_N<12>

- @m38a_lib.M38A

46A7

- @m38a_lib.M38A

PEG_R2D_N<11>

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_SDVO_CTRLDATA

- @m38a_lib.M38A

- @m38a_lib.M38A

PEG_R2D_N<10>

- @m38a_lib.M38A

TP_SDVO_CTRLCLK

PP3V3_FW_ESD_F

- @m38a_lib.M38A

22A7 26D2 44B5

SMB_ALERT_L

SMB_BSB_CLK

PCI_C_BE_L<2> PCI_C_BE_L<3>

22A6 26D2 44B5

SDVO_CTRLDATA

SMB_ALERT_L

SMB_BSB_CLK

PCI_C_BE_L<1>

22B6 44B5

SDVO_CTRLDATA

73B7

46A5 46A6 46B5 46C5 46D5

PCI_C_BE_L<0>

44B5

58C5 59B4 59B6

- @m38a_lib.M38A

PP3V3_FW_ESD - @m38a_lib.M38A

PCI_CLK_TPM

PCI_GNT1_L - @m38a_lib.M38A

58C5 59B6 59C4

SC_TX_L - @m38a_lib.M38A SDVO_CTRLCLK

SMB_BSA_DATA

PCI_CLK_SMC

PCI_IRDY_L - @m38a_lib.M38A

23C5

SC_RX_L - @m38a_lib.M38A

SDVO_CTRLCLK

SMB_BSA_CLK

PCI_CLK_SMC

PCI_IDSEL - @m38a_lib.M38A

SB_SPKR - @m38a_lib.M38A

SC_TX_L

SMB_BSA_DATA

PCI_C_BE_L<2> PCI_C_BE_L<3>

PCI_GNT1_L

21D6 26D7

SMB_BSA_CLK

PCI_C_BE_L<1>

21D6 21D6 26C7 21D6 26D7 21D6 26C7

- @m38a_lib.M38A

58D3

PCI_C_BE_L<0>

PCI_IRDY_L

- @m38a_lib.M38A

SB_RTC_X1 - @m38a_lib.M38A SB_RTC_X2 - @m38a_lib.M38A

58D2 59A3

- @m38a_lib.M38A

PCI_CLK_TPM

PCI_IDSEL

- @m38a_lib.M38A

SB_RTC_RST_L

SB_SM_INTRUDER_L

73B5 73D8

@m38a_lib.M38A

34C4 44B5

SB_INTVRMEN

1

23D3

SB_SM_INTRUDER_L SC_RX_L 94A7 94C5

@m38a_lib.M38A PP3V3_AUDIO_SPDIF_JAC K -

22A7 44B5

- @m38a_lib.M38A

94A6 94A6

2

SB_GPIO37 - @m38a_lib.M38A

SB_RTC_X2 SB_SPKR

PCI_CLK_FW - @m38a_lib.M38A

- @m38a_lib.M38A

SB_RTC_X1

@m38a_lib.M38A

PCI_AD<31> - @m38a_lib.M38A

- @m38a_lib.M38A

SB_RTC_RST_L

@m38a_lib.M38A

PCI_AD<31>

- @m38a_lib.M38A

93C7

-

@m38a_lib.M38A

 

3 SB_GPIO37

@m38a_lib.M38A

PCI_CLK_FW

- @m38a_lib.M38A

 

4

PEG_R2D_C_P<1>

PEG_D2R_C_P<4>

A

 

22B7 44C5

PEG_D2R_C_N<2>

B

6

PCI_AD<17> - @m38a_lib.M38A

PCI_STOP_L

C

 

7

PCI_AD<17>

58B5 59C7 5D1 58B5 59B4 60C3 58D5 59B6

5D1 58C1 60C3

104

8

 

7

6

 

5

 

4

 

3

 

2

 

1

 

8 SMC_WAKE_SCI_L SMC_XDP_TCK

SMC_XDP_TCK

SMC_XDP_TCK_3_3

- @m38a_lib.M38A

SMC_XDP_TMS_L SMC_XDP_TRST_L

SMC_XTAL SMLINK<0>

58C7 58B5 59A5 58B7

 

TP_NB_TESTIN_L

TP_NB_XOR_FSB2_H7

TP_NB_XOR_FSB2_H7

TP_NB_XOR_LVDS_A34

59A5

6

TP_NB_TESTIN_L

TP_NB_XOR_LVDS_A35

- @m38a_lib.M38A - @m38a_lib.M38A

 

5

@m38a_lib.M38A

14D6

=PP1V5_S0_SB_VCC1_5_A

-

- @m38a_lib.M38A

14C6

@m38a_lib.M38A

TP_NB_XOR_LVDS_A35

- @m38a_lib.M38A

14C6

=PP1V5_S0_SB - @m38a_lib.M38A

6C4 25A8 25C8

TP_NB_XOR_LVDS_D27

- @m38a_lib.M38A

14C6

=PP1V5_S0_NB_VCCD_HMP LL -

6C4 17C6 19D7

- @m38a_lib.M38A

14C6

@m38a_lib.M38A

TP_NB_XOR_LVDS_D28

SMC_XTAL - @m38a_lib.M38A

58C3 59B8

TP_PCI_CLK_SPARE

TP_PCI_CLK_SPARE

5B4 34C4

=PP1V5_S0_NB_VCCAUX

SMLINK<0> - @m38a_lib.M38A

23D5

TP_PCI_GNT0_L

TP_PCI_GNT0_L

- @m38a_lib.M38A

22B6

@m38a_lib.M38A

- @m38a_lib.M38A

-

23D5

TP_PCI_GNT2_L

TP_PCI_GNT2_L

- @m38a_lib.M38A

22B6

=PP1V5_S0_NB_TVDAC - @m38a_lib.M38A 6C4 19B2 19D7

SMS_INT_L - @m38a_lib.M38A

23C3 26C2 58B5

TP_PCI_GNT3_L

TP_PCI_GNT3_L

- @m38a_lib.M38A

22B6

=PP1V5_S0_NB_PLL

58A5 59B4

TP_PCI_GNT4_L

TP_PCI_GNT4_L

- @m38a_lib.M38A

22B6

=PP1V5_S0_NB_PCIE

SMS_X_AXIS

SMS_X_AXIS - @m38a_lib.M38A

58B7 59B6

SMS_Y_AXIS

SMS_Y_AXIS - @m38a_lib.M38A NC_SMS_Y_AXIS

- @m38a_lib.M38A

SMS_Z_AXIS

SMS_Z_AXIS - @m38a_lib.M38A

SPARE_SRC3_N

SPARE_SRC3_N

- @m38a_lib.M38A

SPARE_SRC3_P

- @m38a_lib.M38A

SPARE_SRC7_N

- @m38a_lib.M38A

SPARE_SRC7_P

- @m38a_lib.M38A

SPARE_SRC3_P

- @m38a_lib.M38A

- @m38a_lib.M38A -

@m38a_lib.M38A

6C4

19C8 19D7

6C4

13D2 19D7

TP_PCI_PME_L

TP_PCI_PME_L

22A6

=PP1V5_S0_NB_3GPLL - @m38a_lib.M38A 6C4 19A6 19A6

59B5

TP_SB_ACZ_SDIN1

TP_SB_ACZ_SDIN1

- @m38a_lib.M38A

21C6

=PP1V5_S0_NB - @m38a_lib.M38A

6C4 19B2 19D7

58B7 59B6

TP_SB_ACZ_SDIN2

TP_SB_ACZ_SDIN2

- @m38a_lib.M38A

21C6

=PP1V5_S0_CPU

6C4 8B6 8C5

59B5

TP_SB_DRQ0_L

58A7 59B6

TP_SB_GPIO6

TP_SB_DRQ0_L

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_SB_GPIO6 - @m38a_lib.M38A

59B5

TP_SB_GPIO23

TP_SB_GPIO23

34D2

TP_SB_GPIO25_DO_NOT_

TP_SB_GPIO25_DO_NOT_ USE -

34D2

USE

34D2

- @m38a_lib.M38A

21D4

- @m38a_lib.M38A

=PP1V5_S0_AIRPORT

-

@m38a_lib.M38A

6C4

23C5

U600_3

U600_3 - @m38a_lib.M38A

6C7

21D5

U600_6

U600_6 - @m38a_lib.M38A

6B7

23C3

U600_8

U600_8 - @m38a_lib.M38A

6B7

U600_11

@m38a_lib.M38A

U600_11 - @m38a_lib.M38A

6B7

TP_SB_GPIO38

TP_SB_GPIO38

23C3

U650_4

U650_4 - @m38a_lib.M38A

6A6

34D2

TP_SB_RSVD9

TP_SB_RSVD9 - @m38a_lib.M38A

22A6

U2698_4

U2698_4 - @m38a_lib.M38A

26C4

SPI_ARB - @m38a_lib.M38A

22C6 58D5

TP_SB_SATALED_L

TP_SB_SATALED_L

21C6

U3100_VDDQ

U3100_VDDQ - @m38a_lib.M38A

SPI_CE_L SPI_HOLD_L

SPI_CE_L - @m38a_lib.M38A SPI_HOLD_L - @m38a_lib.M38A

22C6 58B5 63C7 63C4

TP_SB_XOR_AD5 TP_SB_XOR_AD9

TP_SB_XOR_AD5 TP_SB_XOR_AD9

- @m38a_lib.M38A - @m38a_lib.M38A

22A7 22A7

U6100_VCC U7400_CEXT

U6100_VCC - @m38a_lib.M38A U7400_CEXT - @m38a_lib.M38A

61C4 74C4

SPI_SCLK

SPI_SCLK - @m38a_lib.M38A

22C6 58D5 63C7

TP_SB_XOR_AE5

TP_SB_XOR_AE5

- @m38a_lib.M38A

22A7

U8595_1

U8595_1 - @m38a_lib.M38A

85D2

SPI_SCLK_R

SPI_SCLK_R - @m38a_lib.M38A

63C4

TP_SB_XOR_AE9

TP_SB_XOR_AE9

- @m38a_lib.M38A

22A6

USB_A_N

USB_A_N - @m38a_lib.M38A

22C2 47D6

SPI_SI

SPI_SI - @m38a_lib.M38A

SPI_SI_R

- @m38a_lib.M38A - @m38a_lib.M38A

22C6 58D5 63C1

TP_SB_XOR_AG4

SPI_SI_R - @m38a_lib.M38A

63C3

TP_SB_XOR_AG8

SPI_SO

SPI_SO - @m38a_lib.M38A

22C6 58D5 63C1

TP_SB_XOR_AH4

SPI_SO_R - @m38a_lib.M38A

63C3

TP_SB_XOR_AH8

TP_SB_XOR_AH8

22A6

USB_B_OC_L

USB_B_OC_L - @m38a_lib.M38A

22C4 22D8

SPI_WP_L

SPI_WP_L - @m38a_lib.M38A

63C4

TP_SB_XOR_T5

TP_SB_XOR_T5

- @m38a_lib.M38A

21C6

USB_B_P

USB_B_P - @m38a_lib.M38A

22C2 53B2

SPKRAMP_MUTE

SPKRAMP_MUTE

SPKRAMP_SS

SPKRAMP_SS - @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_SB_XOR_AG8

- @m38a_lib.M38A

TP_SB_XOR_AH4

- @m38a_lib.M38A - @m38a_lib.M38A

D

31C5

SPI_SO_R

TP_SB_XOR_AG4

22A7

USB_A_OC_L

USB_A_OC_L - @m38a_lib.M38A

22C4 22D8 47B7

22A6

USB_A_P

USB_A_P - @m38a_lib.M38A

22C2 47C6

22A7

USB_B_N

USB_B_N - @m38a_lib.M38A

22C2 53B2

72B5

TP_SB_XOR_U3

TP_SB_XOR_U3

- @m38a_lib.M38A

21C6

USB_CAMERA_N

USB_CAMERA_N - @m38a_lib.M38A

72B4

TP_SB_XOR_U5

TP_SB_XOR_U5

- @m38a_lib.M38A

21C6

USB_CAMERA_P

USB_CAMERA_P - @m38a_lib.M38A

47B2

23C3 59B5

USB_C_N

USB_C_N - @m38a_lib.M38A

22C2 47B6

47B2

SUS_CLK_SB

SUS_CLK_SB - @m38a_lib.M38A

TP_SB_XOR_U7

TP_SB_XOR_U7

- @m38a_lib.M38A

21C6

58C5 59B6

TP_SB_XOR_V3

TP_SB_XOR_V3

- @m38a_lib.M38A

21C6

USB_C_OC_L

USB_C_OC_L - @m38a_lib.M38A

22C4 22D8 47B7

SV_SET_UP

SV_SET_UP - @m38a_lib.M38A

23B6 23C3 60C1

TP_SB_XOR_V4

TP_SB_XOR_V4

- @m38a_lib.M38A

21C6

USB_C_P

USB_C_P - @m38a_lib.M38A

22C2 47B6

SW_RST_BTN_L

SW_RST_BTN_L

- @m38a_lib.M38A

5D1 26C6

TP_SB_XOR_V6

TP_SB_XOR_V6

- @m38a_lib.M38A

21C6

USB_D_N

USB_D_N - @m38a_lib.M38A

22C2 47B3

SW_RST_DEBNC

SW_RST_DEBNC

- @m38a_lib.M38A

26C4

SMC_SUS_CLK

- @m38a_lib.M38A

TP_SB_XOR_V7

TP_SB_XOR_V7

- @m38a_lib.M38A

21C6

USB_D_OC_L

USB_D_OC_L - @m38a_lib.M38A

22C4 22D8

SYS_LED_BRT_D

SYS_LED_BRT_D

60B8

TP_SB_XOR_W1

TP_SB_XOR_W1

- @m38a_lib.M38A

21C6

USB_D_P

USB_D_P - @m38a_lib.M38A

22C2 47B3

SYS_LED_C

SYS_LED_C - @m38a_lib.M38A

60A6

TP_SB_XOR_W3

TP_SB_XOR_W3

- @m38a_lib.M38A

21C6

USB_E_N

USB_E_N - @m38a_lib.M38A

22C2 47A6

SYS_LED_CTL_B

SYS_LED_CTL_B

- @m38a_lib.M38A

60B7

TP_SB_XOR_Y1

TP_SB_XOR_Y1

- @m38a_lib.M38A

21C6

USB_E_OC_L

USB_E_OC_L - @m38a_lib.M38A

22C4 22D8 47B7

SYS_LED_CTL_C

SYS_LED_CTL_C

- @m38a_lib.M38A

60B6

TP_SB_XOR_Y2

TP_SB_XOR_Y2

- @m38a_lib.M38A

21C6

USB_E_P

USB_E_P - @m38a_lib.M38A

22C2 47A6

SYS_LED_CTL_D

SYS_LED_CTL_D

- @m38a_lib.M38A

SYS_ONEWIRE

SYS_ONEWIRE

SYS_POWERFAIL_L

SYS_POWERFAIL_L

SYS_PWRUP_L

SYS_PWRUP_L

THERM_DX_N

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

THERM_DX_N - @m38a_lib.M38A

THERM_DX_P

THERM_DX_P - @m38a_lib.M38A

THRM_ALERT_L

THRM_ALERT_L

THRM_THM

THRM_THM - @m38a_lib.M38A

TMDS_CK_TERM

TMDS_CK_TERM

TMDS_CLK_N

- @m38a_lib.M38A - @m38a_lib.M38A

60A6

TP_U8400_AG14

TP_U8400_AG14

91A5

USB_F_N

USB_F_N - @m38a_lib.M38A

58B7 59B4

TP_U8900_J2

TP_U8900_J2 - @m38a_lib.M38A

89A7

USB_F_P

USB_F_P - @m38a_lib.M38A

22C2

6D8 76D2

TP_U8900_J3

TP_U8900_J3 - @m38a_lib.M38A

89A7

USB_G_N

USB_G_N - @m38a_lib.M38A

22C2 47A3

- @m38a_lib.M38A

22C2

6C7

TP_U8950_J2

TP_U8950_J2 - @m38a_lib.M38A

89A4

USB_BT_N - @m38a_lib.M38A

47A2

10B5 10C5

TP_U8950_J3

TP_U8950_J3 - @m38a_lib.M38A

89A4

USB_G_P

USB_G_P - @m38a_lib.M38A

22C2 47A3

10B5 10C5

TP_U9000_J2

TP_U9000_J2 - @m38a_lib.M38A

90A7

USB_BT_P - @m38a_lib.M38A

47A2

10D3

TP_U9000_J3

TP_U9000_J3 - @m38a_lib.M38A

90A7

USB_H_N

USB_H_N - @m38a_lib.M38A

22C2 47C3

10C4

TP_U9050_J2

TP_U9050_J2 - @m38a_lib.M38A

90A4

USB_H_P

USB_H_P - @m38a_lib.M38A

22C2 47C3

97C8

TP_U9050_J3

TP_U9050_J3 - @m38a_lib.M38A

90A4

USB_IR_N

USB_IR_N - @m38a_lib.M38A

47C2

TSENSE_GPU_DXP

61C5

TMDS_CLK_N - @m38a_lib.M38A

93C3 97C8

USB_IR_P

USB_IR_P - @m38a_lib.M38A

47C2

TMDS_CLK_P

TMDS_CLK_P - @m38a_lib.M38A

93C3 97C8

TSENSE_NB_DXP

TSENSE_NB_DXP

61B5

USB_PORT0_N

USB_PORT0_N - @m38a_lib.M38A

47D5

TMDS_CONN_CLKN TMDS_CONN_CLKP

TMDS_CONN_CLKN TMDS_CONN_CLKP

97C4 97C7 97C4 97C7

TSENSE_NB_GPU_DXN TV_DACA_OUT

TSENSE_NB_GPU_DXN - @m38a_lib.M38A TV_DACA_OUT - @m38a_lib.M38A

61B5 13C5 19B1

USB_PORT0_P USB_PORT1_N

USB_PORT0_P - @m38a_lib.M38A USB_PORT1_N - @m38a_lib.M38A

47C5 47B5

TMDS_CONN_DN<0>

TMDS_CONN_DN<0>

- @m38a_lib.M38A

97C4 97D7

TV_DACB_OUT - @m38a_lib.M38A

13C5 19B1

USB_PORT1_P

USB_PORT1_P - @m38a_lib.M38A

TMDS_CONN_DN<1>

TMDS_CONN_DN<1>

- @m38a_lib.M38A

97C4 97D7

TV_DACC_OUT - @m38a_lib.M38A

13C5 19B1

USB_PORT2_N

USB_PORT2_N - @m38a_lib.M38A

TMDS_CONN_DN<2>

TMDS_CONN_DN<2>

- @m38a_lib.M38A

97C7 97D4

TV_IRTNA - @m38a_lib.M38A

13C5 19B1

USB_PORT2_P

USB_PORT2_P - @m38a_lib.M38A

TMDS_CONN_DP<0>

TMDS_CONN_DP<0>

- @m38a_lib.M38A

97C4 97D7

TV_IRTNB - @m38a_lib.M38A

13C5 19B1

USB_RBIAS_PN

USB_RBIAS_PN - @m38a_lib.M38A

22C2

TMDS_CONN_DP<1>

TMDS_CONN_DP<1>

- @m38a_lib.M38A

97C4 97D7

TV_IRTNC - @m38a_lib.M38A

13C5 19B1

VGA_B

VGA_B - @m38a_lib.M38A

97B6 97C5

TMDS_CONN_DP<2>

TMDS_CONN_DP<2>

- @m38a_lib.M38A

97C7 97D4

TV_IREF - @m38a_lib.M38A

13C5 19B1

VGA_G

VGA_G - @m38a_lib.M38A

97A6 97C5

93C3 97D8

PP3V3_S0_NB_VCCA_TVB G -

TMDS_DATA_N<0>

- @m38a_lib.M38A - @m38a_lib.M38A

TMDS_DATA_N<0>

TMDS_DATA_N<1>

- @m38a_lib.M38A

TMDS_DATA_N<1>

- @m38a_lib.M38A - @m38a_lib.M38A

93C3 97D8

@m38a_lib.M38A

93C3 97C8

PP3V3_S0_NB_VCCA_TVD ACC -

TMDS_DATA_N<3>

TMDS_DATA_N<3>

- @m38a_lib.M38A

93C3 95D6

@m38a_lib.M38A

TMDS_DATA_N<4>

TMDS_DATA_N<4>

- @m38a_lib.M38A

93C3 95D6

PP3V3_S0_NB_VCCA_TVD ACB -

TMDS_DATA_N<5>

TMDS_DATA_N<5>

- @m38a_lib.M38A

93C3 95D6

@m38a_lib.M38A

TMDS_DATA_P<0>

TMDS_DATA_P<0>

- @m38a_lib.M38A

93C3 97D8

PP3V3_S0_NB_VCCA_TVD ACA -

TMDS_DATA_N<2>

- @m38a_lib.M38A

TSENSE_GPU_DXP

TMDS_DATA_N<2>

TMDS_DATA_P<1>

- @m38a_lib.M38A

TMDS_DATA_P<1>

VGA_HSYNC

VGA_HSYNC - @m38a_lib.M38A

VGA_R

VGA_R - @m38a_lib.M38A

47B5 47A5 47A5

97A3 97C5 97A6 97C5

17C6 19B1

VGA_VSYNC VMAIN_AVLBL

VMAIN_AVLBL - @m38a_lib.M38A

41C7

17C6 19B1

VREG_FB

VREG_FB - @m38a_lib.M38A

68A3

VR_PWRGD_CK410

VR_PWRGD_CK410

VR_PWRGOOD_DELAY

VR_PWRGOOD_DELAY

XDP_BPM_L<0>

XDP_BPM_L<0> - @m38a_lib.M38A

7C6 11B3

XDP_BPM_L<1>

XDP_BPM_L<1> - @m38a_lib.M38A

7C6 11B3

XDP_BPM_L<2>

XDP_BPM_L<2> - @m38a_lib.M38A

7C6 11B3

XDP_BPM_L<3>

XDP_BPM_L<3> - @m38a_lib.M38A

7C6 11B3

XDP_BPM_L<4>

XDP_BPM_L<4> - @m38a_lib.M38A

XDP_BPM_L<5>

XDP_BPM_L<5> - @m38a_lib.M38A

17C6 19B1

C

VGA_VSYNC - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

97B3 97C5

23C5 26A8 5C7 14B6 26D5 75C6

93C3 97C8

@m38a_lib.M38A

93C3 97C8

PP1V5_S0_NB_VCCD_TVD AC -

- @m38a_lib.M38A

93C3 95D6

@m38a_lib.M38A

TMDS_DATA_P<4>

TMDS_DATA_P<4>

- @m38a_lib.M38A

93C3 95D6

PP1V5_S0_NB_VCCD_QTV DAC -

TMDS_DATA_P<5>

TMDS_DATA_P<5>

- @m38a_lib.M38A

93C3 95D6

@m38a_lib.M38A

TPM_BADD

TPM_BADD - @m38a_lib.M38A

67C4

=PP1V5_S0_AIRPORT

TPM_GPIO1

TPM_GPIO1 - @m38a_lib.M38A

59B5 67C6

PP1V5_S0 - @m38a_lib.M38A

6C6 11A7 11B7 11B7 80C2

XDP_DBRESET_L

XDP_DBRESET_L

TPM_GPIO2

TPM_GPIO2 - @m38a_lib.M38A

59B5 67C6

=PP1V5_S0_SB

6C4 25A8 25C8

XDP_TCK

XDP_TCK - @m38a_lib.M38A

5D1 7A8 7C6 11B3 11B3

TPM_LRESET_L

TPM_LRESET_L

6B7 67B7

=PP1V5_S0_SB_VCC1_5_ A -

6C4 24A3 25C1

XDP_TDI

XDP_TDI - @m38a_lib.M38A

5D1 7B8 7C6 11B3

TMDS_DATA_P<2>

- @m38a_lib.M38A

17C6 19B1

TMDS_DATA_P<2>

TMDS_DATA_P<3>

- @m38a_lib.M38A

TMDS_DATA_P<3>

- @m38a_lib.M38A

-

@m38a_lib.M38A

- @m38a_lib.M38A

TPM_PP

TPM_PP - @m38a_lib.M38A

59A5 67C6

@m38a_lib.M38A

TPM_RST_L

TPM_RST_L - @m38a_lib.M38A

67B6

=PP1V5_S0_SB_VCC1_5_ A_USB_CORE -

59B7 67C6

@m38a_lib.M38A

59B7 67C6

=PP1V5_S0_SB_VCCUSBP LL -

91A3

@m38a_lib.M38A

23C5

=PP1V5_S0_SB_VCC1_5_ A_ATX -

TPM_XTALI

TPM_XTALI - @m38a_lib.M38A

17C6 19B1 17B6 19A1 6C 4

53D3

5D1 7C6 11B5

XDP_TMS - @m38a_lib.M38A

5D1 7B8 7C6 11B3

XDP_TRST_L

XDP_TRST_L - @m38a_lib.M38A

5D1 7C6 11B3

6C4 24A5 25B6

ZH701P1

ZH701P1 - @m38a_lib.M38A

6A3

ZH702P1

ZH702P1 - @m38a_lib.M38A

6A3

ZH703P1

ZH703P1 - @m38a_lib.M38A

6A3

ZH704P1

ZH704P1 - @m38a_lib.M38A

6B3

TPM_XTALO - @m38a_lib.M38A TP_AZ_DOCK_EN_L

TP_AZ_DOCK_RST_L

TP_AZ_DOCK_RST_L

TP_CLK14P3M_SPARE

TP_CLK14P3M_SPARE

TP_CPU_A32_L

TP_CPU_A32_L

- @m38a_lib.M38A

7C7

@m38a_lib.M38A

TP_CPU_A33_L

TP_CPU_A33_L

- @m38a_lib.M38A

7B7

=PP1V5_S0_SB_VCC1_5_ A_ARX -

TP_CPU_A34_L

TP_CPU_A34_L

- @m38a_lib.M38A

7B7

@m38a_lib.M38A

TP_CPU_A35_L

TP_CPU_A35_L

- @m38a_lib.M38A

7B7

=PP1V5_S0_NB_3GPLL - @m38a_lib.M38A 6C4 19A6 19A6

TP_CPU_A36_L

TP_CPU_A36_L

- @m38a_lib.M38A

7B7

=PP1V5_S0_NB_PLL

TP_CPU_A37_L

TP_CPU_A37_L

- @m38a_lib.M38A

7B7

=PP1V5_S0_NB_VCCAUX

TP_CPU_A38_L

TP_CPU_A38_L

- @m38a_lib.M38A

7B7

@m38a_lib.M38A

19D7

TP_CPU_A39_L

TP_CPU_A39_L

- @m38a_lib.M38A

7B7

=PP1V5_S0_NB_VCCD_HM PLL -

6C4 17C6 19D7

TP_CPU_APM0_L

TP_CPU_APM0_L

7B7

@m38a_lib.M38A

TP_CPU_APM1_L

- @m38a_lib.M38A

- @m38a_lib.M38A

TP_CPU_APM1_L

- @m38a_lib.M38A

6C4 24A5 25C6

@m38a_lib.M38A

34C4

=PP1V5_S0_SB_VCCSATA PLL -

7B7

=PP1V5_S0_NB_PCIE

- @m38a_lib.M38A

-

-

@m38a_lib.M38A

6C4 24B5 25D6

6C4

19C8 19D7

6C4 6C4 16D1 17B6 19A7

6C4

13D2

TP_CPU_CPUSLP_L

TP_CPU_CPUSLP_L

TP_CPU_EXTBREF

TP_CPU_EXTBREF TP_CPU_HFPLL

TP_CPU_SPARE0

TP_CPU_SPARE0

- @m38a_lib.M38A

7B6

TV_IRTNA - @m38a_lib.M38A

TP_CPU_SPARE1

TP_CPU_SPARE1

- @m38a_lib.M38A

7B6

TV_IREF - @m38a_lib.M38A

TP_CPU_SPARE2

TP_CPU_SPARE2

- @m38a_lib.M38A

7B6

TV_DACC_OUT - @m38a_lib.M38A

TP_CPU_SPARE3

TP_CPU_SPARE3

- @m38a_lib.M38A

7B6

TV_DACB_OUT - @m38a_lib.M38A

13C5 19B1

TP_CPU_SPARE4

TP_CPU_SPARE4

- @m38a_lib.M38A

7B6

PP3V3_S0_NB_VCCA_TVD ACC -

17C6 19B1

TP_CPU_SPARE5

TP_CPU_SPARE5

- @m38a_lib.M38A

7B6

@m38a_lib.M38A

TP_CPU_SPARE6

TP_CPU_SPARE6

- @m38a_lib.M38A

7B6

PP3V3_S0_NB_VCCA_TVD ACB -

7B6

@m38a_lib.M38A

TP_CPU_SPARE7

TP_FB_A_MA12

TP_FB_A_MA12

- @m38a_lib.M38A

- @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

TP_FB_A_ODT<0>

TP_FB_A_ODT<0>

- @m38a_lib.M38A

TP_FB_A_ODT<1>

TP_FB_A_ODT<1>

- @m38a_lib.M38A

TP_FB_B_MA12

TP_FB_B_MA12

TP_FB_B_ODT<0>

TP_FB_B_ODT<0>

TP_FB_B_ODT<1>

TP_FB_B_ODT<1>

TP_FW_CNA TP_FW_LKON TP_FW_LPS

- @m38a_lib.M38A

21C4

=PP1V5_S0_CPU

7B6

TV_IRTNC - @m38a_lib.M38A

13C5 19B1

7B7

TV_IRTNB - @m38a_lib.M38A

13C5 19B1

87D5

PP3V3_S0_NB_VCCA_TVD ACA -

87B5

@m38a_lib.M38A

87B5

PP3V3_S0_NB_VCCA_TVB G -

87D1

@m38a_lib.M38A

- @m38a_lib.M38A

87B1

PP1V5_S0_NB_VCCD_TVD AC -

- @m38a_lib.M38A

87B1

@m38a_lib.M38A

TP_FW_CNA - @m38a_lib.M38A

44B3

PP1V5_S0_NB_VCCD_QTV DAC -

TP_FW_LKON - @m38a_lib.M38A

44B3

@m38a_lib.M38A PP1V5_S0 - @m38a_lib.M38A

TP_FW_LPS - @m38a_lib.M38A

44B3

TP_FW_MPCIACT_L

TP_FW_MPCIACT_L

44B3

TP_FW_NANDTREE

TP_FW_NANDTREE

TP_FW_ROM_AD

TP_FW_ROM_AD

TP_FW_VAUX_PRES

TP_FW_VAUX_PRES

TP_LVDS_VBG

TP_LVDS_VBG

TP_MEM_A_A<14>

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A - @m38a_lib.M38A

- @m38a_lib.M38A

TP_MEM_A_A<14>

TP_MEM_A_A<15>

- @m38a_lib.M38A

TP_MEM_A_A<15>

- @m38a_lib.M38A - @m38a_lib.M38A

=PP1V5_S0_SB_VCCUSBP LL -

44B3

@m38a_lib.M38A

44B3

=PP1V5_S0_SB_VCCSATA PLL -

44B3

@m38a_lib.M38A

13D5

=PP1V5_S0_SB_VCC1_5_ A_USB_CORE -

28C3

B

6C4 24B5 25D6

TP_CPU_HFPLL

TP_CPU_SPARE7

- @m38a_lib.M38A

2 3C5

7C6 11B4 26B5

XDP_TDO - @m38a_lib.M38A

TP_ATI_ROMCS_L

- @m38a_lib.M38A

7C6 11B1 11B3

XDP_TMS

TP_AZ_DOCK_EN_L

- @m38a_lib.M38A

7C6 11B3

XDP_TDO

TPM_XTALO

- @m38a_lib.M38A

- @m38a_lib.M38A

6C4 24A3 25B1

TP_ATI_ROMCS_L

1

53D3

SPI_ARB

SPARE_SRC7_N

2

19D7

SMLINK<1> - @m38a_lib.M38A SMS_ONOFF_L

- @m38a_lib.M38A

 

6C4 6C4 16D1 17B6 19A7

SMS_INT_L

- @m38a_lib.M38A

3

6C4 24A3 25C1

TP_NB_XOR_LVDS_A34

TP_NB_XOR_LVDS_D28

TP_NB_XOR_LVDS_D27

58C7

- @m38a_lib.M38A

 

4

14D6

SMS_ONOFF_L

SPARE_SRC7_P

A

23C1 58D5

58C7

NC_SMS_Z_AXIS

B

- @m38a_lib.M38A

- @m38a_lib.M38A

NC_SMS_X_AXIS

C

- @m38a_lib.M38A

SMC_XDP_TDO_3_3_L

SMC_XDP_TMS_L SMC_XDP_TRST_L

SMLINK<1>

D

- @m38a_lib.M38A

SMC_XDP_TCK_3_3

SMC_XDP_TDO_3_3_L

 

7 SMC_WAKE_SCI_L

19D7

6C4 8B6 8C5

13C5 19B1 13C5 19B1 13C5 19B1

17C6 19B1 17C6 19B1 17C6 19B1

A

17C6 19B1 17B6 19A1 6C6 11A7 11B7 11B7 80C2 6C4 24A5 25B6 6C4 24B5 25D6 6C4 24A3 25B1

@m38a_lib.M38A

28C3

=PP1V5_S0_SB_VCC1_5_ A_ATX -

TP_MEM_B_A<14>

TP_MEM_B_A<14>

- @m38a_lib.M38A

5B4 29C3

@m38a_lib.M38A

TP_MEM_B_A<15>

TP_MEM_B_A<15>

- @m38a_lib.M38A

5B4 29C3

=PP1V5_S0_SB_VCC1_5_ A_ARX -

6C4 24A5 25C6 6C4 24B5 25D6 105

8

 

7

6

 

5

 

4

 

3

 

2

 

1

 

8 Title: Design:

 

5

4

 

 

3

C3806

CAP_805-2

m38a[38C1]

C5901

CAP_402

m38a[59D8]

C2504

CAP_402

m38a[25C8]

C2505

CAP_402

C2506

C4101

CAP_402

m38a[41D7]

C5902

CAP_402

m38a[59B7]

m38a[25B7]

C4102

CAP_402

m38a[41D6]

C5903

CAP_402

m38a[59A8]

CAP_402

m38a[25B7]

C4103

CAP_402

m38a[41D6]

C5919

CAP_402

m38a[59B4]

C2507

CAP_402

m38a[25B7]

C4104

CAP_402

m38a[41D6]

C5940

CAP_402

m38a[59A4]

C2508

CAP_805-1

m38a[25A6]

C4105

CAP_402

m38a[41D5]

C5941

CAP_402

m38a[59A3]

C600

CAP_402

m38a[6C7]

C2509

CAP_402

m38a[25B8]

C4106

CAP_402

m38a[41D2]

C5942

CAP_805-1

m38a[59A3]

C601

CAP_402

m38a[6A3]

C2510

CAP_402

m38a[25C1]

C4107

CAP_402

m38a[41D2]

C5943

CAP_402

m38a[59A5]

C602

CAP_402

m38a[6A3]

C2511

CAP_402

m38a[25D6]

C4110

CAP_402

m38a[41D4]

C5951

CAP_402

m38a[60B6]

C603

CAP_402

m38a[6A3]

C2512

CAP_402

m38a[25B1]

C4111

CAP_402

m38a[41D4]

C6000

CAP_402

m38a[60D4]

m38a[6A4]

C2513

m38a[6C7]

Jun 21 19:41:15 2006

CAP_402

CAP_402

m38a[25C6]

C4112

CAP_402

m38a[41C4]

C6001

CAP_402

m38a[60D4]

C2514

CAP_402

m38a[25C6]

C4113

CAP_402

m38a[41C4]

C6002

CAP_402

m38a[60D4]

m38a[6A7]

C2515

CAP_402

m38a[25B6]

C4115

CAP_402

m38a[41B5]

C6003

CAP_402

m38a[60D4]

C699

CAP_P_CASE-C1

m 38a[6D7]

C2516

CAP_P_CASE-C2

m38a[25D3]

C4116

CAP_402

m38a[41B5]

C6100

CAP_402

m38a[61B5]

C0800

CAP_402

m38a[8B5]

C2517

CAP_402

m38a[25D6]

C4117

CAP_402

m38a[41B2]

C6101

CAP_402

m38a[61B5]

C0801

CAP_603

m38a[8B5]

C2518

CAP_402

m38a[25D4]

C4118

CAP_402

m38a[41B2]

C6301

CAP_402

m38a[63C2]

C900

CAP_805

m38a[9B6]

C2519

CAP_402

m38a[25D3]

C4126

CAP_402

m38a[41A8]

C6308

CAP_402

m38a[63C5]

C901

CAP_805

m38a[9B6]

C2520

CAP_402

m38a[25B6]

C4127

CAP_402

m38a[41A8]

C6309

CAP_402

m38a[63C6]

C902

CAP_805

m38a[9A6]

C2521

CAP_402

m38a[25C3]

C4128

CAP_402

m38a[41A8]

C6311

CAP_402

m38a[63C2]

C903

CAP_805

m38a[9A6]

C2522

CAP_402

m38a[25B3]

C4129

CAP_402

m38a[41A8]

C6312

CAP_402

m38a[63D3]

C904

CAP_805

m38a[9A6]

C2523

CAP_402

m38a[25B4]

C4130

CAP_402

m38a[41A7]

C6500

CAP_603

m38a[65D5]

C905

CAP_805

m38a[9A6]

C2524

CAP_603

m38a[25B3]

C4131

CAP_402

m38a[41A7]

C6501

CAP_805

m38a[65D5]

C906 C907

CAP_805 CAP_805

m38a[9A6] m38a[9B5]

C2525 C2526

CAP_402 CAP_402

m38a[25B3] m38a[25A4]

C4132 C4133

CAP_402 CAP_402

m38a[41A7] m38a[41A6]

C6502 C6503

CAP_603 CAP_805

m38a[65B4] m38a[65B5]

C908

CAP_805

m38a[9B7]

C2527

CAP_402

m38a[25A3]

C4134

CAP_402

m38a[41A6]

C6504

CAP_P_6.3X11-TH-LF1

C909

CAP_805

m38a[9B5]

C2528

CAP_402

m38a[25A3]

C4135

CAP_402

m38a[41A5]

C6505

CAP_P_6.3X11-TH-LF1

m38a[65B3]

C910

CAP_805

m38a[9B7]

C2529

CAP_402

m38a[25A3]

C4136

CAP_402

m38a[41A5]

C6600

CAP_603

m38a[66D4]

C911

CAP_805

m38a[9B7]

C2530

CAP_402

m38a[25A3]

C4137

CAP_402

m38a[41A5]

C6601

CAP_805

m38a[66C5]

C912

CAP_805

m38a[9A7]

C2531

CAP_402

m38a[25D1]

C4138

CAP_402

m38a[41A4]

C6602

CAP_P_SM-LF

m38a[66C3]

C913

CAP_805

m38a[9A7]

C2532

CAP_402

m38a[25C1]

C4139

CAP_402

m38a[41A4]

C6650

CAP_402

m38a[66B5]

C914

CAP_805

m38a[9A7]

C2533

CAP_402

m38a[25C1]

C4140

CAP_402

m38a[41B3]

C6651

CAP_402

m38a[66A5]

C915

CAP_805

m38a[9A7]

C2534

CAP_402

m38a[25D1]

C4150

CAP_402

m38a[41D5]

C6652

CAP_402

m38a[66B3]

C916

CAP_805

m38a[9A7]

C2605

CAP_402

m38a[26C7]

C4200

CAP_1210

m38a[42D8]

C6653

CAP_402

m38a[66A3]

C917

CAP_805

m38a[9A7]

C2607

CAP_402

m38a[26D5]

C4201

CAP_402

m38a[42D7]

C6654

CAP_402

m38a[66B4]

C918

CAP_805

m38a[9A7]

C2608

CAP_402

m38a[26D8]

C4202

m38a[42D7]

C6655

CAP_402

m38a[66B2]

C919

CAP_805

m38a[9A7]

C2609

CAP_402

m38a[26D8]

C4203

CAP_1206-1

m38a[42D6]

C6700

CAP_402

m38a[67C4]

C920

CAP_805

m38a[9A5]

C2610

CAP_402

m38a[26C7]

C4204

CAP_402

m38a[42D6]

C6701

CAP_402

m38a[67C4]

C921

CAP_805

m38a[9A7]

C2611

CAP_402

m38a[26B7]

C4205

CAP_1210

m38a[42C5]

C6702

CAP_402

m38a[67C3]

C922

CAP_805

m38a[9A7]

C2698

CAP_402

m38a[26C4]

C4206

CAP_402

m38a[42C5]

C6703

CAP_402

m38a[67C3]

C923

CAP_805

m38a[9B7]

C2699

CAP_402

m38a[26C5]

C4209

CAP_603

m38a[42B7]

C6704

CAP_402

m38a[59B7]

C924

CAP_805

m38a[9A7]

C2800

CAP_402

m38a[28D6]

C4210

CAP_402

m38a[42B6]

C6705

CAP_402

m38a[59B7]

C925

CAP_805

m38a[9A7]

C2801

CAP_603

m38a[28B2]

C4300

CAP_402

m38a[43D7]

C6800

CAP_603

m38a[68D6]

C926

CAP_402

m38a[9B7]

C2802

CAP_603

m38a[28B2]

C4301

CAP_402

m38a[43D6]

C6801

CAP_402

m38a[68D6]

C928

CAP_805

m38a[9B6]

C2803

CAP_603

m38a[28B1]

C4304

CAP_402

m38a[43C6]

C6802

CAP_P_6.3X5 .5-SM

C929

CAP_805

m38a[9B5]

C2804

CAP_603

m38a[28B1]

C4305

CAP_402

m38a[43B6]

C6803

CAP_P_6.3X5 .5-SM

C930

CAP_805

m38a[9A6]

C2810

CAP_402

m38a[28B2]

C4401

CAP_402

m38a[44D1]

C6804

CAP_P_SMA-LF

m38a[68B4]

C931

CAP_805

m38a[9A5]

C2811

CAP_402

m38a[28B2]

C4402

CAP_402

m38a[44C1]

C6805

CAP_805

m38a[68B3]

C932

CAP_805

m38a[9A6]

C2812

CAP_402

m38a[28B1]

C4410

CAP_402

m38a[44D6]

C6806

CAP_805

m38a[68B3]

C934

CAP_402

m38a[9B7]

C2813

CAP_402

m38a[28B1]

C4412

CAP_402

m38a[44D1]

C6807

CAP_P_SMA-LF

C935

CAP_402

m38a[9B7]

C2814

CAP_402

m38a[28B2]

C4500

CAP_402

m38a[45D4]

C6810

CAP_P_SMA-LF

m38a[68B3]

C936

CAP_402

m38a[9B7]

C2815

CAP_402

m38a[28B2]

C4501

CAP_402

m38a[45D3]

C6812

CAP_402

m38a[68B4]

C937

CAP_402

m38a[9B6]

CAP_402

C938

CAP_402

C939 C940

CAP_805 CAP_P_CASE-C1

C941 C942

C650

CAP_402 CAP_402

CAP_1210

CAP_402

m38a[28B1]

C4502

m38a[45D3]

C6813

CAP_402

m38a[68B3]

CAP_402

m38a[28B1]

C4503

CAP_805-1

m38a[45C6]

C6821

CAP_402

m38a[68C6]

C2818 C2819

CAP_402 CAP_402

m38a[28B2] m38a[28B2]

C4504 C4505

CAP_402 CAP_402

m38a[45C4] m38a[45C5]

C6822 C6823

CAP_603 CAP_402

m38a[68A5] m38a[68A4]

CAP_P_3P_D2T

m38a[9A7]

C2820

CAP_402

m38a[28B1]

C4506

CAP_402

m38a[45C5]

C6825

CAP_402

m38a[68A3]

CAP_P_3P_D2T

m38a[9A7]

C2821

CAP_402

m38a[28B1]

C4507

CAP_402

m38a[45C5]

C6826

CAP_603

m38a[68A2]

C943

CAP_P_3P_D2T

m38a[9A7]

C2850

CAP_603

m38a[28D6]

C4508

CAP_402

m38a[45D5]

C6830

CAP_402

m38a[68D4]

C944

CAP_P_3P_D2T

m38a[9A7]

C2851

CAP_603

m38a[28A6]

C4509

CAP_402

m38a[45D5]

C6833

CAP_402

C945

CAP_P_3P_D2T

m38a[9A6]

C2852

CAP_402

m38a[28A6]

C4510

CAP_402

m38a[45D5]

C6835

CAP_402

C946

CAP_P_3P_D2T

m38a[9A6]

C2900

CAP_402

m38a[29D6]

C4515

CAP_805-1

m38a[45D6]

C6836

CAP_402

C950

CAP_402

m38a[9D4]

C2908

CAP_402

m38a[29B2]

C4520

CAP_402

m38a[45D5]

C7200

CAP_P_6.3X8-SM

C951

CAP_402

m38a[9D3]

C2909

CAP_402

m38a[29B2]

C4521

CAP_402

m38a[45D4]

C7201

CAP_1210

m38a[72D5]

C952

CAP_402

m38a[9D3]

C2910

CAP_402

m38a[29B1]

C4522

CAP_402

m38a[45D3]

C7202

CAP_805

m38a[72D4]

C953

CAP_402

m38a[9D2]

C2911

CAP_402

m38a[29B1]

C4523

CAP_402

m38a[45D3]

C7203

CAP_1210

m38a[72D3]

C1000

CAP_402

m38a[10C6]

C2912

CAP_402

m38a[29B2]

C4609

CAP_603-1

m38a[46D5]

C7204

CAP_805

m38a[72D6]

C1001

CAP_402

m38a[10D4]

C2913

CAP_402

m38a[29B2]

C4610

CAP_402

m38a[46D4]

C7205

CAP_805

m38a[72C6]

C1100

CAP_402

m38a[11A3]

C2914

CAP_402

m38a[29B1]

C4611

CAP_402

m38a[46D4]

C7206

CAP_805

m38a[72C6]

C1150

CAP_402

m38a[11D7]

C2915

CAP_402

m38a[29B1]

C4612

CAP_402

m38a[46C4]

C7207

CAP_805

m38a[72C6]

C1151

CAP_402

m38a[11D7]

C2916

CAP_402

m38a[29B2]

C4613

CAP_402

m38a[46C4]

C7208

CAP_603-1

m38a[72C4]

C1152

CAP_402

m38a[11D7]

C2917

CAP_402

m38a[29B2]

C4615

CAP_603-1

m38a[46C2]

C7209

CAP_805

m38a[72B4]

C1153

CAP_402

m38a[11C7]

C2918

CAP_402

m38a[29B1]

C4616

CAP_402

m38a[46B2]

C7210

CAP_402

m38a[72B3]

C1154

CAP_402

m38a[11C7]

C2919

CAP_402

m38a[29B1]

C4620

CAP_402

m38a[46B4]

C7211

CAP_402

m38a[72B2]

C1155

CAP_402

m38a[11C7]

C2920

CAP_402

m38a[29B2]

C4621

CAP_402

m38a[46B4]

C7212

CAP_402

m38a[72B2]

C1156

CAP_402

m38a[11B7]

C2921

CAP_402

m38a[29B2]

C4622

CAP_402

m38a[46A4]

C7213

CAP_402

C1157

CAP_402

m38a[11B7]

C2922

CAP_402

m38a[29B1]

C4623

CAP_402

m38a[46A4]

C7214

CAP_603

C1158

CAP_402

m38a[11B7]

C2923

CAP_402

m38a[29B1]

C4625

CAP_603-1

m38a[46A2]

C7215

CAP_402

C1159

CAP_402

m38a[11B7]

C2950

CAP_603

m38a[29D6]

C4626

CAP_402

m38a[46A2]

C7216

CAP_402

C1160

CAP_402

m38a[11A7]

C2951

CAP_603

m38a[29A7]

C4650

CAP_402

m38a[46C7]

C7217

CAP_P_6.3X8-SM

C1199

CAP_402

m38a[11B2]

C2952

CAP_402

m38a[29A6]

C4654

CAP_402

m38a[46B8]

C7218

CAP_603

m38a[72D5]

C1211

CAP_402

m38a[12C3]

C3004

CAP_402

m38a[30B4]

C4660

CAP_402

m38a[46C7]

C7219

CAP_603

m38a[72D4]

C1226

CAP_402

m38a[12B6]

C3005

CAP_402

m38a[30D4]

C4664

CAP_402

m38a[46B7]

C7221

CAP_402

m38a[72B7]

C1236

CAP_402

m38a[12A6]

C3006

CAP_402

m38a[30B3]

C4700

CAP_805-1

m38a[47C8]

C7223

CAP_1210

m38a[72D3]

C1610

CAP_402

m38a[16B5]

C3007

CAP_402

m38a[30D3]

C4710

CAP_P_B2

m38a[47D6]

C7317

CAP_402

m38a[73B4]

C1611

CAP_402

m38a[16B4]

C3008

CAP_402

m38a[30A3]

C4712

CAP_402

m38a[47D5]

C7318

CAP_805-1

m38a[73B4]

C1612

CAP_402

m38a[16B4]

C3009

CAP_402

m38a[30A4]

C4713

CAP_402

m38a[47D4]

C7326

CAP_402

m38a[73C7]

C1613

CAP_402

m38a[16B8]

C3010

CAP_402

m38a[30D4]

C4720

CAP_P_B2

m38a[47C6]

C7400

CAP_402

m38a[74B4]

C1614

CAP_402

m38a[16B8]

C3011

CAP_402

m38a[30D3]

C4722

CAP_402

m38a[47C4]

C7401

CAP_402

m38a[74D5]

C1615

CAP_402

m38a[16B6]

C3013

CAP_402

m38a[30A4]

C4723

CAP_402

m38a[47C4]

C7402

CAP_402

m38a[74A4]

m38a[68B3] m38a[68D6] m38a[68D3] m 38a[72D5]

m38a[72B2] m38a[72B5] m38a[72C6] m38a[72C6]

m38a[16B5]

C3014

CAP_402

m38a[30A4]

C4730

CAP_P_B2

m38a[47B5]

C7403

CAP_P_6.3X5 .5-SM

CAP_805-1

m38a[16B5]

C3015

CAP_402

m38a[30A3]

C4732

CAP_402

m38a[47A4]

C7404

CAP_P_6.3X5 .5-SM

C1711

CAP_402

m38a[17A3]

C3030

CAP_402

m38a[30C4]

C4733

CAP_402

m38a[47A4]

C7405

C1712

CAP_402

m38a[17A3]

C3033

CAP_402

m38a[30C3]

C4742

CAP_402

m38a[47D1]

C7406

CAP_P_SMA-LF

m38a[74C6]

C1713

CAP_402

m38a[17B3]

C3035

CAP_402

m38a[30C3]

C4743

CAP_402

m38a[47D1]

C7407

CAP_402

m38a[74D8]

C1900

CAP_P_CASE-C1

m38a[19B5]

C3100

CAP_402

m38a[31C4]

C4750

CAP_402

m38a[47B6]

C7408

CAP_402

m38a[74D7]

C1901

CAP_P_CASE-C1

m38a[19B5]

C3101

CAP_805-1

m38a[31B6]

C4751

CAP_402

m38a[47C6]

C7415

CAP_402

m38a[74A8]

C1902

CAP_805-1

m38a[19B5]

C3102

CAP_805-1

m38a[31B4]

C4752

CAP_402

m38a[47D6]

C7416

CAP_402

m38a[74A8]

CAP_402

m38a[74B7] m38a[74B6] m38a[74C7]

C1903

CAP_805-1

m38a[19B4]

C3105

CAP_P_SMC-LF

m38a[31B4]

C4796

m38a[47C7]

C7417

CAP_402

C1904

CAP_402

m38a[19B4]

C3109

CAP_603

m38a[31C5]

C4797

CAP_805-2

m38a[47D2]

C7418

CAP_805

C1905

CAP_402

m38a[19B4]

C3110

CAP_402

m38a[31B6]

C4798

CAP_402

m38a[47B2]

C7419

CAP_603-1

C1906

CAP_402

m38a[19B3]

C3301

CAP_402

m38a[33D6]

C4799

CAP_805-2

m38a[47B2]

C7424

CAP_402

C1907

CAP_402

m38a[19B3]

C3302

CAP_402

m38a[33D6]

C5300

CAP_402

m38a[53B7]

C7435

CAP_P_6.3X8-SM

C1914

CAP_805-1

m38a[19A8]

C3303

CAP_402

m38a[33D6]

C5301

CAP_402

m38a[53B7]

C7500

CAP_402

m38a[75C4]

C1915

CAP_402

m38a[19A7]

C3304

CAP_402

m38a[33D6]

C5304

CAP_402

m38a[53D5]

C7501

CAP_P_TH-MCZ

m38a[75C2]

C1916

CAP_402

m38a[19A8]

C3305

CAP_402

m38a[33D4]

C5305

CAP_402

m38a[53D5]

C7502

CAP_402

m38a[75B4]

C1918

CAP_402

m38a[19A7]

C3306

CAP_402

m38a[33D4]

C5306

CAP_402

m38a[53D4]

C7503

CAP_402

m38a[75C1]

C1934

CAP_805

m38a[19C7]

C3307

CAP_402

m38a[33C4]

C5307

CAP_402

m38a[53C4]

C7504

CAP_402

m38a[75B1]

C1935

CAP_402

m38a[19C7]

C3308

CAP_402

m38a[33D4]

C5308

CAP_402

m38a[53C5]

C7505

CAP_402

m38a[75C8]

C1936

CAP_805

m38a[19C7]

C3309

CAP_805-1

m38a[33D4]

C5309

CAP_402

m38a[53C4]

C7506

CAP_402

m38a[75B7]

C1937

CAP_402

m38a[19C7]

C3310

CAP_402

m38a[33D3]

C5310

CAP_402

m38a[53C4]

C7507

CAP_402

m38a[75B7]

C1965

CAP_603

m38a[19B8]

C3311

CAP_402

m38a[33C6]

C5311

CAP_805-1

m38a[53C3]

C7508

CAP_1210

C1966

CAP_603

m38a[19B7]

C3312

CAP_805-1

m38a[33C6]

C5312

CAP_805-1

m38a[53D4]

C7509

CAP_1210

m38a[75D1]

C1967

CAP_402

m38a[19B7]

C3314

CAP_402

m38a[33D8]

C5313

CAP_402

m38a[53C5]

C7510

CAP_402

m38a[75C8]

C1968

CAP_P_CASE-C1

m38a[19B7]

C3315

CAP_402

m38a[33D7]

C5314

CAP_805-1

m38a[53C4]

C7511

CAP_603

m38a[75B2]

C1972

CAP_P_SMB2 CAP_805-1 CAP_805-1

C1975

CAP_805-1

C1976

CAP_402

C1981

CAP_603

C1982

CAP_603

m38a[74A8] m38a[74A5] m38a[74A4] m38a[74C3] m 38a[74A3]

A

m38a[75C2]

m38a[19A5]

C3316

m38a[33D7]

C5800

CAP_402

m38a[59B8]

C7512

CAP_603

m38a[75C2]

m38a[19A4]

C3317

CAP_805-1

m38a[33D4]

C5801

CAP_402

m38a[59B8]

C7513

CAP_402

m38a[75B7]

m38a[19A4]

C3389

CAP_402

m38a[33C7]

C5802

CAP_805

m38a[58D3]

C7514

CAP_402

m38a[75B8]

m38a[19A4]

C3390

CAP_402

m38a[33C7]

C5803

CAP_402

m38a[58D2]

C7515

CAP_603

m38a[75C4]

m38a[19A4]

C3800

CAP_402

m38a[38B7]

C5804

CAP_402

m38a[58D2]

C7516

CAP_402

m38a[75B4]

m38a[19B6]

C3801

CAP_402

m38a[38B7]

C5805

CAP_402

m38a[58D2]

C7517

CAP_P_SM-3

m38a[19B8]

C3802

CAP_402

m38a[38B7]

C5806

CAP_402

m38a[58D1]

C7518

CAP_P_SM-3

m38a[75D2]

CAP_805-1

B

m 38a[72D6]

C1621

C1971

C

m38a[68B3]

C2817

C1970

D

m38a[68D3]

C2816

CAP_P_SMA-LF

1

m38a[68D4]

m38a[9B6]

CAP_805-1

2

m38a[65C4]

m38a[9A5] m 38a[9C7]

C1620

A

 

m38a[25D8]

m38a[85D1]

C610

B

6 CAP_402

CAP_402

C604

C

m38a

  C2503

C85A0

Date:

D

7

Cref Part Report

m38a[75D2]

C2500

CAP_P_SMB2

m38a[25B8]

C3803

CAP_402

m38a[38B7]

C5807

CAP_402

m38a[58D2]

C7521

CAP_402

m38a[75A6]

C2501

CAP_402

m38a[25A6]

C3804

CAP_402

m38a[38C3]

C5820

CAP_402

m38a[58C3]

C7526

CAP_603

m38a[75D6]

C2502

CAP_402

m38a[25D4]

C3805

CAP_402

m38a[38C2]

C5900

CAP_402

m38a[59D8]

C7527

CAP_603

m38a[75C5] 106

8

 

7

6

 

5

 

4

 

3

 

2

 

1

 

8

D

C

B

 

6

 

 

5

4

 

 

3

CAP_402

m38a[75B5]

C8434

CAP_402

m38a[84C5]

C8690

CAP_805

m38a[86D5]

C9342

CAP_402

m38a[93A5]

C7529

CAP_402

m38a[75B5]

C8435

CAP_402

m38a[84C5]

C8691

CAP_402

m38a[86D5]

C9345

CAP_805

m38a[93A6]

C7530

CAP_402

m38a[75D6]

C8436

CAP_402

m38a[84C5]

C8692

CAP_402

m38a[86D5]

C9346

CAP_402

m38a[93A5]

C7531

CAP_402

m38a[75B5]

C8437

CAP_402

m38a[84C5]

C8711

CAP_402

m38a[87B7]

C9347

CAP_402

m38a[93A5]

C7532

CAP_402

m38a[75B6]

C8438

CAP_402

m38a[84C5]

C8713

CAP_402

m38a[87B7]

C9400

CAP_603-1

m38a[94C7]

C7533

CAP_402

m38a[75B6]

C8439

CAP_402

m38a[84C5]

C8715

CAP_402

m38a[87A7]

C9401

CAP_402

m38a[94C6]

C7534

CAP_402

m38a[75B5]

C8440

CAP_402

m38a[84B5]

C8716

CAP_402

m38a[87A6]

C9410

CAP_402

m38a[94C6]

C7535

CAP_603

m38a[75D5]

C8441

CAP_402

m38a[84B5]

C8721

CAP_402

m38a[87B4]

C9420

CAP_1210

m38a[94C5]

C7550

CAP_603

m38a[75D1]

C8442

CAP_402

m38a[84B5]

C8723

CAP_402

m38a[87B4]

C9450

CAP_805

m38a[94C2]

C7551

CAP_603

m38a[75D1]

C8443

CAP_402

m38a[84B5]

C8725

CAP_402

m38a[87A4]

C9470

CAP_402

m38a[94B2]

C7590

CAP_402

m38a[75C3]

C8444

CAP_402