Apple MacBook Pro A1278 (J30, 820-3115) PDF
Content
8
7
6
5
4
2
3
1 CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
REV
ECN
6
0001395489
DESCRIPTION OF REVISION
APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,MLB,J30
ENGINEERING RELEASED
2012-03-13
03/12/12 D
(.csa)
Date
Page TABLE_TA BLEOFCONTENTS_HEAD
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Contents 1
2
3
7 8
Revision History Revision History
5
11
12
13
14
16
17
18
19
20
21
22
23
BOM Configuration
K90I_MLB
FUNC TEST
K90I_MLB
25
26
27
28
29
30
31
33
34
35
36
37
38
K90I_MLB MASTER
CPU CLOCK/MISC/JTAG
MASTER
CPU DDR3 INTERFACES
MASTER
CPU POWER
MASTER
CPU GROUNDS
MASTER
CPU DECOUPLING-I
JACK_J30
CPU DECOUPLING-II
MASTER
40
41
42
43
45
47
48
49
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
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02/15/2011
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02/15/2011
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02/15/2011
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02/15/2011
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02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
09/27/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
PCH SATA/PCIe/CLK/LPC/SPI
J31_MLB
PCH DMI/FDI/PM/Graphics
J31_MLB
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
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06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
J31_MLB J31_MLB J31_MLB J31_MLB
PCH DECOUPLING
K90I_MLB
CPU & PCH XDP
J31_MLB
Chipset Support
K90I_MLB
USB HUB & MUX
LINDA_J30
CPU Memory S3 Support
K90I_MLB
DDR3 SO-DIMM Connector A
K90I_MLB
DDR3 Byte/Bit Swaps
K90I_MLB
DDR3 SO-DIMM Connector B
K90I_MLB
SD Card Connector
YONAS_J30
DDR3/FRAMEBUF VREF MARGINING
J31_MLB
X19/ALS/CAMERA CONNECTOR
K90I_MLB
T29 Host (1 of 2)
K90I_MLB
T29 Host (2 of 2)
K90I_MLB
T29 Power Support
K90I_MLB
ETHERNET PHY (CAESAR IV)
J31_MLB
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
09/19/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
11/03/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
06/15/2011 02/15/2011
Ethernet Connector
K90I_MLB
FireWire LLC/PHY (FW643E)
K90I_MLB
02/15/2011 06/23/2011
FireWire Port & PHY Power
K90I_MLB
FireWire Connector
K90I_MLB
SATA/IR/SIL Connectors
YONAS_J30
46
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
PCH POWER PCH GROUNDS
39
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
Signal Aliases CPU DMI/PEG/FDI/RSVD
PCH GPIO/MISC/NCTF
24
02/15/2011 03/26/2009
K90I_MLB
PCH PCI/USB/TP/RSVD
TABLE_TABLEOFCO NTENTS_HEAD
MASTER
K20A_MLB
Power Aliases
9 10
(.csa)
External A USB3 Connector
J31_MLB
External B USB3 Connector
J31_MLB
Front Flex Support
K90I_MLB
SMC
YONAS_J30
TABLE_TABLEOFCONTENTS_ITEM
46 47
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
11/08/2011
TABLE_TABLEOFCONTENTS_ITEM
07/08/2011
TABLE_TABLEOFCONTENTS_ITEM
51
Sync 01/02/2012
SMC Support
YONAS_J30 06/15/2011
LPC+SPI Debug Connector
J31_MLB
52
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
53 54 55 56 57 58 59 61 62 64 65 66 67 68
02/15/2011
SMBus Connections Power Sensors: Load Side
K90I_MLB
11/03/2011
Power Sensors: High Side
YONAS_J30
Thermal Sensors
YONAS_J30
08/01/2011 02/15/2011
Fan
K90I_MLB 07/01/2011
WELLSPRING 1
J31_MLB
WELLSPRING 2
JACK_J30
09/28/2011 02/15/2011
Digital Accelerometer
K90I_MLB 02/15/2011
SPI ROM
K90I_MLB
AUDIO: CODEC/REGULATOR
KAVITHA_J30
07/25/2011 02/16/2012
AUDIO: DETECT/MIC BIAS
DIRK_J30 07/25/2011
AUDIO: HEADPHONE FILTER
KAVITHA_J30
AUDI0: SPEAKER AMP
KAVITHA_J30
07/25/2011 11/10/2011
AUDIO: JACK
DIRK_J30
AUDIO:Jack Translators
DIRK_J30 07/29/2011
DC-In & Battery Connectors
JACK_J30
70
09/27/2011
PBus Supply & Battery Charger
JACK_J30
System Agent Supply 5V/3.3V SUPPLY
JACK_J30
08/22/2011 07/28/2011
1.5V DDR3 Supply
JACK_J30
74
08/03/2011
CPU IMVP7 & AXG VCore Regulator
JACK_J30
CPU IMVP7 & AXG VCore Output
JACK_J30
75
07/28/2011
76
09/28/2011
CPUVCCIO (1.05V) Power Supply
JACK_J30
77
07/28/2011
Misc Power Supplies
JACK_J30
Power FETs
K90I_MLB
78
02/15/2011
79 90
94 97
100 101 102 103 104
82 83 84 85 86
09/28/2011 JACK_J30
73
93
105 106
C
02/20/2012
69
72
09/28/2011
LINDA_J30
71
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
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Contents 50
D
Date
Page
02/15/2011 K90I_MLB
System Block Diagram
4
Table of Contents
Sync
02/15/2011
Power Control 1/ENABLE
K90I_MLB
LVDS CONNECTOR
K90I_MLB
02/15/2011 02/15/2011
DisplayPort/T29 A MUXing
K90I_MLB 02/15/2011
Thunderbolt Connector A
K90I_MLB
LCD Backlight Driver
J31_MLB
07/08/2011 02/15/2011
CPU Constraints
K90I_MLB
B
02/15/2011
Memory Constraints
K90I_MLB
PCH Constraints 1
K90I_MLB
PCH Constraints 2
K90I_MLB
02/15/2011 02/15/2011 02/15/2011
Ethernet/FW Constraints
K90I_MLB
T29 Constraints
K90I_MLB
02/15/2011 02/15/2011
SMC Constraints
K90I_MLB
108
02/15/2011
Project Specific Constraints
K90I_MLB
PCB Rule Definitions
K90I_MLB
109
02/15/2011
07/08/2011 02/15/2011 12/21/2011
TABLE_TABLEOFCONTENTS_ITEM
A
A DRAWING TITLE
SCHEM,MLB,J30 DRAWING NUMBER
Schematic / PCB D#’s PART NUMBER QTY ESCRIPTION 051-9058
1
SCHEM,MLB,J30
820-3115
1
PCBF,MLB,J30
REFERENCE DES
SCH
PCB
CRITICAL
Apple Inc.
BOM OPTION
R
NOTICE OF PROPRIETARY PROPERTY:
CRITICAL
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
CRITICAL
DRAWING TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Tue Mar 13 14:00:17 2012
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
BRANCH
PAGE
1 OF 109 SHEET
1 OF 86
1
SIZE
D
8
7
6
5
4 U1000
2
3
1
J2500
XDP CONN
INTEL CPU
PG 23
2.X GHz J3100
IVY BRIDGE 2C-35W
PG 29 J2900
2 DIMMs
PG 27
DDR3-1333/1600MHZ
PG 9-13
DIMM
D
J6900, J6950
D
POWER SUPPLY
DC/BATT
PG 63-73
PG 63
U5511
GPIO
FDI
DMI
RTC
PG 19
PG 17
PG 17
PG 16
TEMP SENSOR PG 51 U5920
Sudden Motion Sensor
U2600
MISC CLK
SYSTEM CLOCK
PG 55
PG 19
U5400,U5410,U5340,U5360,U5370,Q5480,Q5490
BUFFER
PG 24
SPI
1.05V/6GHZ.
0
PG 41
0
J9400
Display Port / T29
U9390
U4900
PANTHER POINT-MPCH
I2C S MS
Fan S er Prt
A DC
SMC
LPC
J5100
SPI
LPC+SPI Conn Port80,serial
PG 45 1.05V/1.5GHZ.
C
PG 47
1 PG 16
U1800
PG 41 U5701
J3501
MUX
X19
U3600
CONN PG 75
4 LANEs
CIO
DP
Bluetooth PG 32
DP OUT
3 1 2 1 1 1 0 1
DVI OUT
PG 17
LVDS OUT PG 17
J4501
U4800
PG 32
U2700 1
2
IR Controller
IR
PG 44
PG 41
3
USB HUB PG 25 J4700
U2760
USB MUX
EHCI XHCI
1
PCI
J9000
PG 54, 53
CAMERA
) S E C I V 9 E 8 B D 8 1 S 4 7 G U 1 P 6 5 O T 4 P 3 U 2 (
TMDS OUT
TRACKPAD/ KEYBOARD
PG 53
J3502
PG 17
RGB OUT
T29 Host PG 33,34
PWR CTRL
PG 16-21
HDMI OUT
J5800, J5713
TP/KB PSOC
eDP OUT
PCIe x4
PG 76
1
PG 52
INTEL PG 16
SATA CONN ODD
DP/TMDS
FAN CONN AND CONTROL
SATA
J4500
C
J5601
PG 56
PG 16
J4501
PG 49, 50
SPI Boot ROM
PG 16
SATA CONN HDD
POWER SENSE
U6100
PG 25
0
EXTERNAL B USB 3
PG 18
PG 43
LVDS
B S U
PCI-E PG 16
PG 74
B
4
3
CONN
8 1 3 G 2 P
J4600
1
EXTERNAL A USB 3
SMBUS
JTAG
B
PG 42
PG 16
PG 16
PCI-E
PEG
(UP TO 8 LINES)
HDA
PG 16
PG 16
PG 16
2
3
J2550
DIMM’s From PCH
1
PCH XDP CONN PG 23
U6201
AUDIO Codec PG 57 EXTMIC
LINEIN HPOUT
SPDIF
MICIN
U6610, U6620, U6630
U6400 U4100
J3300
U3900
FW643E
A
E-NET
MIC BIAS
BCM57765
SD Card CONN
PG 36
PG 30
PG 38
LINEOUT
SPEAKER
PG58
AMPs PG 60
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
System Block Diagram DRAWING NUMBER
J4310
J3501
Apple Inc.
J4000
X19 AirPort
FW800 CONN
PG 32
PG 40
E-NET CONN
J 670 0
J6 70 1
NOTICE OF PROPRIETARY PROPERTY: AUDIO CONNs
PG 37
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PG 61
8
7
6
5
R
J6702 J6703
4
3
2
051-9058 6.0.0
REVISION
BRANCH
PAGE
2 OF 109 SHEET
2 OF 86
1
SIZE
D
A
8
7
6
5 D6990
J30 POWER SYSTEM ARCHITECTURE PPDCIN_G3H
4
2
ENABLE
3
3.425V G3HOT
PPDCIN_S5_P3V42G3H
R6990
2
3
PP3V42_G3H_REG
PM6640
4
SMC PWRGD SMC_RESET_L
SN0903048 U5010 (PAGE 44)
U6990
R6905
(PAGE 63)
1
Q5300
D
J6900
1
Q5310
F6905 6A FUSE
AC
PPBUS_G3H
V
DCIN(16.5V)
V
F7040
A
ADAPTER
U7000
15
R5400
CPUVCCIOS0_EN
ISL95870 U7600
EN
21
D
22
SMC_CPU_FSB_ISENSE PGOOD
(PAGE 70)
PPCPUVCCIO_S0_REG
A
1.05VVOUT
VCC
PPVBAT_G3H
VIN
R7640
PP5V_S0_CPUVCCIOS0
A
R7020
22-1
CPUVCCIOS0_PGOOD
VOUT
IN
ISL6259HRTZ SMC_DCIN_ISENSE
PBUS SUPPLY/ BATTERY CHARGER
R7050
SMC_RESET_L
1
VOUT
A
TPS22924
U4202
PP1V0_FW_FWPHY
EN
V
U7400
CPUIMVP_VR_ON
(PAGE 63)
VR_ON
(PAGE 68)
PPVBAT_G3H_CHGR_R
) V 6
R5330 SMC_GFX_VSENSE
FW_PWR_EN
PPVCORE_S0_AXG_REG
VOUT
PPVBATT_G3H_CONN
25
PPVCORE_S0_CPU_REG
CPU VCORE MAX15119GTM
Q7055
CPUIMVP_AXG_PGOOD
PGOODG
CHGR_BGATE
26
25-1
CPUIMVP_PGOOD
PGOOD
P . 2 2 S 1 3 O
R5320 SMC_CPU_VSENSE
(PAGE 39)
24
SMC_BATT_ISENSE
J6950
V
VIN
COUGAR-POINT
26-1
(PCH)
T 9 (
VIN
S5
C
DDRVTT_EN
0.75V
TPS51916 U7300
6
22
VCC
PVCCSA_EN CPU_VCCSA_VID<1>
PM_SLP_S5_L
R7917
CPU_VCCSA_VID<0>
11
R5410
PPVCCSA_S0_REG
P5V_3V3_SUS_EN
11 10-1
ISL95870A U7100
VID0
RC
P5VS3_EN
PG73
DELAY
5V
EN1
B
DDRREG_EN
PG73
P3V3S3_EN
PM_SLP_S4_L
PG73
7
Q9706
PM_SLP_S3_L PG 17 SLP_S3#(F4)
Q7840
9
Q7922
10-2
PP3V3_S0_VMON
U3900
5
CAESAR IV
R7803
PP1V5_S3RS0_VMON
PP3V3_S4_FET
PPVOUT_SW_LCDBKLT VOUT
Q7800
12
VMON_Q2
ISL88042IRTEZ P17(BTN_OUT)
VMON_Q3 PM_SLP_S5_L
26
PM_SYSRST_L
6-1
PM_PWRBTN_L
SLP_S5_L(P95)
PM_SLP_S4_L
(PAGE 73)
RES*
SMC_RESET_L
4
SLP_S4_L(P94)
PM_SLP_S3_L
(PAGE 76)
SLP_S3_L(P93)
P3V3S4_EN
PG73
Q4260
IMVP_VR_ON(P16)
CPUIMVP_VR_ON
U7960
VMON_Q4
B
PM_RSMRST_L
99ms DLY PWR_BUTTON(P90)
SYSRST(PA2)
PP5V_S0_VMON
PP1V05_S0_VMON
EN
R7978
RSMRST_IN(P13)
SMC_ONOFF_L
(PAGE 36) PM_SLP_S3_L& &WOL_EN||SMC _ADAPTER_EN/ /WOL_EN
10
12 RSMRST_OUT(P15)
PP1V2_ENET_PHY
BCM57765 EN
PM_DSW_PWRGD
PWRGD(P12)
RSMRST_PWRGD
ODD_PWR_EN_L PP3V3_ENET
P5V_3V3_SUS_EN
U9701
PPBUS_SW_LCDBKLT_PWR
RESET*
SMC
25
LP8550
(PAGE 16~21)
(PAGE 9~13)
ALL_SYS_PWRGD
PP5V_SW_ODD
14-1
LCD_BKLT_EN
VIN
15
P5V3V3_PGOOD
&& BKLT_PLT_RST_L
UNCOREPWRGOOD
PVCCSA_PGOOD
Q4590
PP5V_SUS_FET
13 14
U1000
P5VS0_EN
TPS51125 U7200 (PAGE 66) PGOOD
O D L _ 5 S _ V 5 P P
CPU
P1V8S0_PGOOD P5V3V3_PGOOD
8
VOUT2
PG 17
SLP_S4#(H4)
SM_DRAMPWROK
CPUIMVP_AXG_PGOOD
23-1
CPUVCCIOS0_PGOOD PP5V_S0_FET
PP3V3_S5
(R/H)
15 F9700
PVCCSA_PGOOD
PGOOD
Q7860
PP5V_S3_REG
PP3V3_S5_REG
EN2
13-1
13-2
VOUT1
3.3V
P3V3S5_EN_L
DELAY
U1800
(PAGE 65)
(L/H)
VREG5
RC
VID1
14
VIN
P5VS3_EN_L
13
PG73
SLP_SUS
30
23
PPBUS_S5_HS_OTHER_ISNS
A
PG 17
SLP_S5#(E4)
COUGAR-POINT (PCH)
DRAMPWROK
(PAGE 16~21)
VOUT
EN
C
29
28
PM_MEM_PWRGD
Q7801
R7916 PG73
CPU_PWRGD
PP1V5_S3RS0_FET
(PAGE 44)
P3V3S4_EN
PM_DSW_PWRGD
PLT_RERST_L PLTRST#
PROCPWRGD
PP1V5S0FET_GATE
PP5V_S0_FET
DELAY
SMC_PM_G2_EN
PM_RSMRST_L
U2850
DDRREG_PGOOD
PGOOD
7
P3V3S5_EN
RC
P60
RSMRST#
U1800
PM_PCH_PWRGD
(PAGE 67)
U4900
27
PPVTT_S0_DDR_LDO
VOUT2
SMC
16
PPDDR_S3_REG VOUT1
S3
PM_SYSRST_L
VLDOIN
1.5V
DDRREG_EN
PM_PWRBTN_L
PWRBTN#
SYS_RERST#
F4260
PP3V3_S3
14
PP3V3_SUS_FET
10-3
U4900 (PAGE 43)
16
PP3V3_S0
Q7810
PPBUS_FW_FET PM_SLP_S3_L_R P3V3S3_EN
MAX15053EWL
P1V8_S0_EN FWP5ORT_PWR_EN
1V05_S0_LDO_EN
A
RC
CPUVCCIOS0_EN
DELAY
RC
21 21
Q3880
22
P1V5S0_EN
19
DELAY
RC
P1V8S0_EN
8
18
P5V_3V3_SUS_EN
P5VS0_EN
P3V3S0_EN
PBUSVSENS_EN
14-1
PP1V05_SUS_LDO
TPS62201
P1V5S0_EN
19
(PAGE 71)
VIN LT3957
9
EN
U7770
PP1V5_S0_REG
PP1V05_S0_LDO
19 SYNC_MASTER=K20A_MLB
SYNC_DATE=03/26/2009
6
Revision History
20
DRAWING NUMBER
(PAGE8 71)
Apple Inc.
Q7830
U3890
PM_SLP_S3_L_R
PP3V3_FW_P3V3FWFET
14
TPS22924 EN
U4201
R
PP3V3_FW_FE5T
NOTICE OF PROPRIETARY PROPERTY:
(PAGE 39)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
(PAGE 35)
7
U7780
PAGE TITLE
U7740
T29_A_HV_EN
14-1
17
TPS720105 EN
(PAGE 71)
14-1
VOUT PP15V_T29_REG
DELAY
PP1V8_S0_REG
P1V05_S0_LDO_EN
DELAY
RC
U7760
(PAGE 71)
Q7820
TPS720105 PVCCSA_EN
EN
17
5
4
3
2
051-9058 6.0.0
REVISION
BRANCH
PAGE
3 OF 109 SHEET
3 OF 86
1
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D
A
8
7
6
5
4
3
2
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PROTO:
D
D
C
C
B
B
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
Revision History DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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051-9058 6.0.0
REVISION
BRANCH
PAGE
4 OF 109 SHEET
4 OF 86
1
SIZE
D
A
8
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BOM Variants
4
2
3
1
Bar Code Labels / EEEE #’s TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
607-8895
CMN PTS,PCBA,MLB,J30
J30_COMMON,FET_PAIR
085-3092
J30 MLB DEVELOPMENT BOM
J30_DEVEL:ENG
607-8721
POWER FETS PAIR,FAIRCHILD,DDR,J30
DDR_POWER_FET:FAIR
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_BOMGROUP_ITEM
1
LBL,P/N LABEL,PCB,28MM X 6 MM
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YH]
CRITICAL
EEEE_F1YH
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YJ]
CRITICAL
EEEE_F1YJ
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YK]
CRITICAL
EEEE_F1YK
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YL]
CRITICAL
EEEE_F1YL
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YM]
CRITICAL
EEEE_F1YM
826-4393
[EEEE:F1YG]
CRITICAL
EEEE_F1YG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
607-8722
POWER FETS PAIR,FAIRCHILD,5V_S3,J30
5V_S3_POWER_FET:FAIR
607-8723
POWER FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30
CHARGER_POWER_FET:FAIR
607-9309
POWER FETS PAIR,RENESAS,DDR,J30
DDR_POWER_FET:REN
607-9310
POWER FETS PAIR,RENESAS,5V_S3,J30
5V_S3_POWER_FET:REN
607-9311
POWER FETS PAIR,RENESAS,PBUS_CHARGER,J30
CHARGER_POWER_FET:REN
826-4393 TABLE_BOMGROUP_ITEM
826-4393 TABLE_BOMGROUP_ITEM
D
826-4393
D
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
639-3752
PCBA,MLB,MOL,2.9G,J30
J30_CMNPTS,CPU_2_9GHZ,SODIMM:MOLEX,EEEE_F1YK
6 39 -3 75 6
P CB A, ML B, HY B, 2. 9G ,J 30
J30_CMNPTS,CPU_2_9GHZ,SODIMM:HYBRID,EEEE_F1YH
6 39 -3 75 3
P CB A, ML B, FO X, 2. 5G ,J 30
J30_CMNPTS,CPU_2_5GHZ,SODIMM:FOXCONN,EEEE_F1YL
639-3755
PCBA,MLB,HYB,2.5G,J30
J30_CMNPTS,CPU_2_5GHZ,SODIMM:HYBRID,EEEE_F1YJ
639-3751
PCBA,MLB,MOL,2.5G,J30
J30_CMNPTS,CPU_2_5GHZ,SODIMM:MOLEX,EEEE_F1YM
639-3754
PCBA,MLB,FOX,2.9G,J30
J30_CMNPTS,CPU_2_9GHZ,SODIMM:FOXCONN,EEEE_F1YG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Programmable Parts PART NUMBER
1 1
335S0550
1
341S3430
C
J30 BOM GROUPS
QTY
335S0862 341S3096
1
DESCRIPTION IC,FLASH,SERIAL,SPI,!MBIT,2V7,REV
REFERENCE DES
F
IC ENET,1!MBITFLAH,CIV REV01,K9x IC,EEPROM,SERIAL,SPI,4Kx8,1.8V,MLP8,LF
BOM OPTION
CRITICAL CRITICAL
ENET_PROG
U3690
CRITICAL
T29ROM:BLANK
CRITICAL
T29ROM:PROG
U3690
IC,T29 EEPROM,LR,J30/J31
CRITICAL
U3990 U3990
ENET_BLANK
337S3997
1
CRITICAL
T29MCU:BLANK
341S3365
1
IC,PROGRMD,T29,PORTMCU,K90IA,K91A,K92A
U9330
CRITICAL
T29MCU:PROG
338S1098
1
IC,SMC12-A3,40MHZ/50DMI PS MCU,9x9,157BGA
U490 0
CRITICAL
341S3300
1
IC,SMC,EXTERNAL,FSB,A3,J30
U4900
CRITICAL
SMC_PROG
U6100
CRITICAL
BOOTROM_BLANK
CRITICAL
BOOTROM_BLANK
CRITICAL
BOOTROM_PROG
U9330
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
C
SMC_BLANK
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
335S0807
335S0812
1
IC,SPI SRL
50MHZ FLASH,64MBT,8SOP,FUSE =1
TABLE_BOMGROUP_ITEM
J30_COMMON
ALTERNATE,COMMON,J30_COMMON1,J30_COMMON2,J30_DEBUG:ENG,J30_PROGPARTS,T29BST:Y,TBTHV:P15V
1
U6100
64 MBIT SPI SRL DUAL I/O FLSH,SOIC8
TABLE_BOMGROUP_ITEM
J30_COMMON1
1
IC,EFI,V00C7,J30/J31
341S2384
1
IR,ENCORE II, CY7C63803-LQXC
341S3522
1
IC,PSOC,TP/KB,J30/J31
341S3558
BATT_3S,CPUMEM_S0,USBHUB2513B,HUB_3NONREM,T29:YES,SDRV_PD,SDRVI2C:MCU,AXG_PHASE1,BTPWR:S4,UV_GLUE_J30
U6100
TABLE_BOMGROUP_ITEM
J30_COMMON2
MIKEY,TPAD:Z2,RAMCFG_SLOT
U4800
CRITICAL
TABLE_BOMGROUP_ITEM
J30_PROGPARTS
BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG
U5701
CRITICAL
TPAD_PROG
TABLE_BOMGROUP_ITEM
J30_DEVEL:ENG
BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS_CONN:YES,LOADISNS:YES,DDRVREF_DAC,S0PGOOD_ISL TABLE_BOMGROUP_ITEM
J30_DEVEL:PVT
LPCPLUS_CONN:YES,XDP_CONN
Alternate Parts
TABLE_BOMGROUP_ITEM
J30_DEBUG:ENG
DEVEL_BOM,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO_DAC
TABLE_ALT_HEAD
TABLE_ALT_HEAD
TABLE_BOMGROUP_ITEM
J30_DEBUG:PVT
P AR T N UM BE R
ALTERNATE FOR PART NUMBER
138S0603
138S0602
ALL
157S0058
157S0084
ALL
DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2514B
B OM O PT IO N
REF DES COMMENTS:
P AR T N UM BE R
ALTERNATE FOR PART NUMBER
152S1499
152S0864
B OM O PT IO N
REF DES COMMENTS:
ALL
Coilcraft alt to Murata
152S1493
152S1300
ALL
Coilcraftalt toMurata
138S0652
138S0648
ALL
Samsung/Murata
138S0684
138S0660
ALL
Murata alt to Taiyo
152S1512
152S1295
152S1019
152S1271
3 7 6S 1 0 2 3
37 6 S 0 96 0
ALL
Siliconix alt to Renesas
353S3312
353S3055
ALL
NXP alt to Pericom
353S3238
353S1428
ALL
Intersil alt to TI
353S3519
353S2179
ALL
Intersil alt to TI
155S0578
155S0367
ALL
Taiyo alt to Murata
138S0681
138S0638
ALL
Taiyo alt to Samsung
138S0671
138S0673
ALL
Taiyo alt to Murata
376S0903
376S0796
ALL
Fairchidl alt to Vishay
377S0124
377S0057
ALL
Amotech alt to Tdk
341S3492
341S3096
ALL
Numonix alt to Atmel (ENET ROM)
376S1053
376S0604
ALL
Diodes alt to fairchild
376S1076
376S0634
ALL
Diodes alt to onsemi
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
J30_DEBUG:PROD
BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,LOADISNS:NO,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2513B
Murata alt to Samsung TABLE_ALT_ITEM
Delta alt to TDK Magnetics
TABLE_ALT_ITEM
TABL E_A LT_I TEM
128S0303
Module Parts
128S0353
ALL
Panasonic alt to Sanyo
TAB LE_ ALT_ ITE M
alt
to
Taiyo
TABLE_ALT_ITEM
138S0676
138S0691
ALL
Murata alt to Samsung
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
152S0778
152S0693
ALL
Cyntec alt to Vishay
376S0855
376S1032
ALL
Diodes alt to Toshiba
376S0977
376S0859
ALL
Diodes alt to Toshiba
ALL
Cyntec alt to NEC TABLE_ALT_ITEM
TABLE_ALT_ITEM
1
337S4113
U1000
IC,IVB,2C,35W,1023BGA
CRITICAL
CPU_IVB_2C
ALL
CyntecalttoTOKO
TABLE_ALT_ITEM
B
1
337S4264
U1000
IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA
CRITICAL
CPU_2_5GHZ
TABLE_ALT_ITEM
337S4265
1
U1000
IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA
CRITICAL
376S0972
CPU_2_9GHZ
376S1017
ALL
Rohm alt to Toshiba
TABLE_ALT_ITEM
337S4269
1
PANTHERPOINT,C1,SLJ8C,PRQ,BD82HM77
U1800
CRITICAL
376S0937
376S0845
ALL
Fairchild alt to Renesas
376S0777
376S0761
ALL
AON alt to Siliconix
376S0957
376S0958
ALL
Fairchild alt to Fairchild
376S0953
376S0958
ALL
Fairchild alt to Renesas
TABLE_ALT_ITEM
TABLE_ALT_ITEM
343S0534
1
338S0753
1
338S1072
1
IC,BCM57765B0,ENET&SD,8X8
U3900
CRITICAL
TABLE_ALT_ITEM
TABLE_ALT_ITEM
IC,FW643E,1394B
PHY/OHCI
LINK/PCI-E,12
U4100
CRITICAL
U3600
CRITICAL
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
IC,T29,PRQ,S LJJY,FCBGA,15x15MM,C1
T29:YES TABLE_ALT_ITEM
TABLE_ALT_ITEM
353S3055
1
U9390
IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN
377S0107
CRITICAL
377S0126
ALL
ONsemi alt to Semtech
TABLE_ALT_ITEM
TABLE_ALT_ITEM
946-3827
1
J30 MLB DYMAX ADHESIVE 29993-SC 0.48G
516S0806
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN
UV_GLUE_J30
CRITICAL
UV_GLUE_J30
CRITICAL
SODIMM:FOXCONN
371S0709
371S0652
ALL
NXP alt to Infineon
514-0788
514-0671
ALL
Acon(w liteon) alt to Acon
TABLE_ALT_ITEM
J3100
TABLE_ALT_ITEM
TABLE_ALT_ITEM
516-0246
1
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
J2900
516S0805
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
516-0245
1
516S0805 516-0246
B
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL
SODIMM:FOXCONN
J3100
CRITICAL
SODIMM:MOLEX
CONN,204P,SODIMM,DDR3,P=0.6MM,MOLEX
J2900
CRITICAL
SODIMM:MOLEX
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
J3100
CRITICAL
SODIMM:HYBRID
1
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
J2900
CRITICAL
SODIMM:HYBRID
607-9310
607-8722
ALL
Renesas alternate to fairchild
607-9311
607-8723
ALL
Renesas alternate to fairchild
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Sub BOM PART NUMBER
A
QTY
085-3092
1
607-8895
1
607-8721
1
607-8722
1
607-8723
1
DESCRIPTION
REFERENCE DES DEVEL
J30 MLB DEVELOPMENT CMN POWER_FETS POWER_FETS
CMNPTS
PTS,PCBA,MLB,J30
CSET1
PAIR,FAIRCHILD,DDR,J30 PAIR,FAIRCHILD,5V_S3,J30
CRITICAL
BOM OPTION
CRITICAL
DEVEL_BOM
CRITICAL
J30_CMNPTS
CRITICAL
SYNC_MASTER=K90I_MLB
BOM Configuration DRAWING NUMBER
FET_PAIR
CSET2
CRITICAL
FET_PAIR
CSET3
CRITICAL
FET_PAIR
Apple Inc. R
POWER_FETS
PAIR,FAIRCHILD,PBUS_CHARGER,J30
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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SYNC_DATE=02/15/2011
PAGE TITLE
2
051-9058 6.0.0
REVISION
BRANCH
PAGE
5 OF 109 SHEET
5 OF 86
1
SIZE
D
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NC_EDP_TXP<0..3> MAKE_BASE=TRUE NC_EDP_TXN<0..3> MAKE_BASE=TRUE NC_EDP_AUXP MAKE_BASE=TRUE NC_EDP_AUXN
Functional Test Points NC NO_TESTs NO_TEST
X19 CONN
Fan Connectors I12 I15 I16
PP5V_S0
TRUE TRUE TRUE
FAN_RT_PWM FAN_RT_TACH
6 7
I303
52
I301 I302
52
(NEED TO ADD 1 GND TP)
I300 I299
D
MIC I554 I553 I555
FUNC_TEST
I298
BI_MIC_LO
TRUE TRUE TRUE
BI_MIC_HI BI_MIC_SHIELD
61 62
I293
61 62
I288
61 62
(NEED TO ADD 1 GND TP)
I292 I295 I290
I271 I289
SPEAKER FUNC_TEST I227 I226 I228 I230 I229 I231
I595
SPKRAMP_L_N_OUT SPKRAMP_L_P_OUT
TRUE TRUE TRUE TRUE TRUE TRUE
60 61 85
I594
60 61 85
I593
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
(NEED 3 TP) 6 PP3V3_WLAN PCIE_AP_D2R_PI_P 32 PCIE_AP_D2R_PI_N 32 PCIE_AP_R2D_P 32 PCIE_AP_R2D_N 32 PCIE_CLK100M_AP_CONN_P 32 PCIE_CLK100M_AP_CONN_N 32 PP3V3_S3RS4_BT_F 32 PCIE_WAKE_L 17
32 80
I376
TRUE TRUE TRUE TRUE TRUE
32
I278
USB_BT_CONN_P USB_BT_CONN_N AP_CLKREQ_Q_L AP_RESET_CONN_L AP_TEMP_SMB_SDA_R AP_TEMP_SMB_SCL_R WIFI_EVENT_L_R
32 46
DEBUG
81
81
I287
81
I285
85
I414
85
I280 I281
24 32
32 80
I282 I283
32
I270
32
I416
32
I273
32
I274 I275
60 61 85
I417
60 61 85
I392
60 61 85
I391 I390
IPD_FLEX_CONN I375 I374 I372 I370
I259 I258 I260
I407
C
I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249
PP3V3_LCDVDD_SW_F
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
(NEED 2 TP)
PP3V3_S0_LCD_F PPVOUT_SW_LCDBKLT (NEED LVDS_DDC_CLK LVDS_DDC_DATA LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2> LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
LED_RETURN_5 LED_RETURN_6
6 74
I371
6 74
I369
2 TP) 74 77
I368
8 74
I361
8 74
I366
17 74 80
I365
17 74 80 17 74 80
I363 I364
17 74 80
I362
17 74 80
I360
17 74 80
I359
74 85
I357
74 85
I358
74 77
I377
74 77
I564
74 77
I626
I345
B
I265 I266
I628 I627
PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SMC_SSD_TEMP_CTL_R HDD_OOB_TEMP
I346
(NEED 2 TP)
6 41
I347 I349
41 45 I348
41 85 I350
41 85 I352
41 80 I351
41 80 I353 I327 I328
(NEED TO ADD 3 GND TP)
I329 I343
SATA
HDD/IR/SIL
I342 I341
I319 I314 I315 I318 I317 I307 I309
I625 I311
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
Z2_MOSI Z2_MISO Z2_SCLK
53 54
I419 I382
53 54 53 54
(NEED PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R IR_RX_OUT SMC_SSD_THROTTLE_R PP5V_S3_IR_R
2 TP)
6 41
41 80 41 80 41 80 41 80 41 41 44
I339 I340 I338 I336 I337 I333 I335 I334
41
(NEED TO ADD 3 GND TP)
I332 I330 I331
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I565 I380
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PPVCORE_S0_CPU PPVCORE_S0_AXG PP1V2_S3_ENET_INTREG PP1V05_S0 PP1V5_S3RS0 PP1V8_S0
7
7 7 85
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
7 85
PP5V_S0
6 7
PP5V_S3 PPVCCSA_S0_CPU PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET PP3V3_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP18V5_Z2 PP3V3_S0_LCD_F PP3V3_LCDVDD_SW_F PP4V5_AUDIO_ANALOG PP1V5_S3 SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L
I321
A
I320 I305
TRUE TRUE TRUE TRUE
6 45 48 84
I356
TRUE
I394
TRUE
63 63 64
I323 I324 I325 I308
TRUE TRUE TRUE TRUE TRUE
NC_CPU_THERMDC
TP_LVDS_IG_CTRL_CLK
17
TP_LVDS_IG_CTRL_DATA
17
TP_PCH_LVDS_VBG
7
16
7 85 6 7
NC_CRT_IG_DDC_CLK TRUE MAKE_BASE=TRUE NC_CRT_IG_DDC_DATA TRUE MAKE_BASE=TRUE
16
TP_HDA_SDIN2 TP_HDA_SDIN3
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
7
18
TP_PCI_PME_L
18
TP_PCI_CLK33M_OUT3
NC_CRT_IG_VSYNC
57 62
7 45 73
16
TP_CLINK_DATA
16
TP_CLINK_RESET_L
NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3
16
TP_PCIE_CLK100M_PEBN
16
TP_PCIE_CLK100M_PEBP
TRUE
=PEG_R2D_C_N<0..7>
9
TRUE
=PEG_D2R_P<0..7>
9
NC_PEG_D2RN<0..7>
=PEG_D2R_N<0..7>
9
NC_PEG_R2D_CP<8..11>
TRUE
=PEG_R2D_C_P<8..11> 9
NC_PEG_R2D_CN<8..11>
TRUE
=PEG_R2D_C_N<8..11> 9
NC_PEG_D2RP<8..11>
TRUE
=PEG_D2R_P<8..11>
9
NC_PEG_D2RN<8..11>
TRUE
=PEG_D2R_N<8..11>
9
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCI_PME_L
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
TP_FW643_SDA
38
TP_FW643_SM
38
TP_FW643_TCK
38
TP_FW643_TMS
38
TP_FW643_FW620_L
38
TP_FW643_VBUF
38
TP_FW643_OCR10_CTL
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
38
6 45 48 84
38
MAKE_BASE=TRUE
16
TP_PCIE_CLK100M_PE4N
16
TP_PCIE_CLK100M_PE4P
NC_CLINK_CLK
16
TP_PCIE_CLK100M_PE5N
NC_CLINK_DATA
16
TP_PCIE_CLK100M_PE5P
NC_CLINK_RESET_L
TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PEBP
NC_FW643_SDA NC_FW643_SM NC_FW643_TCK NC_FW643_TMS NC_FW643_FW620_L NC_FW643_VBUF NC_FW643_OCR10_CTL
TP_PCIE_CLK100M_PE7P 53
TP_PSOC_P1_3
16
TP_SATA_C_D2RN
16
TP_SATA_C_D2RP
16
TP_SATA_C_R2D_CN
16
TP_SATA_C_R2D_CP
16
TP_SATA_D_D2RN
16
TP_SATA_D_D2RP TP_SATA_D_R2D_CN
16
TP_SATA_D_R2D_CP
16
6 45 48 84 53 54
PP18V5_DCIN_FUSE ADAPTER_SENSE
TRUE TRUE
53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53 53
I598 I597 I596 I599 I600 I601 I602 I603 I604 I605 I606 I607 I608 I610 I611 I612 I614 I613 I617 I616 I618 I620 I619 I622
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TP_XDPPCH_HOOK2
23
TP_XDPPCH_HOOK3
23
TP_XDP_PCH_OBSFN_D<0..1>
23
TP_XDP_PCH_HOOK4
23
TP_XDP_PCH_HOOK5
16
TP_PCH_GPIO64_CLKOUTFLEX0
16
TP_PCH_GPIO65_CLKOUTFLEX1
16
TP_PCH_GPIO66_CLKOUTFLEX2
16
TP_PCH_GPIO67_CLKOUTFLEX3
63
DEBUG_CONN
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK33M_LPCPLUS LPC_FRAME_L LPC_PWRDWN_L LPC_SERIRQ LPCPLUS_GPIO LPCPLUS_RESET_L PM_CLKRUN_L PP3V42_G3H
TP_XDP_PCH_OBSFN_B<0..1>
23
63
6 7
LPC+SPI
TP_XDP_PCH_OBSFN_A<0..1>
23
(NEED 3 TP)
6 7
16 45 47 81
16 45 47 81 16 45 47 81 24 47 81 16 45 47 81 17 45 47 16 45 47 19 47
TP_SATA_E_D2RN TP_SATA_E_D2RP
16
TP_SATA_E_R2D_CN
16
TP_SATA_E_R2D_CP
16
TP_SATA_F_D2RN
16
TP_SATA_F_D2RP
16
TP_SATA_F_R2D_CN
16
TP_SATA_F_R2D_CP
33
TP_TBT_MONDC0
33
TP_TBT_MONDC1
33
TP_TBT_MONOBSP
PP3V42_G3H SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SMC_BIL_BUTTON_L SMC_LID_R
6 7 6 45 48 84 6 45 48 84
I408 I409 I410 I297
45 46 63 I294
63
7
TRUE TRUE TRUE TRUE TRUE
PP5V_S3_ALSCAMERA_F SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA USB_CAMERA_CONN_P USB_CAMERA_CONN_N
NO_TEST
6 7
45 46 47
NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_C_D2RN NC_SATA_C_D2RP
NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP
NC_TBT_MONDC0
TRUE MAKE_BASE=TRUE
NC_TBT_MONDC1
TRUE MAKE_BASE=TRUE
NC_TBT_MONOBSP
TRUE MAKE_BASE=TRUE
33
TP_TBT_MONOBSN
33
TP_DP_T29SRC_ML_CP<0..3>
33
TP_DP_T29SRC_ML_CN<0..3>
33
TP_DP_T29SRC_AUXCH_CP
33
TP_DP_T29SRC_AUXCH_CN
NC_TBT_MONOBSN
TRUE MAKE_BASE=TRUE
33 6
TP_T29_PCIE_RESET0_L
33 6
TP_T29_PCIE_RESET1_L
33 6
TP_T29_PCIE_RESET2_L
33 6
TP_T29_PCIE_RESET3_L
C
NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP
NC_DP_T29SRC_ML_CP<0..3> TRUE MAKE_BASE=TRUE NC_DP_T29SRC_ML_CN<0..3> TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
NC_DP_T29SRC_AUXCH_CP
NC_DP_T29SRC_AUXCH_CN
TP_T29_PCIE_RESET0_L TRUE MAKE_BASE=TRUE
TP_T29_PCIE_RESET1_L TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L TRUE MAKE_BASE=TRUE
6 33 6 33 6 33
TRUE
NC_FW2_TPBP
40
45 46 47
I499
TRUE
NC_FW2_TPBN
40
45 46 47
I498
TRUE
45 46 47
I497
45 46 47 45 46 47
TRUE
NC_FW2_TPBIAS NC_FW2_TPAP
40
I522
TRUE
PCH_VSS_NCTF<1>
81
I495
TRUE
NC_FW2_TPAN
40
I521
TRUE
PCH_VSS_NCTF<2>
81
I496
TRUE
NC_FW0_TPBP
40
I520
TRUE
PCH_VSS_NCTF<5>
81
I494
47
I493
47
TRUE TRUE
NC_FW0_TPBN
40
40
NC_FW0_TPAP
40
I519
TRUE
47
I518
TRUE
47
I517
TRUE
19 47 56
TRUE
XDP_PCH_AP_PWR_EN
TRUE
XDP_PCH_USB_HUB_SOFT_RST_L
I581
TRUE
XDP_PCH_SDCONN_STATE_RST_L
I580
TRUE
XDP_PCH_ENET_PWR_EN
I582
TRUE
XDP_PCH_SDCONN_DET_L
I583
TRUE
XDP_PCH_S5_PWRGD
I584
TRUE
I585
TRUE
XDP_PCH_PWRBTN_L 23 XDP_PCH_ISOLATE_CPU_MEM_L
I586
TRUE
XDP_FW_CLKREQ_L
I588
TRUE
I587
TRUE
I492
(NEED TO ADD 2 GND TP)
I491
53
54
54
23
XDP_AP_CLKREQ_L XDP_PCH_AUD_IPHS_SWITCH_EN
PCH_VSS_NCTF<9>
81
PCH_VSS_NCTF<11>
81
PCH_VSS_NCTF<12>
8
TP_LVDS_IG_B_CLKN
8
TP_LVDS_IG_B_CLKP
81
PCH_VSS_NCTF<15>
I547
TRUE
I546
TRUE
I545
TRUE
PCH_VSS_NCTF<17> PCH_VSS_NCTF<19>
I544
TRUE
PCH_VSS_NCTF<19>
6 81
I543
TRUE
PCH_VSS_NCTF<21>
81
I542
TRUE
PCH_VSS_NCTF<25>
81
I541
TRUE
PCH_VSS_NCTF<27>
81
I540
TRUE
PCH_VSS_NCTF<29>
81
81 81
6 81
NC_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP TRUE MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE
TP_LVDS_IG_BKL_PWM SMC_BS_ALRT_L
TRUE MAKE_BASE=TRUE
NC_SMC_BS_ALRT_L
A
SYNC_MASTER=K90I_MLB PAGE TITLE
FUNC TEST DRAWING NUMBER
Apple Inc.
32 17
TP_SDVO_TVCLKINN
17
TP_SDVO_TVCLKINP
32 80
17
TP_SDVO_STALLN
32 80
17
TP_SDVO_STALLP
17
TP_SDVO_INTN
17
TP_SDVO_INTP
6 45 48 84 6 45 48 84
5
B
6 33
NC NO_TESTs
I500
(NEED TO ADD 2 GND TP)
6
NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P
17 45 47
6 7
SPI_ALT_MOSI SPIROM_USE_MLB
16
NC_PCIE_CLK100M_PE4P
24 47
PP5V_S0
SMC_TX_L SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO
NC_PCH_GPIO64_CLKOUTFLEX0 TRUE MAKE_BASE=TRUE NC_PCH_GPIO65_CLKOUTFLEX1 TRUE MAKE_BASE=TRUE NC_PCH_GPIO66_CLKOUTFLEX2 TRUE MAKE_BASE=TRUE NC_PCH_GPIO67_CLKOUTFLEX3 TRUE MAKE_BASE=TRUE
16 45 47 81
SMC_RX_L
SMC_TCK SMC_TDI SMC_TDO SMC_TMS
NC_TP_XDP_PCH_OBSFN_A<0..1> TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_OBSFN_B<0..1> TRUE MAKE_BASE=TRUE NC_TP_XDPPCH_HOOK2 TRUE MAKE_BASE=TRUE NC_TP_XDPPCH_HOOK3 TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_OBSFN_D<0..1> TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_HOOK4 TRUE MAKE_BASE=TRUE NC_TP_XDP_PCH_HOOK5 TRUE MAKE_BASE=TRUE
23
16
NC_PCIE_CLK100M_PE4N
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PEBN
TRUE NC_FW643_AVREG MAKE_BASE=TRUE NC_FW643_TDI TRUE MAKE_BASE=TRUE
TP_FW643_AVREG TP_FW643_TDI
9
TRUE
MAKE_BASE=TRUE
53 54
53
SMC_KDBLED_PRESENT_L
38
D
=PEG_R2D_C_P<0..7>
NC_PEG_D2RP<0..7>
NC_PEG_R2D_CN<0..7>
NC_PCI_CLK33M_OUT3
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
17 26 32 45 73
53 54
53
KBDLED_ANODE
TP_CPU_RSVD<8..27>
TRUE
NC_PEG_R2D_CP<0..7>
8 17 26 45 73
(NEED TO ADD 4 GND TP)
WS_LEFT_OPTION_KBD WS_CONTROL_KBD
TP_CPU_RSVD<30..45>
TRUE
MAKE_BASE=TRUE
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
TP_CLINK_CLK
16
6 74 6 74
53 54
I304
WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD
TRUE
MAKE_BASE=TRUE
6 54
53 54
DC POWER CONN
TP_CPU_THERMDC
NC_CPU_RSVD<8..27>
MAKE_BASE=TRUE
6 41
(NEED TO ADD 6 GND TP)
CONN
WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22
TP_CPU_THERMDA
MAKE_BASE=TRUE
6 41
53 54
54
WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18
9
TRUE
NC_CPU_RSVD<30..45>
7 6 32 46
53 54
53 54
WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13
TP_EDP_AUX_N
NC_CRT_IG_HSYNC
NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_DATA TRUE MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE MAKE_BASE=TRUE
TP_HDA_SDIN1
16
53 54
PP5V_S5_CUMULUS
WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9
9
TRUE
TRUE
MAKE_BASE=TRUE
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
17
9
TP_EDP_AUX_P
MAKE_BASE=TRUE
NC_CRT_IG_RED
CAMERA/ALS CONN
(NEED TO ADD 2 GND TP)
8
TP_CRT_IG_VSYNC
9
TP_EDP_TX_N<0..3>
MAKE_BASE=TRUE
(NEED TO ADD 1 GND TP)
BIL CONN I326
17
TP_EDP_TX_P<0..3>
TRUE
MAKE_BASE=TRUE
7
6 45 48 84
(NEED 5 TP)
TP_CRT_IG_DDC_DATA TP_CRT_IG_HSYNC
7
KBD BACKLIGHT CONN
(NEED TO ADD 5 GND TP)
TP_CRT_IG_DDC_CLK
17
17
TRUE TRUE
NC_CPU_THERMDA
NC_CRT_IG_GREEN
7
PP3V3_S0
(NEED TO ADD 2 GND TP)
I322
TP_CRT_IG_RED
NC_CRT_IG_BLUE
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
71
BATT POWER CONN SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L PPVBAT_G3H_CONN
17
17
7
54
PICKB_L
PP3V3_S4 PP3V42_G3H
TP_CRT_IG_GREEN
53 54
I312
KEYBOARD
SATA ODD CONN
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
I386 I383
Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA PSOC_F_CS_L
TRUE TRUE TRUE TRUE TRUE TRUE
I418
74 77
I344
I267
53 54
6 7
74 77
I355
I269
6 54
(NEED TO ADD 2 GND TP)
I354
I268
I388
PP3V3_S4 PP18V5_Z2
Z2_CS_L Z2_DEBUG3
74 77
(NEED TO ADD 5 GND TP)
I264
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3
60 61 85
LVDS FUNC_TEST
TP_CRT_IG_BLUE
17
81
(NEED TO ADD 5 GND TP)
SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_SUB_P_OUT
VOLTAGE
17
1
4
NC_SDVO_TVCLKINN
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
NC_SDVO_TVCLKINP
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
NC_SDVO_STALLP
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
NC_SDVO_INTP
NC_SDVO_STALLN
NC_SDVO_INTN
3
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
BRANCH
PAGE
7 OF 109 SHEET
6 OF 86
1
SIZE
D
8
7
6
64 63
=PPBUS_G3H
PPBUS_G3H
6
66
=PP3V3_S5_REG
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE
PPVIN_SW_T29BST VOLTAGE=12.8V
50
=PPVIN_S5_HS_COMPUTING_ISNS
=PPVIN_S5_HS_OTHER_ISNS
=PP18V5_DCIN_CONN
=PP3V42_G3H_REG
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE
=PPBUS_S5_FWPWRSW
39
=PP3V3_S3_P3V3S3FET
72
=PP1V8_S0_CPU_VCCPLL
14
=PP1V8_S0_PCH_VCCTX_LVDS
22
=PP1V8_S0_PCH_VCC_DFTERM
19 20 22
=PP1V8_S0_P1V05S0LDO
71
=PP1V8R1V5_S0_PCH_VCCVRM
20
=PPVDDIO_S0_SBCLK
24
50
=PP3V3_S5_CPU_VCCDDR
26
8 35
=PP3V3_S4_P3V3S4FET
72
=PPVIN_S5_HS_COMPUTING_ISNS_R
50
=PP3V3_S5_LCD
74
=PPVIN_S5_HS_OTHER_ISNS_R
50
=PP3V3_S5_PCH
17
=PP3V3_S5_PCHPWRGD
PPBUS_S5_HS_COMPUTING_ISNS
68 69 67
=PPVIN_S0_CPUVCCIOS0
70
=PPVIN_S0_VCCSAS0
65
=PPVIN_S0_CPUAXG
69
PPBUS_S5_HS_OTHER_ISNS 72
=PP3V3_SUS_FET
=PPVRTC_G3_OUT
=PP3V3_S5_PWRCTL
73
=PP3V3_S5_P3V3SUSFET
72
=PP1V5_S3_MEMRESET =PP1V5_S3_MEM_A
=PP3V3_S4_TBTAPWRSW
76
=PP1V5_S3_MEM_B
29
=PP3V3_S5_PCH_GPIO
19
=PPVIN_S0_DDRREG_LDO
67
=PPDDR_S3_MEMVREF
31
PP1V5_S3
6
VOLT AGE=3 .3V MAKE_ BASE= TRUE
20 22
=PP3V3_SUS_PCH_VCCSUS
20
=PP1V5_S3_P1V5S3RS0_FET
72
=PP1V5_S3_DDR_ISNS_R
49
16 17 18 19
=PP3V3_SUS_PWRCTL
73
=PPDCIN_S5_CHGR
64
=PP3V3_SUS_P1V05SUSLDO
71
=PPDCIN_S5_VSENSE
50
=PP3V3_SUS_SMC
46
PP3V42_G3H
6
=PP3V3_SUS_ROM
72
=PP3V3_S5_LPCPLUS
47
=PP3V3_S5_SMC
45 46
=PP3V42_G3H_BATT
63
=PP3V42_G3H_CHGR
64
=PP3V42_G3H_ONEWIREPROT
63
=PP3V42_G3H_PWRCTL
73
=PP3V42_G3H_SMBUS_SMC_BSA
48
=PP3V42_G3H_SMCUSBMUX
42
=PP3V42_G3H_TPAD
53
=PPVIN_S5_SMCVREF
46
=PPVBAT_G3_SYSCLK
24
=PP3V42_G3H_AUDIO
58
=PP3V3_S4_FET
20 22
6
VOLTAGE=3.3V MAKE_ BASE= TRUE 53 54
=PP3V3_S4_SMC
46
=PP3V3_S4_SD_HPD
=PP3V3_S3_FET
6
=PP3V3_S3_BT
32
=PP3V3_S3_MEMRESET
26
16 17 20
72
=PP3V3_S0_FET
PP5V_SUS MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
B 66
=PP5V_S3_REG
=PP5V_SUS_PCH
22
6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE
=PP5V_S3_ALSCAMERA =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP =PP5V_S3_DDRREG =PP5V_S3_IR =PP5V_S3_MEMRESET =PP5V_S3_ODD =PP5V_S3_P5VS0FET =PP5V_S3_USB
72
=PP5V_S0_FET
41 72
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE
=PP5V_S0_BKL
A
77 68 69 70
=PP5V_S0_FAN_RT
52
=PP5V_S0_HDD_ISNS_R
49
=PP5V_S0_KBDLED
54
=PP5V_S0_LPCPLUS =PP5V_S0_VCCSAS0
47
=PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_ISNS
=PP5V_S0_HDD_ISNS
65 22 24 73
7
=PP1V05_T29_FET
33 34 35
=PP3V3_T29_PCH_GPIO
16 19
PP1V05_T29
35
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
C
=PP1V05_T29_RTR
34
49
6
1V05 S0 LDO 27 29 26
=PP3V3_S3_P3V3ENETFET
73
=PP3V3_S3_PCH_GPIO
PPVCCSA_S0_CPU
6
18 24
=PPVCCSA_S0_REG
65
25
PP3V3_S0
71
PP1V05_S0_PCH_VCCADPLL
=PP1V05_S0_LDO
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCADPLL
22
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.9V MAKE_BASE=TRUE
49
=PPVCCSA_S0_CPU
12 15
6 85
VOLTAGE=3.3V MAKE_BASE=TRUE
=PP1V05_SUS_LDO
71
=PP3V3_S0_HDD
41
=PP3V3_S0_AUDIO
57 61 62
=PP3V3_S0_BKL_VDDIO
77
=PP3V3_S0_ISNS
49
=PP3V3_S0_HS_COMPUTING_ISNS
50 51
PP1V05_SUS MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
=PPCPUVCCIO_S0_REG
70
Chipset "VCore" Rails
=PP1V05_SUS_PCH_JTAG
23
PP1V05_S0
6
? mA
=PP3V3_S0_LCD
74
8
=PP3V3_S0_ENETPHY
36
=PPVCCIO_S0_CPUIMVP
68
=PP3V3_S0_FAN_RT
52
=PPVCCIO_S0_XDP
23
=PP1V05_S0_CPU_VCCIO
39 40
73
=PP1V05_S0_P1V05T29FET
35
1
2
39
XW0801
16 22
=PP3V3_S0_PCH_GPIO
16 17 18 19 30 22
=PP3V3_S0_PCH_VCC3_3_GPIO
20 22
=PP3V3_S0_PCH_VCC3_3_HVCMOS
20 22
=PP3V3_S0_PCH_VCC3_3_PCI
20 22
=PP3V3_S0_PCH_VCC3_3_SATA
20 22
=PP3V3_S0_PCH_VCCADAC
22
=PP3V3_S0_PCH_VCCA_LVDS
20
=PP3V3_S0_PWRCTL
73
=PP3V3_S0_RSTBUF
24
SM
1
24
48 48
=PP3V3_S0_SMC
41
=PP3V3_S0_KBDLED
54
=PP3V3_S0_VMON
73
9 12 14
=PPCPUVCORE_S0_VSENSE
49
PPVCORE_S0_AXG
6
B
VOLTAGE=1.05V MAKE_BASE=TRUE
39
=PPVCORE_S0_CPU_VCCAXG
9 12 15
=PPAXGVCORE_S0_VSENSE
49
PP1V05_S0_PCH MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V MAKE_BASE=TRUE
15 12
=PP1V05_S0_PCH_VCCIO_PLLPCIE
20
=PP1V05_S0_PCH
16 22
=PP1V05_S0_PCH_VCCIO
20 22
=PP1V05_S0_PCH_VCCIO_PCIE
17
=PP1V05_S0_PCH_VCCIO_SATA
16 20 22
=PP1V05_S0_PCH_VCCASW
20 22
=PP1V05_S0_PCH_VCCIO_USB
48
=PP3V3_S0_SMBUS_SMC_B_S0
2
=PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
39
=PP1V05_S0_FWPWRCTL =PP1V05_FW_P1V0FWFET =PP1V05_S0_VMON
41
=PPVCORE_S0_AXG_REG
46
35
XW0800 SM
6
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE
69
=PPVCCIO_S0_SMC
39
=PP3V3_S0_PCH_VCC3_3_CLK
PPVCORE_S0_CPU
=PPVCORE_S0_CPU_REG
9 10 12 14
30 71
69
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V MAKE_BASE=TRUE
=PP3V3_S0_DP_DDC
20 22
=PP1V05_S0_PCH_VCC_CORE
20 22
=PP1V05_S0_PCH_VCCIO_CLK
20 22
=PP1V05_S0_PCH_VCCDIFFCLK
16 20 22
=PP1V05_S0_PCH_VCCSSC
20 22
=PP1V05_S0_PCH_V_PROC_IO
20 22
=PP1V05_S0_PCH_VCCIO_PLLUSB =PP1V05_S0_PCH_VCC_DMI
PP1V5_S3_CPU_VCCDQ
=PP1V5_S3_CPU_VCCDQ
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE
14 12 8
PP1V05_S0_CPU_VCCPQE
=PP1V05_S0_CPU_VCCPQE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE
14 12
=PP1V8_S0_CPU_VCCPLL_R
PP1V8_S0_CPU_VCCPLL_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE
20 20 22
=PP1V05_S0_PCH_VCCIO_PLLFDI
20
=PP1V05_S0_PCH_VCCDMI_FDI
20
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Power Aliases
27
DRAWING NUMBER
SIZE
29
=PP3V3_S0_P1V5S0 =PP3V3_S0_T29PWRCTL =PP3V3_S0_HS_OTHER_ISNS
41
PP0V75_S0_DDRVTT MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE
=PP0V75_S0_MEM_VTT_B
=PPSPD_S0_MEM_A =PPSPD_S0_MEM_B
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.4MM VOLTAGE=5V MAKE_BASE=TRUE
8
35
24
=PP3V3_T29_RTR
PPVTTDDR_S3
=PP0V75_S0_MEM_VTT_A
=PP3V3_S0_SB_PM
PP5V_S0_HDD
=PP5V_S0_HDD
73
=PPVTT_S0_VTTCLAMP
=PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0
=PP5V_S0_AUDIO 49
20 22 24
=PP1V5_S0_VMON
24
=PP3V3_FW_P3V3FWFET =PP3V3_S0_PCH
42
=PP5V_S0_CPUVCCIOS0
57
=PP3V3R1V5_S0_PCH_VCCSUSHDA
32
=PP3V3_S0_ODD
26
=PP5V_S0_CPUIMVP
57
=PP3V3R1V5_S0_AUDIO
=PP3V3_S3_SDBUF
=PP3V3_S0_P1V8S0
41 44
6
=PP1V8R1V5_S0_AUDIO
=PP3V3_S3_WLAN
=PP3V3_S0_SDCARD
67
46
41
=PPVDDIO_T29_CLK
MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE
25
=PP3V3_S0_FWLATEVG =PP3V3_S0_P3V3T29FET
60
=PP5V_S3_SYSLED
=PP1V5_S0_RDRVR
31
=PP3V3_S0_FWPWRCTL 32 57
PP5V_S0
=PPVTT_S0_DDR_LDO
48
25
=PP3V3_S0_CPUTHMSNS
PP5V_S3
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
10 12 15 26
=PP3V3_S3_VREFMRGN
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM
72
72
=PPVTT_S3_DDR_BUF
67
48
55
=PP3V3_S3_ISNS =PP3V3_S3_USBMUX
54
67 31
76
PP3V3_T29
=PP3V3_T29_FET
MIN_LINE_WIDTH=0.3 MM
PP5V_S5
=PP5V_S5_P1V5DDRFET
35
MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE
32
=PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET
=PP5V_S5_TPAD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=17.8V MAKE_BASE=TRUE
PP1V5_S0
=PP1V5_S0_REG
VOLTAGE=3.3V MAKE_BASE=TRUE
=PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMBUS_SMC_MGMT
PPVRTC_G3H
=PP5V_S5_P5VSUSFET
PP15V_T29
=PP15V_T29_REG
6 85
=PP1V5_S3_CPU_VCCDDR
30
PP3V3_S3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
PP1V5_S3RS0 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE
71
=PP3V3_S4_TPAD
38 39
T29 Rails (off when no cable) 35 8
56
=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_S4_BT 72
=PP1V0_FW_FWPHY
=PPHV_SW_TBTAPWRSW =PP1V5_S3RS0_FET
72
PP3V3_S4 MIN_LINE_WIDTH=0.50MM MIN_N ECK_W IDTH= 0.20M M
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE
=PP5V_SUS_FET
MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE
=PP3V3_SUS_PCH_VCCSUS_GPIO
22
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE
27
=PP3V3_SUS_PCH_VCCSUS_USB
20 22
D
38 39 40
PP1V0_FW_FWPHY
=PP1V0_FW_FET_R
26
66
5V Rails
72
=PPDDR_S3_REG
67
39
66
=PPVRTC_G3_PCH
=PP5V_S5_LDO
MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.5V MAKE_BASE=TRUE
PP3V3_SUS
=PP3V3_SUS_PCH_GPIO
40
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
=PP3V3_S0_P1V05FWFET
73
=PP3V3_SUS_PCH
40
PP3V3_FW_FWPHY
=PP3V3_FW_FET
=PP3V3_FW_FWPHY
=PP3V3_S5_VMON
49
=PPVIN_S5_3V3S5 PPDCIN_G3H
=PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET
39
PP1V5_S3_DDR
=PP1V5_S3_DDR_ISNS
20 22 24
MIN_L INE_W IDTH= 0.50M M MIN_N ECK_W IDTH= 0.20M M
PPVP_FW
=PPBUS_FW_FET
46
=PP3V3_S5_PCH_VCCDSW
=PPVIN_S5_5VS3
MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3V MAKE_BASE=TRUE
66
39
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.8V MAKE_BASE=TRUE
=PP3V3_S5_SYSCLK
=PP3V3_S3_SMS 24
2A max supply
24
=PP3V3_S5_SMCBATLOW
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE
C
6
72
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE
63
PP1V8_S0
=PP1V8_S0_REG
71 23
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.8V MAKE_BASE=TRUE
63
6 85
VOLTAGE=3.3V MAKE_BASE=TRUE
=PP3V3_S0_P3V3S0FET
=PPVIN_SW_T29BST
1
"FW" (FireWire) Rails
=PP3V3_S5_XDP
=PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG
50
PP3V3_S5 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
2
3 1.8V/1.5V/1.2V/1.05V Rails
77
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE
D
4
=PPBUS_S0_LCDBKLT =PPBUS_S0_VSENSE 35
5 3.3V Rails
"G3Hot" (Always-Present) Rails
ENET Rails
71 35
73
=PP3V3_ENET_FET
Apple Inc.
PP3V3_ENET
6
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE
50
NOTICE OF PROPRIETARY PROPERTY:
=PP3V3_S0_DPSDRVA
75
=PP3V3_S0_P1V05S0LDO
71
=PP3V3_ENET_PHY
=PP3V3_S0_IMVPISNS
49
=PP3V3_ENET_SYSCLK
24
=PP3V3_S0_XDP
23
=PPVDDIO_ENET_CLK
24
=PP3V3_S0_T29I2C
48
5
4
R
24 36 71
3
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
BRANCH
PAGE
8 OF 109 SHEET
7 OF 86
1
D
A
8
7
6
5
4
CPU signals
9 9
HEATSINK STANDOFFS
26
MEMVTT_EN
=DDRVTT_EN
26 67
DP_EXTA_ML_C_P<3..0>
81 75
MAKE_BASE=TRUE
=PEG_R2D_C_N<12..15>
9
=PEG_D2R_P<12..15>
9
=PEG_D2R_N<12..15>
MAKE_BASE=TRUE
Z0902 STDOFF-4.5OD.98H-1.1-3.48-TH
MAKE_BASE=TRUE MAKE_BASE=TRUE
DP_EXTA_ML_C_N<3..0>
81 75
PCIE_T29_R2D_C_P<3..0>
33 81
PCIE_T29_R2D_C_N<3..0>
33 81
PCIE_T29_D2R_P<3..0>
33 81
PCIE_T29_D2R_N<3..0>
33 81
17
TP_DP_IG_B_MLN<3..0>
17
DP_EXTA_AUXCH_C_P
DPA_IG_AUX_CH_P
17
DP_EXTA_AUXCH_C_N
DPA_IG_AUX_CH_N
5% 1/16W MF-LF 402
17
MAKE_BASE=TRUE
Z0904
D
FAN STANDOFF
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
FW_PLUG_DET_L
1
FW_PME_L
19 39
BELOW CPU
FW643_WAKE_L
39
2
TP_DP_IG_D_CTRL_CLK
17
TP_DP_IG_D_CTRL_DATA
LEFT OF CPU
MLB MOUNTING (TO C. BRACKET) SCREW HOLES OMIT
OMIT
Z0906
Z0907
3R2P5
3R2P5
PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P
16
PCIE_EXCARD_R2D_C_N
16
PCIE_EXCARD_R2D_C_P PCIE_CLK100M_EXCARD_N
PCIE_PCH_D2R_N<5..8> PCIE_PCH_R2D_C_N<5..8> PCIE_PCH_R2D_C_P<5..8> PEG_CLK100M_P PEG_CLK100M_N
17
17 17
OMIT
OMIT
Z0909
Z0910
3R2P5
3R2P5
3R2P5
C
17
OMIT
OMIT
Z0911
Z0912
33 83
DP_T29SNK0_AUXCH_C_N
33 83
33
MAKE_BASE=TRUE MAKE_BASE=TRUE
TP_DP_IG_D_AUXN
DP_T29SNK1_ML_C_N<3..0> DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N
D 33 83 33 83 33 83 33 83
MAKE_BASE=TRUE
R09241
R09251
5% 1/16W MF-LF 402 2
BCM57765_CE_L_MS_INS_L
5% 1/16W MF-LF 402 2
NO_TEST=TRUE
2.2K
6
TP_LVDS_IG_B_CLKP
6
TP_LVDS_IG_B_CLKN
LVDS_IG_B_CLK_P
17 80
LVDS_IG_B_CLK_N
17 80
MAKE_BASE=TRUE
DPA_IG_DDC_CLK
17
DPA_IG_DDC_DATA
17
DPA_IG_HPD
17
MAKE_BASE=TRUE
DP_EXTA_DDC_DATA DP_EXTA_HPD
MAKE_BASE=TRUE MAKE_BASE=TRUE
1
R0908
NC_PCIE_PCH_R2D_CN<5..8> NC_PEG_CLK100MP
NC_LVDS_IG_A_DATAP<3>
5% 1/16W MF-LF 402
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
74 6
17 80
LVDS_IG_A_DATA_P<3>
17 80
LVDS_IG_A_DATA_N<3>
17 80
LVDS_IG_DDC_CLK
17
LVDS_IG_DDC_DATA
17
LVDS_IG_BKL_PWM
17
LVDS_IG_PANEL_PWR
17
LVDS_IG_BKL_ON
17
NO_TEST=TRUE
MAKE_BASE=TRUE
2
LVDS_IG_B_DATA_N<0..3>
NO_TEST=TRUE
100K
NC_PEG_CLK100MN
17 80
NO_TEST=TRUE
NC_LVDS_IG_B_DATAN<0..3>
MAKE_BASE=TRUE
NC_PCIE_PCH_R2D_CP<5..8>
LVDS_IG_B_DATA_P<0..3>
NC_LVDS_IG_B_DATAP<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
LVDS_DDC_CLK MAKE_BASE=TRUE
77
PPBUS_SW_LCDBKLT_PWR
1
MAKE_BASE=TRUE
16
TP_PCH_CLKOUT_DPN
NC_PCH_CLKOUT_DPN TRUE MAKE_BASE=TRUE
16
TP_PCH_CLKOUT_DPP
NC_PCH_CLKOUT_DPP TRUE MAKE_BASE=TRUE
74 6
0
LVDS_DDC_DATA MAKE_BASE=TRUE
2
77
PPBUS_SW_BKL
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=12.6V MAKE_BASE=TRUE
5% 1/16W MF-LF 402
LCD_BKLT_PWM
=PPBUS_SW_BKL
74
LCD_IG_PWR_EN MAKE_BASE=TRUE
77
77
LCD_BKLT_EN
C
MAKE_BASE=TRUE
CPU_VCCIO_SEL
NC_CPU_VCCIO_SEL
3R2P5
3R2P5
MAKE_BASE=TRUE
1
1
MAKE_BASE=TRUE
=PP3V3_S0_DP_DDC
MAKE_BASE=TRUE 75
33 83
DP_T29SNK0_AUXCH_C_P
DP_T29SNK1_ML_C_P<3..0>
TP_DP_IG_D_MLP<3..0> TP_DP_IG_D_AUXP
DP_EXTA_DDC_CLK
75
33 83
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK1_HPD
TP_DP_IG_D_MLN<3..0>
R0910
1
1
1
TP_DP_IG_D_HPD
17
MAKE_BASE=TRUE
Z0908
MAKE_BASE=TRUE
17
MLB MOUNTING (TO TOPCASE) SCREW HOLES OMIT
33
DP_T29SNK0_ML_C_P<3..0>
MAKE_BASE=TRUE
17
2.2K
NC_PCIE_PCH_D2RP<5..8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE
NC_BCM57765_CE_L_MS_INS_L
NC_PCIE_PCH_D2RN<5..8>
TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE
PCIE_PCH_D2R_P<5..8>
81 16
DPB_IG_AUX_CH_N
MAKE_BASE=TRUE
75
81 16
DPB_IG_AUX_CH_P
17
2
DP_IG_D_CTRL_DATA
38 39
NC_PCIE_EXCARD_D2RN TRUE MAKE_BASE=TRUE NC_PCIE_EXCARD_D2RP TRUE MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_CN TRUE MAKE_BASE=TRUE NC_PCIE_EXCARD_R2D_CP TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_EXCARDN TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_EXCARDP TRUE MAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_P
1
1
TP_DP_IG_C_MLN<3..0>
17
DP_T29SNK0_HPD
MAKE_BASE=TRUE
8 7
16
81 16
17
SMC_EXCARD_PWR_EN
16
81 16
TP_DP_IG_C_MLP<3..0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Z0920
2
MAKE_BASE=TRUE
=FW_PME_L
TP_SMC_EXCARD_PWR_EN
1
DPB_IG_HPD
17
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
5% 1/16W MF-LF 402
DP_IG_D_CTRL_CLK
17
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
DPB_IG_DDC_CLK DPB_IG_DDC_DATA
TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA
Z0905
1
2
2.2K
2.2K
2.2K 5% 1/16W MF-LF 402
R0923
R0922
R0921
2.2K
1
1
1
1
R0920
MAKE_BASE=TRUE 81 75
17
MAKE_BASE=TRUE
=PP3V3_S0_DP_DDC
8 7
MAKE_BASE=TRUE 81 75
1 T29 DP Ports
MAKE_BASE=TRUE
TP_DP_IG_B_MLP<3..0>
MAKE_BASE=TRUE
1
2
3
=PEG_R2D_C_P<12..15>
12 78
NO_TEST=TRUE
USB Signals NC_USB3_EXTD_TXN MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
0
1
MAKE_BASE=TRUE
80 32
18
80 53
USB3_EXTD_RX_P
18
80 53
14 12 7
80 44
R0940
DP_A_BIAS0
C0960
C0962
1
0.01UF
B
ZS0900
ZS0902
ZS0901
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
SM
SM
1
ZS0910
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
SM
10
DP_A_BIAS2
75
10
EMI IO (SHORT) POGO PINS
R0971 201 76 75 8
1
NC_USB_SMCN
USB_SMC_P
NC_USB_SMCP
MF
1
EMI TALL POGO PINS ZS0905
ZS0906
ZS0907
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
SM
VOLTAGE=3.3V
ZS0921
ZS0922
ZS0923
ZS0924
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
1
NO STUFF NO STUFF
SM
SM
NO STUFF
51 1
51 1
USB3_EXTC_RX_N
18
B
18
USB3_EXTC_RX_P USB_EXTD_XHCI_N
18 80
NO_TEST=TRUE
NC_USB_EXTD_XHCIP MAKE_BASE=TRUE
USB_EXTD_XHCI_P
18 80
CPU_THERMD_P
9 85
CPU_THERMD_N
9 85
NO_TEST=TRUE
TP_CPU_THERMDP MAKE_BASE=TRUE
TP_CPU_THERMDN MAKE_BASE=TRUE
10% 10V X5R-CERM 0201
T29_A_BIAS_D2RN1
MF
VOLTAGE=3.3V
83 33
OUT
T29_D2R_P<2..3>
83 33
OUT
T29_D2R_N<2..3>
83 33
IN
T29_R2D_C_P<2..3>
83 33
IN
T29_R2D_C_N<2..3>
33
IN
T29_LSEO<2>
33
IN
T29_LSEO<3>
T29_A_BIAS_D2RP1
2 5%
VOLTAGE=3.3V
C0973
1
CPU_VTTSELECT
10% 10V X5R-CERM 2 0201
2
SM 1
Digital Ground
NC_T29_D2RP<2..3> MAKE_BASE=TRUE
NO_TEST=TRUE
NC_T29_D2RN<2..3> M A KE _ B ASE =TR UE
0.01UF
GND
NO_ TES T=T RUE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
NC_T29_R2D_CP<2..3> MAKE_BASE=TRUE
NO_TEST=TRUE
NC_T29_R2D_CN<2..3> M A KE _ B ASE =TR UE
NO_ TES T=T RUE
T29_LSOE<2> MAKE_BASE=TRUE
T29_LSOE<3>
MAKE_BASE=TRUE
OUT
33
OUT
33
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
Signal Aliases DRAWING NUMBER
NO STUFF
TBT JTAG
NO STUFF
7
18
NO_TEST=TRUE
NC_USB3_EXTC_RXP MAKE_BASE=TRUE NO_TEST=TRUE NC_USB_EXTD_XHCIN
1
2 5%
1/20W
MF
23 19
IN
19
IN
19
8
18
USB3_EXTC_TX_P
NO_TEST=TRUE NO_TEST=TRUE
76
10% 10V X5R-CERM 2 0201
0.01UF
POGO-2.0OD-3.5H-K86-K87
1
18 80
USB3_EXTC_TX_N
NO_TEST=TRUE
MAKE_BASE=TRUE
VOLTAGE=3.3V
USB_EXTC_P
2
C0972 1
ZS0920
SM
MAKE_BASE=TRUE
NC_USB3_EXTC_TXN
T29_A_BIAS_R2DN1
2 5%
18 80
NO_TEST=TRUE
MAKE_BASE=TRUE
POGO-2.0OD-3.5H-K86-K87
1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=TBT_S0_EN
PM_SLP_S3_L
18
USB_EXTC_N
Unused T29 Ports
TALL POGO PINS close to DIMM conn.
SM
NC_USB_EXTCP
MAKE_BASE=TRUE
C0971
R0973 201 1/20W
1
5% 1/16W MF-LF 402
0.01UF
1
1
R0972 201
A
NC_USB_EXTCN
1K
18
USB_EXTD_EHCI_P
NO_TEST=TRUE
R0941
2
SM
SM
1
1
DPLL_REF_CLKN
NO_TEST=TRUE
USB_EXTD_EHCI_N
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_CPU_VTT_SELECT
ZS0904 POGO-2.0OD-3.5H-K86-K87 SM
MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MF
0.01UF 10% 10V X5R-CERM 0201
25
NO_TEST=TRUE
T29_A_BIAS_R2DP0
2 5%
1/20 W
25
USB_SMC_N
NC_USB_EXTD_EHCIN
75
51
1/20W
51
R0970 201
USBHUB_DN2_N
80 45
NC_USB_EXTD_EHCIP
MAKE_BASE=TRUE
75
T29_A_BIAS_R2DP1 T29_A_BIAS_R2DN0
T29_A_BIAS
25
80 45
NC_USB3_EXTC_RXN
C0970 1
1
DPLL_REF_CLK_N
2
1
1
USBHUB_DN3_P
USBHUB_DN2_P
MAKE_BASE=TRUE
SM
1
USB_IR_P
NC_USB3_EXTC_TXP
1.4DIA-SHORT-SILVER-K99
SM
USB_IR_N
MAKE_BASE=TRUE
10% 10V X5R-CERM 2 0201
10% 10V X5R-CERM 2 0201
ZS0909
1.4DIA-SHORT-SILVER-K99
USB_TPAD_P
DPLL_REF_CLKP
0.01UF
0.01UF
10% 10V X5R-CERM 2 0201
DPLL_REF_CLK_P
C0964 1
1
73 45 26 17 6
ZS0903
25
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
SM
1
1
25
USBHUB_DN3_N
MAKE_BASE=TRUE
1
Unused eDP CLK 75
25
USBHUB_DN1_P
MAKE_BASE=TRUE
=PP1V05_S0_CPU_VCCPQE
1K
T29_A_BIAS
USB_TPAD_N
MAKE_BASE=TRUE
5% 1/8W MF-LF 805
76 75 8
USBHUB_DN1_N
USB_BT_P
MAKE_BASE=TRUE
NO_TEST=TRUE
7 35
USB_BT_N MAKE_BASE=TRUE MAKE_BASE=TRUE
80 44
=PP15V_T29_REG
2
80 32
18
USB3_EXTD_RX_N
NO_TEST=TRUE
NC_USB3_EXTD_RXP
R0960
=PPVIN_SW_T29BST
35 7
18
USB3_EXTD_TX_P
NO_TEST=TRUE
NC_USB3_EXTD_RXN
T29BST:N
USB3_EXTD_TX_N
NO_TEST=TRUE
NC_USB3_EXTD_TXP
6
OUT
JTAG_ISP_TCK
OUT
33
JTAG_TBT_TDI
OUT
19 33
MAKE_BASE=TRUE
JTAG_ISP_TDI MAKE_BASE=TRUE
JTAG_TBT_TDO
JTAG_ISP_TDO MAKE_BASE=TRUE
5
Apple Inc.
Unused PGOOD signal
JTAG_TBT_TCK
TP_P1V5S3RS0_RAMP_DONE
P1V5S3RS0_RAMP_DONE
MAKE_BASE=TRUE
TP_DDRREG_PGOOD
DDRREG_PGOOD
MAKE_BASE=TRUE
IN
33
4
3
R
IN
72
IN
67
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
BRANCH
PAGE
9 OF 109 SHEET
8 OF 86
1
SIZE
D
A
8
7
6
5
4 NOTE:
OMIT_TABLE 78
78 17
D
DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>
IN IN
78 17
IN
78 17
IN
78 17
IN
78 17
IN
78 17
IN
M2 P6
DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>
78 17
IN
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
DMI_RX_0*
PEG_ICOMPI G3 PEG_ICOMPO G1 PEG_RCOMPO G4
DMI_RX_1*
IVY-BRIDGE
P1
DMI_RX_2*
2C-35W
P10
DMI_RX_3*
N3
DMI_RX_0
P7
DMI_RX_1
P3
DMI_RX_2
P11
DMI_RX_3
DMI_N2S_N<0> DMI_N2S_N<1>
K1
DMI_TX_0*
M8
DMI_TX_1*
DMI_N2S_N<2> DMI_N2S_N<3>
N4 R2
DMI_TX_2* DMI_TX_3*
DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>
U1000
BGA
(1 OF 9)
PEG_RX_0* H22 PEG_RX_1* J21 PEG_RX_2* B22 PEG_RX_3* D21 PEG_RX_4* A19 PEG_RX_5* D17 PEG_RX_6* B14 PEG_RX_7* D13 PEG_RX_8* A11 PEG_RX_9* B10
I M D
K3
DMI_TX_0
PEG_RX_10* G8
M7
DMI_TX_1
PEG_RX_11* A8
P4
DMI_TX_2
PEG_RX_12* B6
T3
DMI_TX_3
PEG_RX_13* H8 PEG_RX_14* E5
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
C
14 12 10 9 7
FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7> FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3>
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT OUT
78 17
OUT
78 17
IN
78 17
IN
FDI_FSYNC<0> FDI_FSYNC<1>
78 17
IN
FDI_INT
=PP1V05_S0_CPU_VCCIO
R1030 24.9 1
78 17
IN
78 17
IN
2
78
1% 1/16W MF-LF 402
FDI0_TX_0* FDI0_TX_1*
W1
FDI0_TX_2*
AA6
FDI0_TX_3*
W6
FDI1_TX_0*
V4
FDI1_TX_1*
Y2
FDI1_TX_2*
AC9
FDI1_TX_3*
U6
FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7>
78 17
U7 W11
FDI0_TX_1
W3
FDI0_TX_2
AA7
FDI0_TX_3
W7
FDI1_TX_0
T4
FDI1_TX_1
AA3
FDI1_TX_2
AC8
FDI1_TX_3
U11
FDI_LSYNC<0> FDI_LSYNC<1> EDP_COMP
EDP_HPD
FDI0_LSYNC FDI1_LSYNC
AD2
EDP_ICOMPO
AF3
EDP_COMPIO
AG11
1
10K
6
2
6
1% 1/16W MF-LF 402
TP_EDP_AUX_N TP_EDP_AUX_P
PLACE_NEAR=U1000.AG11:12.7MM
6 6 6 6
6 6
B
6 6
TP_EDP_TX_N<0> TP_EDP_TX_N<1> TP_EDP_TX_N<2> TP_EDP_TX_N<3> TP_EDP_TX_P<0> TP_EDP_TX_P<1> TP_EDP_TX_P<2> TP_EDP_TX_P<3>
PEG_RX_2 C21 PEG_RX_3 D19 PEG_RX_4 C19 PEG_RX_5 D16 PEG_RX_6 C13 PEG_RX_7 D12 PEG_RX_8 C11 S L A N G I S E C A F R E T N I D E S A B S S E R P X E I C P
FDI_INT
AG8
EDP
R1031
FDI0_FSYNC FDI1_FSYNC
AA10
PLACE_NEAR=U1000.AF3:12.7MM
PEG_RX_0 K22 PEG_RX_1 K19
S L A N G I S E C A F R E T N I Y A L P S I D E L B I X E L F L E T N I
FDI0_TX_0
W10
AA11 AC12
PEG_RX_15* K7
EDP_AUX*
AF4
EDP_AUX
AC3
EDP_TX_0*
AC4
EDP_TX_1*
AE11
EDP_TX_2*
AE7
EDP_TX_3*
AC1
EDP_TX_0
AA4
EDP_TX_1
AE10
EDP_TX_2
AE6
EDP_TX_3
PEG_RX_12 C5 PEG_RX_13 H6 PEG_RX_14 F6 PEG_RX_15 K6 PEG_TX_0* G22 PEG_TX_1* C23 PEG_TX_2* D23 PEG_TX_3* F21 PEG_TX_4* H19 PEG_TX_5* C17 PEG_TX_6* K15 PEG_TX_7* F17 PEG_TX_8* F14 PEG_TX_9* A15
T R O P Y A L P S I D D E D D E B M E
EDP_HPD
AG4
PEG_RX_9 C9 PEG_RX_10 F8 PEG_RX_11 C8
PEG_TX_10* J14 PEG_TX_11* H13 PEG_TX_12* M10 PEG_TX_13* F10 PEG_TX_14* D9 PEG_TX_15* J4 PEG_TX_0 F22 PEG_TX_1 A23 PEG_TX_2 D24 PEG_TX_3 E21 PEG_TX_4 G19 PEG_TX_5 B18 PEG_TX_6 K17 PEG_TX_7 G17
Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.
NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating even if internal Graphics is disabled since they are shared with other interfaces.
PEG_TX_8 E14 C15
PEG_TX_9
PEG_TX_10 K13 PEG_TX_11 G13
NOTE: The EDP_HPD processor input is a low voltage active low signal. Therefore, an inverting level shifter is required on the motherboard to convert the active high signal from Embedded DisplayPort sink device to low voltage signals for the processor (refer to latest Processor EDS for DC specifications). If HPD is disabled while eDP interface is still enabled, connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard. This signal can be left as no-connect if entire eDP interface is disabled.
78 23 9 78 23 9 78 23 9 78 23 9 78 23 9
23 9
CPU_CFG<7> CPU_CFG<6> CPU_CFG<5> CPU_CFG<4> CPU_CFG<2>
R1042
1
78 23 9 78 23 9
EDP
1
R1044
NOSTUFF 1
R1045
1K
1K
A
78 23 9
1K
5%
5%
5%
1/20W
1/20W
1/20W
MF
MF
MF
201
2
201
2
201
NOSTUFF
1
R1046 5% MF
2
201
NOSTUFF 1
2
PEG_TX_14 D8 PEG_TX_15 K4
R1040
1
NOSTUFF
R1041
1K
NOSTUFF
1
R1043
1K
1
NOSTUFF
R1049
1K
=PEG_D2R_N<0> =PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3> =PEG_D2R_N<4> =PEG_D2R_N<5> =PEG_D2R_N<6> =PEG_D2R_N<7> =PEG_D2R_N<8> =PEG_D2R_N<9> =PEG_D2R_N<10> =PEG_D2R_N<11> =PEG_D2R_N<12> =PEG_D2R_N<13> =PEG_D2R_N<14> =PEG_D2R_N<15> =PEG_D2R_P<0> =PEG_D2R_P<1> =PEG_D2R_P<2> =PEG_D2R_P<3> =PEG_D2R_P<4> =PEG_D2R_P<5> =PEG_D2R_P<6> =PEG_D2R_P<7> =PEG_D2R_P<8> =PEG_D2R_P<9> =PEG_D2R_P<10> =PEG_D2R_P<11> =PEG_D2R_P<12> =PEG_D2R_P<13> =PEG_D2R_P<14> =PEG_D2R_P<15> =PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7> =PEG_R2D_C_N<8> =PEG_R2D_C_N<9> =PEG_R2D_C_N<10> =PEG_R2D_C_N<11> =PEG_R2D_C_N<12> =PEG_R2D_C_N<13> =PEG_R2D_C_N<14> =PEG_R2D_C_N<15> =PEG_R2D_C_P<0> =PEG_R2D_C_P<1> =PEG_R2D_C_P<2> =PEG_R2D_C_P<3> =PEG_R2D_C_P<4> =PEG_R2D_C_P<5> =PEG_R2D_C_P<6> =PEG_R2D_C_P<7> =PEG_R2D_C_P<8> =PEG_R2D_C_P<9> =PEG_R2D_C_P<10> =PEG_R2D_C_P<11> =PEG_R2D_C_P<12> =PEG_R2D_C_P<13> =PEG_R2D_C_P<14> =PEG_R2D_C_P<15>
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
PLACE_NEAR=U1000.H43:50.8MM PLACE_SIDE=BOTTOM
=PPVCORE_S0_CPU NOSTUFF
1
IN
6
R1064
IN
6
49.9
IN
8
IN
8
1% 1/16W MF-LF 402
IN
8
IN
8
1
R1070 49.9 1% 1/16W MF-LF
2
2 402 PLACE_NEAR=U1000.H45:50.8MM
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
8
IN
8
IN
8
Note. VOLTAGE=0V
IN
8
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23
IN
78 23
IN
78 23
IN
78 23
IN
23 78
IN
78 23
IN
78 23
IN
78 23
IN
23 9
IN
23
IN
12 15
CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10>
B50 CFG_0 C51 CFG_1
CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16> CPU_CFG<17>
K53 CFG_11 F53 CFG_12 G53 CFG_13
Note. VOLTAGE=1.05V Note. VOLTAGE=0V
1
R1065
R1071 49.9
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
(5 OF 9) RESERVED
C55 CFG_6 H49 CFG_7
E W G 5 D 3 I R C B 2 Y V I
BGA
A55 CFG_8 H51 CFG_9 K49 CFG_10
L51 CFG_14 F51 CFG_15 D52 CFG_16 L53 CFG_17
H45 VAXG_VAL_SENSE K45 VSSAXG_VAL_SENSE
TP_CPU_VCC_DIE_SENSE
F48 VCC_DIE_SENSE
OUT
85 8
OUT
CPU_THERMD_P CPU_THERMD_N
VSS_VAL_SENSE
H48 RSVD_6 K48 RSVD_7
NOTE: Intel does not recommend to use BA19 RSVD_8 this alnalog sense due to accuracy concern. NC 2 AV19 RSVD_9 PLACE_NEAR=U1000.K45:50.8MM
NC AT21 NC BB21 NC BB19 NC AY21 NC BA22 NC AY22 NC
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.K43:50.8MM PLACE_SIDE=BOTTOM
NOTE:
U1000
A51 CFG_4 C53 CFG_5
CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N
85 8
Intel validation sense lines per
doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.
AU19 NC AU21 NC BD21 NC BD22 NC BD25 NC BD26 NC BG22 NC BE22 NC BG26 NC BE26 NC BF23 NC BE24 NC
PPCPU_MEM_VREFDQ_A PPCPU_MEM_VREFDQ_B
SB_DIMM_VREFDQ BG7
H43 VCC_VAL_SENSE K43
1
49.9
SA_DIMM_VREFDQ BE7
B54 CFG_2 D53 CFG_3
CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N
NOSTUFF
NOSTUFF
OUT
IN
PLACE_SIDE=BOTTOM Note. VOLTAGE=1.25V
IN
78 23 9
7 12 14
=PPVCORE_S0_CPU_VCCAXG 7 NOSTUFF
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V
7 9 10 12 14
D
RSVD_35 M14 NC RSVD_36 U14 NC RSVD_37 W14 NC
RSVD_38 P13 NC RSVD_39 AT49 NC RSVD_40 K24 NC RSVD_41 AH2 NC RSVD_42 AG13
NC
RSVD_43 AM14 NC RSVD_44 AM15
NC
RSVD_45 N50 NC
DC_TEST_A4 A4 DC_TEST_C4 C4
TP_CPU_DC_TEST_A4 CPU_DC_TEST_C4_D3
DC_TEST_D3 D3 DC_TEST_D1 D1 A58
DC_TEST_A58
TP_CPU_DC_TEST_D1 TP_CPU_DC_TEST_A58
DC_TEST_A59 A59 CPU_DC_TEST_C59_A59 DC_TEST_C59 C59
RSVD_12
DC_TEST_A61 A61 CPU_DC_TEST_C61_A61
RSVD_13
DC_TEST_C61 C61
RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20
31
RSVD_34 M13 NC
RSVD_11
RSVD_15
31
OUT
RSVD_32 L45 NC RSVD_33 L47 NC
RSVD_10
RSVD_14
OUT
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V
RSVD_30 N42 NC RSVD_31 L42 NC
C
DC_TEST_D61 D61 TP_CPU_DC_TEST_D61 DC_TEST_BD61 BD61 TP_CPU_DC_TEST_BD61 DC_TEST_BE61 BE61 CPU_DC_TEST_BE59_BE61 DC_TEST_BE59 BE59 DC_TEST_BG61 BG61 CPU_DC_TEST_BG59_BG61 DC_TEST_BG59 BG59 DC_TEST_BG58 BG58 TP_CPU_DC_TEST_BG58
RSVD_21
DC_TEST_BG4 BG4
RSVD_22
DC_TEST_BG3 BG3
RSVD_23
DC_TEST_BE3 BE3
RSVD_24
DC_TEST_BG1 BG1
CPU_DC_TEST_C4_BE1_BG1
RSVD_25 RSVD_26
DC_TEST_BE1 BE1 DC_TEST_BD1 BD1
TP_CPU_DC_TEST_BD1
TP_CPU_DC_TEST_BG4 CPU_DC_TEST_C4_BE3_BG3
RSVD_27
B
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
201
2
2
201
201
2
1
1K
5% 1/20W
201
CRITICAL
=PP1V05_S0_CPU_VCCIO
2 1% 1/16W MF-LF 402
CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>
NOSTUFF
R1047
OMIT_TABLE
24.9 1
PLACE_NEAR=U1000.G3:12.7MM
CPU_CFG<16>
1K
1K 1/20W
PEG_TX_12 K10 PEG_TX_13 G10
CPU_PEG_COMP
1
Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.
R1010
CRITICAL 78 17
2
3
201
2
2
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU DMI/PEG/FDI/RSVD DRAWING NUMBER These can be Placed close to
Apple Inc. R
CFG [7] :PEG DEFER TRAINING
1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB
CFG [6:5] :PCIE BIFURCATION
11 = 1 X16 (DEFAULT)
10 = 2 X8
1 = DISABLED
CFG [3] :PCIE x4 LANE REVERSAL
1 = NORMAL OPERATION
0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL
1 = NORMAL OPERATION
0 = LANES REVERSED
8
7
NOTICE OF PROPRIETARY PROPERTY:
0 = WAIT FOR BIOS
01 = RSVD
CFG [4] :eDP ENABLE/DISABLE
SIZE
J2500 and Only for debug access
FOR IVYBRIDGE PROCESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
00 = X8, X4, X4
0 = ENABLED
6
5
4
3
2
051-9058 6.0.0
REVISION
D
BRANCH
PAGE
10 OF 109 SHEET
9 OF 86
1
A
8
7
6
5
4
2
3
1
D
D
14 12 10 9 7
OMIT_TABLE
=PP1V05_S0_CPU_VCCIO
CRITICAL
U1000 NOSTUFF
R1100 1
1
1
2
2
201
R1102
2C-35W
1/20W
NC
201
19
OUT
CPU_PROC_SEL_L
78 45
OUT
CPU_CATERR_L
C49 CATERR*
78 46 19
R1103 78 68 46 45
26 15 12 7
BI
CPU_PROCHOT_L
2
R1120
56
78 46 19
78 26 17
IN
78 17
R1121
2
PM_MEM_PWRGD
2
130
C45 PROCHOT*
OUT
D45 THERMTRIP*
IN
PM_SYNC
C48 PM_SYNC
78 23 19
IN
CPU_PWRGD
B46 UNCOREPWRGOOD
PM_MEM_PWRGD_R
1
BE45 SM_DRAMPWROK
PLT_RESET_LS1V1_L 26
OUT
D44 RESET*
=MEM_RESET_L
AT30 SM_DRAMRST*
CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>
78 78 78
BF44 SM_RCOMP_0 BE43 SM_RCOMP_1 BG43 SM_RCOMP_2
=PP1V05_S0_CPU_VCCIO
1
B
R1126
1
1% 1/16W MF-LF 402
IN
CPU_RESET_L
2 2
R1112
1
140
75
24 23
16 78
IN
8
IN
8
K C O L C
ITPCPU_CLK100M_P ITPCPU_CLK100M_N
IN
16 78
IN
16 78
A48 PECI
PM_THRMTRIP_L
1% 1/16W MF-LF 402
14 12 10 9 7
IN
16 78
L A M R E H T
BCLK_ITP N59 BCLK_ITP* N58 (IPU)
PRDY*
N53
(IPU)
PREQ*
N55
(IPU)
TCK
L56
(IPU)
TMS
L55
(IPU)
TRST*
J58
(IPU)
TDI
M60
TDO
L59
XDP_CPU_PRDY_L XDP_CPU_PREQ_L XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L
OUT
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
C
1
200 1% 1/16W MF-LF 402
BI
CPU_PECI
CPU_PROCHOT_R_L
1
5% 1/20W MF 201
=PP1V5_S3_CPU_VCCDDR
IN
DPLL_REF_CLK_P DPLL_REF_CLK_N
H2
DPLL_REF_CLK AG3
C57 PROC_DETECT* F49 PROC_SELECT*
C
DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N
BCLK*
201
MF 2
AG1 S DPLL_REF_CLK*
(2 OF 9)
MF
2
BCLK J3
BGA
5%
1/20W MF
201
1/20W
IVY-BRIDGE
NOSTUFF 1K
5%
5% 1/20W MF
5%
1
51
1K
R1101 62
NOSTUFF
R1104
R1113
1
25.5
R1114
1%
1%
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
402
2
402
1
2
402
C S I M 3 R D D
M P B & G A T J
DBR* K58 (IPU) BPM_0* (IPU) BPM_1*
G58
(IPU) BPM_2* (IPU) BPM_3*
E59
(IPU) BPM_4* (IPU) BPM_5*
G59
(IPU) BPM_6* (IPU) BPM_7*
J59
OUT
23 78
XDP_DBRESET_L
OUT
23 24 78
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>
E55 G55 H60 J61
BI
23 78
BI
23 78
BI
23 78
BI
23 78
BI
23
BI
23
BI
23
BI
23
R1111
B
10K
200
1%
T M G M R W P
XDP_CPU_TDI XDP_CPU_TDO
5% 1/20W MF
2
201
R1125 43.2 2
1 1% 1/20W MF 201
A
S YN C_ MA ST ER =M AS TE R
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
CPU CLOCK/MISC/JTAG DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
11 OF 109 SHEET
10 OF 86
1
A
8
7
6
5
4
CRITICAL
CRITICAL
79 28 79 28
D
BI BI
79 28
BI BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28 79 28
BI BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28 79 28
B
BI
79 28
79 28
C
BI
BI BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 27
OUT
79 27
OUT
79 27
OUT
79 27
OUT
79 27
OUT
79 27
OUT
MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61>
AG6 AJ6
AP11
SA_DQ_0
U1000
SA_DQ_1
BGA
SA_DQ_2
AL6
SA_DQ_3
AJ10
SA_DQ_4
AJ8
SA_DQ_5
(3 OF 9) E W G 5 D 3 I R C B 2 Y V I
SA_CK_0 AU36 SA_CK_0* AV36 SA_CKE_0 AY26
SA_CKE_1 BB26
MEM_A_CKE<1>
SA_DQ_6 SA_DQ_7
AR11
SA_DQ_8
AP6
SA_DQ_9
AU6
SA_DQ_10
AV9 AR6
SA_DQ_11 SA_DQ_12
AP8
SA_DQ_13
AT13
SA_DQ_14
AU13
SA_DQ_15
BC7
SA_DQ_16
SA_DQS_0* AL11 SA_DQS_1* AR8
BB7
SA_DQ_17
SA_DQS_2* AV11
SA_DQ_18
SA_DQS_3* AT17 SA_DQS_4* AV45
SA_DQ_20
BA9
SA_DQ_21
BB9
SA_DQ_22
AY13 AV14
SA_DQ_23
AR14
SA_DQ_25
AY17
SA_DQ_26
AR19
SA_DQ_27
BA14
SA_DQ_28
AU14
SA_DQ_29
BB14
SA_DQ_30
BB17 BA45
SA_DQ_31 SA_DQ_32
AR43
SA_DQ_33
AW48
SA_DQ_34
BC48
SA_DQ_35
BC45
SA_DQ_36
AR45 AT48
SA_DQ_37
SA_DQ_24
SA_DQ_38
SA_CS_0* BB40 SA_CS_1* BC41 SA_ODT_0 AY40 SA_ODT_1 BA41
SA_DQ_19
BA7
A L E N N A H C Y R O M E M
MEM_A_CKE<0> MEM_A_CLK_P<1> MEM_A_CLK_N<1>
AL7
BB11
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
SA_CK_1 AT40 SA_CK_1* AU40
AL8
BA13
SA_DQS_5* AY51 SA_DQS_6* AT55 SA_DQS_7* AK55
SA_DQS_0 AJ11 SA_DQS_1 AR10 SA_DQS_2 AY11 SA_DQS_3 AU17 SA_DQS_4 AW45 SA_DQS_5 AV51 SA_DQS_6 AT56 SA_DQS_7 AK54 SA_MA_0 BG35 SA_MA_1 BB34 SA_MA_2 BE35 SA_MA_3 BD35 SA_MA_4 AT34 SA_MA_5 AU34 SA_MA_6 BB32 SA_MA_7 AT32
AY48
SA_DQ_39
BA49
SA_DQ_40
AV49
SA_DQ_41
BB51
SA_DQ_42
AY53
SA_DQ_43
BB49 AU49
SA_DQ_44 SA_DQ_45
BA53
SA_DQ_46
SA_MA_12 BC30 SA_MA_13 AW41
BB55 BA55
SA_DQ_47 SA_DQ_48
SA_MA_14 AY28 SA_MA_15 AU26
AV56 AP50
MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_ODT<0> MEM_A_ODT<1> MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7> MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7> MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>
OUT OUT OUT
27 79 27 79
79 28 79 28
27 79
OUT
27 79
OUT
27 79
OUT
27 79
OUT
27 79
BI
79 28
BI
79 28
BI
79 28
BI
27 79
OUT
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
79 28
BI
BI
28 79
79 28
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI BI
28 79 28 79
79 28 79 28
BI
BI BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
79 28
BI BI
OUT
27 79
79 28
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
SA_DQ_49
79 28
BI
79 28
BI
AP53
SA_DQ_50 SA_DQ_51
79 28
BI
AV54
SA_DQ_52
79 28
BI
AT54
SA_DQ_53
79 28
BI
AP56
SA_DQ_54
79 28
BI
AP52
SA_DQ_55
79 28
AN57
1
OMIT_TABLE
OMIT_TABLE
79 28
2
3
SA_MA_8 AY32 SA_MA_9 AV32 SA_MA_10 BE37 SA_MA_11 BA30
SA_DQ_56
79 28
BI BI
AN53
SA_DQ_57
79 28
BI
AG56
SA_DQ_58
79 28
BI
AG53
SA_DQ_59
79 28
BI
AN55
SA_DQ_60
79 28
BI
AN52
SA_DQ_61
79 28
BI
MEM_A_DQ<62> MEM_A_DQ<63>
AG55 AK56
SA_DQ_62 SA_DQ_63
79 28
BI
79 28
BI
MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>
BD37 BF36
SA_BS_0 SA_BS_1
79 29 79 29
OUT
BA28
SA_BS_2
79 29
OUT
MEM_A_CAS_L MEM_A_RAS_L MEM_A_WE_L
BE39
SA_CAS*
79 29
OUT
BD39
SA_RAS*
79 29
OUT
AT41
SA_WE*
79 29
OUT
OUT
MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10>
AL4
SB_DQ_0
AL1
MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61>
U1000
SB_DQ_1
BGA
AN3
SB_DQ_2
(4 OF 9)
AR4
SB_DQ_3
AK4
SB_DQ_4
AK3
E W G 5 D 3 I R C B 2 Y V I
SB_DQ_5
AN4
SB_DQ_6
AR1
SB_DQ_7
AU4
SB_DQ_8
AT2
SB_DQ_9
AV4
SB_DQ_10
BA4 AU3
SB_DQ_11 SB_DQ_12
AR3
SB_DQ_13
AY2
SB_DQ_14
BA3
SB_DQ_15
BE9
SB_DQ_16
BD9
SB_DQ_17
BD13
SB_DQ_18
BF12
SB_DQ_19
B L E N N A H C Y R O M E M
SB_CK_0 BA34 SB_CK_0* AY34
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
SB_CKE_0 AR22
MEM_B_CKE<0>
SB_CK_1 BA36 SB_CK_1* BB36
MEM_B_CLK_P<1> MEM_B_CLK_N<1>
SB_CKE_1 BF27
MEM_B_CKE<1>
SB_CS_0* BE41 SB_CS_1* BE47 SB_ODT_0 AT43 SB_ODT_1 BG47 SB_DQS_0* AL3 SB_DQS_1* AV3 SB_DQS_2* BG11 SB_DQS_3* BD17 SB_DQS_4* BG51
BF8
SB_DQ_20
BD10
SB_DQ_21
BD14
SB_DQ_22
BE13 BF16
SB_DQ_23
BE17
SB_DQ_25
BE18
SB_DQ_26
BE21
SB_DQ_27
BE14
SB_DQ_28
BG14
SB_DQ_29
BG18
SB_DQ_30
BF19
SB_DQS_7 AK61
BD50
SB_DQ_31 SB_DQ_32
BF48
SB_DQ_33
BD53
SB_DQ_34
SB_MA_0 BF32 SB_MA_1 BE33
BF52
SB_DQ_35
BD49
SB_DQ_36
BE49 BD54
SB_DQ_37
SB_DQ_24
SB_DQS_5* BA59 SB_DQS_6* AT60 SB_DQS_7* AK59
SB_DQS_0 AM2 SB_DQS_1 AV1 SB_DQS_2 BE11 SB_DQS_3 BD18 SB_DQS_4 BE51 SB_DQS_5 BA61 SB_DQS_6 AR59
SB_MA_2 BD33 SB_MA_3 AU30 SB_MA_4 BD30 SB_MA_5 AV30
SB_DQ_38
BE53
SB_DQ_39
BF56
SB_DQ_40
BE57
SB_DQ_41
BC59
SB_DQ_42
AY60
SB_DQ_43
BE54 BG54
SB_DQ_44 SB_DQ_45
BA58
SB_DQ_46
SB_MA_12 AV28 SB_MA_13 BD46
AW59 AW58
SB_DQ_47 SB_DQ_48
SB_MA_14 AT26 SB_MA_15 AU22
AU58
SB_DQ_49
AN61 AN59
SB_DQ_50 SB_DQ_51
AU59
SB_DQ_52
AU61
SB_DQ_53
AN58
SB_DQ_54
AR58
SB_DQ_55
AK58
SB_DQ_56
AL58
SB_DQ_57
AG58
SB_DQ_58
AG59
SB_DQ_59
AM60
SB_DQ_60
AL59
SB_DQ_61
MEM_B_DQ<62> MEM_B_DQ<63>
AF61 AH60
SB_DQ_62 SB_DQ_63
MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>
BG39
SB_BS_0 SB_BS_1
MEM_B_CAS_L MEM_B_RAS_L MEM_B_WE_L
AV43
BD42 AT22
SB_MA_6 BG30 SB_MA_7 BD29 SB_MA_8 BE30 SB_MA_9 BE28 SB_MA_10 BD43 SB_MA_11 AT28
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
MEM_B_CS_L<0> MEM_B_CS_L<1>
OUT
29 79
OUT
29 79
MEM_B_ODT<0> MEM_B_ODT<1>
OUT
29 79
OUT
29 79
MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7> MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7> MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI BI
D
28 79
C
28 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
B
SB_BS_2 SB_CAS*
BF40
SB_RAS*
BD45
SB_WE*
A
S YN C_ MA ST ER =M AS TE R
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
CPU DDR3 INTERFACES DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
12 OF 109 SHEET
11 OF 86
1
A
8
7
6
5
4
2
3
15 12 9 7
=PPVCORE_S0_CPU_VCCAXG
1
OMIT_TABLE
CRITICAL 14 12 9 7
=PPVCORE_S0_CPU
OMIT_TABLE
D
VAXG_1
AB47
VAXG_2
BGA
AB50
VAXG_3
(7 OF 9) E W G 5 D 3 I R C B 2 Y V I
U1000
VCCIO_1
AF46
BGA
VCCIO_3
AG48
AB51
VAXG_4
A31 VCC_3 A34 VCC_4
(6 OF 9)
VCCIO_4
AG50
AB52
VAXG_5
VCCIO_5
AG51
AB53
VAXG_6
VCCIO_6
AJ17
AB55
VAXG_7
VCCIO_7
AJ21
AB56
VAXG_8
VCCIO_8
AJ25
AB58
VAXG_9
VCCIO_9
AJ43
AB59
VAXG_10
VCCIO_10
AJ47
AC61
VCCIO_11
AK50
AD47
C32 VCC_11 C34 VCC_12
VCCIO_12
AK51
AD48
VCCIO_13
AL14
AD50
VAXG_14
C37 VCC_13 C39 VCC_14
VCCIO_14
AL15
AD51
VAXG_15
VCCIO_15
AL16
AD52
VAXG_16
C42 VCC_15 D27 VCC_16
VCCIO_16
AL20
AD53
VAXG_17
VCCIO_17
AL22
AD55
VAXG_18
D32 VCC_17 D34 VCC_18
VCCIO_18
AL26
AD56
VAXG_19
VCCIO_19
AL45
AD58
VAXG_20
D37 VCC_19 D39 VCC_20
VCCIO_20
AL48
AD59
VAXG_21
VCCIO_21
AM16
AE46
VAXG_22
D42 VCC_21 E26 VCC_22
VCCIO_22
AM17
VCCIO_23
AM21
E28 VCC_23 E32 VCC_24
VCCIO_24
AM43
VCCIO_25
AM47
E34 VCC_25 E37 VCC_26
VCCIO_26
AN20
VCCIO_27
AN42
A39 VCC_7 A42 VCC_8 C26 VCC_9 C27 VCC_10
E G D I R B Y V I
E38 VCC_27 F25 VCC_28
H25 VCC_37 H26 VCC_38 H28 VCC_39 H29 VCC_40 H32 VCC_41 H34 VCC_42
VCCIO_28 VCCIO_29
AA15
G E P
VCCIO_32
AB17
VCCIO_33
AB20
VCCIO_34
AC13
VCCIO_35
AD16
VCCIO_36
AD18
Y L L P U S
VCCIO_37
AD21
VCCIO_38
AE14
VCCIO_39
AE15
E R O C
VCCIO_40
AF16
VCCIO_41
AF18
VCCIO_42 VCCIO_43
AF20
VCCIO_44
AG16
VCCIO_45 VCCIO_46
AG17
VCCIO_47
AG21
VCCIO_48 VCCIO_49
AJ14
J28 VCC_49 J29 VCC_50
VCCIO_50
J32 VCC_51 J34 VCC_52
VCCIO_51
J35 VCC_53 J37 VCC_54
VCCIO_SEL
J38 VCC_55 J40 VCC_56 J42 VCC_57 K26 VCC_58 K27 VCC_59 K29 VCC_60 K32 VCC_61 K34 VCC_62 K35 VCC_63 K37 VCC_64 K39 VCC_66 K42 VCC_67
T E L I I U A Q R
D I V S
E S S E N N E I S L
AJ33
VDDQ_3
AJ36
VDDQ_4
AJ40
VDDQ_5
AL30
VDDQ_6
AL34
VDDQ_7
AL38
VDDQ_8
AL42
VAXG_11
VDDQ_9
AM33
VAXG_12
VDDQ_10
AM36
VAXG_13
VDDQ_11
AM40
VDDQ_12
AN30
VDDQ_13
AN34
VDDQ_14
AN38
VDDQ_15
AR26
VDDQ_16
AR28
VDDQ_17
AR30
VDDQ_18
AR32
VDDQ_19
AR34
VDDQ_20
AR36
VDDQ_21
AR40
N45 VAXG_23 P47 VAXG_24
VDDQ_22
AV41
VDDQ_23
AW26
VDDQ_24
BA40
P51 VAXG_27 P52 VAXG_28
VDDQ_25
BB28
VDDQ_26
BG33
VCCDQ_1
AM28
VCCDQ_2
AN26
VDDQ_SENSE
BC43
A44
VIDSCLK
B43
=PP1V05_S0_CPU_VCCIO
15 12 9 7
7 9 10 12 14
R1302 130 PLACE_NEAR=U1000.C44:2.54mm
CPU_VCCIO_SEL
1% 1/16W MF-LF
R1310 201 1/20 W
1
1
R1380 PLACE_NEAR=U1000.BC43:50.8mm PLACE_SIDE=BOTTOM
=PP1V5_S3_CPU_VCCDQ
CPU_VDDQ_SENSE_P Note. CPU_VDDQ_SENSE_N
BA43
201 1/20 W
0 1
=PP1V05_S0_CPU_VCCPQE 14 7 8
CPU_VIDSOUT_R
VSS_SENSE
G43
W56 VAXG_53 W61 VAXG_54 Y48 VAXG_55 Y61 VAXG_56
R1370
PLACE_NEAR=U1000.F45:50.8mm PLACE_SIDE=BOTTOM
CPU_VIDALERT_L
2 5%
CPU_VIDSCLK
MF
IN
68 78
OUT
68 78
78 68
OUT
78 68
OUT
R1312 201 1/20 W
0 1
CPU_AXG_SENSE_P CPU_AXG_SENSE_N 14 7
2 5%
CPU_VIDSOUT
MF
BI
Note. VOLTAGE=1.05V Note. VOLTAGE=0V
=PP1V8_S0_CPU_VCCPLL_R
68 78
NOSTUFF
=PPVCORE_S0_CPU 7 =PP1V05_S0_CPU_VCCIO 7
CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N
NOSTUFF
R13601
L25 VCC_68 L28 VCC_69
PLACE_NEAR=U1000.F43:50.8mm PLACE_SIDE=BOTTOM
L33 VCC_70 L36 VCC_71
2
9 12 14
Note. VOLTAGE=0V
CPU_VCCSASENSE
VCCSA_VID_0
D48
VCCSA_VID_1
D49
CPU_VCCSA_VID<0> 65 CPU_VCCSA_VID<1> OUT
AY43
CPU_SM_VREF VOLTAGE=0.75V
2
Note. VOLTAGE=1.25V
N30 VCC_74 N34 VCC_75
Note. VOLTAGE=0V Note. VOLTAGE=1.05V
N38 VCC_76
Note. VOLTAGE=0V
OUT
68 78
OUT
68 78
OUT
70 78
OUT
70 78
65
65
12
1
1
1
R1313
2
10K
10K 5% 1/20W MF 201
100 1% 1/16W MF-LF 402
2
2
5% 1/20W MF 201
PLACEMENT NOTE:
1% 1/16W MF-LF 402
F45 VAXG_SENSE E E S N G45 VSSAXG_SENSE N I
26 15 12 10 7
Please place all sense line resistors on BOTTOM side.
BB3 VCCPLL_1 BC1 VCCPLL_2 BC4 VCCPLL_3
B
=PP1V5_S3_CPU_VCCDDR 1
R1330
E L S
PLACE_NEAR=U1000.BJ44:2.54mm
1K
5% 1/16W
V I L 8 . A 1 R
2
Please place all sense line resistors on BOTTOM side.
L17 VCCSA_1 L21 VCCSA_2
MF-LF 402 2
CPU_SM_VREF
N22 VCCSA_5 P17 VCCSA_6 P20 VCCSA_7 R16 VCCSA_8 R18
VCCSA_9
12
1
R1331
1
PLACE_NEAR=U1000.BJ44:2.54mm 1K PLACE_NEAR=U1000.BJ44:2.54mm 1K
5% 1/16W MF-LF 402
N16 VCCSA_3 N20 VCCSA_4 L I A R A S
C1330 0.1UF
2 2
10% 16V X7R-CERM 0402
PLACE_NEAR=U1000.BJ44:2.54mm
R21 VCCSA_10 U15 VCCSA_11 V16 VCCSA_12 V17 VCCSA_13 V18 VCCSA_14 V21 VCCSA_15
NOSTUFF 1
R1361
A
100
PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=BOTTOM
PLACEMENT NOTE:
L40 VCC_72 N26 VCC_73
PLACE_NEAR=U1000.G45:50.8mm PLACE_SIDE=BOTTOM
R1362 1% 1/16W MF-LF 402
15 12 7
R1371
9 10 12 14
NOSTUFF
100
OUT
=PPVCCSA_S0_CPU
1
1
100 1% 1/16W MF-LF 402
C
7 15
VOLTAGE=1.05V
U10
R1314
PLACE_NEAR=U1000.A44:38mm
R1311 CPU_VIDALERT_L_R CPU_VIDSCLK_R
CPU_VCCSENSE_P CPU_VCCSENSE_N
100 1% 1/16W MF-LF 402 2
1
75
MF
2
100 1% 1/16W MF-LF 402 2
VAXG_51 W55 VAXG_52
NOSTUFF
R1300
2 201
2 5%
100 1% 1/16W MF-LF 402
W52 VAXG_50 W53
1% 1/20W MF
43
2 402
8 78
F43
AN17
1
R1382 PLACE_NEAR=U1000.U10:50.8mm
PLACE_NEAR=U1000.BA43:50.8mm PLACE_SIDE=BOTTOM
W50 VAXG_48 W51 VAXG_49
=PPVCORE_S0_CPU_VCCAXG
PLACE_NEAR=R1310.2:2.54mm 1
1
C44
VSS_SENSE_VCCIO
26 15 12 10
=PPVCCSA_S0_CPU
R1381
V58 VAXG_46 V59 VAXG_47
VIDSOUT
AN16
15 12 7
=PP1V5_S3_CPU_VCCDDR 7
VCCSA_SENSE
SM_VREF
V55 VAXG_44 V56 VAXG_45
VCC_SENSE
VCCIO_SENSE
D
V52 VAXG_42 V53 VAXG_43
IVB supports 1.05V VCCIO. VCCIO_SEL can be NC.
AN22
(IPU)
V50 VAXG_40 V51 VAXG_41
W17
AM25
VSS_SENSE_VDDQ
E E S N N I E S L
V47 VAXG_38 V48 VAXG_39
W16
VCCPQE_2
T E L I I A U R Q
T61 VAXG_36 U46 VAXG_37
AJ15
VCCPQE_1
VAXG_29
T58 VAXG_34 T59 VAXG_35
AG20
VIDALERT*
(IPU)
P61 VAXG_32 T48 VAXG_33
AG15
BC22
S L I A S R C I V H 5 P . R 1 G 3 R D D
P48 VAXG_25 P50 VAXG_26
P55 VAXG_30 P56 VAXG_31
AA14
J25 VCC_47 J26 VCC_48
VDDQ_2
AN48
VCCIO_31
H38 VCC_45 H40 VCC_46
AJ28
P53
VCCIO_30
H35 VCC_43 H37 VCC_44
VDDQ_1
AN45
D N A
F32 VCC_31 F34 VCC_32 F37 VCC_33 F38 VCC_34 F42 VCC_35 G42 VCC_36
W 5 3 C 2
R D D
F26 VCC_29 F28 VCC_30
B
(NOT controlled by VCCIO_SEL) Fixed at 1.05V
U1000
AA46
A26 VCC_1 A29 VCC_2
A35 VCC_5 A38 VCC_6
C
=PP1V5_S3_CPU_VCCDDR
=PP1V05_S0_CPU_VCCIO
CRITICAL
PLACE_NEAR=U1000.G43:50.8mm PLACE_SIDE=BOTTOM
1
W20 VCCSA_16
R1363
100 1% 1/16W MF-LF 402 2
NOSTUFF
100
2
1% 1/16W MF-LF 402
PLACE_NEAR=U1000.AN17:50.8mm PLACE_SIDE=BOTTOM
S YN C_ MA ST ER =M AS TE R
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
CPU POWER DRAWING NUMBER
PLACEMENT NOTE:
Apple Inc.
Please place all sense line resistors on BOTTOM side. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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REVISION
SIZE
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13 OF 109 SHEET
12 OF 86
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1
OMIT_TABLE
CRITICAL OMIT_TABLE
CRITICAL BG13
VSS
BG17
VSS
BG21 BG24
D
VSS VSS
BG28
VSS
BG37
VSS
BG41
VSS
BG45
VSS
BG49
VSS
BG53
VSS C29 VSS
VSS
M15
VSS
VSS
M58
E W G 5 3 D I R C 2 B Y V I
VSS
N1
VSS
N17
VSS
N21
VSS
N25
VSS
N28
VSS
N33
VSS
N36
VSS
N40
A53 VSS AA1 VSS
VSS AN36
VSS VSS
N43 N47
AA8 VSS
VSS AN43
VSS
N48
D6
VSS
VSS
N51
D10 VSS D14 VSS
VSS
N52
VSS
N56
D18 VSS D22 VSS
VSS
N61
VSS
P9
D26 VSS D29 VSS
VSS
P14
VSS
P16
D35 VSS D40 VSS
VSS
P18
VSS
P21
D43 VSS D46 VSS
VSS
P58
VSS
P59
D50 VSS D54 VSS
VSS
R4
VSS
R17
D58 VSS
VSS
R20
VSS
VSS
R46
E25 VSS E29 VSS
VSS
T1
VSS
T47
E35 VSS E40 VSS
VSS
T50
VSS
T51
F13 VSS F15 VSS
VSS
T52
VSS
T53
F19 VSS F29 VSS
VSS VSS
T56
F35 VSS F40 VSS
VSS
U8
VSS
U13
F55 VSS
VSS
G6 VSS G48 VSS G51 VSS
VSS
V61
VSS
W8
VSS
W13
G61 VSS
VSS
W15
VSS
VSS
W18
H10 VSS H14 VSS
VSS
W21
VSS
W46
H17 VSS H21 VSS
VSS
Y4
VSS
Y47
H53 VSS H58 VSS
VSS
Y58
VSS
Y59
J1
A21 VSS A25 VSS A28 VSS A33 VSS A37 VSS A40 VSS A45 VSS A49 VSS
VSS_NCTF BD3
L26 VSS L30 VSS L34 VSS L38 VSS
VSS_NCTF BE4
L43 VSS L48 VSS
VSS_NCTF C3
BD59
BE58
VSS_NCTF BG57 VSS_NCTF C58 VSS_NCTF D59
M4
VSS
VSS_NCTF E1
M6
VSS
VSS_NCTF E61
VSS AN33 VSS AN40
VSS AN50
VSS
VSS AN54 VSS AP7
AA53
VSS
VSS AP10
AA55
VSS
VSS AP51
AA56
VSS
AB16
VSS
VSS AP55 VSS AR7
AB18
VSS
VSS AR13
AB21
VSS
VSS AR17
AB48
VSS
VSS AR21
AB61
VSS
VSS AR41
AC6 VSS
VSS AR48
AC10
VSS
AC14
VSS
VSS AR61 VSS AT4
AC46
VSS
VSS AT14
AD4 VSS
VSS AT19 AT36
VSS
VSS
AD20
VSS
VSS AT45
AD61
VSS
VSS AT52
AE8 VSS
VSS AT58 VSS AU1 VSS
C
AU7
VSS
VSS AU11
AF47
VSS VSS
VSS VSS AU32
AF48
VSS
VSS AU51
AF50
VSS
VSS AV17
AF51
VSS
VSS AV21
AF52
VSS
VSS AV22
AF53
VSS
VSS AV34
AF55
VSS
VSS AV40
AF56
VSS
VSS AV48
AF58
VSS
AF59
VSS
VSS AV55 VSS AW7
AG7 VSS
VSS AW13
AU28
AG10
VSS
VSS AW43
AG14
VSS
AG18
VSS
VSS AW61 VSS AY4
AG47
VSS
VSS
AG52
VSS
VSS AY14
VSS AH4 VSS
VSS AY19
AY9
VSS AY30 VSS AY36 VSS AY41
AJ13
VSS
VSS AY45
AJ16
VSS
VSS AY49
AJ20
VSS
VSS AY55
AJ22
VSS
AJ26
VSS
VSS AY58 VSS BA1
AJ30
VSS
VSS BA11
AJ34
VSS
VSS BA17
AJ38
VSS
VSS BA21
AJ42
VSS
VSS BA26
AJ45
VSS
VSS BA32
VSS AK1 VSS
VSS BA48
AJ48
A
AN28
AA52
VSS AJ7 VSS
VSS_NCTF VSS_NCTF BG5
L61 VSS
VSS
VSS AN47
AH58
VSS_NCTF BC61 VSS_NCTF
VSS AN25
VSS
VSS
D
VSS AN21
AA51
AF1 VSS
VSS_NCTF A5 VSS_NCTF A57
VSS AM58 VSS AN1
VSS
AG61
L20 VSS L22 VSS
VSS AM48
AF21
V20
K51 VSS L16 VSS
VSS AM45
E W G 5 3 D I R C 2 B Y V I
VSS
AF17
VSS
K8 VSS K11 VSS K21 VSS
VSS AM42
VSS
AA50
AE13
T55
(8 OF 9)
AA13
AD17
J49 VSS J55 VSS
B
VSS AM38
VSS
BGA
VSS
H4
VSS AM34
BGA
U1000 (9 OF 9)
D4
E3
A13 VSS A17 VSS
U1000
M11
C35 VSS C40 VSS
C
A9 VSS
B
VSS BA51
AK52
VSS
AL10
VSS
VSS BB53 VSS BC5
AL13
VSS
VSS BC13
AL17
VSS
AL21
VSS
VSS BC57 VSS BD8
AL25
VSS
VSS BD12
AL28
VSS
VSS BD16
AL33
VSS
VSS BD19
AL36
VSS
VSS BD23
AL40
VSS
VSS BD27
AL43
VSS
VSS BD32
AL47
VSS
VSS BD36
AL61
VSS
VSS BD40
AM4 VSS
VSS BD44
AM13
VSS
VSS BD48
SYNC_MASTER=MASTER
AM20
VSS
VSS BD52
PAGE TITLE
AM22
VSS
AM26
VSS
VSS BD56 VSS BE5
VSS
VSS
AM30
SYNC_DATE=02/15/2011
CPU GROUNDS DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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BG9
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REVISION
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All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide
CPU VCORE DECOUPLING Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF
12 9 7
CRITICAL CRITICAL
=PPVCORE_S0_CPU
C1600
1
2.2UF
20% 4V 2 X5R 402
20% 4V 2 X5R 402
D
C1604
1
2.2UF
CRITICAL
2.2UF
20% 4V 2 X5R 402
CRITICAL CRITICAL
C1625
1
2.2UF
C1628
1
CRITICAL
CRITICAL 1
C1607
1
2.2UF
1
2.2UF
C1609
1
CRITICAL 1
2.2UF
1
1
1
2.2UF
1
2.2UF
1
20% 4V 2 X5R 402
CRITICAL
C1638
1
1
C1639
1
C1640 2.2UF
C1617 2.2UF
20% 4V 2 X5R 402
CRITICAL
2.2UF
2.2UF
C1615 2.2UF
20% 4V 2 X5R 402
20% 4V 2 X5R 402
C1637
C1613 2.2UF
CRITICAL CRITICAL
C1635
CRITICAL CRITICAL
CRITICAL
C1612 2.2UF
20% 4V 2 X5R 402
20% 4V 2 X5R 402
C1632
C1610 2.2UF
2.2UF
CRITICAL
C1631
CRITICAL CRITICAL
CRITICAL 1
20% 4V 2 X5R 402
CRITICAL 1
C1608 2.2UF
2.2UF
20% 4V 2 X5R 402
CRITICAL
C1627
1
2.2UF
C1606
1
1
C1641 2.2UF
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
402
402
402
402
402
402
402
402
402
402
402
C1650
1
C1651
1
2.2UF
CRITICAL
CRITICAL
1
1
1
C1624 2.2UF
20% 4V 2 X5R 402
C1642 2.2UF
D
1
CRITICAL
CRITICAL
CRITICAL
C1643 2.2UF
1
C1644
1
C1645 2.2UF
2.2UF
CRITICAL 1
C1647 2.2UF
CRITICAL 1
C1648 2.2UF
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
20% 4V 2 X5R
402
402
402
402
402
402
CRITICAL CRITICAL
2.2UF
2.2UF
20% 4V 2 X5R 402
20% 4V 2 X5R 402
20% 4V 2 X5R 402
20% 4V 2 X5R 402
2.2UF
20% 4V 2 X5R 402
C1652 1 C1653 1 C1654 2.2UF
2.2UF
20% 4V 2 X5R 402
C1623
CRITICAL CRITICAL
20% 4V 2 X5R
CRITICAL
CRITICAL CRITICAL 1
PLACEMENT_NOTE (C1655-C1666): Place close to U1000 on top side. OMIT
C1655
1
OMIT
C1656
1
1
OMIT
C1658
NOSTUFF
C1659
1
1
OMIT
C1661
1
NOSTUFF
C1662
1
NOSTUFF
C1663
1
NOSTUFF
C1665
1
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
OMIT
C1666
138S0691
22UF
22UF
16
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
CRITICAL
C1655,C1660,C1661,C1664,C1666,C1667,C1670,C1677,C1678,C1679,C1657,C1672,C1658,C1669,C1668,C1656
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
PART NUMBER
CRITICAL
CRITICAL
OMIT
C1664 22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
CRITICAL 1
22UF
22UF
22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
CRITICAL
CRITICAL
CRITICAL
OMIT
C1660 22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
CRITICAL 1
22UF
22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
CRITICAL
CRITICAL
OMIT
C1657 22UF
22UF
22UF
20% 6.3V 2 X5R-CERM-1 603
C
CRITICAL
CRITICAL
CRITICAL 1
C
PLACEMENT_NOTE (C1667-C1679): Place close to U1000 on bottom side.
1
CRITICAL
CRITICAL
CRITICAL
CRITICAL
OMIT
OMIT
OMIT
OMIT
C1667
1
C1668
1
C1669
1
22UF
22UF
22UF
C1670
NOSTUFF
C1671
1
OMIT
C1672
1
NOSTUFF
C1673
1
22UF
22UF
CRITICAL
NOSTUFF
C1674
1
C1675
CRITICAL 1
NOSTUFF
C1676
1
22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
NOSTUFF
22UF
22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
CRITICAL
CRITICAL
CRITICAL 1
22UF
22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
CRITICAL
CRITICAL
CRITICAL
CRITICAL
OMIT
OMIT
OMIT
C1677
1
C1678
1
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
C1679 22UF
22UF
22UF
20% 6.3V 2 X5R-CERM-1 603
PLACEMENT_NOTE (C1640-C1645): Place near inductors on bottom side.
1
1
C1680 470UF-4MOHM
3
2
20% 2.0V POLY-TANT D2T-SM1
1
C1681
2
1
C1682
C1683
470UF-4MOHM
470UF-4MOHM 3
20% 2.0V POLY-TANT D2T-SM1
3
2
470UF-4MOHM
20% 2.0V POLY-TANT D2T-SM1
3
2
20% 2.0V POLY-TANT D2T-SM1
CPU VCCIO/VCCPQ DECOUPLING CPU VCCPLL DECOUPLING
Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF
Intel recommendation (section 6.4): 2x 1uF, 1x 330uF
PLACEMENT_NOTE (C1684-C167F): 12 10 9 7
=PP1V05_S0_CPU_VCCIO
B
PLACEMENT_NOTE (C1646-C1671):
U100. Place on bottom side of U1000
Place near U1000 on top side 1
C1684
1
1UF 2
C1685
C1686
1
1UF
10% 10V X5R 402
2
1
C1687 1UF
1UF
10% 10V X5R 402
10% 10V X5R 402
2
1
1
1UF
10% 10V X5R 402
2
C1688
2
C1689
1
2
1
10% 10V X5R 402
2
C1691
1
10% 10V X5R 402
2
C1692
1
1UF
1UF
1UF
1UF
10% 10V X5R 402
C1690
10% 10V X5R 402
2
C1693
1
1UF
10% 10V X5R 402
2
C1694
1
2
1
10% 10V X5R 402
2
10% 10V X5R 402
2
R1600
C1696 1UF
1UF
1UF
10% 10V X5R 402
C1695
7 =PP1V8_S0_CPU_VCCPLL
10% 10V X5R 402
1
0
=PP1V8_S0_CPU_VCCPLL_R
B
7 12
2
5% 1/16W MF-LF
PLACE_NEAR=U1000.BC1:5mm
1
402
PLACE_NEAR=U 1000.AK63:2. 54 mm:NO_VIA
C160X
1
1UF
2
10% 10V X5R 402
C160Y
C160Z
330UF-0.006OHM
1UF
2
1
20%
10% 10V X5R 402
2V 2 POLY CASE-D2-SM
PLACE_NEAR= U1000.AK65:2 .54 mm:NO_VIA
1
C1697
1
1UF 2
C1698
C1699
1
1UF
10% 10V X5R 402
2
1
10% 10V X5R 402
2
C169A
1
1UF
1UF
10% 10V X5R 402
2
C169B
1
2
C169C
1
10% 10V X5R 402
2
C169D
1
10% 10V X5R 402
2
C169E
1
10% 10V X5R 402
2
C169F
1
10% 10V X5R 402
2
C161A
1
10% 10V X5R 402
2
10% 10V X5R 402
C161B
1
2
10% 10V X5R 402
C161C
1
2
10% 10V X5R 402
C161D
CPU VCCPLL Low pass filter
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10% 10V X5R 402
2
10% 10V X5R 402
PLACEMENT_NOTE (C1672-C1681): Place near U1000 on bottom side 1
C161E
1
1
1
C161F 10UF
10UF 2
20% 6.3V X5R 603
2
C167D 330UF
1
1
C162A
2
C167E 330UF
1
20% 6.3V CERM-X5R 0402-1
C167G 330UF
C162B
1
C162C
2
1
20% 6.3V CERM-X5R 0402-1
C167H
330UF
1
1
2
20% 6.3V CERM-X5R 0402-1
C162D
1
10UF
10UF
10UF
10UF
20% 6.3V CERM-X5R 0402-1
2
20% 6.3V CERM-X5R 0402-1
C162E
1
20% 6.3V CERM-X5R 0402-1
1
C167A 10UF
10UF 2
2
C167B
1
2
20% 6.3V CERM-X5R 0402-1
C167C 10UF
10UF
20% 6.3V CERM-X5R 0402-1
2
20% 6.3V CERM-X5R 0402-1
C167J 330UF
20% 20% 20% 20% 20% 2 2.5V 2 2.5V 2 2.5V 2 2.5V 2 2.5V TANT TANT TANT TANT TANT CASE-B2-SM1 CASE-B2-SM1 CASE-B2-SM1 CASE-B2-SM1 CASE-B2-SM1
A
SYNC_MASTER=JACK_J30
SYNC_DATE=09/27/2011
PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
DRAWING NUMBER
SIZE
R1601
Apple Inc.
0.010 1
2
=PP1V05_S0_CPU_VCCPQE
7 8 12 R
1% 1/4W MF 0603
1
NOTICE OF PROPRIETARY PROPERTY:
1UF 2
8
C167F
7
10% 10V X5R 402
Note:The smallest 10mOhm available in the library are 0805s
6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
5
4
3
2
051-9058 6.0.0
REVISION
D
BRANCH
PAGE
16 OF 109 SHEET
14 OF 86
1
A
8
7
6
5
4
2
3
1
VAXG DECOUPLING Intel recommendation (section 6.3): 21x 1uF, 6x 10uF, 6x 22uF, 2x 470uF
12 9 7
PLACEMENT_NOTE (C1700-C1710):
=PPVCORE_S0_CPU_VCCAXG
Place on bottom side of U1000 U100.
CRITICAL
D
CRITICAL
C1700
1
2
C1701
1
CRITICAL
C1703
1
1
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1702
1
C1704
1
C1705
1
CRITICAL
C1706
1
CRITICAL
CRITICAL
C1707
1
C1708
1
C1709
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
10% 10V X5R 402
2
2
2
2
2
2
2
2
2
CRITICAL 1
C1710 1UF
2
10% 10V X5R 402
D
PLACEMENT_NOTE (C1711-C1716):
CRITICAL
CRITICAL 1
1
C1711
2
CRITICAL
CRITICAL 1
C1712
1
C1713
CRITICAL 1
C1714
C1715
10UF
10UF
10UF
10UF
10UF
20% 6.3V CERM-X5R 0402-1
20% 6.3V CERM-X5R 0402-1
20% 6.3V CERM-X5R 0402-1
20% 6.3V CERM-X5R 0402-1
20% 6.3V CERM-X5R 0402-1
2
2
2
2
CRITICAL 1
C1716 10UF
2
20% 6.3V CERM-X5R 0402-1
PLACEMENT_NOTE (C1717-C1722):
CRITICAL
CRITICAL
OMIT
C1717
1
1
22UF
1
22UF
20% 6.3V 2 X5R-CERM-1 603
CRITICAL
CRITICAL
OMIT
C1718
OMIT
C1719
1
20% 6.3V 2 X5R-CERM-1 603
OMIT
C1720
CRITICAL
OMIT
C1721
1
22UF
20% 6.3V 2 X5R-CERM-1 603
20% 6.3V 2 X5R-CERM-1 603
CRITICAL 1
22UF
22UF
OMIT
PART NUMBER
C1722 22UF
20% 6.3V 2 X5R-CERM-1 603
QTY 6
138S0691
20% 6.3V 2 X5R-CERM-1 603
DESCRIPTION
REFERENCE DES
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
C1717,C1718,C1719,C1720,C1721,C1722
CRITICAL
BOM OPTION
CRITICAL
PLACEMENT_NOTE (C1723-C1724): Place near inductors on bottom side.
1
1
C1723 470UF-4MOHM
C
3
20% 2.0V POLY-TANT D2T-SM1
2
C1724
C
470UF-4MOHM 3
2
20% 2.0V POLY-TANT D2T-SM1
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation (Section 6.5): 10x 1uF, 8x 10uF, 1x 330uF PLACEMENT_NOTE (C1738-C1747):
26 12 10 7
=PP1V5_S3_CPU_VCCDDR
CPU VCCSA DECOUPLING
Place on bottom side of U1000 U100.
1
C1738
1
2
C1739
C1740
1
10% 10V X5R 402
2
1
1UF
1UF
1UF
10% 10V X5R 402
1
2
10% 10V X5R 402
C1742
1
2
10% 10V X5R 402
C1743
1
2
10% 10V X5R 402
C1744
1
2
C1745
1
1UF
1UF
1UF
1UF
1UF
10% 10V X5R 402
2
C1741
10% 10V X5R 402
2
10% 10V X5R 402
C1746
1
2
10% 10V X5R 402
C1747
Intel recommendation (Section 6.6): 6x 1uf, 5x 10uf, 1x 330uf
1UF
1UF 2
PLACEMENT_NOTE (C1758-C1762):
10% 10V X5R 402
12 7
=PPVCCSA_S0_CPU
U1000 Place on bottom side of U100.
Place close to U1000 on bottom side 1
1
1
C1748 10UF
B
2
1
C1749
2
C1750
20% 6.3V CERM-X5R 0402-1
2
C1751
1
20% 6.3V X5R 603
2
20% 6.3V CERM-X5R 0402-1
C1752
1
2
20% 6.3V CERM-X5R 0402-1
C1753
1
2
20% 6.3V CERM-X5R 0402-1
C1754
1
2
20% 6.3V X5R 603
C1755
2
C1758
20% 6.3V CERM-X5R 0402-1
2
1
10% 10V X5R 402
1
C1756 330UF-0.006OHM 2
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
1
R1702 2
1 20% 6.3V CERM-X5R 0402-1
1
2
10% 10V X5R 402
1
20% 6.3V CERM-X5R 0402-1
2
10% 10V X5R 402
1
2
2
10% 10V X5R 402
B
1
C1766 10UF
20% 6.3V CERM-X5R 0402-1
C1762 1UF
1
C1765 10UF 2
C1761 1UF
1
C1764 10UF 2
C1760 1UF
10% 10V X5R 402
C1767 10UF
20% 6.3V CERM-X5R 0402-1
2
20% 6.3V CERM-X5R 0402-1
C1768
330UF-0.006OHM
20% 2 2V POLY CASE-D2-SM
0.010 1% 1/4W MF 0603
C1759 1UF
2
C1763 10UF
20% 2 2V POLY CASE-D2-SM
1
1
1UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20% 6.3V CERM-X5R 0402-1
1
=PP1V5_S3_CPU_VCCDQ
1
7 12
C1757 1UF
2
10% 10V X5R 402
A
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU DECOUPLING-II DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
17 OF 109 SHEET
15 OF 86
1
A
8
7
6
5
4
2
3
OMIT_TABLE 81 24
SYSCLK_CLK32K_RTC
IN
NC
OMIT_TABLE
A20
RTCX1
U1800
FWH0/LAD0
C38
LPC_AD_R<0>
C20
RTCX2
PANTHERPOINT
FWH1/LAD1
A38
LPC_AD_R<1>
16
FWH2/LAD2
B37
LPC_AD_R<2>
16
FWH3/LAD3 (IPU)
C37
LPC_AD_R<3>
16
FWH4/LFRAME*
D36
LPC_FRAME_R_L
16
C C (IPU) LDRQ0* LDRQ1*/GPIO23 T P(IPU) R L
E36
TP_LPC_DREQ0_L
K36
TBT_PWR_EN_PCH
V5
LPC_SERIRQ
MOBILE FCBGA
(1 OF 10) 16
D
D20
RTC_RESET_L
RTCRST*
16
PCH_SRTCRST_L
G22
16
PCH_INTRUDER_L
K22
INTRUDER*
16
PCH_INTVRMEN_L
C17
INTVRMEN
81 16
81 16
SRTCRST*
HDA_BIT_CLK_R
N34
HDA_BCLK
HDA_SYNC_R
SERIRQ
L34
HDA_SYNC (IPD-BOOT)
PCH_SPKR
T10
SPKR (IPD-PLTRST#)
HDA_RST_R_L
K34
HDA_RST*
VSel strap not functional (VCCVRM = 1.8V) 16
81 16
81 57
IN
PCIE_ENET_D2R_N
BG34
PERN1
U1800
81 36
IN
PCIE_ENET_D2R_P
BJ34
PERP1
PANTHERPOINT
OUT
PCIE_ENET_R2D_C_N
AV32
PETN1
81 36
OUT
PCIE_ENET_R2D_C_P
AU32
PETP1
81 32
IN
PCIE_AP_D2R_N
BE34
PERN2
81 32
IN
PCIE_AP_D2R_P
BF34
PERP2
81 32
OUT
PCIE_AP_R2D_C_N
BB32
PETN2
81 32
OUT
PCIE_AP_R2D_C_P
AY32
PETP2
81 38
IN
PCIE_FW_D2R_N
BG36
PERN3
81 38
IN
BJ36
PERP3
AV34
PETN3
OUT
R1820 10K
24
2
5% 1/20W MF 201
6 45 47
BI
IN
41 80
81 38
OUT
PCIE_FW_D2R_P PCIE_FW_R2D_C_N
IN
41 80
81 38
OUT
41 80
SATA0RXN
AM3
SATA_HDD_D2R_N
SATA0RXP
AM1
SATA_HDD_D2R_P
SATA0TXN
AP7
SATA_HDD_R2D_C_N
SATA0TXP
AP5
SATA_HDD_R2D_C_P
OUT
41 80
SATA1RXN
AM10
SATA_ODD_D2R_N
IN
41 80
8
SATA1RXP
AM8
SATA_ODD_D2R_P
IN
41 80
8
OUT
41 80
OUT
41 80
OUT
PCIE_FW_R2D_C_P
AU34
PETP3
8
IN
PCIE_EXCARD_D2R_N
BF36
PERN4
8
IN
PCIE_EXCARD_D2R_P
BE36
PERP4
OUT
PCIE_EXCARD_R2D_C_N
AY34
PETN4
OUT
PCIE_EXCARD_R2D_C_P
BB34
PETP4
NC_PCIE_5_D2RN
SATA1TXN
BG37
PERN5
HDA_SDIN0 (IPD)
SATA1TXP
AP10
E34
NC_PCIE_5_D2RP
BH37
PERP5
G34
HDA_SDIN1 (IPD)
SATA2RXN
AD7
TP_SATA_C_D2RN
6
NC_PCIE_5_R2D_CN
AY36
PETN5
6
C34
HDA_SDIN2 (IPD)
SATA2RXP
AD5
TP_SATA_C_D2RP
6
NC_PCIE_5_R2D_CP
BB36
PETP5
6
TP_HDA_SDIN3
A34
HDA_SDIN3 (IPD)
SATA2TXN
AH5
TP_SATA_C_R2D_CN
6
SATA2TXP
TP_SATA_C_R2D_CP
NC_PCIE_6_D2RN
BJ38
AH4
PERN6
6
NC_PCIE_6_D2RP
BG38
PERP6
SATA3RXN
AB8
TP_SATA_D_D2RN
6
NC_PCIE_6_R2D_CN
AU36
PETN6
SATA3RXP
AB10
TP_SATA_D_D2RP
6
NC_PCIE_6_R2D_CP
AV36
PETP6
SATA3TXN
AF3
TP_SATA_D_R2D_CN
6
AF1
TP_SATA_D_R2D_CP
NC_PCIE_7_D2RN
BG40
SATA3TXP
PERN7
6
NC_PCIE_7_D2RP
BJ40
PERP7
SATA4RXN
Y7
TP_SATA_E_D2RN
6
SATA4RXP
Y5
TP_SATA_E_D2RP
6
SATA4TXN
AD3
TP_SATA_E_R2D_CN
6
SATA4TXP
AD1
TP_SATA_E_R2D_CP
6
SATA5RXN SATA5RXP
Y3 Y1
TP_SATA_F_D2RP
6
SATA5TXN
AB3
TP_SATA_F_R2D_CN
6
SATA5TXP
AB1
TP_SATA_F_R2D_CP
6
A36
HDA_SDOUT_R
HDA_SDO (IPD-BOOT)
OUT
JTAG_TBT_TMS
C36
HDA_DOCK_EN*/GPIO33
IN
ENET_MEDIA_SENSE_RDIV
N32
HDA_DOCK_RST*/GPIO13
23
IN
XDP_PCH_TCK
J3
JTAG_TCK (IPD)
23
IN
XDP_PCH_TMS
H7
JTAG_TMS (IPU)
IN
XDP_PCH_TDI
K5
OUT
XDP_PCH_TDO
H1
81 47
OUT
SPI_CLK_R
T3
81 47
OUT
SPI_CS0_R_L
JTAG_TDI (IPU) JTAG_TDO
A T A S
G A T J
Y14
SPI_CS0*
T1
SPI_CS1*
I P S
81 47
OUT
SPI_MOSI_R
V4
SPI_MOSI (IPD-BOOT)
81 47
IN
SPI_MISO
U3
SPI_MISO (IPU)
SATAICOMPO
Y11
SATAICOMPI
Y10
SATA3RCOMPO
AB12
SATA3COMPI
AB13
SATA3RBIAS
7 17 20
1
1
20K 1
R1800 1 330K
1M
5% 1/20W MF 201
5% 1/20W MF 201
2
2
5% 1/20W MF 201
R1801
C1802
2
2
1
1
1UF
B
2
V14
PETP7
BE38
PERN8
37.4
BC38
PERP8
NC_PCIE_8_R2D_CN
AW38
PETN8
NC_PCIE_8_R2D_CP
AY38
6
2
1% 1/20W MF 201
=PP1V05_S0_PCH
7 22
OUT
PCIE_CLK100M_ENET_N
Y40
81 36
OUT
PCIE_CLK100M_ENET_P
Y39
81 38
OUT
R1831 49.9
16
MF 201
PLACE_NEAR=U1800.AB12:2.54mm
PCH_SATA3COMP
81 38
1
16
CLKOUT_PCIE1N
OUT
PCIE_CLK100M_FW_P
CLKOUT_PCIE1P
IN
FW_CLKREQ_L
OUT
PCIE_CLK100M_AP_N
AA48
CLKOUT_PCIE2N
81 32
OUT
PCIE_CLK100M_AP_P
AA47
CLKOUT_PCIE2P
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
OUT
23
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
OUT
23
2
32 16
IN
AP_CLKREQ_L
V10
PCIECLKRQ2*/GPIO20 CLKOUT_PCIE3N
1% 1/20W MF 201
PCIE_CLK100M_EXCARD_P
Y36
IN
EXCARD_CLKREQ_L
6
16 16
6
C1803 10% 10V X5R 402
R1877 R1878
4.7K
R1834 R1833
10K
1
2
R1842 R1869 R1844 R1845 R1847 R1814 R1815
10K
1
2
10K
1
2
10K
1
2
10K
1
2
10K
1
2
10K
2
1
10K
1
2
R1843 R1846 R1848
10K
1
2
10K
1
2
R1853 R1854 R1855
10K 10K
1
2
1
2
10K
1
2
R1879
10K
1
2
1
2
1
2
16
16
LPC_AD_R<0>
16
LPC_AD_R<1>
16
LPC_AD_R<2>
16
LPC_AD_R<3>
16
LPC_FRAME_R_L HDA_BIT_CLK_R
R1860 R1861 R1862 R1863 R1864 R1810
33
1
2
33
1
2
33
1
2
33
1
2
33
1
2
33
1
PLACE_NEAR=U1800.N34:1.27mm R1811 33 1 HDA_SYNC_R PLACE_NEAR=U1800.L34:1.27mm R1812 33 1 HDA_RST_R_L PLACE_NEAR=U1800.K34:1.27mm R1813 33 1 HDA_SDOUT_R PLACE_NEAR=U1800.A36:1.27mm
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2 5%
1/20W
MF
201
5%
1/20W
MF
201
2 2
5%
1/20W
MF
201
5%
1/20W
MF
201
2
LPC_AD<0>
BI
6 45 47 81
LPC_AD<1>
BI
6 45 47 81
LPC_AD<2>
BI
LPC_AD<3>
BI
LPC_FRAME_L
OUT
6 45 47 81
36 16
OUT
10K
1
2
10K
1
2
1
2
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
HDA_BIT_CLK
OUT
57 81
HDA_SYNC
OUT
57 81
HDA_RST_L
OUT
57 81
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5% 5%
1/20W 1/20W
MF MF
201 201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
16 33
PCH_SPKR
16
78 10
OUT
57 81
23 75
SATARDRVR_EN
23 41
FW_CLKREQ_L
16 39
AP_CLKREQ_L
16 32
JTAG_DPMUXUC_TRST_L ENET_CLKREQ_L PEG_CLKREQ_L
48 81
SML1ALERT*/PCHHOT*/GPIO74
C13
USB_EXTD_SEL_XHCI
OUT
16
SML1CLK/GPIO58
E14
SML_PCH_1_CLK
OUT
48 81
SML1DATA/GPIO75
M16
SML_PCH_1_DATA
BI
48 81 48 81
BI
BI
48 81
M7
TP_CLINK_CLK
6
(IPU/IPD) CL_DATA1
T11
TP_CLINK_DATA
6
CL_RST1*
P10
TP_CLINK_RESET_L
6
PEG_A_CLKRQ*/GPIO47
M10
PEGCLKRQA_L_GPIO47
16
CLKOUT_PEG_A_N
AB37
TP_PCIE_CLK100M_PEGAN
CLKOUT_PEG_A_P
AB38
TP_PCIE_CLK100M_PEGAP
CLKOUT_DMI_N
AV22
DMI_CLK100M_CPU_N
OUT
10 78
CLKOUT_DMI_P
AU22
DMI_CLK100M_CPU_P
OUT
10 78
CLKOUT_DP_N
AM12
TP_PCH_CLKOUT_DPN
OUT
8
CLKOUT_DP_P
AM13
TP_PCH_CLKOUT_DPP
OUT
8
CLKIN_DMI_N
BF18
PCIE_CLK100M_PCH_N
IN
16 80
CLKIN_DMI_P
BE18
PCIE_CLK100M_PCH_P
IN
16 80
CLKIN_GND1_N
BJ30
PCH_CLKIN_GNDN1
16
CLKIN_GND1_P
16
(IPU/IPD) CL_CLK1
D
48 81
C
BG30
PCH_CLKIN_GNDP1
CLKIN_DOT_96N
G24
PCH_CLK96M_DOT_N
IN
16 80
CLKIN_DOT_96P
E24
PCH_CLK96M_DOT_P
IN
16 80
CLKIN_SATA_N
AK7
PCH_CLK100M_SATA_N
IN
16 80
CLKIN_SATA_P
AK5
PCH_CLK100M_SATA_P
IN
16 80
REFCLK14IN
K45
PCH_CLK14P3M_REFCLK
IN
16 80
CLKIN_PCILOOPBACK
H45
PCH_CLK33M_PCIIN
IN
24 80
XTAL25_IN
V47
SYSCLK_CLK25M_SB_R
XTAL25_OUT
V49
R1841 78 10
ITPCPU_CLK100M_P
1
0
TP_PCIE_CLK100M_PE4N
Y43
CLKOUT_PCIE4N
TP_PCIE_CLK100M_PE4P
Y45
CLKOUT_PCIE4P
JTAG_DPMUXUC_TRST_L
L12
PCIECLKRQ4*/GPIO26
TP_PCIE_CLK100M_PE5N
V45
CLKOUT_PCIE5N
TP_PCIE_CLK100M_PE5P
V46
CLKOUT_PCIE5P
L14
ENET_CLKREQ_L
IN
DOES THIS NEED LENGTH MATCH???
PCIECLKRQ5*/GPIO44 (IPU-RSMRST#)
6
TP_PCIE_CLK100M_PEBN
AB42
CLKOUT_PEG_B_N
6
TP_PCIE_CLK100M_PEBP
AB40
CLKOUT_PEG_B_P
0
2
5% 1/20W MF 201
R1890
PEG_B_CLKRQ*/GPIO56
90.9 1%
CLKOUT_PCIE6N
1/20W MF 201
OUT
V42
CLKOUT_PCIE6P
IN
PEG_CLKREQ_L
T13
PCIECLKRQ6*/GPIO45
81 33
OUT
CLKOUT_PCIE7N
OUT
PCIE_CLK100M_T29_N PCIE_CLK100M_T29_P
V38
81 33
V37
CLKOUT_PCIE7P
35 16
IN
TBT_CLKREQ_L
K12
PCIECLKRQ7*/GPIO46 (IPU-RSMRST#)
81 8
78 23
ITPXDP_CLK100M_N
AK14
CLKOUT_ITPXDP_N
78 23
ITPXDP_CLK100M_P
AK13
CLKOUT_ITPXDP_P
5% 1/20W MF 201
IN
SYSCLK_CLK25M_SB
80 16
PCH_CLK96M_DOT_P
10K
1
2
PCH_CLK96M_DOT_N
R1891 R1892
80 16
10K
1
2
PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N
R1893 R1894
10K
1
2
10K
1
2
80 16 16 16
80 16
PCIE_CLK100M_PCH_P
R1895
10K
1
2
16
80 16
PCIE_CLK100M_PCH_N
R1896
10K
1
2
80 16
PCH_CLK14P3M_REFCLK
R1897
10K
1
2
ENET_MEDIA_SENSE_RDIV
16 24
16
16 16
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V. If HDA = S0, must also ensure that signal cannot be high in S3.
6
5
S K X C E O L L F C
1
PCH_CLKIN_GNDP1 PCH_CLKIN_GNDN1
4
R1870 R1871
10K 10K
1 1
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
PLACE_NEAR=U1800.Y47:2.54mm PCH_XCLK_RCOMP
2
XCLK_RCOMP
Y47
CLKOUTFLEX0/GPIO64 (IPD-PWROK)
K43
TP_PCH_GPIO64_CLKOUTFLEX0
6
CLKOUTFLEX1/GPIO65 (IPD-PWROK)
F47
TP_PCH_GPIO65_CLKOUTFLEX1
6
CLKOUTFLEX2/GPIO66 (IPD-PWROK)
H47
TP_PCH_GPIO66_CLKOUTFLEX2
6
CLKOUTFLEX3/GPIO67 (IPD-PWROK)
K49
TP_PCH_GPIO67_CLKOUTFLEX3
6
5% 5%
1/20W 1/20W
MF MF
201 201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
SYSCLK_CLK25M_SB_R
2
16 81
1.8V -> 1.1V 1
R1873 1K
2
1% 1/20W MF 201
S Y NC _M A ST E R= J3 1 _M L B
S Y NC _ DA T E= 0 6/ 13 / 20 1 1
PAGE TITLE
PCH SATA/PCIe/CLK/LPC/SPI DRAWING NUMBER
Apple Inc. R
2 2
604 1% 1/16W MF-LF 402
Unused clock terminations for FCIM Mode
80 16
16 25
1
R1872
16
PCH_GPIO11 USB_EXTB_SEL_XHCI USB_EXTD_SEL_XHCI
=PP1V05_S0_PCH_VCCDIFFCLK
V40
PEGCLKRQB_L_GPIO56
81 24
16
NC 22 20 7
2
16
16 35
B
16 81
PEG_CLK100M_N PEG_CLK100M_P
OUT
16
1
NO STUFF
PCIECLKRQ3*/GPIO25
16
TBT_CLKREQ_L
7
OUT
SML_PCH_0_DATA
OUT
E6
16 36
PCIECLKRQ0_L_GPIO73 PEGCLKRQA_L_GPIO47 PEGCLKRQB_L_GPIO56
ITPCPU_CLK100M_N
16
DP_AUXCH_ISOL
EXCARD_CLKREQ_L
SML_PCH_0_CLK
G12
S K C O L C
CLKOUT_PCIE3P
6
16
HDA_SDOUT
A8
6
81 8
R1840
JTAG_TBT_TMS
PCH_SATALED_L
C8
SML0CLK SML0DATA
6 45 47 81 6 45 47 81
NO STUFF
5%
16 25
PCIECLKRQ1*/GPIO18
OUT
16
7 19
R1876
M1
39 16
81 32
750
81 8
16
OUT
16
CLKOUT_PCIE0N Controlled by PCIECLKRQ5# CLKOUT_PCIE0P
R1832
5% 1/20W MF 201
PCH_INTRUDER_L
USB_EXTB_SEL_XHCI
PCIECLKRQ0*/GPIO73
20K
PCH_SRTCRST_L
A12
SML0ALERT*/GPIO60
* E - K I N C I P L C
AB47
Y37
PCH_INTVRMEN_L
SMBUS_PCH_DATA
S U B M S
AB49
PCIE_CLK100M_EXCARD_N
16
SMBUS_PCH_CLK
C9
(2 OF 10)
PCIE_CLK100M_FW_N
7 17 18 19 30
=PP3V3_T29_PCH_GPIO
J2
PCIECLKRQ0_L_GPIO73
1% 1/20W
OUT
RTC_RESET_L
PCH_GPIO11
H14
SMBDATA
PETP8
81 36
7 17 18 19
=PP3V3_S0_PCH_GPIO
8
7 20 22
81 8
81 24 16
10K
PETN7
BB40
NC_PCIE_8_D2RP
2
PCH_SATA3RBIAS
P1
81 16
AY40
NC_PCIE_8_D2RN
=PP1V05_S0_PCH_VCCIO_SATA PLACE_NEAR=U1800.Y11:2.54mm
PCH_SATAICOMP
PCH_SATALED_L
SATA1GP/GPIO19
81 16
10K
80
AH1
SATA0GP/GPIO21
81 16
=PP3V3_SUS_PCH_GPIO
TP_SATA_F_D2RN
NC_PCIE_7_R2D_CN NC_PCIE_7_R2D_CP
R1830
1
R1803
1UF
10% 10V X5R 2 402
SATA_ODD_R2D_C_P
P3
(IPU)
R1802
E12
SMBCLK
FCBGA
PLACE_NEAR=U1800.AH1:2.54mm SATALED*
=PPVRTC_G3_PCH
SATA_ODD_R2D_C_N
1
SPI_CLK
SMBALERT*/GPIO11
MOBILE
1
TP_HDA_SDIN2
TP_SPI_CS1_L
A
81 36
81 36
TP_HDA_SDIN1
24 16
23
7 22
HDA_SDIN0
33 16
23
=PP3V3_S0_PCH
6
81 24 16
C
A D H I
16
AP11
IN
1
3
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
18 OF 109 SHEET
16 OF 86
1
A
8
7
=PP3V3_SUS_PCH_GPIO
7 16 17 18 19
=PP1V05_S0_PCH_VCCIO_PCIE
7
6
5
4
2
3
1
PLACE_NEAR=U1800.BJ24:12.7mm 1
R1905
1
49.9
10K 5% 1/20W MF 201
R1900
2
2
1% 1/20W MF 201
OMIT_TABLE
D
78 9
IN
DMI_N2S_N<0>
BC24
DMI0RXN
78 9
IN
DMI_N2S_N<1>
BE20
DMI1RXN
DMI_N2S_N<2>
BG18
78 9 78 9
IN
U1800 PANTHERPOINT MOBILE
DMI2RXN
IN
DMI_N2S_N<3>
BG20 BE24
DMI0RXP
FCBGA
(3 OF 10)
DMI3RXN
OMIT_TABLE FDI_RXN0
BJ14
FDI_DATA_N<0>
IN
9 78
17 8
OUT
LVDS_IG_BKL_ON
J47
L_BKLTEN
FDI_RXN1
AY14
FDI_DATA_N<1>
IN
9 78
17 8
OUT
LVDS_IG_PANEL_PWR
M45
L_VDD_EN
FDI_RXN2
BE14
FDI_DATA_N<2>
IN
9 78 8
OUT
LVDS_IG_BKL_PWM
P45
L_BKLTCTL
FDI_RXN3
BH13
FDI_RXN4
BC12
FDI_RXN5
BJ12
FDI_RXN6 FDI_RXN7 FDI_RXP0
FDI_DATA_P<1>
IN
9 78
FDI_DATA_P<2>
IN
9 78
FDI_DATA_N<3>
IN
9 78
FDI_DATA_N<4> FDI_DATA_N<5>
IN
9 78
8
OUT
IN
9 78
8
OUT
BG10
FDI_DATA_N<6>
IN
9 78
BG9
FDI_DATA_N<7>
IN
9 78
BG14
FDI_DATA_P<0>
IN
9 78
IN
DMI_N2S_P<0>
78 9
IN
DMI_N2S_P<1>
BC20
DMI1RXP
78 9
IN
DMI_N2S_P<2>
BJ18
DMI2RXP
78 9
IN
DMI_N2S_P<3>
BJ20
DMI3RXP DMI0TXN
FDI_RXP1
BB14
DMI1TXN
FDI_RXP2
BF14
FDI_RXP3
BG13
FDI_RXP4
BE12
FDI_RXP5
BG12
FDI_RXP6
BJ10
FDI_RXP7
BH9
78 9
78 9
OUT
DMI_S2N_N<0>
AW24
78 9
OUT
DMI_S2N_N<1>
AW20
OUT
DMI_S2N_N<2>
BB18
OUT
DMI_S2N_N<3>
AV18
DMI3TXN
OUT
DMI_S2N_P<0>
AY24
DMI0TXP
OUT
DMI_S2N_P<1>
AY20
OUT
DMI_S2N_P<2>
AY18
DMI_S2N_P<3>
AU18
78 9 78 9
78 9 78 9 78 9 78 9
OUT
DMI2TXN
DMI1TXP DMI2TXP DMI3TXP
BJ24
PCH_DMI_COMP
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
PCH_DMI2RBIAS
I I M D D F
DMI2RBIAS
FDI_INT
AW16
FDI_FSYNC0
AV12
FDI_FSYNC1
BC10
FDI_DATA_P<3>
750
2
1% 1/20W MF 201
17
45 24
C
45 24 23
24
24
78 26 10
73
P12
PM_PCH_SYS_PWROK
IN
L22
PM_PCH_PWROK
IN IN
PM_PCH_APWROK
L10
OUT
PM_MEM_PWRGD
B13
IN
PM_RSMRST_L
C21
PCH_SUSWARN_L
K16
17
45 23 17
K3
PM_SYSRST_L
IN
E20
PM_PWRBTN_L
IN
R SUSACK* (IPU) E T W N SYS_RESET* O E P M SYS_PWROK E M PWROK G E A APWROK T N S A DRAMPWROK Y S M RSMRST*
C12
PCH_SUSACK_L
R1950 2.37K
LVDS_IG_A_CLK_N
AK39
FDI_DATA_P<7>
IN
9 78
80 74
OUT
LVDS_IG_A_CLK_P
AK40
LVDSA_DATA0* LVDSA_DATA1*
FDI_FSYNC<0> FDI_FSYNC<1>
=PPVRTC_G3_PCH OUT OUT
73 46 45
IN
SMC_ADAPTER_EN
H20
46
IN
PM_BATLOW_L
E10
A18
PCH_DSWVRMEN
DPWROK
E22
PM_DSW_PWRGD
9 78
PM_CLKRUN_L LPC_PWRDWN_L
SLP_A*
IN BI OUT
6 17 24 32
1
SLP_SUS*
ACPRESENT/GPIO31 (IPD-DeepS4/S5) BATLOW*/GPIO72 (IPU)
PMSYNCH
1
SLP_LAN*/GPIO29
PM_CLK32K_SUSCLK_R
OUT
46
OUT
17 45 73
PM_SLP_S4_L
OUT
6 17 26 32 45 73
PM_SLP_S3_L
OUT
6 8 17 26 45 73
K14
5% 1/20W MF 201
R1983
45
R1909 5% 1/20W MF 201
PCH_SUSWARN_L
17
A
1K
AN47
LVDSA_DATA0
80 74 6
OUT
LVDS_IG_A_DATA_P<1>
AM49
LVDSA_DATA1
OUT
LVDS_IG_A_DATA_P<2>
AK49
LVDSA_DATA2
OUT
LVDS_IG_A_DATA_P<3>
AJ47
LVDSA_DATA3
OUT
LVDS_IG_B_CLK_N
AF40
LVDSB_CLK
LVDSB_CLK*
80 8
OUT
LVDS_IG_B_CLK_P
AF39
80 8
OUT
LVDS_IG_B_DATA_N<0>
AH45
LVDSB_DATA0*
80 8
OUT
LVDS_IG_B_DATA_N<1>
AH47
LVDSB_DATA1*
80 8
OUT
LVDS_IG_B_DATA_N<2>
AF49
LVDSB_DATA2*
80 8
OUT
LVDS_IG_B_DATA_N<3>
AF45
LVDSB_DATA3*
80 8
OUT
LVDS_IG_B_DATA_P<0>
AH43
LVDSB_DATA0
80 8
OUT
80 8
OUT
LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_P<2>
AF47
80 8
OUT
LVDS_IG_B_DATA_P<3>
AF43
LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3
TP_PM_SLP_A_L PM_SLP_SUS_L
OUT
17 73
PM_SYNC
OUT
10 78
GPIO29
OUT
6
TP_SDVO_TVCLKINP
6
TP_SDVO_STALLN
6
AM40
TP_SDVO_STALLP
6
SDVO_INTN (IPD) SDVO_INTP (IPD)
AP39
TP_SDVO_INTN
6
AP40
TP_SDVO_INTP
6
SDVO_CTRLCLK
P38
DPA_IG_DDC_CLK
8
SDVO_CTRLDATA (IPD-PLTRST#)
M39
DPA_IG_DDC_DATA
8
DDPB_AUXN
AT49
DPA_IG_AUX_CH_N
8
DDPB_AUXP
AT47
DPA_IG_AUX_CH_P
8
DDPB_HPD
AT40
DPA_IG_HPD
8
AV42
TP_DP_IG_B_MLN<0>
8
AV40
TP_DP_IG_B_MLP<0>
8
AV45
TP_DP_IG_B_MLN<1>
8
AV46
TP_DP_IG_B_MLP<1>
8
AU48
TP_DP_IG_B_MLN<2>
8
AU47
TP_DP_IG_B_MLP<2>
8
AV47
TP_DP_IG_B_MLN<3>
8
AV49
TP_DP_IG_B_MLP<3>
8
P46
DPB_IG_DDC_CLK
8
P42
DPB_IG_DDC_DATA
8
AP47
DPB_IG_AUX_CH_N
8
AP49
DPB_IG_AUX_CH_P
8
AT38
DPB_IG_HPD
8
AY47
TP_DP_IG_C_MLN<0>
8
AY49
TP_DP_IG_C_MLP<0>
8
AY43
TP_DP_IG_C_MLN<1>
8
AY45
TP_DP_IG_C_MLP<1>
8
BA47
E DDPB_0N C DDPB_0P A DDPB_1N F DDPB_1P R E DDPB_2N T DDPB_2P N DDPB_3N I DDPB_3P Y A DDPC_CTRLCLK L DDPC_CTRLDATA (IPD-PLTRST#) P DDPC_AUXN S I DDPC_AUXP D DDPC_HPD L DDPC_0N A DDPC_0P T DDPC_1N I DDPC_1P G DDPC_2N I DDPC_2P D
TP_DP_IG_C_MLN<2>
8
BA48
TP_DP_IG_C_MLP<2>
8
DDPC_3N
BB47
TP_DP_IG_C_MLN<3>
8
DDPC_3P
BB49
TP_DP_IG_C_MLP<3>
8
DDPD_CTRLCLK
M43
TP_DP_IG_D_CTRL_CLK
8
DDPD_CTRLDATA (IPD-PLTRST#)
M36
TP_DP_IG_D_CTRL_DATA
8
DDPD_AUXN
AT45
TP_DP_IG_D_AUXN
8
DDPD_AUXP
AT43
TP_DP_IG_D_AUXP
8
DDPD_HPD
BH41
TP_DP_IG_D_HPD
8
DDPD_0N
BB43
TP_DP_IG_D_MLN<0>
8
DDPD_0P DDPD_1N
BB45
TP_DP_IG_D_MLP<0>
8
6
TP_CRT_IG_BLUE
N48
6
TP_CRT_IG_GREEN
P49
6
TP_CRT_IG_RED
T49
6
TP_CRT_IG_DDC_CLK
T39
CRT_DDC_CLK
6
TP_CRT_IG_DDC_DATA
M40
CRT_DDC_DATA
BF44
TP_DP_IG_D_MLN<1>
8
6
TP_CRT_IG_HSYNC
M47
CRT_HSYNC
DDPD_1P
BE44
TP_DP_IG_D_MLP<1>
8
6
TP_CRT_IG_VSYNC
M49
CRT_VSYNC
DDPD_2N DDPD_2P
BF42
TP_DP_IG_D_MLN<2>
8
BE42
TP_DP_IG_D_MLP<2>
8
CRT_BLUE CRT_GREEN
CRT_RED
17
PCH_DAC_IREF PLACE_NEAR=U1800.T43:2.54mm
T R C
T43
DAC_IREF
DDPD_3N
BJ42
TP_DP_IG_D_MLN<3>
8
T42
CRT_IRTN
DDPD_3P
BG42
TP_DP_IG_D_MLP<3>
8
D
C
1 2
R1951
R1986 0
1K 1
PCH_SUSACK_L
17
2
5% 1/20W MF 201
B
7
PM_PWRBTN_L
2
R1991
8.2K
1
2
10K
1
2
R1925
1K
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
PM_CLKRUN_L
5% 5%
R1924
100K
2
1
R1921 R1922 R1923
100K 100K
2
1
2
1
100K
2
1
R1981 R1984
100K
2
1
8
LVDS_IG_A_DATA_P<0>
TP_SDVO_TVCLKINN
AM42
(IPD)
7 16 18 19 30
1
R1982
100K
LVDSA_DATA3*
OUT
AP45
SDVO_STALLP
7 16 17 18 19
=PP3V3_S0_PCH_GPIO =PP3V3_S5_PCH
R1985
LVDSA_DATA2*
S D V L
AH49
5% 1/20W MF 201
=PP3V3_SUS_PCH_GPIO
OUT
LVDSA_CLK
1
2
B
OUT
LVDSA_CLK*
80 74 6
80 8
10K 5% 1/20W MF 201
LVDS_IG_A_DATA_N<3>
AJ48
80 74 6
=PP3V3_SUS_PCH_GPIO
19 18 17 16 7
LVDS_IG_A_DATA_N<2>
AK47
80 8
100K
6 45 47
PM_SLP_S5_L
AP14
AM47
R1915 390K
6 17 45 47
D10
G16
LVDS_IG_A_DATA_N<1>
80 74 6
IN
N14
G10
LVDS_IG_A_DATA_N<0>
OUT
80 8
H4
F4
RI*
PCIE_WAKE_L
OUT
80 74 6
7 16 20
9 78
2
PWRBTN* (IPU)
A10
PCH_RI_L
DSWVRMEN
80 74 6
AN48
AP43
(IPD)
SDVO_STALLN (IPD)
2
9 78
9 78
SUSWARN*/SUSPWRDNACK/GPIO30 SLP_S3*
LVD_VREFL
OUT
OUT
SLP_S4*
AE47
80 74
FDI_LSYNC<1>
SUSCLK/GPIO62
LVD_VREFH
9 78
BB10
SLP_S5*/GPIO63
AE48
IN
OUT
(4 OF 10)
L_CTRL_DATA
FDI_DATA_P<6>
FDI_INT
FCBGA
L_CTRL_CLK
9 78
1% 1/20W MF 201
MOBILE
LVD_IBG LVD_VBG
9 78
FDI_LSYNC1
G8
P39
IN
9 78
SUS_STAT*/GPIO61
T45
AF37 AF36
IN
OUT
CLKRUN*/GPIO32
1
L_DDC_DATA (IPD-PLTRST#)
FDI_DATA_P<5>
FDI_LSYNC<0>
N3
6
PCH_LVDS_IBG TP_PCH_LVDS_VBG
K47
FDI_DATA_P<4>
AV14
B9
TP_LVDS_IG_CTRL_DATA
L_DDC_CLK
9 78
FDI_LSYNC0
WAKE*
TP_LVDS_IG_CTRL_CLK
6
PLACE_NEAR=U1800.AF37:2.54mm
2
R1920
6
T40
IN
PLACE_NEAR=U1800.BH21:2.54mm 1
LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
U1800 SDVO_TVCLKINN (IPD) PANTHERPOINTSDVO_TVCLKINP
2
1
1/20W 1/20W
MF MF
17 23 45
6 17 45 47
GPIO29
17
PCIE_WAKE_L
6 17 24 32
201 201 MAKE_BASE=TRUE
PM_SLP_S3_L 5% 5%
1/20W 1/20W
MF MF
201 201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
S Y NC _M A ST E R= J3 1 _M L B =TBT_WAKE_L
PCH DMI/FDI/PM/Graphics
75
DRAWING NUMBER
SIZE
6 8 17 26 45 73
PM_SLP_S4_L PM_SLP_S5_L PM_SLP_SUS_L
17 45 73
LVDS_IG_BKL_ON
8 17
LVDS_IG_PANEL_PWR
8 17
7
S Y NC _ DA T E= 0 6/ 13 / 20 1 1
PAGE TITLE IN
Apple Inc.
6 17 26 32 45 73 R
17 73
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
5
4
3
2
051-9058 6.0.0
REVISION
D
BRANCH
PAGE
19 OF 109 SHEET
17 OF 86
1
A
8
7
6
5
4
2
3
1
OMIT_TABLE
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
D
NC NC NC NC NC NC TP_PCH_TP23
NC
R2054
10K
1
2
10K
1
2
10K 10K
1
2
1
2
10K
2
A
7 24 7 16 17 18 19 30
1
2
1
2
R2014 R2031
10K 1NO STUFF 2
R2033
10K
10K
1
2
5%
MF
201
MF
201
5%
1/20W
MF
201
R2069
10K
1
R2060 R2061 R2062 R2068
10K 10K
1
2
1
2
10K
1
2
10K
1
2
1/20W
MF
18
BLC_I2C_MUX_SEL
18
USE_HDD_OOB_L
18
BLC_GPIO
18
AUD_IP_PERIPHERAL_DET
18 62
RSVD9
AT3
TP11
RSVD10
AT1
TBT_PWR_REQ_L
NC NC NC NC NC NC NC NC NC
D
H3
TP12
RSVD11
AY3
AH12
TP13
RSVD12
AT5
AM4
TP14
RSVD13
AV3
AM5
TP15
RSVD14
AV1
Y13
TP16
RSVD15
BB1
K24
TP17
RSVD16
BA3
L24
TP18
RSVD17
BB5
AB46
TP19
RSVD18
BB3
AB45
TP20
RSVD19
BB7
TP21
RSVD20
BE8
B21
RSVD21
BD4
RSVD22
BF6
RSVD23
AV5
RSVD24
AV10
RSVD25
AT8
RSVD26
AY5
RSVD27
BA2
RSVD28
AT12
RSVD29
BF3
USBP0N
C24
USB_EXTA_N
BI
M20
TP22
AY16
TP23
BG46
TP24
NC NC NC NC NC NC NC NC NC NC NC NC NC NC
USB_EXTA_P
BI
42 80
C25
USB3_EXTD_RX_N
USB_EXTB_XHCI_N
BI
25 80
USBP1P
B25
USB_EXTB_XHCI_P
BI
25 80
USBP2N
C26
USB_EXTC_N
BI
8 80
USBP2P
A26
USB_EXTC_P
BI
8 80
USBP3N
K28
USB_EXTD_XHCI_N
BI
8 80
USBP3P
H28
USB_EXTD_XHCI_P
BI
8 80
USBP4N
E28
TP_USB_4N
USBP4P
D28
TP_USB_4P
USBP5N
IN
USB3RN1
80 42
IN
USB3_EXTA_RX_P
BC28
USB3RP1
80 43
IN
USB3_EXTB_RX_P
BE30
USB3RP2
IN
USB3_EXTC_RX_P
BF32
USB3RP3
IN
USB3_EXTD_RX_P
BG32
USB3RP4
OUT
USB3_EXTA_TX_N
AV26
USB3TN1
USB3_EXTB_TX_N
BB26
USB3TN3
OUT
B S U
USB3TN2
42 80
8
OUT
USB3_EXTC_TX_N
8
OUT
USB3_EXTD_TX_N
AY30
USB3TN4
C28
TP_USB_SDN
A28
AU26
USB3TP1
TP_USB_SDP
OUT
USB3_EXTA_TX_P
USBP5P
80 42
OUT
USB3_EXTB_TX_P
AY26
USB3TP2
USBP6N
C29
TP_USB_WLANN
8
OUT
USB3_EXTC_TX_P
AV28
USB3TP3
USBP6P
B29
TP_USB_WLANP
8
OUT
USB3_EXTD_TX_P
AW30
USB3TP4
USBP7N
N28
USB_HUB_UP_N
BI
25 80
USBP7P
M28
USB_HUB_UP_P
BI
25 80
USBP8N
L30
USB_CAMERA_N
BI
USBP8P
K30
USB_CAMERA_P
BI
32 80
USBP9N
G30
USB_EXTB_EHCI_N
BI
25 80
USBP9P
E30
USB_EXTB_EHCI_P
BI
25 80
USBP10N
C30
USB_EXTD_EHCI_N
BI
8
USBP10P
A30
USB_EXTD_EHCI_P
BI
8
USBP11N
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
PCI_INTA_L
K40
PIRQA*
PCI_INTB_L
K38
PIRQB*
PCI_INTC_L
H38
PIRQD*
PIRQC*
I C P
PCI_INTD_L
G38
18
OUT
JTAG_GMUX_TMS
C46
REQ1*/GPIO50
18
OUT
BLC_I2C_MUX_SEL
C44
REQ2*/GPIO52
L32
OUT
USE_HDD_OOB_L
E40
REQ3*/GPIO54
TP_USB_BT_HSN
18
USBP11P
K32
TP_USB_BT_HSP
TP_PCH_STRP_BBS1
D47
GNT1*/GPIO51
USBP12N
G32
TP_USB_12N
TP_PCH_STRP_ESI_L
E42
GNT2*/GPIO53
USBP12P
E32
TP_USB_12P
PCH_STRP_TOPBLK_SWP_L
F46
GNT3*/GPIO55
USBP13N
C32
TP_USB_13N
201
MF
201
(IPU-PCIERST#)
18
IN
BLC_GPIO
G42
PIRQE*/GPIO2
62 18
IN
PIRQF*/GPIO3
IN
AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L
G40
75 18
C42
PIRQG*/GPIO4
IN
AUD_I2C_INT_L
D44
PIRQH*/GPIO5
TP_PCI_PME_L
K10
PME* (IPU)
OUT
C6
PLT_RESET_L
PLTRST*
Ext D (XHCI) (Mobiles: Trackpad?)
RSVD: SD RSVD: WiFi USB Hub (All LS/FS Devices)
32 80
USBP13P
A32
USBRBIAS*
C33
USBRBIAS
B33
OC0*/GPIO59 OC1*/GPIO40
A14
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
K20
OC2*/GPIO41
B17
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
Camera Ext B (EHCI) Ext D (EHCI) RSVD: BT (HS)
80
1/20W
MF
PCH_USB_RBIAS PLACE_NEAR=U1800.B33:2.54mm 1
1/20W
MF
IN
18 23
IN
18 23
IN
18 23
81 24
OUT
LPC_CLK33M_SMC_R
H49
CLKOUT_PCI0
OC3*/GPIO42
C16
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
IN
18 23
24
OUT
LPC_CLK33M_LPCPLUS_R
H43
CLKOUT_PCI1
OC4*/GPIO43
L16
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
IN
23
TP_PCI_CLK33M_OUT2
J48
CLKOUT_PCI2
OC5*/GPIO9
A16
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
IN
23
TP_PCI_CLK33M_OUT3
K42
D14
XDP_DB2_PCH_GPIO10_AP_PWR_EN
OUT
23
OUT
PCH_CLK33M_PCIOUT
H40
CLKOUT_PCI3 CLKOUT_PCI4
OC6*/GPIO10
24
OC7*/GPIO14
C14
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
(IPD)
IN
R2070 22.6
2
1% 1/20W MF 201
18 23
18 75
S Y NC _M A ST E R= J3 1 _M L B
S Y NC _ DA T E= 0 6/ 13 / 20 1 1
PAGE TITLE
18 62
PCH PCI/USB/TP/RSVD
201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
2
B
Unused Unused
TP_USB_13P
(IPD)
C
Ext C (XHCI/EHCI)
Unused
AU28
80 43
Ext A (XHCI/EHCI) Ext B (XHCI)
201
AUD_I2C_INT_L
5%
8
TP10
N30
Redundant to pull-up on audio page
2
2
201
1/20W 1/20W
5%
10K
MF
201
5%
5%
R2067
1/20W
MF
5%
NO STUFF 1
C18
NC NC
USBP1N
6
1/20W
AT4
USBP0P
1
JTAG_GMUX_TMS
AU2
RSVD8
USB3RN3 USB3RN4
7 16 17 19
=PP3V3_S0_PCH_GPIO
BC8
RSVD7
USB3RN2
26 24
=PP3V3_S3_PCH_GPIO
AT10
RSVD6
BJ32
5%
1/20W
RSVD5
NC NC NC NC
BE32
6
10K
TP9
BG4
USB3_EXTC_RX_N
62 18
10K
AK45
AU3
IN
5%
5%
R2030
TP8
AV7
RSVD4
IN
NO STUFF
5%
TP7
AK43
AY7
RSVD2 RSVD3
8
B
2
TP6
AH37
=PP3V3_S0_PCH_GPIO
R2010 R2011 R2012 R2013
1
TP5
AH38
(5 OF 10)
RSVD1
80 43
80 43
10K
BG16
FCBGA
A24
8
2
TP4
MOBILE
BC30
80 42
1
BJ16
PANTHERPOINT
BE28
8
10K
TP3
USB3_EXTB_RX_N
8
R2016 R2017 R2018
TP2
BH25
USB3_EXTA_RX_N
C
=PP3V3_SUS_PCH_GPIO
U1800
TP1
BJ26
IN
80 42
30 19 18 17 16 7
BG26
DRAWING NUMBER
18 23
SIZE
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
18 23 18 23
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
18 23
AP_PWR_EN
7
Apple Inc.
18 23
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
23 32 73
6
5
4
3
2
051-9058 6.0.0
REVISION
D
BRANCH
PAGE
20 OF 109 SHEET
18 OF 86
1
A
8
7
6
5
4
2
3
1 TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
RAMCFG_SLOT
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
TABLE_BOMGROUP_ITEM
Systems with no chip-down memory should pull all Systems with chip-down memory should add pull-downs on another page 30 19 18 17 16 7
R2172
1
RAMCFG2:H
5% 1/20W MF 201
OMIT_TABLE XDP_FC1_PCH_GPIO0
IN
FW_PME_L
A42
TACH1/GPIO1
MOBILE
IN
DPMUX_UC_IRQ
H36
TACH2/GPIO6
(6 OF 10)
SMC_RUNTIME_SCI_L
E38
R2173
TACH3/GPIO7
TP_PCH_GPIO8
C10
GPIO8 (IPU-RSMRST#)
WOL_EN
OUT
23
IN
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
23
OUT
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
BI
LPCPLUS_GPIO
41 19
OUT
ODD_PWR_EN_L
46 19
IN
19
23
R2180
0
1
PCH_GPIO24 (PU necessary?) SMC_SCI_L
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
OUT
2
19
5% MF
1/20W 201 23
23 19
C
23
19 8
8
24 19
23
56 47 19 6
OUT OUT
C4
LAN_PHY_PWR_CTRL/GPIO12
G2
GPIO15 (IPD)
U2
SATA4GP/GPIO16
D40
C40
MLB_RAMCFG3
TACH5/GPIO69
B41
MLB_RAMCFG2
TACH6/GPIO70
C41
MLB_RAMCFG1
TACH7/GPIO71
A40
MLB_RAMCFG0
T5
SCLOCK/GPIO22
E8
GPIO24
E16 P8
2
2
RAMCFG0:H
1
1
2
2
5% 1/20W MF 201
R2175 10K
10K
5% 1/20W MF 201
D
5% 1/20W MF 201
STP_PCI*/GPIO34
K4
GPIO35
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
V8
C S THRMTRIP* I M INIT3_3V* / (IPU) O U I DF_TVS P P (IPD-PLTRST#?) C G
SATA2GP/GPIO36 (IPD-PLTRST#)
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
M5
SATA3GP/GPIO37 (IPD-PLTRST#)
IN
JTAG_ISP_TDO
N2
SLOAD/GPIO38
OUT
JTAG_ISP_TDI
M3
SDATAOUT0/GPIO39
OUT
FW_PWR_EN_PCH
V13
SDATAOUT1/GPIO48
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH SPIROM_USE_MLB
PROCPWRGD
GPIO28 (IPU-RSMRST#)
K1
XDP_DC1_PCH_GPIO35_MXM_GOOD
P4
PCH_A20GATE
AU16
PCH_PECI
P5
PCH_RCIN_L
SATA5GP/GPIO49/TEMP_ALERT*
AY11
R2140
0
1
2
PM_THRMTRIP_L_R
R2156
390
1
2
PCH_INIT3V3_L PCH_DF_TVS
BI
1/20W 201
10 46 78
CPU_PWRGD 1/20W 201
=PP1V8_S0_PCH_VCC_DFTERM OUT
10 23 78
IN
10 46 78
PM_THRMTRIP_L 1/20W 201
R2179 2.2K
R2178 2
TS_VSS1 TS_VSS2
AK11
1K
TS_VSS3
AH10
TS_VSS4
AK10
5% 1/20W MF 201
NC_1
P37
VSS_NCTF_14
BG2
VSS_NCTF_15
BG48
VSS_NCTF_16
BH3 BH47
VSS_NCTF_18
BJ4
VSS_NCTF_1
VSS_NCTF_19
BJ44
A45
VSS_NCTF_2
VSS_NCTF_20
BJ45
A46
VSS_NCTF_3
VSS_NCTF_21
BJ46
A5
VSS_NCTF_4
VSS_NCTF_22
BJ5
A6
VSS_NCTF_5
VSS_NCTF_23
BJ6
B3
VSS_NCTF_6 VSS_NCTF_7
VSS_NCTF_24 VSS_NCTF_25
C2
VSS_NCTF_8
VSS_NCTF_26
D1
VSS_NCTF_9 VSS_NCTF_10
VSS_NCTF_27
D49
VSS_NCTF_28
E1
BE49
VSS_NCTF_11
VSS_NCTF_29
E49
BF1
VSS_NCTF_12 VSS_NCTF_13
VSS_NCTF_30
F1
VSS_NCTF_31
F49
R2130
1K
1
5% 1/20W MF 201
1 This has internal pull up and should not
2
5% 1/20W MF 201
CPU_PROC_SEL_L
10
DF_TVS:DMI & FDI Term Voltage Set to Vss when Low
C
Set to Vcc when High
pulled low.
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND
7 20 22
1
NO STUFF AH8
VSS_NCTF_17
BF49
CPU_PECI
2
PCH_PROCPWRGD
T14
VSS_NCTF_0
BE1
46
AY1
GPIO57
BD49
1
5% MF
A4
BD1
43
19
5% MF AY10
D6
F T C N
R2170
5% MF
A44
B47
19
NO STUFF
RCIN*
GPIO27 (IPU-DeepS4/S5)
TBT_SW_RESET_R_L
V3
A20GATE (IPD) PECI
TACH0/GPIO17
OUT
BI
TACH4/GPIO68
R2174
10K
FCBGA
IN
47 19 6
TBT_SW_RESET_L
U1800 PANTHERPOINT
19
73 19
OUT
BMBUSY*/GPIO0
39 19 8
45 19
35
T7
RAMCFG1:H
1
10K
23 19
and set straps per software.
=PP3V3_S0_PCH_GPIO RAMCFG3:H
D
4 RAMCFG GPIOs high.
WE ARE NOT USING IT.
2
NC
C48
B
B
=PP3V3_S5_PCH_GPIO
7
=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO
7 16 17 18 19 30
7 16 17 18
=PP3V3_T29_PCH_GPIO
R2186 R2199 R2160 R2185 R2196 R2190
7 16
10K
1
2
10K
1
2
10K
1
2
10K
1
2
10K
1
2
100K
1
2
5%
A
10K
1
2
10K
1
2
R2150 R2155
10K 10K
1
2
R2194 R2192 R2193
10K
1
2
10K
1
2
100K
1
2
1
10K
1
2
20K
2
1
R2111 R2195 R2112 R2198 R2113 R2116
100K
2
1
10K
2
1
8
10K
2
1
10K
2
1
2
201
MF
201
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1
JTAG_ISP_TDO
8 19
JTAG_TBT_TDI
8 33
XDP_FC1_PCH_GPIO0
19 23
FW_PME_L
8 19 39
SMC_RUNTIME_SCI_L
19 45
LPCPLUS_GPIO
6 19 47
Must stuff R2197 when R2180 NO STUFFed. 5%
1/20W
MF
201
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
TBT_SW_RESET_R_L
19
FW_PWR_EN_PCH
19 24
PCH_A20GATE
19
201
2
R2191
10K
MF
1/20W 1/20W
NO STUFF
R2197 R2184
1/20W
5% 5%
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
PCH_RCIN_L
19
WOL_EN
19 73
PCH_GPIO24
19
SPIROM_USE_MLB
6 19 47 56
SMC_SCI_L
19 46
DPMUX_UC_IRQ AUD_IPHS_SWITCH_EN_PCH
23 24
ODD_PWR_EN_L
19 41
SYNC_MASTER=J31_MLB
SYNC_DATE=06/13/2011
PAGE TITLE
PCH GPIO/MISC/NCTF DRAWING NUMBER
19
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
NOTICE OF PROPRIETARY PROPERTY:
19 23
JTAG_ISP_TCK
8 23
ENET_LOW_PWR_PCH
23 24
7
Apple Inc. R
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
21 OF 109 SHEET
19 OF 86
1
A
8
7
6
5
4
2
3
1
D
D
OMIT_TABLE 22 7
VCCACLK pin left as NC per DG 22 7
22
U1800 VCCIO_29_USB PANTHERPOINT VCCIO_30_USB
TP_PPVOUT_PCH_DCPSUSBYP
V12
DCPSUSBYP
PP3V3_S0_PCH_VCC3_3_CLK_F
T38
VCC3_3_5_CLK
BH23
NC
=PP1V05_S0_PCH_VCCIO_CLK
AL24 left as NC per DG 22 20 7
VCCACLK
T16
VCCAPLLDMI2 pin left as NC per DG 22 20 7
AD49
NC
=PP3V3_S5_PCH_VCCDSW
NC
=PP1V05_S0_PCH_VCCASW
AA23
VCCCORE
U1800
AC23
VCCCORE
PANTHERPOINT
P28
AD21
FCBGA
VCCCORE
(8 OF 10)
VCCIO_32_USB
T27
AD23
VCCCORE
VCCIO_33_USB
T29
AF21
VCCCORE
AF23
VCCCORE
VCCAPLLDMI2
AL29
VCCIO_14_PLLCLK
AL24
DCPSUS_3_CLK VCCASW_1_CLK
AA21
VCCASW_2_CLK
AA24
VCCASW_3_CLK
AA26
VCCASW_4_CLK
AA27
VCCASW_5_CLK
AA29
VCCASW_6_CLK
AC26 AC27
VCCASW_9_CLK VCCASW_10_CLK
AC31
VCCASW_11_CLK
AD29
VCCASW_12_CLK
AD31
VCCASW_13_CLK
W21
PCH output, for decoupling only PLACE_NEAR=U1800.N16:2.54mm
C2210
1
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
0.1UF 20% 10V CERM 2 402
20 7
VCCASW_20_CLK
=PP1V8R1V5_S0_PCH_VCCVRM
Y49
VCCADPLLA
BF47
VCCADPLLB
=PP1V05_S0_PCH_VCCIO_CLK
AF17
VCCIO_7_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
AF33
VCCDIFFCLKN
AF34
VCCDIFFCLKN
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
NC-ed per DG NC NC
PLACE_NEAR=U1800.V16:2.54mm 22 7
17 16 7
=PP1V05_S0_PCH_V_PROC_IO =PPVRTC_G3_PCH
C2231
1
1
2
2
1UF
C2232
1
20% 10V CERM 402
AG34
VCCDIFFCLKN
AG33
VCCSSC
V16
DCPSST
T17
DCPSUS_1_CLK
V19
DCPSUS_2_CLK
BJ8
V_PROC_IO
A22
VCCRTC
=PP1V05_S0_PCH_VCCIO_USB
=PP3V3_SUS_PCH_VCCSUS_USB
7 22
7 22
VCCSUS3_3_9_USB
V23
VCCSUS3_3_10_USB
V24
VCCSUS3_3_6_USB
P24
VCCIO_34_PLLUSB
T26
=PP1V05_S0_PCH_VCCIO_PLLUSB
7
V5REF_SUS
M26
=PP5V_SUS_PCH_V5REFSUS
22
DCPSUS_4_USB
AN23
VCCSUS3_3_1_USB
AN24
NC NC-ed per DG =PP3V3_SUS_PCH_VCCSUS
7
V5REF
P34
=PP5V_S0_PCH_V5REF
22
VCCSUS3_3_2_GPIO
N20
=PP3V3_SUS_PCH_VCCSUS_GPIO
7 22
7
C S VCCSUS3_3_3_GPIO N22 I M VCCSUS3_3_4_GPIO P20 / K VCCSUS3_3_5_GPIO P22 L C / O I P C G P / L I C P
AA16
VCC3_3_8_GPIO
W16
VCC3_3_4_GPIO
T34
VCC3_3_2_SATA
AJ2
=PP3V3_S0_PCH_VCC3_3_SATA
7 22
VCCIO_5_PLLSATA
AF13
=PP1V05_S0_PCH_VCCIO_SATA
7 16 20 22
VCCIO_12_SATA3
AH13
VCCIO_13_SATA3
AH14
VCCIO_6_PLLSATA3 A T A S
VCCAPLLSATA
C S I M
C T R
VCCCORE
AG24
VCCCORE
AG26
VCCCORE
AG27
VCCCORE
AG29
VCCCORE
AJ23
VCCCORE
AJ26
VCCCORE
AJ27
VCCCORE
AJ29
VCCCORE
AJ31
VCCCORE
NC VCCAPLLSATA pin left as NC per DG
AF11
=PP1V8R1V5_S0_PCH_VCCVRM
7 20
AC16
=PP1V05_S0_PCH_VCCIO_SATA
7 16 20 22
AC17
AN19
VCCIO_28_PLLPCIE
BJ22
VCCAPLLEXP
=PP1V05_S0_PCH_VCCIO
AN16
VCCIO_15_FDI
AN17
VCCIO_16_FDI
AN21
VCCIO_17_PCIE
AN26
VCCIO_18_PCIE
AN27
VCCIO_19_PCIE
AP21
VCCIO_20_PCIE
AP23
VCCIO_21_PCIE
AP24
VCCIO_22_PCIE
AP26
VCCIO_23_PCIE
AT24
VCCIO_24_PCIE
AN33
VCCIO_25_DP
AN34
VCCIO_26_DP
VCCASW_23_MISC
V21
VCCASW_21_MISC
T19
VCCSUSHDA
P32
=PP1V05_S0_PCH_VCCASW
22 7
=PP3V3_S0_PCH_VCC3_3_PCI
BH29
VCC3_3_3_PCIE
20 7
=PP1V8R1V5_S0_PCH_VCCVRM
AP16
VCCVRM_2_FDI
NC
BG6
VCCAFDIPLL
7
=PP1V05_S0_PCH_VCCIO_PLLFDI
AP17
VCCIO_27_PLLFDI
7
=PP1V05_S0_PCH_VCCDMI_FDI
AU20
VCCDMI_2_FDI
T R C
VCCADAC
U48
VSSADAC
U47
VCCALVDS
AK36
VSSALVDS
AK37
VCCTX_LVDS
AM37
VCCTX_LVDS
AM38
VCCTX_LVDS
AP36
VCCTX_LVDS
AP37
S D V L
TP_1V05_S0_PCH_VCCAPLLEXP
VCCAFDIPLL pin left as NC per DG
AD17
FCBGA
E R O C C C V
=PP1V05_S0_PCH_VCCIO_PLLPCIE
7 22
VCCIO_2_SATA VCCIO_3_SATA
VCCASW_22_MISC
H
VCCCORE
AG23
AF14 AK1
T21
A D
=PP3V3_S0_PCH_VCC3_3_GPIO
VCCVRM_1_SATA
VCCIO_4_SATA
U P C
22 7
VCC3_3_1_GPIO
AG21
MOBILE
(7 OF 10)
PP3V3_S0_PCH_VCCA_DAC_F
22
=PP3V3_S0_PCH_VCCA_LVDS
7
PP1V8_S0_PCH_VCCTX_LVDS_F
22
=PP3V3_S0_PCH_VCC3_3_HVCMOS
7 22
C
S VCC3_3_6_HVCMOS V33 O M C V VCC3_3_7_HVCMOS V34 H O I C C V
I M D
I P I S D F / T F D
VCCVRM_3_DMI
AT16
=PP1V8R1V5_S0_PCH_VCCVRM
7 20
VCCDMI_1_DMI
AT20
=PP1V05_S0_PCH_VCC_DMI
7 22
VCCCLKDMI
AB36
PP1V05_S0_PCH_VCCCLKDMI_F
22
=PP1V8_S0_PCH_VCC_DFTERM
7 19 22
VCCDFTERM
AG16
VCCDFTERM
AG17
VCCDFTERM
AJ16
VCCDFTERM
AJ17
=PP3V3_SUS_PCH_VCC_SPI
7 22
VCCSPI
V1
7 20 22
B =PP3V3R1V5_S0_PCH_VCCSUSHDA
7 22 24
10 mA Max, 1mA Idle
C2233 0.1UF
0.1UF
10% 6.3V CERM 402
PLACE_NEAR=U1800.A22:2.54mm
T24
VCCVRM_4_CLK
BD47
=PP1V05_S0_PCH_VCCSSC
VCCSUS3_3_8_USB
DCPRTC
PP1V05_S0_PCH_VCCADPLLB_F
PPVOUT_S0_PCH_DCPSST
20% 10V 2 CERM 402
W33
PP1V05_S0_PCH_VCCADPLLA_F
22 7
0.1UF
VCCASW_19_CLK
N16
55mA Max, 5mA Idle
C2222
VCCASW_18_CLK
W31
22
22 16 7
1
VCCASW_17_CLK
W29
22
22 20 7
B
VCCASW_16_CLK
W26
PPVOUT_G3_PCH_DCPRTC
T23
B S U
VCCASW_14_CLK VCCASW_15_CLK
W24
N26
VCCSUS3_3_7_USB
VCCASW_7_CLK VCCASW_8_CLK
AC29
W23
OMIT_TABLE
=PP1V05_S0_PCH_VCC_CORE
1.44 A Max, 474mA Idle
P26
VCCIO_31_USB
MOBILE
AA19
AA31
C
VCCDSW3_3
2
20% 10V CERM 402
PLACE_NEAR=U1800.A22:2.54mm PLACE_NEAR=U1800.A22:2.54mm
A
SYNC_MASTER=J31_MLB
SYNC_DATE=06/13/2011
PAGE TITLE
PCH POWER DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
22 OF 109 SHEET
20 OF 86
1
A
8
7
6
5
4
U1800
VSS
AK38
VSS
AK4
VSS
AK42
VSS
AK46
VSS
AK8
VSS
AL16
VSS
VSS
AL17
VSS
VSS
AL19
AB39
VSS
VSS
AL2
AB4
VSS
VSS
AL21
AB43
VSS
AB5
VSS VSS
AA3 AA33 AA34 AB11 AB14
D
VSS VSS VSS
MOBILE FCBGA
(9 OF 10) VSS
VSS
AL23
VSS
VSS
AL26
AB7
VSS
VSS
AL27
AC19
VSS
VSS
AL31
AC2
VSS
VSS
AL33
AC21
VSS
VSS
AL34
AC24
VSS
VSS
AL48
VSS
AM11
VSS
AM14
VSS
VSS
AM36
AD10
VSS
VSS
AM39
AD11
VSS
VSS
AM43
VSS
VSS
AM45
VSS
VSS
AM46
VSS
VSS
AM7
AD24
VSS
VSS
AN2
AD26
VSS
VSS
AN29
AD27
VSS
VSS
AN3
AD33
VSS
VSS
AN31
AD34
VSS
VSS
AP12
AD36
VSS
VSS
AP19
AD37
VSS
VSS
AP28
AD38
VSS
VSS
AP30
AD39
VSS
VSS
AP32
VSS
AP38
VSS
AP4
VSS
AP42
VSS
AP46
VSS
VSS
AP8
VSS
VSS
AR2
AD8
VSS
VSS
AR48
AE2
VSS
VSS
AT11
VSS VSS
VSS VSS
AF12
VSS
VSS
AT22
AD14
VSS
VSS
AT26
AD16
VSS
VSS
AT28
AF16
VSS
VSS
AT30
AF19
VSS
VSS
AT32
AF24
VSS
VSS
AT34
AF26
VSS
VSS
AT39
AF27
VSS
VSS
AT42
AF29
VSS
VSS
AT46
VSS
AT7
VSS
AU24
VSS
AU30
VSS
AV11
VSS
VSS
AV16
AF5
VSS
VSS
AV20
AF7
VSS
VSS
AV24
AF8
VSS
VSS
AV30
AG19
AC33 AC34 AC48
AD12 AD13 AD19
AD4 AD40 AD42
C
VSS
AA2
AD43 AD45 AD46
VSS VSS
VSS VSS VSS VSS
AF31 AF38 AF4 AF42 AF46
B
VSS VSS VSS VSS
VSS
VSS
AV38
AG2
VSS
VSS
AV4
VSS
VSS
AV43
AG48
VSS
VSS
AV8
VSS
VSS
AW14
VSS
VSS
AW18
AH36
VSS
VSS
AW2
AH39
VSS
VSS
AW22
AH40
VSS
VSS
AW26
AH42
VSS
VSS
AW28
AH46
VSS
VSS
AW32
AH3
VSS
VSS
AW34
AJ19
VSS
VSS
AW36
AJ21
VSS
VSS
AW40
AJ24
VSS
VSS
AW48
AJ33
VSS
VSS
AY12
AJ34
VSS
VSS
AY22
VSS
VSS
AY28
AK3
7
VSS
H46
PANTHERPOINT
VSS
K18
VSS
VSS
K26
VSS
(10 OF 10)
VSS
K39
B11
VSS
VSS
VSS
K46
B15
VSS
VSS
K7
B19
VSS
VSS
L18
B23
VSS
VSS
L2
VSS
6
MOBILE FCBGA
B27
VSS
VSS
L20
B31
VSS
VSS
L26
B35
VSS
B39
VSS
L28
VSS
VSS
L36
B7
VSS
VSS
L48
F45
VSS
VSS
M12
BB12
VSS
VSS
P16
BB16
VSS
VSS
M18
BB20
VSS
VSS
M22
BB22 BB24
VSS VSS
VSS VSS
M24 M30
BB28
VSS
VSS
M32
BB30
VSS
VSS
M34
BB38
VSS
VSS
M38
BB4
VSS
VSS
M4
BB46
VSS
VSS
M42
BC14
VSS
VSS
M46
BC18
VSS
VSS
M8
BC2
VSS
VSS
N18
BC22
VSS
VSS
P30
BC26
VSS
VSS
N47
BC32
VSS
VSS
P11
BC34
VSS
VSS
P18
BC36
VSS
VSS
T33
BC40
VSS
VSS
P40
BC42
VSS
VSS
P43
BC48
VSS
VSS
P47
BD46
VSS
VSS
BD5
VSS
VSS
R2
BE22
VSS
VSS
R48
BE26
VSS
VSS
T12
BE40
VSS
VSS
T31
BF10
VSS
VSS
T37
BF12
VSS
VSS
T4
BF16
VSS
VSS
W34
BF20
VSS
VSS
T46 T47
D
P7
BF22
VSS
VSS
BF24
VSS
VSS
T8
BF26
VSS
VSS
V11
BF28
VSS
VSS
V17
BD3
VSS
VSS
V26
BF30
VSS
VSS
V27
BF38
VSS
VSS
V29
BF40
VSS
VSS
V31
BF8
VSS
VSS
V36
BG17
VSS
VSS
V39
BG21
VSS
VSS
V43
BG33
VSS
VSS
V7
BG44
VSS
VSS
W17
BG8
VSS
VSS
W19
BH11
VSS
VSS
W2
BH15
VSS
VSS
W27
BH17
VSS
VSS
W48
BH19
VSS
VSS
Y12 Y38
H10
VSS
VSS
BH27
VSS
VSS
Y4
BH31
VSS
VSS
Y42
BH33
VSS
VSS
Y46
BH35
VSS
VSS
Y8
BH39
VSS VSS VSS
VSS
BG29
D3
VSS
VSS
N24
D12
VSS
VSS
AJ3
D16
VSS
VSS
AD47
D18
VSS
D22
VSS
VSS
B43
D24
VSS
VSS
D26
VSS
VSS
BG41
D30
VSS
D32
VSS
VSS
G14
D34
VSS
VSS
H16
D38
VSS
D42
VSS
VSS
T36
BH7
A
8
U1800
VSS
AY8
C
B
BH43
AH7
AK12
VSS
AY46
AT18
AG31
AH11
AY4 AY42
AT13
AE3 AF10
1
OMIT_TABLE
PANTHERPOINT
H5 AA17
2
3
OMIT_TABLE
5
4
BE10
D8
VSS
E18
VSS
VSS
E26
VSS
VSS
BG24
G18
VSS
VSS
C22
G20
VSS
VSS
AP13
G26
VSS
VSS
M14
G28
VSS
VSS
AP3
G36
VSS
VSS
AP1
G48
VSS
VSS
BE16
H12
VSS
VSS
BC16
H18
VSS
VSS
BG28
H22
VSS
VSS
BJ28
H24
VSS
H26
VSS
H30
VSS
H32
VSS
H34
VSS
F3
VSS
3
BG22
SYNC_MASTER=J31_MLB
SYNC_DATE=06/13/2011
PAGE TITLE
PCH GROUNDS DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
23 OF 109 SHEET
21 OF 86
1
A
8
7
6
5
4
2
3
PCH VCCSUS3_3 BYPASS
L2406
=PP1V05_S0_PCH
1
2 PP1V05_S0_PCH_VCCCLKDMI_R 1
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V
0603
0
20 7
5% 1/16W MF-LF 402
1
C2484
1
20% 6.3V 2 CERM-X5R 0402-1
2 CERM 402
1UF
PLACE_NEAR=U1800.AC17:2.54mm
D
=PP3V3R1V5_S0_PCH_VCCSUSHDA 1
0.1UH
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.8V
20 7
C2441
20 7
=PP1V05_S0_PCH_VCCSSC
20% 10V 2 CERM
=PP1V05_S0_PCH_V_PROC_IO
1
C2408 1
C2406 1 0.01UF
1
10% 16V 2 X7R-CERM
20%
6.3V 2 X5R
PLACE_NEAR=U1800.BJ8:2.54mm PLACE_NEAR=U1800.BJ8:2.54mm PLACE_NEAR=U1800.BJ8:2.54mm
C2417 0.1UF
4.7UF
10% 16V
X7R-CERM 2 0402
X7R-CERM 2 0402
805
C2416 1
0.01UF
10% 16V
20%
402
0402
1
C2430
1
=PP3V3_SUS_PCH_VCC_SPI 1
PP3V3_S0_PCH_VCCA_DAC_F
5% 1/16W MF-LF 402
C2451 1
10UF
0.1UF
20%
603
20 7
10%
C
C2499 1 0.1UF
PCH VCCCORE BYPASS (PCH 1.05V CORE PWR)
20%
10V CERM 2
(PCH PCI 3.3V PWR)
20 7
=PP1V05_S0_PCH_VCC_CORE
402
1 PLACE_NEAR=U1800.AT20:2.54mm
=PP3V3_S0_PCH =PP5V_S0_PCH
D2400
5
NC
N C
=PP3V3_S0_PCH_VCC3_3_CLK 1
7
1
2
100
5% 1/16W MF-LF 402
BAT54DW-X-G
6
1
2
SOT-363
2
1UF
20
C2453
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 1 MM VOLTAGE=3.3V
C2454
10UF
0402-1
20 7
=PP3V3_SUS_PCH =PP5V_SUS_PCH
C24291 C2414
2
10
NC
5%
1/16W MF-LF 402
N C
D2400
PCH VCCADPLLA Filter
BAT54DW-X-G NEED PWR CONSTRAINT
7
=PP1V05_S0_PCH_VCCADPLL
0 2 R2460 1
C2438
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE
0.1UF
<1 MA S0-S5
1
20% 10V 2 CERM 402
CERM 2
PLACE_NEAR=U1800.M26:2.54mm
C24021 C2461 0.1UF
=PP5V_SUS_PCH_V5REFSUS 20
20% 10V
PP1V05_S0_PCH_VCCADPLLA_F
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
5% 1/16W MF-LF 402
PP5V_SUS_PCH_V5REFSUS
1
C24071 C2463 C2401 1 1UF
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
10UF 20%
6.3V 2 X5R 603
B
(PCH DPLLA PWR)
3 SOT-363
1
603
PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm
PCH V5REF_SUS Filter & Follower
4
2
1
1UF
10% 2 6.3V CERM 402
(PCH Reference for 5V Tolerance on USB)
R2404
20%
6.3V 2 X5R
=PP1V05_S0_PCH_VCCIO
1
1 mA S0-S5
1
10UF
PLACE_NEAR=U1800.T38:2.54mm PLACE_NEAR=U1800.T38:2.54mm
20
1UF
7
1UF
10% 10V 2 X5R 402
6.3V CERM-X5R 2
10% 6.3V 2 CERM 402
7
C2483 C2460
10% 6.3V 2 CERM 402
1UF
<1 MA
=PP5V_S0_PCH_V5REF
10% 10V X5R 2 402
1
PLACE_NEAR=U1800.AD21:2.54mm PLACE_NEAR=U1800.AG24:2.54mm PLACE_NEAR=U1800.AJ27:2.54mm PLACE_NEAR=U1800.AG26:2.54mm
PP3V3_S0_PCH_VCC3_3_CLK_F
0603
NEED PWR CONSTRAINT
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE
C2439 1
B
1UF
L2451
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
20%
1
C2482
10% 6.3V 2 CERM 402
10UH-0.12A-0.36OHM 1 PP3V3_S0_PCH_VCC3_3_CLK_R
5% 1/16W MF-LF 402
PP5V_S0_PCH_V5REF
PLACE_NEAR=U1800.P34:2.54mm
1
1UF
R2451
PCH V5REF Filter & Follower (PCH Reference for 5V Tolerance on PCI)
R2405
C2481
10% 6.3V 2 CERM 402
1 mA
1UF
=PP3V3_S5_PCH_VCCDSW
20 7
PCH VCC3_3 BYPASS
PLACE_NEAR=U1800.U48:2.54mm PLACE_NEAR=U1800.U48:2.54mm PLACE_NEAR=U1800.U48:2.54mm
24 7
C2469
10% 6.3V 2 CERM 402 PLACE_NEAR=U1800.AF17:2.54mm
PLACE_NEAR=U1800.T16:2.54mm
16 7
1
10% 6.3V 2 CERM 402
C2419
10% 2 6.3V CERM 402
0.01UF
16V X7R-CERM 2 0402
=PP1V05_S0_PCH_VCCIO_CLK
C2434 1UF
PLACE_NEAR=U1800.AF34:2.54mm
1UF
C2455 1
10%
16V X7R-CERM 2 0402
6.3V 2 X5R
=PP1V05_S0_PCH_VCCDIFFCLK 1
=PP1V05_S0_PCH_VCC_DMI 1
C2450 1
20 16 7
PCH VCCIO BYPASS
20 7
C
10% 2 6.3V CERM 402
20
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
C2442 1UF
PLACE_NEAR=U1800.V1:2.54mm
2
1UF
0.1UF
20 7
=PP3V3_S0_PCH_VCCADAC
C2476
6.3V 2 10% CERM 402
0402
PLACE_NEAR=U1800.AM37:2.54mm PLACE_NEAR=U1800.AM37:2.54mm PLACE_NEAR=U1800.AM37:2.54mm
7
1
PLACE_NEAR=U1800.P22:2.54mm
10% 16V 2 X7R-CERM
R2450 0
=PP3V3_SUS_PCH_VCCSUS_GPIO
C2475
10% 1UF 6.3V 2 CERM 402
402 PLACE_NEAR=U1800.AG33:2.54mm
6.3V CERM 2
20 7
0.1UF
PLACE_NEAR=U1800.P32:2.54mm
PP1V8_S0_PCH_VCCTX_LVDS_F
22UF
C2446
10% 6.3V 2 CERM 402
(PCH HD Audio 3.3V/1.5V PWR)
L2407
C2400 1
1
2 6.3V CERM 402
PCH VCCSUSHDA BYPASS
24 20 7
20
=PP1V05_S0_PCH_VCCIO_USB
PLACE_NEAR=U1800.P28:2.54mm
PLACE_NEAR=U1800.P24:2.54mm
D
2
20 7
10%
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.V24:2.54mm
0805
C2452 1UF
6.3V 2 CERM 402
20% 10V
0402
0402
1
10%
0.1UF
2 X7R-CERM
2 X7R-CERM
C2444 1UF
C2440
PLACE_NEAR=U1800.AJ16:2.54mm
C2413 10% 16V
10% 16V
C2411
1
0.1UF
0.1UF
10UF
=PP1V8_S0_PCH_VCCTX_LVDS1
(PCH USB 1.05V PWR)
1
=PP3V3_SUS_PCH_VCCSUS_USB
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE 1
7
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V8_S0_PCH_VCC_DFTERM
(PCH SUSPEND USB 3.3V PWR)
PP1V05_S0_PCH_VCCCLKDMI_F 20
2
PLACE_NEAR=U1800.AB36:2.54mm
20 16 7 20 19 7
R2415
10UH-0.12A-0.36OHM 16 7
1 PCH VCCIO BYPASS
402
1UF
20
68 mA 20 7
=PP1V05_S0_PCH_VCCASW
PLACE_NEAR=U1800.BD47:2.54MM
10% 6.3V 2 CERM 402
1
C2426 1 C2456 1 C2496 C2428 1 C2420 1UF
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
22UF 20%
6.3V CERM 2 805
1
22UF 20%
6.3V 2 CERM 805
PCH VCCADPLLB Filter 20 7
=PP3V3_S0_PCH_VCC3_3_PCI 1
20 7
=PP3V3_S0_PCH_VCC3_3_SATA
R2465 1
C2421
1
0.1UF
C2423
5% 1/16W MF-LF 402
0.1UF
10% 16V 2 X7R-CERM
0402
PLACE_NEAR=U1800.AJ2:2.54mm
10% 16V 2 X7R-CERM
0
(PCH DPLLB PWR)
PP1V05_S0_PCH_VCCADPLLB_F
2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1
C24651 C2466 0.1UF
0402
20% 2 10V CERM 402
PLACE_NEAR=U1800.BH29:2.54mm
20
PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm
69 mA
PLACE_NEAR=U1800.BF47:2.54MM
1UF
10% 6.3V 2 CERM 402
A
SYNC_MASTER=K90I_MLB 20 7
1
PCH DECOUPLING
C2424 0.1UF
20 7
DRAWING NUMBER
=PP3V3_S0_PCH_VCC3_3_GPIO
10% 16V 2 X7R-CERM
1
0402
Apple Inc.
C2486 1 C2485 0.1UF
PLACE_NEAR=U1800.V33:2.54mm
10% 25V 2 X5R 402
R
0.1UF
10% 25V 2 X5R PLACE_NEAR=U1800.AA16:2.54mm 402
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
PLACE_NEAR=U1800.T34:2.54mm
8
SYNC_DATE=02/15/2011
PAGE TITLE
=PP3V3_S0_PCH_VCC3_3_HVCMOS
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
24 OF 109 SHEET
22 OF 86
1
A
8
7
6
5 23 7
4
=PPVCCIO_S0_XDP
CRITICAL XDP_CONN 7
M-ST-SM
62
1K
D 10
IN
10
IN
10
IN
10
IN
78 9
IN
78 9
IN
78 9
IN
78 9
IN
78 19 10
45 23 17
IN
OUT
(R2560-R2563) XDP_CPU:BPM
R2560 R2561 R2562 R2563
XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>
R2564 R2565 R2566 R2567
CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>
R2500
CPU_PWRGD
0 0 0 0
1
OUT
CPU_CFG<0>
OUT
PM_PCH_SYS_PWROK
78 10
IN
78 10
IN
78 10
IN
78 10
IN
201
1/20W
MF
201
1
1/20W 1/20W
MF MF
201 201
1
78 9
IN
78 9
IN
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
201
MF
1
2 5%
1/20W
MF
201
XDP 0
1
2 5 %
1/20W
201
MF
XDP
R2501
1K
R2504
330
1
2 5%
PLACE_NEAR=U1000.B57:2.54mm
1/20W
MF
201
XDP 1
2 5%
1/20W
MF
48 23
BI
48 23
IN
78 23 10
XDP SIGNALS OUT OUT
23
OUT
23
OUT
XDP
R2520 R2521 R2522 R2523
33 33 33 33
R2524 R2525 R2526 R2527 R2528
33 33 33 33 33
1
2
33
1
2
XDP_DC0_ISOLATE_CPU_MEM_L XDP_DC1_MXM_GOOD XDP_DC2_DP_AUXCH_ISOL XDP_DC3_SATARDRVR_EN XDP_DD0_DP_GPU_TBT_SEL XDP_DD1_JTAG_ISP_TCK
R2529 R2530 R2531 R2532 R2533 R2534 R2535
33 33 33 33 33 33
XDP_DD2_AUD_IPHS_SWITCH_EN XDP_DD3_ENET_LOW_PWR
R2536 R2537
33 33
23
IN
23
OUT
23
OUT
23
OUT
XDP_FC1
OUT
23
OUT
23
IN
23
IN
23
IN
23
IN
23
IN
23
IN
23
IN
23
IN
PCH SIGNALS
XDP_DA0_USB_EXTA_OC_L XDP_DA1_USB_EXTB_OC_L XDP_DA2_USB_EXTC_OC_L XDP_DA3_USB_EXTD_OC_L XDP_DB0_USB_EXTB_OC_EHCI_L XDP_DB1_USB_EXTD_OC_EHCI_L XDP_DB2_AP_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE XDP_FC0
23
B
OBSDATA_A0 OBSDATA_A1
XDP_BPM_L<2> XDP_BPM_L<3>
OBSDATA_A2 OBSDATA_A3
CPU_CFG<10> CPU_CFG<11>
1
25
28
27
CPU_CFG<4> CPU_CFG<5>
IN
30
29
9 78
IN
9 78
OBSDATA_D2 OBSDATA_D3
CPU_CFG<6> CPU_CFG<7>
IN
9 78
IN
38
37
XDP_CPU_PWRGD XDP_CPU_PWRBTN_L
40
39
42
41
44
43
XDP_CPU_CFG<0> XDP_VR_READY
PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3
9 78
46
45
48
47
50
49
=SMBUS_XDP_SDA =SMBUS_XDP_SCL
SDA SCL
52
51
54
53
TCK1 TCK0
56
55
58
57
60
59
64
63
C2500 1 0.1UF 10%
1
C2501 0.1UF
OUT
23 18
OUT
23 18
IN
2 2
1
2
1
2 2
1
2
1
2
5%
1/20W
5%
1/20W
5%
1/20W
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L 201 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L MF 201 XDP_DB2_PCH_GPIO10_AP_PWR_EN MF 201 XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE MF 201 XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L MF
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/ 20W
MF
18
IN
18
OUT
XDP_FC1_PCH_GPIO0
18 23
IN
18 23
IN
19 23
IN
19
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L OUT 201 XDP_DC1_PCH_GPIO35_MXM_GOOD OUT 201 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOLOUT 201 XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 201 XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL OUT 201 XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK OUT
998-2516
PCH Micro2-XDP
19
23 23
23
signal path
23 23
6
1/20W
MF
201
6
2 1/20W
MF
201
6
48 23
BI
48 23
IN
19 23
62
OBSFN_A0 OBSFN_A1 OBSDATA_A0 OBSDATA_A1 OBSDATA_A2 OBSDATA_A3
TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>
OBSFN_B0 OBSFN_B1
XDP_DB0_USB_EXTB_OC_EHCI_L XDP_DB1_USB_EXTD_OC_EHCI_L
OBSDATA_B0 OBSDATA_B1
XDP_DB2_AP_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE
OBSDATA_B2 OBSDATA_B3
OUT
=SMBUS_XDP_SDA =SMBUS_XDP_SCL XDP_PCH_TCK
PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3
SDA SCL TCK1 TCK0
NC
61
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
64
63
XDP
C2580 1 0.1UF 10% 16V
X7R-CERM 2 0402
6
2
51
2
78 23 10
XDP_CPU_TRST_L
R2514
51
1/20W
MF
201
MF
201
XDP
PLACE_NEAR=U1000.H59:2.54mm
XDP
PLACE_NEAR=U1000.J58:2.54mm
1
5%
1/20W
MF
201
1
5%
XDP
1/20W
MF
D
201
PLACE_NEAR=U1000.H63:2.54mm
2
1
5%
1/20W
MF
201
XDP
PLACE_NEAR=R1841.1:2.54mm
XDP
PLACE_NEAR=R1840.1:2.54mm
1
ITPXDP_CLK100M_P
2
5% 1
5%
XDP 1
1/20W
MF
IN
201
ITPXDP_CLK100M_N
2
1/20W
MF
201
16 78
IN
16 78
IN
10 24
PLACE_NEAR=U1000.G3:2.54mm 2
CPU_RESET_L
5%
1/20W
MF
201
C Non-XDP Signals
OUT
23 16
IN
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
23 19
OUT
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
23 16
IN
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
IN
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
R2590 0 R2591 0 R2596 0 R2597 0 R2573 0 R2570 0 R2572 0 R2574 0
1
2
1
2
1
2
1
2
1
USB_EXTA_OC_L USB_EXTB_OC_L AP_PWR_EN SDCONN_STATE_CHANGE
5%
1/20W
MF
2 01
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
SATARDRVR_EN
2 5%
1
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
2 01
2
1
2
1
2 5%
1/20W
MF
42
IN
42
IN OUT
18 32 73 24
16 41
ISOLATE_CPU_MEM_L
OUT
DP_AUXCH_ISOL
OUT
16 75
OUT
67
OUT
8 19
OUT
19 24
OUT
19 24
MEM_VDD_SEL_1V5_L
201
IN
OUT
26
=PP3V3_S5_XDP 7
M-ST-SM
19 23
XDP_DA2_USB_EXTC_OC_L XDP_DA3_USB_EXTD_OC_L
TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3
51
R2513
0
23 18
J2550
19 23
OUT
XDP_DA0_USB_EXTA_OC_L XDP_DA1_USB_EXTB_OC_L
XDP_PCH_S5_PWRGD XDP_PCH_PWRBTN_L
R2512
XDP_CPU_TCK
5%
CRITICAL XDP_CONN
16 23
OUT
TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>
6 6
XDP_CPU_TMS
78 23 10
1/20W
1
16 23
19
DF40RC-60DP-0.4V
201
R2515
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DB2_PCH_GPIO10_AP_PWR_EN XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
23 19 19 23
78 23 10
2
0402
NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.
201
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH MF 20 1 XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
1/20W
IN
51
10% 2 16V X7R-CERM 23 18
1/20W
1
5%
R2511
XDP_CPU_TDI
PCH SIGNALS
18
5%
PLACE_NEAR=J2500.52:2.54mm
PLACE_NEAR=U1000.K61:2.54mm
XDP
XDP
16V X7R-CERM 2 0402
XDP XDP
2
78 23 10
ITPCLK/HOOK4 78 XDP_CPU_CLK100M_P R2516 0 ITPCLK#/HOOK5 78 XDP_CPU_CLK100M_N VCC_OBS_CD RESET#/HOOK6 78 XDP_CPURST_L 1K XDP_DBRESET_L R2505 10 23 24 78 DBR#/HOOK7 OUT NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page XDP_CPU_TDO TDO IN 10 23 78 XDP_CPU_TRST_L TRSTn OUT 10 23 78 XDP_CPU_TDI TDI OUT 10 23 78 XDP_CPU_TMS TMS OUT 10 23 78 XDP_PRESENT#
IN
23 16
7
9 78
OBSDATA_D0 OBSDATA_D1
201
6
8
9 78
IN
MF
2
A
IN
1/20W
2
5%
26
35
XDP
1
CPU_CFG<8> CPU_CFG<9>
5%
XDP 0
9 78
OBSFN_D0 OBSFN_D1
18
23
R2585
9 78
IN
18 23
5%
PLACE_NEAR=U4900.P17:2.54mm
23
36
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
23
PM_PWRBTN_L
IN
18 23
1
5%
24
33
1K
CPU_CFG<2> CPU_CFG<3>
IN
1
PLACE_NEAR=J2550.39:2.54mm
21
31
NC
IN
OBSDATA_C2 OBSDATA_C3
IN
2
1
22
34
5% MF
9 23 78 9 78
IN
2
1
17
32
R2580 1 2
IN
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
2
1
15 19
OBSDATA_B2 OBSDATA_B3
1/20W 201
51
13
18 20
XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>
XDP_CPU_TCK
CPU_CFG<0> CPU_CFG<1>
201
2
1
5% MF
OBSDATA_C0 OBSDATA_C1
20 1XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L 201
R252x, R253x, R257x and R259x should be placed where needs to split between route from PCH to J2550 and path to non-XDP signal destination.
OUT
11
9
MF
6
45 23 17
9
IN
MF MF
1
1
7
12
9
1/20W
6
1K
8 10
IN
1/ 20W 1/20W
2
1
OUT
1K
23
R2584
5
CPU_CFG<16> CPU_CFG<17>
5%
2
1
it is functional in that state, else add BOM options. - For isolated GPIOs: - ’Output’ non-XDP signals require pulls. - ’Output’ PCH/XDP signals require pulls.
ALL_SYS_PWRGD
6
OBSFN_C0 OBSFN_C1
2 5% 5%
2
1 1
1/20W 201
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3 doc id 404081. Initially, stuffing both 33 and 0 ohms and validate whether
IN
1 3
OBSDATA_B0 OBSDATA_B1
PCH/XDP Signal Isolation Notes:
73 45 24
2 4
16
OBSFN_B0 OBSFN_B1
R2510
XDP_CPU_TDO
61
XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>
R2581 1 2
(R2520-R2537)
23
XDP_BPM_L<0> XDP_BPM_L<1>
201
C 23
OBSFN_A0 OBSFN_A1
XDP 1K
R2502
78 23 9
MF
5%
2 5% 5%
PLACE_NEAR=U4900.P17:2.54mm
45 24 17
IN
5% 1/16W MF-LF 4022
14 1/20W
5%
2 2
PLACE_NEAR=U1000.C60:2.54mm
PM_PWRBTN_L
78 10
XDP_CPU_PREQ_L XDP_CPU_PRDY_L
2
1 1
(R2564-R2567) XDP_CPU:CFG
0 0 0 0
BI
78 23 10
DF40RC-60DP-0.4V
R25401
78 10
1 =PPVCCIO_S0_XDP
23 7
NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.
J2500
=PP3V3_S0_XDP NO STUFF
2
3
CPU Micro2-XDP
5
998-2516
23 19
OUT
23 19
OUT
23 19
OUT
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
R2575 R2576 R2577
0 0 0
1
2
1
2
1
2
5%
1/20W
5%
1/20W
5%
1/20W
JTAG_ISP_TCK MF 201 AUD_IPHS_SWITCH_EN_PCH MF 201 ENET_LOW_PWR_PCH MF
201
B OBSFN_C0 OBSFN_C1
XDP_FC0 XDP_FC1
23
OBSDATA_C0 OBSDATA_C1
XDP_DC0_ISOLATE_CPU_MEM_L XDP_DC1_MXM_GOOD
23
OBSDATA_C2 OBSDATA_C3
XDP_DC2_DP_AUXCH_ISOL XDP_DC3_SATARDRVR_EN
23
OBSFN_D0 OBSFN_D1
TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1>
23
23
23
7
OBSDATA_D0 OBSDATA_D1
XDP_DD0_DP_GPU_TBT_SEL XDP_DD1_JTAG_ISP_TCK
OBSDATA_D2 OBSDATA_D3
XDP_DD2_AUD_IPHS_SWITCH_EN XDP_DD3_ENET_LOW_PWR
=PP1V05_SUS_PCH_JTAG
6 6
XDP
23 16
XDP_PCH_TDO
R2550
51
2
23 16
XDP_PCH_TDI
R2551
51
2
23
23
23 16
XDP_PCH_TMS
R2552
1
5%
23
23
PLACE_NEAR=J2550.52:2.54mm
XDP
5%
51
2
TP_XDP_PCH_HOOK4 ITPCLK/HOOK4 6 XDP_PCH_TCK R2556 51 2 23 16 TP_XDP_PCH_HOOK5 ITPCLK#/HOOK5 6 VCC_OBS_CD XDPPCH_PLTRST_L 1K series R on PCH Support Page RESET#/HOOK6 IN 24 XDP_DBRESET_L DBR#/HOOK7 OUT 10 23 24 78 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page XDP_PCH_TDO TDO IN 16 23 SYNC_MASTER=J31_MLB TP_XDP_PCH_TRST_L TRSTn PAGE TITLE XDP_PCH_TDI TDI OUT 16 23 XDP_PCH_TMS TMS OUT 16 23 XDP_PRESENT#
1/20W
MF
201
PLACE_NEAR=U1800.K5:2.54mm 1
XDP
1/20W
MF
201
PLACE_NEAR=U1800.H7:2.54mm 1
5%
XDP
1/20W
MF
201
PLACE_NEAR=U1800.J3:2.54mm 1
5%
1/20W
MF
201
SYNC_DATE=06/13/2011
CPU & PCH XDP
1
Apple Inc.
XDP
C2581
R
0.1UF
10% 16V 2 X7R-CERM
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
0402
4
3
2
DRAWING NUMBER
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
25 OF 109 SHEET
23 OF 86
1
A
8
7
6
5
4
2
3
Ethernet WAKE# Isolation =PP3V3_ENET_PHY
Unbuffered
7 36 71
System RTC Power Source & 32kHz / 25MHz Clock Generator R2630
Coin-Cell:
VBAT (300-ohm &
10K
SSM3K15AMFVAPE 1
=PPVBAT_G3_SYSCLK
7
10uF
VESM
RC) 32 17 6
=PP3V3_S5_SYSCLK Coin-Cell & G3Hot:
D
D
PCIE_WAKE_L
OUT
S
3
26 18
5% 1/16W MF-LF 2402
G
No Coin-Cell: 3.42V G3Hot (no RC) 7
R2681
1
Q2630
ENET_WAKE_L
PLT_RESET_L
IN
IN
2
7
Ethernet XTAL Power
7
SB XTAL Power
7
T29 XTAL Power
7
No bypass necessary
5
C2624 1 0.1UF 10% 16V
X5R-CERM 2 0201
C2620 1
C2622 1
1
10% 16V
10% 16V
0201
0201
C2602
+V3.3A should be first
TQFN
C2605 SYSCLK_CLK25M_X2
1 5% 50V
2
NC
4
0
1
Y2605
X2
4
X1
12
25MHZ_A 9
2
1
PAD
0 6 7 1 1
0
OUT
16 81
OUT
16 81
OUT
36 81
OUT
33 81
7 1
PM_SYSRST_L
2
BI
7
Buffered
10% 2 6.3V CERM 402
5
U2680
74LVC1G07 4
NC
31
XDPPCH_PLTRST_L
OUT
23
=T29_RESET_L
OUT
35
2
BKLT_PLT_RST_L
OUT
77
=FW_RESET_L
OUT
39
Series R is R4283
C
PLT_RST_BUF_L
NC
20% 10V
1
8
C2650
7 T A1 G Y1 2 B1 8 3 5 0 A2 G Y2 6 2 B2 C V GND L 4 4 7
R2680 100K
CPU_RESET_L
5% 1/16W MF-LF 2 402
IN
36
OUT
E NE T_ ME DI A_ SE NS E
1
12K 5% 2
E NE T_ ME DI A_ SE NS E_ RD IV
OUT
16
FW_PWR_EN
OUT
R2627
30 36
24 18 7
39
CRITICAL SSM6N37FEAPE 3
=PP3V3_S3_PCH_GPIO
81 18
D
Q2610
IN
LPC_CLK33M_SMC_R
R26111
18
100K
5% 1/20W MF 2012
5 G
IN
1
8
1 PLACE_NEAR=U1800.H43:5.1mm
IN
PCH_CLK33M_PCIOUT
1
PLACE_NEAR=U1800.H40:2.54MM:5.1mm
16
IN
24 17
IN
TBT_PWR_EN_PCH PM_PCH_PWROK
23 19
IN
AUD_IPHS_SWITCH_EN_PCH
08
7 T A1 G Y1 2 8 3 5 B1 0 A2 G Y2 6 2 B2 C V GND L 4 4 7 1
R2612
20% 10V 2 CERM 402
SOT833
1
TBT_PWR_EN
OUT
35
AUD_IPHS_SWITCH_EN
OUT
62
SOT563
=PP3V3_S3_SDBUF 23
2 G
1
SDCONN_STATE_CHANGE
S 1
CRITICAL SOT665 4
Y
1
SDCONN_STATE_CHANGE_SMC 30
IN
IN
1
20% 10V
5% 1/16W MF-LF 4022
68
24 22 20 7
2 CERM 402
1
ALL_SYS_PWRGD CPUIMVP_PGOOD
2
5
100K
SPI_DESCRIPTOR_OVERRIDE_LS5V
S
3
SPI_DESCRIPTOR_OVERRIDE
4
1
Q2620
R2621
D 6
1K
5% 1/20W MF 2201
SSM6N37FEAPE SOT563
24
C2660
2 G
0.1UF
45
IN
HDA_SDOUT_R IPD = 9-50k
S 1
OUT
16 81
SPI_DESCRIPTOR_OVERRIDE_L
MC74VHC1G08 SC70-HF
U2650
4
PM_S0_PGOOD
1 2
5
R2662
MC74VHC1G08 SC70-HF
U2660 4
SYS_PWROK_R1
R2660 SMC_DELAYED_PWRGD
1
0
5% 1/16W MF-LF 402
6
3.0K
5% 1/16W MF-LF 402
3
7
R2620
5% 1/20W MF 2 201
5
D
20% 10V 2 CERM 402
3
46 45 35
1
=PP3V3R1V5_S0_PCH_VCCSUSHDA
2
=PP3V3_S5_PCHPWRGD 7
0.1UF
B
=PP5V_S0_PCH
SSM6N37FEAPE
5% 1/16W MF-LF 402
1K
16 80
G
R2663
C2600
OUT
PCH_CLK33M_PCIIN
2
5% 1/16W MF-LF 402
Q2620
46
SOT563
1
6 47 81
22 7
NO STUFF
R26501
OUT
PCH ME Disable Strap
A
3
=PP3V3_S5_PCHPWRGD =PP3V3_S0_SB_PM
45 81
5% 1/16W MF-LF 402
20% 10V 2 402 CERM
U2670 2 B
0
OUT
LPC_CLK33M_LPCPLUS
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
7
C2670 0.1UF
TC7SZ08FEAPE 5
1
2
SDCONN_STATE_CHANGE ISOLATION
D 6
ENET_MEDIA_SENSE_EN
PCH S0 PWRGD
22
SSM6N37FEAPE
0
5% 1/16W MF-LF 2 402
22
LPC_CLK33M_SMC
R2626
LPC_CLK33M_LPCPLUS_R
R2629
Q2610
C2652 0.1UF
VCC
U2652
2
5% 1/16W MF-LF 402
S 4
18
73 45 23
22
1
PLACE_NEAR=U1800.H49:5.1mm
SOT563
=PP3V3R1V5_S0_PCH_VCCSUSHDA CRITICAL
10 23
402 MF-LF 1/16W
ENET_LOW_PWR
=PP3V3_S3_PCH_GPIO
B
OUT
VTT voltage divider on CPU page
402
ENET_MEDIA_SENSE_EN_L 24 18 7
3
R2610
0.1UF
20% 10V 2 CERM 402
08
1 1
C2680 1 CERM 2
1
ENET_LOW_PWR_PCH PM_PCH_PWROK FW_PWR_EN_PCH
8
32
OUT
5% 1/16W MF-LF 402
=PP3V3_S0_RSTBUF
0.1UF
VCC
24 7
0
1
C2610
=PP3V3_S3_PCH_GPIO
SOT833
24 7
OUT
PCA9557D_RESET_L
MAKE_BASE=TRUE
U2601
IN
AP_RESET_L
Series R is R3803
SC70
CRITICAL
19
30
R2693
SILK_PART=SYS RESET
ENET_MEDIA_SENSE ISOLATION CIRCUIT
IN
2
0
5% 1/16W MF-LF 2402
2
24 18 7
24 17
OUT
5% 1/16W MF-LF 402
R2697
GPIO Glitch Prevention
IN
2
1K
1
OMIT
C0G-CERM 0402
23 19
=ENET_RESET_L
R2689
1
1UF
SYSCLK_CLK25M_X1
45
XDP
5% 1/16W MF-LF 402
17 45
NOTE: 30 PPM crystal required
5% 50V
OUT
D
2
For SB RTC Power
THRM
GND
5% 1/20W MF 2201
1
0
1
5% 1/16W MF-LF 402
SYSCLK_CLK25M_SB SYSCLK_CLK25M_ENET SYSCLK_CLK25M_T29 =PPVRTC_G3_OUT 7
VDD_RTC_OUT 1
R2606
1M
25.000MHZ-12PF-20PPM
XDP_DBRESET_L
SYSCLK_CLK32K_RTC
25MHZ_C 15
1
SM-3.2X2.5MM 3
12PF
1
C
VDDIO_25M_C
3
IN
to reduce VBAT draw.
32KHZ_A
25MHZ_B 8
SYSCLK_CLK25M_X2_R NO STUFF
2
5% 1/20W MF 201
CRITICAL
1
C0G-CERM 0402 NC
C2606
14
R2605
12PF 2
VDDIO_25M_B
23 10 78
available ~3.3V power
CRITICAL VDDIO_25M_A
6
R2696
create VDD_RTC_OUT.
SMC_LRESET_L
5% 1/16W MF-LF 402
R2671
5% 1/16W MF-LF 2402
XDP
internally ORed to
SLG3NB148A 11
10K R2695
VBAT and +V3.3A are
U2600
10% 10V 2 X5R 402-1
X5R-CERM 2
X5R-CERM 2
0
1 1
V 2 4 . 3 +
A 3 . 3 V +
1UF
0.1UF
0.1UF
2
R2688
3 1
2
M 5 2 _ D D V
81
6 47
5% 1/16W MF-LF 402
=PP3V3_S0_SB_PM
24 7
=PPVDDIO_ENET_CLK =PPVDDIO_S0_SBCLK =PPVDDIO_T29_CLK
33
1
PCH Reset Button
3.3V S5
=PP3V3_ENET_SYSCLK
OUT OUT
R2683
36
Coin-Cell & No G3Hot: 3.3V S5 GreenClk 25MHz Power
LPC_RESET_L LPCPLUS_RESET_L
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
3.42V G3Hot
No Coin-Cell:
A
33
1
MAKE_BASE=TRUE
=ENET_WAKE_L
MAKE_BASE=TRUE
2
1
Platform Reset Connections
2
S YN C_ MA ST ER =K 90 I_ ML B
PM_PCH_SYS_PWROK OUT
2
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
Chipset Support
17 23 45
PLACE_NEAR=U1800.L22:5.54mm
DRAWING NUMBER
NO STUFF 1
R2661 0
Apple Inc.
5% 1/16W MF-LF 2402
R
NOTICE OF PROPRIETARY PROPERTY:
PM_PCH_PWROK OUT
17 24
PM_PCH_APWROK OUT
17
MAKE_BASE=TRUE
5
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
26 OF 109 SHEET
24 OF 86
1
A
8
7
6
5
4
2
3
1 TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
HUB_ALLREM
HUB_NONREM1_0,HUB_NONREM0_0
HUB_1NONREM
HUB_NONREM1_0,HUB_NONREM0_1
HUB_2NONREM
HUB_NONREM1_1,HUB_NONREM0_0
HUB_3NONREM
HUB_NONREM1_1,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
USB MUX FOR LS/FS INTERNAL DEVICES D
25 7
C2700
NON_REM 1 :
BYPASS=U2700.5::2MM
BYPASS=U27000.5::5MM
=PP3V3_S3_USB_HUB
TABLE_BOMGROUP_ITEM
C2701
1
4.7UF
0.1UF
20% 6.3V X5R 603
10% 16V X7R-CERM 0402
2
C2702
1
1
2
2
1
0.1UF
0.1UF
10% 16V X7R-CERM 0402
10% 16V X7R-CERM 0402
2
C2703
0 0 1 1
NON_REM
: : : :
0
0 1 0 1
STRAP PIN CFG
D
ALL PORTS ARE REMOVABLE PORT 1 IS NON REMOVABLE PORT 1&2 ARE NON REMOVABLE PORT 1&2&3 ARE NON REMOVABLE
CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
BOM TABLE TABLE_5_HEAD
P AR T#
BYPASS=U2700.15::2MM
QTY
D ES C RI PT I ON
1
USB HUB 2514B
REFERENCE
DESIGNATOR(S)
CRITICAL
BOM OPTION
CRITICAL
USBHUB2514B
TABLE_5_ITEM
338S0824
BYPASS=U2700.10::2MM
U2700
TABLE_5_ITEM
BYPASS=U2700.23::5MM
BYPASS=U2700.23::2MM
33 8S 09 23
1
US B HU B 2 5 13 B
33 8S 09 83
1
US B HU B 2 5 12 B
U2700
CRITICAL
USBHUB2513B
CRITICAL
USBHUB2512B
TABLE_5_ITEM
C2704
C2705
1
C2706
1
C2708
1
4.7UF
0.1UF
0.1UF
0.1UF
20% 6.3V X5R 603
10% 16V X7R-CERM 0402
10% 16V X7R-CERM 0402
10% 16V X7R-CERM 0402
2
2
2
1
PPUSB_HUB2_VDD1V8 VOLTAGE=1.8V
2
5 3 9 6 1 2 2 3
4 1
T L I F R C
VDD33
BYPASS=U2650.29::2MM
Y2700 24.000M-60PPM-16PF 1 2 USB_HUB_XTAL2
C2709
1
18PF
HUB_NONREM1_1
HUB_NONREM0_1
5% 50V C0G-CERM 0402
R2702
1
1
10K 5% 1/16W MF-LF 402
2
1
2
CRITICAL
R2700
VOLTAGE=1.8V
1
2
USB_HUB_TEST
2
R2705 5% 1/16W MF-LF 402
1
2
1
0.1UF 2
10% 16V X7R-CERM 0402
2
C2712
2
1UF 10% 16V X5R 402
=PP3V3_S3_USB_HUB NOSTUFF 1
25
USB_HUB_RESET_L
11
TEST
26
RESET*
33
XTALIN/CLKIN
USB_HUB_XTAL1 USB_HUB_XTAL2_R
32
1
USBHUB_DN1_N
USBDP_DN1/PRT_DIS_P1
2
USBHUB_DN1_P
BI
8
USBDM_DN2/PRT_DIS_M2
3
USBHUB_DN2_N
BI
8
USBDP_DN2/PRT_DIS_P2
4
USBHUB_DN2_P
BI
8
USBDM_DN3/PRT_DIS_M3 SUSP_IND/LOCAL_PWR/NON_REM0 USBDP_DN3/PRT_DIS_P3
6
USBHUB_DN3_N
BI
8 25
BI
R2706
XTALOUT
USB_HUB_NONREM0 USB_HUB_NONREM1
22
SDA/SMBDATA/NON_REM1
USB_HUB_CFG_SEL0
24
SCL/SMBCLK/CFG_SEL0
USB_HUB_CFG_SEL1
25
HS_IND/CFG_SEL1
1
10K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
7
USBHUB_DN3_P
NC
8
USBHUB_DN4_N
NC
9
USBHUB_DN4_P
PRTPWR1/BC_EN1*
12
TP_USB_HUB_PRTPWR1
PRTPWR2/BC_EN2*
16
NC_USB_HUB_PRTPWR2
18
NC_USB_HUB_PRTPWR3
NC
20
NC_USB_HUB_PRTPWR4
IPU
OCS1*
13
IPU
OCS2*
17
IPU
OSC3*
19
IPU
NC
21
PRTPWR3/BC_EN3*
R2707
10K
BI
8
BLUETOOTH FOR J5 & J3X 2
28
=PP3V3_S3_USB_RESET
5% 1/16W MF-LF 402
1
NOSTUFF
R2717 10K 5% 1/16W MF-LF
2 402
1
NOSTUFF
R2718 5% 1/16W MF-LF
2 402
1
7 25
NOSTUFF
R2719 10K
10K
5% 1/16W MF-LF
C
2 402
TP/KB FOR J5, IR FOR J3X
SMC DEBUG PORT FOR J5, TP/KB FOR J3X
25 8
USBHUB_DN3_N
25 8
USBHUB_DN3_P
25
USBHUB_DN4_N
25
USBHUB_DN4_P
8 25
25
BI BI
NC FOR J5, SMC DEBUG PORT FOR J3X
25
=PP3V3_S3_USB_HUB
TP_USB_HUB_OCS1
1
NC_USB_HUB_OCS2
7 25
R2708 10K
NC_USB_HUB_OCS3 NC_USB_HUB_OCS4
RBIAS
35
VBUS_DET
27
USB_HUB_VBUS_DET
USBDM_UP
30
USB_HUB_UP_N
BI
18 80
USBDP_UP
31
USB_HUB_UP_P
BI
18 80
THRM_PAD
R2716 10K
USBDM_DN1/PRT_DIS_M1 OMIT
J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION J3X USE 197S0284 FOR Y2700 TO SAVE COST
5% 1/16W MF-LF 402
USB_HUB_RBIAS
CRITICAL
1
R2709 12K
PCH PORT 7 (EHCI1) 2
7 3
B
C2714
2
10% 16V X5R 402
2
7
1
10% 16V X7R-CERM 0402
1UF
QFN
10K
2
C2711
U2700
100 5% 1/16W MF-LF 402
2 5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
1
T L I F L L P
C2713 0.1UF
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
4 3
U2700
J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
USB2513B
R2701
5% 50V C0G-CERM 1 0402
1M 1
R2703
2
HUB_NONREM0_0
10K 5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
C2710 18PF
0
10K
HUB_NONREM1_0
R2704
1
R2710
2
C
SYM VER 1
CRITICAL 5X3.2X1.4-SM
1
2
1
PPUSB_HUB2_VDD1V8PLL 0 5 1
BYPASS=U2700.36::2MM
CRITICAL
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
1% 1/16W MF 402
B
1
R2712 10K
2
5% 1/16W MF-LF 402
USB_HUB_RESET_L
C2715
25
1
0.1UF 10% 16V X7R-CERM 0402
2
PLACE_NEAR=U2700.26:2.5MM
USB XHCI/EHCI2 PORT MUX FOR EXT B 7
=PP3V3_S3_USBMUX
C2760
1 9
0.1UF
18 80
BI
80 18
BI
PCH PORT 9 (EHCI2)
A
USB_EXTB_EHCI_P
20% 10V CERM 2 402
VCC 5
USB_EXTB_EHCI_N
4
M+
1
USB_EXTB_MUX_P
BI
43 80
Y- 2
USB_EXTB_MUX_N
BI
43 80
Y+
M-
U2760
TO CONNECTOR
PI3USB102ZLE
PCH PORT 1 (XHCI)
18 80
BI
USB_EXTB_XHCI_P
7
80 18
BI
USB_EXTB_XHCI_N
6
D+ D-
SYNC_MASTER=LINDA_J30
TQFN
CRITICAL
8
SEL 10
OE* GND 3
SYNC_DATE=09/19/2011
PAGE TITLE
PULL-UP TO 3.3V SUS ON PCH
USB HUB & MUX
PAGE, SEL PIN IS LEAKAGE-SAFE
USB_EXTB_SEL_XHCI
IN
16
DRAWING NUMBER
PCH GPIO60
Apple Inc.
SEL=0 CHOOSE USB EHCI2 PORT SEL=1 CHOOSE USB XHCI PORT
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
27 OF 109 SHEET
25 OF 86
1
A
8
7
6
5
4
2
3
1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary. ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
D
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
D
WHEN LOW:
CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN
= (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN
= (ISOLATE_CPU_MEM_L + PLT_RST_L)
1V5 S0 "PGOOD" for CPU
* PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
7
73 45 32 17 6
=PP3V3_S5_CPU_VCCDDR
PM_SLP_S4_L
IN
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page CPUMEM_S0 1
R2805
15 12 10 7
=PP1V5_S3_CPU_VCCDDR
PM_MEM_PWRGD 1
10K 5% 1/16W MF-LF 402
2
=PP3V3_S3_MEMRESET
OUT
R2820
72
R2801
D
Q2805
1% 1/16W MF-LF 402
6
SSM6N37FEAPE
1
2
1
5% 1/16W MF-LF 402
DMB53D0UV SOT-563
G
S
5
P1V5_S0_DIV
1
CPUMEM_S0
D
3
3
D
23
S
DMB53D0UV
1
1% 1/16W MF-LF 402
4
4
S
G
4
NO STUFF
1
C2820
33.2K
SOT563
1
0.001UF 20% 50V CERM 402
2
C
2
5
ISOLATE_CPU_MEM_L
IN
R2821
Q2805 SSM6N37FEAPE
S
Q2820 SOT-563
SOT563
G
CRITICAL
3
2
2
SSM6N37FEAPE
5
Q2820
SOT563
CPUMEM_S0
Q2800
D
2
P1V5CPU_EN_L
C
6
G
2
PM_MEM_PWRGD_L
100K 5% 1/16W MF-LF 402
CRITICAL
27.4K
CPUMEM_S0 CPUMEM_S0
10 17 78
10K
P1V5CPU_EN 7
OUT
R2822
PM_SLP_S3_L
IN
6 8 17 45 73
CPUMEM_S0 1
R2810 10K
2
26 7
5% 1/16W MF-LF 402
MEMVTT_EN
=PP5V_S3_MEMRESET
OUT
8
MEMVTT Clamp
CPUMEM_S0 CPUMEM_S0
R2815
1
R2802
100K 5% 1/16W MF-LF 402
D
Q2810
CPUMEM_S0
6
Ensures CKE signals are held low in S3
SSM6N37FEAPE
1
SOT563
100K 5% 1/16W MF-LF 402
2
2
2
G
S
7
1
=PPVTT_S0_VTTCLAMP CPUMEM_S0
MEMVTT_EN_L
R2850 CPUMEM_S0
CPUMEM_S0
D
Q2800
Q2815
3
6
D
SSM6N37FEAPE
SOT563
1
75mA max load @ 0.75V
10 5% 1/10W MF-LF 603
Q2810
SSM6N37FEAPE
SSM6N37FEAPE SOT563
CPUMEM_S0
SOT563
2
60mW max power 2
VTTCLAMP_L
G 2
B
D
G
S
4
1
S
G
5
S
6
26 7
=PP5V_S3_MEMRESET
CPUMEM_S0
Q2850
CPUMEM_S0
PLT_RESET_L
IN
1
18 24
R2851
D
B
6
SSM6N37FEAPE
1
SOT563
100K 5% 1/16W MF-LF 402
NOSTUFF
C2817
1
=PP1V5_S3_MEMRESET
0.047UF 10% 6.3V X5R 201
CPUMEM_S0 2
Q2815 31
5
MEMRESET_ISOL_LS5V_L
2 10
IN
=MEM_RESET_L
S
CPU_MEM_RESET_L MAKE_BASE=TRUE
1
R2816
CPUMEM_S0
5% 1/16W MF-LF 402
2
Q2850
10% 16V X7R-CERM 0402
D
3
G
S
1
MEM_RESET_L
3
OUT
20% 50V CERM 402
27 29
5
67 8
IN
G
1
0.001UF
SOT563
CPUMEM_S3
NO STUFF
C2851
SSM6N37FEAPE
D
4
2
2
VTTCLAMP_EN
C2816 0.1UF
1K
SOT563
G
7
CPUMEM_S0
CPUMEM_S0 1
SSM6N37FEAPE
S
2
4
=DDRVTT_EN
R2817 0 1
2 5% 1/16W MF-LF 402
Step
A
ISOLATE_CPU_MEM_L
PLT_RESET_L
PM_SLP_S3_L
PM_SLP_S4_L
CPU_MEM_RESET_L
MEM_RESET_L
MEMVTT_EN
P1V5CPU_EN
S0
0
to
1
0
1
1
1
1
1
1
1
2
0
0
1
1
1
1
0
1
3
0
0
0
1
X
1
0
0
S3 to S0
1
1
1
1
1
CPU_MEM_RESET_L
1
1
4
0
0
1
1
X
1
0
5
0
1
1
1
0 (*)
1
1
1
6
0
1
1
1
1
1
1
1
7
1
1
1
1
1
CPU_MEM_RESET_L
1
1
S YN C_ MA ST ER =K 90 I_ ML B
1
CPU Memory S3 Support DRAWING NUMBER
Apple Inc.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
R
NOTICE OF PROPRIETARY PROPERTY:
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition.
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
8
Rails will power-up as if from S3, but MEM_RESET_L will not properly assert.
7
6
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
Software
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
28 OF 109 SHEET
26 OF 86
1
A
8
7
6
5
4
2
3
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes 7
=PP1V5_S3_MEM_A
Power aliases required by this page: - =PP1V5_S0_ME M_A
1
- =PP1V5_S3_ME M_A
C2911
1
2
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
C2900
1
- =I2C_SODIMMA _SCL
1
20% 10V CERM 402
2
C2912
1
0.1UF 2
C2913
1
2
C2914
1
20% 10V CERM 402
2
C2915
1
0.1UF
0.1UF
0.1UF
20% 10V CERM 402
20% 10V CERM 402
2
C2916
1
2
20% 10V CERM 402
C2917
1
2
20% 10V CERM 402
C2918
1
2
20% 10V CERM 402
C2919
1
2
20% 10V CERM 402
C2920
1
2
C2921
1
20% 10V CERM 402
2
20% 10V CERM 402
C2922
1
2
20% 10V CERM 402
C2923 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
10UF
20% 6.3V X5R 603
2 BOM options provided by this page:
20% 10V CERM 402
C2901
10UF
- =I2C_SODIMMA _SDA
1
0.1UF
0.1UF
- =PP0V75_S0_ME M_VTT_A
D
C2910
2
20% 6.3V X5R 603 31
D
PP0V75_S3_MEM_VREFDQ_A
(NONE)
1
1
C2930 2.2UF
0.1UF
20%
20%
6.3V 2
C2931 10V
2
CERM 402-LF
CERM 402
OMIT_TABLE OMIT_TABLE
79 11
IN
MEM_A_CKE<0>
NC 79 11
IN
KEY
73
CKE0
CKE1
74
75
VDD
VDD
76
77
NC
A15
78
MEM_A_A<15>
A14
80
MEM_A_A<14>
79
A12/BC* A9
BA2
81 79 11
IN
MEM_A_A<12>
83
79 11
IN
MEM_A_A<9>
85
F-RT-THB
VDD
87
VDD
79 11
IN
MEM_A_A<8>
89
A8
79 11
IN
MEM_A_A<5>
91
A5
79 11
IN
MEM_A_A<3>
95
A3
79 11
IN
MEM_A_A<1>
97
A1
79 11
IN
MEM_A_CLK_P<0>
79 11
IN
MEM_A_CLK_N<0>
93
VDD
6 ) 2 K - L F A O U D 2 - M L M I O D B O M S Y - S 3 ( R D D
IN IN
28
2 4
=MEM_A_DQ<4>
DQ5
6
=MEM_A_DQ<0>
5
DQ0
BI
=MEM_A_DQ<1>
7
DQ1
9
VSS
11 79 11 79
VSS DQ4
BI
IN
CRITICAL
=MEM_A_DM<0>
11
DM0
J2900
VSS
F-RT-THB
82
13
A11
MEM_A_A<11>
IN
11 79
28
BI
=MEM_A_DQ<2>
15
DQ2
A7
86
MEM_A_A<7>
IN
11 79
28
BI
=MEM_A_DQ<3>
17
DQ3
VDD
88
A6
90
MEM_A_A<6>
IN
11 79
28
BI
A4
92
MEM_A_A<4>
IN
11 79
28
19
VSS
=MEM_A_DQ<8>
21
DQ8
BI
=MEM_A_DQ<9>
23
DQ9
VDD
94
25
VSS
A2
96
MEM_A_A<2>
IN
11 79
28
BI
=MEM_A_DQS_N<1>
27
DQS1*
A0
98
MEM_A_A<0>
IN
11 79
28
BI
=MEM_A_DQS_P<1>
29
DQS1
6 ) K 2 L A F U O D - 1 M M L I O D B O M S Y 3 S R ( D D
BI
28
=MEM_A_DQ<5>
BI
28
DQS0*
10
=MEM_A_DQS_N<0>
BI
28
DQS0
12
=MEM_A_DQS_P<0>
BI
28
DQ6
16
=MEM_A_DQ<6>
BI
28
DQ7
18
=MEM_A_DQ<7>
BI
28
VSS
VSS
8
14
VSS
20
DQ12
22
=MEM_A_DQ<12>
BI
DQ13
24
=MEM_A_DQ<13>
BI
VSS
28 28
26
DM1
28
=MEM_A_DM<1>
IN
28
RESET*
30
MEM_RESET_L
IN
26 29
31
VSS
VSS
32
CK0
102
MEM_A_CLK_P<1>
IN
11 79
28
BI
=MEM_A_DQ<10>
33
DQ10
DQ14
34
=MEM_A_DQ<14>
BI
28
CK0*
CK1*
104
MEM_A_CLK_N<1>
IN
11 79
28
BI
=MEM_A_DQ<11>
35
DQ11
DQ15
36
=MEM_A_DQ<15>
BI
28
VDD
VDD
106
37
VSS
VSS
38
BA1
108
MEM_A_BA<1>
IN
11 79
28
BI
=MEM_A_DQ<16>
39
DQ16
DQ20
40
=MEM_A_DQ<20>
BI
28
MEM_A_RAS_L
IN
11 79
28
BI
=MEM_A_DQ<17>
41
DQ17
DQ21
42
=MEM_A_DQ<21>
BI
28
43
VSS
VSS
44
VDD
VDD CK1
100
IN
MEM_A_A<10>
107
A10/AP
79 11
IN
MEM_A_BA<0>
109
BA0
RAS*
110
VDD
VDD
112
79 11
IN
MEM_A_WE_L
113
WE*
114
MEM_A_CS_L<0>
IN
11 79
28
BI
=MEM_A_DQS_N<2>
45
DQS2*
=MEM_A_DM<2>
IN
79 11
IN
MEM_A_CAS_L
115
CAS*
ODT0
116
MEM_A_ODT<0>
IN
11 79
28
BI
=MEM_A_DQS_P<2>
47
DQS2
VSS
48
117
VDD
VDD
118
49
VSS
DQ22
50
=MEM_A_DQ<22>
BI
28
79 11
IN
MEM_A_A<13>
119
A13
ODT1
120
28
BI
=MEM_A_DQ<18>
51
DQ18
DQ23
52
=MEM_A_DQ<23>
BI
28
79 11
IN
MEM_A_CS_L<1>
121
S1*
NC
122
28
BI
=MEM_A_DQ<19>
53
DQ19
VSS
54
VDD
VDD
124
55
VSS
DQ28
56
=MEM_A_DQ<28>
BI
28
=MEM_A_DQ<24>
57
DQ29
58
=MEM_A_DQ<29>
BI
28
=MEM_A_DQ<25>
59
DQ25
VSS
60
61
VSS
DQS3*
62
=MEM_A_DQS_N<3>
BI
28
DM3
DQS3
64
=MEM_A_DQS_P<3>
BI
28
125
TEST
VREFCA
VSS
VSS
128
DQ32
DQ36
130
=MEM_A_DQ<36>
BI
28
28
BI
=MEM_A_DQ<33>
131
DQ33
DQ37
132
=MEM_A_DQ<37>
BI
28
VSS
VSS
134
28
BI
=MEM_A_DQS_N<4>
135
DQS4*
DM4
=MEM_A_DM<4>
IN
28
BI
=MEM_A_DQS_P<4>
137
DQS4
VSS
138
139
VSS
DQ38
140
=MEM_A_DQ<38>
BI
28
28
BI
=MEM_A_DQ<34>
141
DQ34
DQ39
142
=MEM_A_DQ<39>
BI
28
28
BI
=MEM_A_DQ<35>
143
DQ35
VSS
144
28
BI
=MEM_A_DQ<40>
28
BI
=MEM_A_DQ<41>
IN
=MEM_A_DM<5>
145
VSS
147
DQ40
149
DQ41
151
VSS
153
BI
=MEM_A_DQ<42>
157 159
146
=MEM_A_DQ<44>
BI
28
DQ45
148
=MEM_A_DQ<45>
BI
28
VSS
150 =MEM_A_DQS_N<5>
BI
28
=MEM_A_DQS_P<5>
BI
28
DQ46
158
=MEM_A_DQ<46>
BI
28
DQ44
152
DM5
DQS5
154
VSS
VSS
156
DQ47
=MEM_A_DQ<47>
BI
28
VSS
VSS
162
163
DQ48
DQ52
164
=MEM_A_DQ<52>
BI
28
DQ49
DQ53
166
=MEM_A_DQ<53>
BI
=MEM_A_DM<6>
IN
=MEM_A_DQ<43>
BI
=MEM_A_DQ<48>
28
BI
=MEM_A_DQ<49>
28
BI
=MEM_A_DQS_N<6>
169
28
BI
=MEM_A_DQS_P<6>
171
28
BI
=MEM_A_DQ<50>
28
BI
=MEM_A_DQ<51>
=MEM_A_DQ<56>
28
BI
=MEM_A_DQ<57>
28
IN
=MEM_A_DM<7>
DQ43
165
VSS DM6
170
DQS6
VSS
172
173 175
VSS
DQ54
174
=MEM_A_DQ<54>
BI
28
DQ55
176
=MEM_A_DQ<55>
BI
28
VSS
178
VSS
DQ60
180
=MEM_A_DQ<60>
BI
28
181
DQ56 DQ57
DQ61
182
=MEM_A_DQ<61>
BI
28
VSS
184
183
187
28
BI BI
=MEM_A_DQ<59>
193
MEM_A_SA<1>
R2940 10K
2
VSS
VSS
66
BI
=MEM_A_DQ<26>
67
DQ26
DQ30
68
=MEM_A_DQ<30>
BI
28
28
BI
=MEM_A_DQ<27>
69
DQ27
DQ31
70
=MEM_A_DQ<31>
BI
28
71
VSS
VSS
72
186
=MEM_A_DQS_N<7>
BI
28
DQS7
188
=MEM_A_DQS_P<7>
BI
28
VSS
190
DQ62
192
=MEM_A_DQ<62>
BI
28
DQ63
194
=MEM_A_DQ<63>
VSS
196
DQ59 VSS
BI
200
=I2C_SODIMMA_SDA
BI
SA1
SCL
202
=I2C_SODIMMA_SCL
IN
VTT
VTT
MEM_EVENT_L
20% 10V 2
CERM
OUT
CERM 402
28
198
SDA
SA0 VDDSPD
201
31
C2936 0.1UF
6.3V 2
402-LF
EVENT*
197
1
C2935
29 45 46
"Factory" (top) slot
48 48
204
=PP0V75_S0_MEM_VTT_A
7
R2941
MF-LF
402
65 28
PP0V75_S3_MEM_VREFCA_A
1
1
1/16W
MF-LF 2
63
B
5%
1/16W
CERM
=MEM_A_DM<3>
KEY
10K
5%
6.3V
IN
20%
DQS7*
VSS
199
203
1
28
2.2UF
VSS DM7
DQ58
195 MEM_A_SA<0> 7 =PPSPD_S0_MEM_A
28
28
DQ50 DQ51
177
191
BI
DQ24
46
28
179
=MEM_A_DQ<58>
BI
DM2
C
168
VSS DQS6*
189 28
28
161
BI
28
BI
28
160
28
28
136
DQS5*
DQ42
185
20%
28
129
167
2.2UF
11 79
127
28
C2940
IN
NC
126
=MEM_A_DQ<32>
155
1
MEM_A_ODT<1>
BI
28
B
S0*
28
133
402-LF
28
84
VDD
79 11
NC
2
28
103
123
1
11 79
VSS
101
111
A
IN
VREFDQ
3
105
99
C
J2900
MEM_A_BA<2>
MEM_A_CKE<1>
1
SPD
C2950
1
1UF
ADDR=0xA0(WR)/0xA1(RD)
402
2
10% 10V X5R 402
C2951
1
1UF 2
10% 10V X5R 402
C2952
1
1UF 2
10% 10V X5R 402
C2953
SYNC_MASTER=K90I_MLB
1UF 2
10% 10V X5R 402
SYNC_DATE=02/15/2011
PAGE TITLE
DDR3 SO-DIMM Connector A DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
29 OF 109 SHEET
27 OF 86
1
A
8
7
6
CPU CHANNEL A DQS 0 -> DIMM A DQS 0 79 11
MEM_A_DQS_N<0>
79 11
MEM_A_DQS_P<0>
79 11
MEM_A_DQ<7>
79 11
MEM_A_DQ<6>
79 11
MEM_A_DQ<5>
=MEM_A_DQS_N<0> MAKE_BASE=TRUE MAKE_BASE=TRUE
79 11 79 11
MEM_A_DQ<3>
79 11
MEM_A_DQ<2>
79 11
D
MEM_A_DQ<4>
79 11
MEM_A_DQ<1> MEM_A_DQ<0>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQS_P<0>
27
79 11
MEM_B_DQS_N<0>
27
79 11
MEM_B_DQS_P<0>
79 11
MEM_B_DQ<7>
79 11
MEM_B_DQ<6>
79 11
MEM_B_DQ<5>
27
=MEM_A_DQ<3>
27
=MEM_A_DQ<6>
27
=MEM_A_DQ<1> =MEM_A_DQ<5>
27 27
79 11
MEM_B_DQ<4>
=MEM_A_DQ<2>
27
79 11
MEM_B_DQ<3>
=MEM_A_DQ<7>
27
79 11
MEM_B_DQ<2>
=MEM_A_DQ<0> =MEM_A_DQ<4>
27 27
79 11 79 11
79 11
MEM_A_DQS_P<1>
79 11
MEM_A_DQ<15>
79 11
MEM_A_DQ<14>
MAKE_BASE=TRUE MAKE_BASE=TRUE
79 11
MEM_A_DQ<13>
79 11
MEM_A_DQ<12>
79 11 79 11 79 11 79 11
MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MEM_B_DQ<1> MEM_B_DQ<0>
=MEM_A_DQS_N<1>
27
79 11
MEM_B_DQS_N<1>
=MEM_A_DQS_P<1>
27
79 11
MEM_B_DQS_P<1>
27
=MEM_A_DQ<11>
27
79 11
MEM_B_DQ<15>
=MEM_A_DQ<10>
27
79 11
MEM_B_DQ<14>
=MEM_A_DQ<12>
27
79 11
MEM_B_DQ<13>
=MEM_A_DQ<9>
27
79 11
MEM_B_DQ<12>
=MEM_A_DQ<15> =MEM_A_DQ<14> =MEM_A_DQ<13> =MEM_A_DQ<8>
79 11
MEM_A_DQS_P<2>
79 11
MEM_A_DQ<23>
MAKE_BASE=TRUE
79 11 79 11 79 11 79 11
MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19>
79 11
MEM_A_DQ<18>
79 11
MEM_A_DQ<17>
79 11
MEM_A_DQ<16>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
27 27 27 27
79 11 79 11 79 11 79 11
MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8>
=MEM_A_DQS_P<2>
27 27 27
=MEM_A_DQ<23>
27
=MEM_A_DQ<21> =MEM_A_DQ<20> =MEM_A_DQ<18>
79 11
MEM_A_DQS_P<3>
MAKE_BASE=TRUE MAKE_BASE=TRUE
79 11 79 11
79 11
MEM_B_DQS_P<2>
79 11
MEM_B_DQ<23>
27 27 27 27
79 11 79 11 79 11 79 11
MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19>
27
79 11
MEM_B_DQ<18>
=MEM_A_DQ<16>
27
79 11
MEM_B_DQ<17>
=MEM_A_DQ<17>
27
79 11
MEM_B_DQ<16>
MEM_A_DQ<31> MEM_A_DQ<30>
79 11
MEM_A_DQ<29> MEM_A_DQ<28>
MAKE_BASE=TRUE
79 11
MEM_A_DQ<27>
79 11
MEM_A_DQ<26>
79 11
MEM_A_DQ<25>
79 11
MEM_A_DQ<24>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
27
79 11
27
=MEM_A_DM<3>
27
=MEM_A_DQ<26>
27
79 11
MEM_B_DQ<31>
=MEM_A_DQ<24>
27
79 11
MEM_B_DQ<30>
27
79 11
27
79 11
MEM_B_DQ<29> MEM_B_DQ<28>
79 11
MEM_A_DQS_P<4>
79 11
MEM_A_DQ<39>
79 11
MEM_A_DQ<38>
79 11
MEM_A_DQ<37>
79 11
MEM_A_DQ<36>
79 11
MEM_A_DQ<35>
79 11
MEM_A_DQ<34>
79 11
MEM_A_DQ<33>
79 11
MEM_A_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQ<31>
27
79 11
MEM_B_DQ<27>
=MEM_A_DQ<27>
27
79 11
MEM_B_DQ<26>
=MEM_A_DQ<30>
27
79 11
MEM_B_DQ<25>
=MEM_A_DQ<29>
27
79 11
MEM_B_DQ<24>
79 11
MEM_B_DQS_P<3>
B
79 11
MEM_A_DQS_P<5>
79 11
MEM_A_DQ<47>
79 11
MEM_A_DQ<46>
MAKE_BASE=TRUE MAKE_BASE=TRUE
79 11
MEM_A_DQ<45>
79 11
MEM_A_DQ<44>
79 11
MEM_A_DQ<43>
79 11
MEM_A_DQ<42>
79 11 79 11
MEM_A_DQ<41> MEM_A_DQ<40>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
27
79 11
MEM_A_DQS_N<6> MEM_A_DQS_P<6>
79 11
MEM_A_DQ<55>
79 11
MEM_A_DQ<54>
79 11
MEM_A_DQ<53>
79 11
MEM_A_DQ<52>
79 11
MEM_A_DQ<51>
MAKE_BASE=TRUE MAKE_BASE=TRUE
79 11
MEM_A_DQ<50>
79 11
MEM_A_DQ<49>
79 11
MEM_A_DQ<48>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
27
79 11
MEM_B_DQS_P<4>
=MEM_A_DM<4>
27
=MEM_A_DQ<38>
27
79 11
MEM_B_DQ<39>
=MEM_A_DQ<39>
27
79 11
MEM_B_DQ<38>
=MEM_A_DQ<37>
27
79 11
MEM_B_DQ<37>
=MEM_A_DQ<33>
27
79 11
MEM_B_DQ<36>
=MEM_A_DQ<34>
27
79 11
MEM_B_DQ<35>
=MEM_A_DQ<35>
27
79 11
MEM_B_DQ<34>
=MEM_A_DQ<32>
27
79 11
MEM_B_DQ<33>
=MEM_A_DQ<36>
27
79 11
MEM_B_DQ<32>
79 11
A
79 11
MEM_A_DQ<63>
79 11
MEM_A_DQ<62>
MAKE_BASE=TRUE MAKE_BASE=TRUE
79 11
MEM_A_DQ<61>
MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQS_N<5>
27
79 11
MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58>
79 11
MEM_A_DQ<57>
79 11
MEM_A_DQ<56>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQS_P<5>
27
79 11
MEM_B_DQS_P<5>
=MEM_A_DM<5>
27
=MEM_A_DQ<46>
27
79 11
MEM_B_DQ<47>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DQ<43>
27
79 11
MEM_B_DQ<46>
=MEM_A_DQ<45>
27
79 11
=MEM_A_DQ<41>
27
79 11
=MEM_A_DQ<47>
27
79 11
MEM_B_DQ<43>
=MEM_A_DQ<42>
27
79 11
MEM_B_DQ<42>
27
79 11
=MEM_A_DQ<40> =MEM_A_DQ<44>
MAKE_BASE=TRUE MAKE_BASE=TRUE
27
79 11
MEM_B_DQ<45> MEM_B_DQ<44>
MEM_B_DQ<41> MEM_B_DQ<40>
29
=MEM_B_DQ<7>
29
=MEM_B_DQ<6>
29
=MEM_B_DQ<5>
29
=MEM_B_DQ<1>
29
=MEM_B_DQS_N<1>
29
=MEM_B_DQS_P<1>
29
D
=MEM_B_DM<1>
29
=MEM_B_DQ<15>
29
=MEM_B_DQ<14>
29
=MEM_B_DQ<13>
29
=MEM_B_DQ<8>
29
=MEM_B_DQ<11>
29
=MEM_B_DQ<10>
29
=MEM_B_DQ<12>
29
=MEM_B_DQ<9>
29
=MEM_B_DQS_N<2>
29
=MEM_B_DQS_P<2>
29
=MEM_B_DM<2>
29
=MEM_B_DQ<23>
29
=MEM_B_DQ<18>
29
=MEM_B_DQ<16>
29
=MEM_B_DQ<17>
29
=MEM_B_DQ<22>
29
=MEM_B_DQ<19>
29
=MEM_B_DQ<21>
29
=MEM_B_DQ<20>
29
=MEM_B_DQS_N<3>
29
=MEM_B_DQS_P<3>
29
=MEM_B_DM<3>
29
C
=MEM_B_DQ<26>
29
=MEM_B_DQ<30>
29
=MEM_B_DQ<28> =MEM_B_DQ<29>
29 29
=MEM_B_DQ<27>
29
=MEM_B_DQ<31>
29
=MEM_B_DQ<25>
29
=MEM_B_DQ<24>
29
=MEM_B_DQS_N<4>
29
=MEM_B_DQS_P<4>
29
=MEM_B_DM<4>
29
=MEM_B_DQ<38>
29
=MEM_B_DQ<39>
29
=MEM_B_DQ<33>
29
=MEM_B_DQ<37>
29
=MEM_B_DQ<34>
29
=MEM_B_DQ<35>
29
=MEM_B_DQ<32>
29
=MEM_B_DQ<36>
29
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQS_N<5>
29
=MEM_B_DQS_P<5>
29
=MEM_B_DM<5>
29
=MEM_B_DQ<43>
29
=MEM_B_DQ<46>
29
=MEM_B_DQ<40>
29
=MEM_B_DQ<45>
29
=MEM_B_DQ<47>
29
=MEM_B_DQ<42>
29
=MEM_B_DQ<41> =MEM_B_DQ<44>
B
29 29
MAKE_BASE=TRUE
CPU CHANNEL B DQS 6 -> DIMM B DQS 6
=MEM_A_DQS_N<6>
27
79 11
MEM_B_DQS_N<6>
=MEM_A_DQS_P<6>
27
79 11
MEM_B_DQS_P<6>
27
=MEM_A_DQ<51>
27
79 11
MEM_B_DQ<55>
=MEM_A_DQ<54>
27
79 11
MEM_B_DQ<54>
=MEM_A_DQ<49>
27
79 11
MEM_B_DQ<53>
79 11
MEM_B_DQ<52>
79 11
MEM_B_DQ<51>
=MEM_A_DQ<53> =MEM_A_DQ<50>
27 27
=MEM_A_DQ<55>
27
79 11
MEM_B_DQ<50>
=MEM_A_DQ<48>
27
79 11
MEM_B_DQ<49>
=MEM_A_DQ<52>
MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<6>
27
79 11
MEM_B_DQ<48>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQS_N<6>
29
=MEM_B_DQS_P<6>
29
=MEM_B_DM<6>
29
=MEM_B_DQ<54>
29
=MEM_B_DQ<55>
29
=MEM_B_DQ<53>
29
=MEM_B_DQ<49>
29
=MEM_B_DQ<51>
29
=MEM_B_DQ<50>
29
=MEM_B_DQ<48>
29
=MEM_B_DQ<52>
29
MAKE_BASE=TRUE
CPU CHANNEL B DQS 7 -> DIMM B DQS 7
=MEM_A_DQS_N<7> =MEM_A_DQS_P<7> =MEM_A_DM<7> =MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<60>
27
79 11
27
79 11
MEM_B_DQS_N<7> MEM_B_DQS_P<7>
MAKE_BASE=TRUE MAKE_BASE=TRUE
27 27 27
79 11 79 11
MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61>
27
79 11
27
79 11
27
79 11
MEM_B_DQ<60> MEM_B_DQ<59>
27
79 11
MEM_B_DQ<58>
MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQS_N<7> =MEM_B_DQS_P<7> =MEM_B_DM<7> =MEM_B_DQ<56> =MEM_B_DQ<59> =MEM_B_DQ<61>
29 29
S YN C_ MA ST ER =K 90 I_ ML B
29
DDR3 Byte/Bit Swaps
29
=MEM_A_DQ<62>
DRAWING NUMBER
29 29
=MEM_A_DQ<61>
27
79 11
MEM_B_DQ<57>
=MEM_A_DQ<56>
27
79 11
MEM_B_DQ<56>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_B_DQ<60> =MEM_B_DQ<63>
29
=MEM_B_DQ<58>
29
=MEM_B_DQ<57>
29
=MEM_B_DQ<62>
29
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
MAKE_BASE=TRUE
Ivybridge does not use DM signals per doc 460452 CR SFF DG Section 2.6.14
8
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
29
SIZE
MAKE_BASE=TRUE
=MEM_A_DQ<57> =MEM_A_DQ<63>
MAKE_BASE=TRUE
NOTE:
MAKE_BASE=TRUE
MEM_B_DQS_N<5>
MAKE_BASE=TRUE
79 11
29
=MEM_B_DQ<4>
CPU CHANNEL B DQS 5 -> DIMM B DQS 5
79 11
79 11
29
=MEM_B_DQ<0>
MAKE_BASE=TRUE
CPU CHANNEL A DQS 7 -> DIMM A DQS 7 MEM_A_DQS_N<7> MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
MAKE_BASE=TRUE
MEM_B_DQS_N<4>
=MEM_A_DQS_P<4>
CPU CHANNEL A DQS 6 -> DIMM A DQS 6 79 11
29
=MEM_B_DQ<2>
CPU CHANNEL B DQS 4 -> DIMM B DQS 4
MAKE_BASE=TRUE
79 11
29
=MEM_B_DQ<3>
MAKE_BASE=TRUE
CPU CHANNEL A DQS 5 -> DIMM A DQS 5 MEM_A_DQS_N<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
MAKE_BASE=TRUE
29
=MEM_B_DM<0>
MAKE_BASE=TRUE
=MEM_A_DQ<28> =MEM_A_DQ<25>
=MEM_A_DQS_N<4> MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<3>
=MEM_A_DQS_P<3>
CPU CHANNEL A DQS 4 -> DIMM A DQS 4 MEM_A_DQS_N<4>
MAKE_BASE=TRUE
29
=MEM_B_DQS_P<0>
CPU CHANNEL B DQS 3 -> DIMM B DQS 3
MAKE_BASE=TRUE
79 11
MAKE_BASE=TRUE
=MEM_B_DQS_N<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE 79 11
MAKE_BASE=TRUE
MEM_B_DQS_N<2>
=MEM_A_DQ<19>
=MEM_A_DQS_N<3>
MEM_A_DQS_N<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DM<2> =MEM_A_DQ<22>
79 11
CPU CHANNEL A DQS 3 -> DIMM A DQS 3 79 11
1
CPU CHANNEL B DQS 2 -> DIMM B DQS 2
MAKE_BASE=TRUE
C
2
MAKE_BASE=TRUE
=MEM_A_DQS_N<2> MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DM<1>
CPU CHANNEL A DQS 2 -> DIMM A DQS 2 MEM_A_DQS_N<2>
3
CPU CHANNEL B DQS 1 -> DIMM B DQS 1
MAKE_BASE=TRUE
79 11
4
MAKE_BASE=TRUE
CPU CHANNEL A DQS 1 -> DIMM A DQS 1 MEM_A_DQS_N<1>
MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<0>
MAKE_BASE=TRUE
79 11
5
CPU CHANNEL B DQS 0 -> DIMM B DQS 0
7
6
5
4
3
2
051-9058 6.0.0
REVISION
D
BRANCH
PAGE
30 OF 109 SHEET
28 OF 86
1
A
8
7
6
5
4
2
3
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes 7
=PP1V5_S3_MEM_B
Power aliases required by this page: -
=PP1V5_S0_MEM_B
-
=PP1V5_S3_MEM_B
1
2
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
Signal aliases required by this page: -
=I2C_SODIMMB_SCL
-
=I2C_SODIMMB_SDA
C3100
1
1
C3111
1
C3112
1
0.1UF
20% 10V CERM 402
2
2
C3113
1
0.1UF
20% 10V CERM 402
2
C3114
1
2
C3115
1
0.1UF
0.1UF
20% 10V CERM 402
20% 10V CERM 402
2
C3116
1
2
20% 10V CERM 402
C3117
1
20% 10V CERM 402
2
C3118
1
2
20% 10V CERM 402
C3119
1
2
20% 10V CERM 402
C3120
1
2
C3121
1
C3122
20% 10V CERM 402
2
20% 10V CERM 402
1
2
20% 10V CERM 402
C3123 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20% 10V CERM 402
2
20% 10V CERM 402
10UF
20% 6.3V X5R 603
BOM options provided by this page:
1
0.1UF
20% 10V CERM 402
C3101
10UF 2
D
C3110 0.1UF
- =PP0V75_S0_M EM_VTT_B
2
20% 6.3V X5R 603 31
D
PP0V75_S3_MEM_VREFDQ_B
(NONE)
1
1
C3130
0.1UF
2.2UF
20%
20%
10V
6.3V 2
C3131
2
CERM
CERM 402
402-LF
OMIT_TABLE OMIT_TABLE
79 11
MEM_B_CKE<0>
IN
NC
KEY
73
CKE0
CKE1
74
75
VDD
VDD
76
77
NC BA2
79 11
IN
MEM_B_BA<2>
79
79 11
IN
MEM_B_A<12>
83
MEM_B_A<9>
85
81
79 11
IN
VDD
A14 VDD
F-RT-BGA6
A9 VDD
M ) 2 M I D F O O S 2 3 ( R D D
=MEM_B_DM<0>
11
DM0
J3100
13
VSS
F-RT-BGA6
BI
=MEM_B_DQ<2>
15
DQ2
=MEM_B_DQ<3>
17
MEM_B_A<7>
IN
11 79
28
BI
88
DQ3
19
VSS
M ) M 2 I D O F S O - 3 1 R ( D D
BI
28
=MEM_B_DQ<5>
BI
28
DQS0*
10
=MEM_B_DQS_N<0>
DQS0
12
8
BI
28
=MEM_B_DQS_P<0>
BI
28
VSS
14
DQ6
16
=MEM_B_DQ<6>
BI
28
DQ7
18
=MEM_B_DQ<7>
BI
28
VSS
20
DQ12
22
=MEM_B_DQ<12>
BI
DQ13
24
=MEM_B_DQ<13>
BI
28
=MEM_B_DM<1>
IN
28
30
MEM_RESET_L
IN
26 27
A6
90
MEM_B_A<6>
IN
11 79
28
BI
=MEM_B_DQ<8>
21
DQ8
A4
92
MEM_B_A<4>
IN
11 79
28
BI
=MEM_B_DQ<9>
23
DQ9
25
VSS
VSS
26
96
MEM_B_A<2>
IN
11 79
28
BI
=MEM_B_DQS_N<1>
27
DQS1*
DM1
98
MEM_B_A<0>
IN
11 79
28
BI
=MEM_B_DQS_P<1>
29
DQS1
RESET*
VDD
94
IN
MEM_B_A<3>
95
A3
A2
79 11
IN
MEM_B_A<1>
97
A1
A0
79 11
IN
MEM_B_CLK_P<0>
79 11
IN
MEM_B_CLK_N<0>
31
VSS
VSS
32
101
CK0
102
MEM_B_CLK_P<1>
IN
11 79
28
BI
=MEM_B_DQ<10>
33
DQ10
DQ14
34
=MEM_B_DQ<14>
103
CK0*
CK1*
104
MEM_B_CLK_N<1>
IN
11 79
28
BI
=MEM_B_DQ<11>
35
DQ11
DQ15
36
105
VDD
VDD
106
37
VSS
VSS
38
VDD
VDD
CK1
100
28 28
BI
28
=MEM_B_DQ<15>
BI
28
BA1
108
MEM_B_BA<1>
IN
11 79
28
BI
=MEM_B_DQ<16>
39
DQ16
DQ20
40
=MEM_B_DQ<20>
BI
28
BA0
RAS*
110
MEM_B_RAS_L
IN
11 79
28
BI
=MEM_B_DQ<17>
41
DQ17
DQ21
42
=MEM_B_DQ<21>
BI
28
VDD
VDD
112
43
VSS
VSS
44
DM2
46
79 11
IN
MEM_B_A<10>
107
A10/AP
79 11
IN
MEM_B_BA<0>
109
79 11
IN
MEM_B_WE_L
113
WE*
114
MEM_B_CS_L<0>
IN
11 79
28
BI
=MEM_B_DQS_N<2>
45
DQS2*
=MEM_B_DM<2>
IN
79 11
IN
MEM_B_CAS_L
115
CAS*
ODT0
116
MEM_B_ODT<0>
IN
11 79
28
BI
=MEM_B_DQS_P<2>
47
DQS2
VSS
48
117
VDD
VDD
118
49
VSS
DQ22
50
=MEM_B_DQ<22>
BI
28
79 11
IN
MEM_B_A<13>
119
A13
ODT1
120
28
BI
=MEM_B_DQ<18>
51
DQ18
DQ23
52
=MEM_B_DQ<23>
BI
28
79 11
IN
MEM_B_CS_L<1>
121
S1*
NC
122
28
BI
=MEM_B_DQ<19>
53
DQ19
VSS
54
VDD
VDD
124
55
VSS
DQ28
56
=MEM_B_DQ<28>
BI
28
=MEM_B_DQ<24>
57
DQ29
58
=MEM_B_DQ<29>
BI
28
=MEM_B_DQ<25>
59
DQ25
VSS
60
61
VSS
DQS3*
62
=MEM_B_DQS_N<3>
BI
28
DM3
DQS3
64
=MEM_B_DQS_P<3>
BI
28
125
S0*
VREFCA
TEST
MEM_B_ODT<1>
IN
11 79
NC
126
28
127
VSS
VSS
128
28
BI
=MEM_B_DQ<32>
129
DQ32
DQ36
130
=MEM_B_DQ<36>
BI
28
28
BI
=MEM_B_DQ<33>
131
DQ33
DQ37
132
=MEM_B_DQ<37>
BI
28
VSS
VSS
134
28
BI
=MEM_B_DQS_N<4>
135
DQS4*
=MEM_B_DM<4>
IN
28
BI
=MEM_B_DQS_P<4>
137
DQS4
VSS
138
139
VSS
DQ38
140
=MEM_B_DQ<38>
BI
28
28
BI
=MEM_B_DQ<34>
141
DQ34
DQ39
142
=MEM_B_DQ<39>
BI
28
28
BI
=MEM_B_DQ<35>
143
DQ35
VSS
144
28
BI
=MEM_B_DQ<40>
28
BI
=MEM_B_DQ<41>
DQ40
149
DQ41 VSS
153
IN
=MEM_B_DM<5>
BI
=MEM_B_DQ<42>
157 159
DM4
VSS
147
151
146
=MEM_B_DQ<44>
BI
28
148
=MEM_B_DQ<45>
BI
28
150 =MEM_B_DQS_N<5>
BI
28
=MEM_B_DQS_P<5>
BI
28
DQ46
158
=MEM_B_DQ<46>
BI
28
=MEM_B_DQ<47>
BI
28
=MEM_B_DQ<52>
BI
28
152
DM5
DQS5
154
VSS
VSS
156
DQ47
VSS
VSS
162
163
DQ48
DQ52
164
DQ49
DQ53
=MEM_B_DQ<43>
BI
=MEM_B_DQ<48>
28
BI
=MEM_B_DQ<49>
28
BI
=MEM_B_DQS_N<6>
169
28
BI
=MEM_B_DQS_P<6>
171
28
BI
=MEM_B_DQ<50>
28
BI
=MEM_B_DQ<51>
DQ43
165
BI
=MEM_B_DQ<56>
28
BI
=MEM_B_DQ<57>
28
IN
=MEM_B_DM<7>
VSS DM6
170
DQS6
VSS
172
173
28
175
DQ54
174
=MEM_B_DQ<54>
BI
28
DQ55
176
=MEM_B_DQ<55>
BI
28
VSS
178
VSS
DQ60
180
=MEM_B_DQ<60>
BI
28
181
DQ56 DQ57
DQ61
182
=MEM_B_DQ<61>
BI
28
VSS
184
183
187
BI
=MEM_B_DQ<59>
193
MEM_B_SA<1>
10K
R3141 10K
5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
2
402
65
VSS
VSS
66
28
BI
=MEM_B_DQ<26>
67
DQ26
DQ30
68
=MEM_B_DQ<30>
BI
28
28
BI
=MEM_B_DQ<27>
69
DQ27
DQ31
70
=MEM_B_DQ<31>
BI
28
71
VSS
VSS
72
KEY
B
186
=MEM_B_DQS_N<7>
BI
28
DQS7
188
=MEM_B_DQS_P<7>
BI
28
VSS
190
DQ62
192
=MEM_B_DQ<62>
BI
28
DQ63
194
=MEM_B_DQ<63>
VSS
196
DQ59 VSS
197
SA0 VDDSPD
201
=I2C_SODIMMB_SDA
BI
SCL
202
=I2C_SODIMMB_SCL
IN
VTT
204
MTG PIN
MTG PIN
206
MTG PIN
MTG PIN
MTG PINS
0.1UF
207 209
MTG PIN MTG PIN
MTG PIN
210
MTG PIN
212
MEM_EVENT_L
20%
6.3V 2
OUT
31
C3136 10V
2
CERM
CERM 402
28
200
205
211
BI
198
SDA
VTT
1
C3135
402-LF
EVENT*
SA1
PP0V75_S3_MEM_VREFCA_B
1
20%
DQS7*
VSS
199
203
R3140
63
2.2UF
VSS DM7
DQ58
195
1
=MEM_B_DM<3>
28
VSS
BI
IN
28
DQ50 DQ51
177
191
MEM_B_SA<0>
BI
IN
179
=MEM_B_DQ<58>
7 =PPSPD_S0_MEM_B
=MEM_B_DQ<53>
=MEM_B_DM<6>
BI
DQ24
168
VSS DQS6*
189 28
166
BI
C
28
28
28
VSS
161
BI
28
28
DQ45
DQ44
160
28
28
136
DQS5*
DQ42
185
2
IN
28
A7
167
20%
28
11 79
79 11
28
CERM
11 79
A5
155
6.3V
VSS
VSS
IN
91
28
402-LF
9
CRITICAL
IN
MEM_B_A<5>
145
2.2UF
BI
DQ1
IN
IN
133
C3140
=MEM_B_DQ<4>
6
DQ0
7
MEM_B_A<11>
79 11
NC
2
4
5
=MEM_B_DQ<1>
MEM_B_A<14>
A8
123
1
2
DQ5
=MEM_B_DQ<0>
82
86
89
111
A
VSS DQ4
BI
80
84
MEM_B_A<8>
99
1
28 11 79
IN
VDD
28
11 79
VSS
MEM_B_A<15>
A11 VDD
IN
VREFDQ
3
78
79 11
93
B
J3100
A12/BC*
87
C
A15
MEM_B_CKE<1>
1
27 45 46 48
"Expansion" (bottom) slot 48
=PP0V75_S0_MEM_VTT_B
7
208 1
C3150
1
1UF 2
10% 10V X5R 402
C3151
1
1UF 2
10% 10V X5R 402
C3152
1
1UF 2
10% 10V X5R 402
C3153
S YN C_ MA ST ER =K 90 I_ ML B
1UF 2
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
10% 10V X5R 402
DDR3 SO-DIMM Connector B DRAWING NUMBER
SPD
Apple Inc.
ADDR=0xA4(WR)/0xA5(RD) R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
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REVISION
SIZE
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31 OF 109 SHEET
29 OF 86
1
A
8
7
6
5
4
2
3
1
SD Card Connector 516-0225 CRITICAL
J3300
SD-CARD-K19-K24 F-RT-TH
CRITICAL
L3300
3
47NH-1.3OHM
82 36
BI
82 36
BI
SDCONN_CLK SDCONN_CMD SDCONN_DATA<0> SDCONN_DATA<1>
BI
SDCONN_DATA<2>
82 36 82 36
D
82 36
IN OUT
82 36
BI
82 36
BI
SDCONN_DATA<3> SDCONN_DATA<4>
82 36
BI
SDCONN_DATA<5>
82 36
BI
R3379 R3361 R3371 R3372 R3373 R3374 R3375 R3376 R3377
BI
SDCONN_DATA<6> SDCONN_DATA<7>
30
OUT
SDCONN_CARDDETECT_L
36
OUT
82 36
33
1
2
5%
1 /1 6W
M F- LF 402
33 33
1
2 5 %
1 /1 6W
MF-LF 402
1
2 5 %
1 /1 6W
MF-LF 402
33
1
2 5 %
1 /1 6W
M F- LF 402
SDCONN_CLK_R SDCONN_CMD_R SDCONN_R_DATA<0> SDCONN_R_DATA<1>
33 33
1
2 5 %
1 /1 6W
M F- LF 402
1
2
1 /1 6W
M F- LF 402
1
2 5 %
33 33 33 33
R3378
1
6
2
5
SDCONN_CLK_R_L
2
0402
7
SDCONN_R_DATA<2>
9
DAT2
1 10
1 /1 6W
M F- LF 402
2 5 %
1 /1 6W
M F- LF 402
SDCONN_R_DATA<5>
11
1
2
1/16W
MF-LF 402
SDCONN_R_DATA<6> SDCONN_R_DATA<7>
12
2 5 %
5%
1 /1 6W
M F- LF 402
13 14 15
SDCONN_WP
16 4
=PP3V3_S0_SW_SD_PWR
30
CMD
DAT1
1
1
CLK
NOSTUFF 1
Place near attr for series resistors:
NOSTUFF
C3373
1
10PF
PLACE_NEAR=U3900.21:5MM 2
1
10PF
5%
PLACE_NEAR=U3900.26:5MM PLACE_NEAR=U3900.25:5MM
NOSTUFF
C3375
2
COG-CERM 0201
1
2
C3381
1
50V
2
COG-CERM 0201
1
NOSTUFF
17
C3370
18
15PF
19
50V
20
5%
5%
5%
50V
C3371 22PF
10PF
5%
50V
COG-CERM 0201
NOSTUFF
NOSTUFF
C3379 10PF
5%
50V
2
COG-CERM 0201
1
10PF
5%
50V
NOSTUFF
C3377
2
COG-CERM 0201
50V
2
CERM 0402
CERM
D
DAT0
8
SDCONN_R_DATA<3> SDCONN_R_DATA<4>
5%
VSS VSS
CD/DAT3 DAT4 DAT5 DAT6 DAT7
SD Not Inserted, CARD_DETECT is OPEN.
CARD_DETECT_SW
CAESAR-IV Card Detect is programmable,
CARD_DETECT_GND WRITE_PROTECT_SW
but a Silicon bug makes the active high case unusable.
VDD
SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
402
PLACE_NEAR=U3900.24:5MM PLACE_NEAR=U3900.23:5MM PLACE_NEAR=U3900.22:5MM
NOSTUFF
PLACE_NEAR=U3900.52:5MM
1
PLACE_NEAR=U3900.53:5MM
NOSTUFF
C3372
PLACE_NEAR=U3900.55:5MM
1
10PF
5%
2
NOSTUFF
C3374
1
10PF
PLACE_NEAR=U3900.54:5MM
COG-CERM 0201
NOSTUFF 1
2
COG-CERM 0201
NOSTUFF
C3378
1
10PF
5%
50V
2
C3376 10PF
5%
50V
2
COG-CERM 0201
C3380 10PF
5%
50V
5%
50V
2
COG-CERM 0201
50V
COG-CERM 0201
C
C SD Detect & Reset Logic SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit Converts SDCONN from active-low level signal to active-high pulses.
=PP3V3_S4_SD_HPD
7
Must STUFF R3312 and NOSTUFF R3314 when R3311 is NOT STUFFED. R3314 and R3312 mutually exclusive
C3310
1 0 1
1UF
R3311 and R3310 mutually exclusive
10% 10V X5R 2
to control effect of =ENET_RESET_L
1
CRITICAL
10K
VDD
5% 1/16W MF-LF
402-1
on DET_CHANGED# logic.
U3311 TDFN
IN
ENET_LOW_PWR
24
IN
=ENET_RESET_L
2
R3311 -> From PCH GPI0
1
0
3
RST_IN*
7
DET_IN (IPU)
402 30
B
IN
R3314
RST
SLG_ENET_RESET_OUT_L
RST_OUT*
4
DET_CH_EN*
6
SD_DET_CH_EN_L
9
8
1
DLY
R O X
(OD)
0
ENET_RESET_L
2
OUT
36 82
SDCONN_STATE_CHANGE_SMC
OUT
24 46
SDCONN_DETECT_L
OUT
36
LOGIC
SLG_ENET_RESET_IN_L
2
5% 1/16W MF-LF
-> From SD Conn
LOW_PWR
402
2
SLG4AP026V 36 24
to bypass reset logic
R3315
5% 1/16W MF-LF
402
-> To Isolation Circuit (then to PCH GPIOi) & SMC
DET_CHNGD*
SDCONN_CARDDETECT_L SD_DET_LVL_L
(Low active) 1
1
R3310 5% 1/16W MF-LF
2
402
10K
GND
5% 1/16W MF-LF
5
DET_OUT
THRM
1
PAD
R3317
1
B
2
NOSTUFF
R3312 0
10K
1 1
402
2
-> To ENET Chip
DET_LVL
R3316
10K
(OD)
R O X
1
5% 1/16W MF-LF
5% 1/16W MF-LF
402
402
2
DLY block is 20ms nominal
NOSTUFF When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms regardless ofmove RST_IN# state. Otherwise RST_OUT# follows RST_IN#
SD Card 3.3V Overcurrent Protection TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.
CRITICAL =PP3V3_S0_SW_SD_PWR
U3300
30
TPS2065-1 7
36
=PP3V3_S0_SDCARD
2
IN0
3
IN1
4
ENET_CR_PWREN
A
DGN
C3300
1
10UF 20%
2
6.3V
X5R 603
2
C3301
GND
0.1UF
1
10% 16V
X7R-CERM 0402
6
OUT1
7
OUT2
8
OC*
5
EN
CRITICAL 1
OUT0
THRM
PP3V3_S0_SW_SD_PWR
353S3004
1
10UF
PAD
9
C3302
C3303
1
6.3V
2
X5R 603
=PP3V3_S0_PCH_GPIO
5% 1/16W MF-LF
10% 16V X7R-CERM 0402
R3300 47K
0.1UF
20% 2
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
NOSTUFF
CRITICAL 1
2
SYNC_MASTER=YONAS_J30 7 16 17 18 19
SD Card Connector
R3301
DRAWING NUMBER
10K 5% 1/16W MF-LF
Apple Inc.
402 2
R
R3302 SDCONN_OC_L_R
1
0
2
NOTICE OF PROPRIETARY PROPERTY: SDCONN_OC_L
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
5% 1/16W MF-LF
402
8
7
6
SYNC_DATE=11/03/2011
PAGE TITLE
1
402
5
4
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REVISION
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NOTE: Must not enable more than two SO-DIMM margining 7
=PP3V3_S3_VREFMRGN
buffers at once or VRef source may be overloaded. VREFDQ:LDO_DAC
OMIT
R3418 1
SHORT
67 7
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
NONE NONE NONE 402
C3400
1
1
20% 6.3V CERM 402-LF
D
C3401
DDRVREF_DAC
0.1UF 2
2
C3403
CRITICAL
20% 10V CERM 402
VDD
48
BI
=I2C_VREFDACS_SCL
6 SCL
=I2C_VREFDACS_SDA
7 SDA 9 A0
Addr=0x98(WR)/0x99(RD)
MSOP
4 7 5 5 C A D
10 A1
VOUTA
1
VREFMRGN_SODIMMA_DQ
VOUTB
2
VREFMRGN_SODIMMB_DQ
VOUTC
4
VREFMRGN_SODIMMS_CA
VOUTD
5
NONE NONE NONE 402
both at the same time!
1
DDRVREF_DAC 1
R3401
DDRVREF_DAC
48
BOM options provided by this page:
48
IN BI
VREFMRGN_DQ_SODIMMB_BUF
1
PCA9557 DDRVREF_DAC
(OD) P0
6
A0
P1
7
VREFMRGN_DQ_SODIMMA_EN
4
A1
P2
9
VREFMRGN_DQ_SODIMMB_EN
5
A2
P3 P4
10
VREFMRGN_CA_SODIMMA_EN
P5
12
VREFMRGN_MEMVREG_EN
=I2C_PCA9557D_SCL
1
SCL
P6
13
VREFMRGN_FRAMEBUF_EN
=I2C_PCA9557D_SDA
2
SDA
P7
14
RESET*
THRM
VREFDQ:LDO - LDO outputs sent to DQ inputs. VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
PAD
GND
7
8
NC
R3402
2
VREFMRGN_CA_SODIMMB_EN
11
1
100K
CRITICAL
5% 1/16W MF-LF 402
DDRVREF_DAC
C3404
DDRVREF_DAC
1 A2
20% 10V CERM 402
NC
MAX4253
V+
A1 A3
15
VREFMRGN_CA_SODIMMA_BUF
1
B4
PP0V75_S3_MEM_VREFCA_A
27
C
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
2
PLACE_NEAR=R3409.2:1mm
VREFCA:LDO_DAC
R3411 1
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs. 24
IN
PCA9557D_RESET_L
R3407
RST* on ’platform reset’ so that system watchdog will disable margining.
DDRVREF_DAC
100K
NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.
2
C2
MAX4253
V+
C3
VREFMRGN_CA_SODIMMB_BUF
1
Q3420
1
G
SOT563
S
PPCPU_MEM_VREFDQ_A
2
1
PLACE_NEAR=R3411.2:1mm
DDRVREF_DAC
R3421
1
1K
10% 16V X7R-CERM 0402
2
1% 1/16W MF-LF 402
R3408
DDRVREF_DAC
100K
2
D
PP0V75_S3_MEM_VREFDQ_A
C3405
5% 1/16W MF-LF 402
CRITICAL
1
DDRVREF_DAC
0.1UF 20% 10V CERM 402
27 31
6
1
29
VREFDQ:M1_M3
C3420 0.1UF
SSM6N15AFE 2
PP0V75_S3_MEM_VREFCA_B MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
2
1% 1/16W MF-LF 402
C4
VB4
MEMRESET_ISOL_LS5V_L
133
PLACE_NEAR=Q3420.6:1mm
PLACE_NEAR=Q3420.6:2mm VREFDQ:M1_M3
CRITICAL VREFDQ:M1_M3
PLACE_NEAR=J3100.126:2.54mm
R3412
UCSP
C1
=PPDDR_S3_MEMVREF
2
VREFCA:LDO_DAC
U3403
B1
5% 1/16W MF-LF 402
200 1% 1/16W MF-LF 402
CRITICAL
DDRVREF_DAC 1
B
133 1% 1/16W MF-LF 402
A4
V-
PLACE_NEAR=J2900.126:2.54mm
R3410
UCSP
2
2
VREFCA:LDO_DAC
U3403
B1
0.1UF
200 1% 1/16W MF-LF 402
VREFCA:LDO - LDO outputs sent to CA inputs.
9
PLACE_NEAR=R3405.2:1mm
R3409
1
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
31 26
29 31
1
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
31 7
PP0V75_S3_MEM_VREFDQ_B MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
2
VREFCA:LDO_DAC
3
- Stuffs Apple margining circuit.
133 1% 1/16W MF-LF 402
C4
V-
2
R3406
UCSP
U3401
Addr=0x30(WR)/0x31(RD)
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA =I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
MAX4253
B4
QFN
Signal aliases required by this page:
C3
DDRVREF_DAC
VCC
20% 10V 2 CERM 402
200 PLACE_NEAR=J3100.1:2.54mm
VREFDQ:LDO_DAC
U3402
B1 C2
CRITICAL 6 1
1
0.1UF
D
PLACE_NEAR=R3403.2:1mm
1% 1/16W MF-LF 402
CRITICAL
C1
C3402
27 31
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V
2
R3405
a DAC output, cannot enable
V+
DDRVREF_DAC
PP0V75_S3_MEM_VREFDQ_A
133 1% 1/16W MF-LF 402
A4
V-
PP3V3_S3_VREFMRGN_CTRL MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
- =PP3V3_S3_VREFMRGN - =PPVTT_S3_DDR_BUF - =PPDDR_S3_MEMVREF
DDRVREF_DAC
1
VREFDQ:LDO_DAC
5% 1/16W MF-LF 2 402
Power aliases required by this page:
C
VREFMRGN_DQ_SODIMMA_BUF
B4
R3419
-
A1 A3
OMIT
2
PLACE_NEAR=J2900.1:2.54mm
R3404
UCSP
100K
SHORT
2
VREFDQ:LDO_DAC
MAX4253
V+
VREFMRGN_MEMVREG_FBVREF
3
Page Notes
U3402
B1 A2 2
NOTE: MEMVREG and FRAMEBUF share
GND
1
1
20% 10V CERM 402
U3400
200 1% 1/16W MF-LF 402
DDRVREF_DAC
0.1UF
DDRVREF_DAC 8
IN
1
CRITICAL
DDRVREF_DAC
DDRVREF_DAC 2.2UF
48
R3403
=PPVTT_S3_DDR_BUF
10mA max load
PP3V3_S3_VREFMRGN_DAC
2
V+
MAX4253 C1
C3
R3422
C4
VREFMRGN_MEMVREG_BUF
1
PLACE_NEAR=R7320.2:1mm
V-
1K
PLACE_NEAR=R3421.2:1mm
R3414
UCSP
VREFDQ:M1_M3 1
DDRVREF_DAC
U3404
B1 C2
2
B4
33.2K
2
DDRREG_FB
OUT
B
67
1% 1/16W MF-LF 402
1% 1/16W MF-LF 2 402
31 7
PLACE_NEAR=Q3420.3:2mm
VREFDQ:M1_M3
G
1
SOT563 2
9
S
PPCPU_MEM_VREFDQ_B
4
1
VREFDQ:M1_M3
Q3420 SSM6N15AFE 5
MEMRESET_ISOL_LS5V_L
1K
0.1UF
1% 1/16W MF-LF 402
2
1
1
5% 1/16W MF-LF 402
2
1
R3417
PART NUMBER
0
V2
B4
5% 1/16W MF-LF 402
MEM B VREF DQ
1
1% 1/16W MF-LF 402
2
R3415 100K
MEM B VREF CA
MEM A VREF CA
C
C
3
4
0.75V (DAC: 0x3A)
RES,MTL
FILM,0,5%,0402,SM,LF
116S0004
2
RES,MTL
FILM,0,5%,0402,SM,LF
4
114S0171
2
GPU Frame Buffer (1.8V, 70% VRef)
CRITICAL
BOM OPTI ON VREFDQ:LDO
R3403,R3405
VREFCA:LDO
R3409,R3411
RES,MTL RES,MTL
REFERENCE DES
FILM,1K,1%,0402,SM,LF
R3421,R3422,R3441,R3442
FILM,332,1%,0402,SM,LF
R3404,R3406
CRITICAL
BOM OPTI ON
VREFDQ:M1_DAC
VREFDQ:M1_DAC
SYNC_MASTER=J31_MLB
DDR3/FRAMEBUF VREF MARGINING DRAWING NUMBER
Apple Inc.
1.267V (DAC: 0x8B)
R
0.300V - 1.200V (+/- 450mV)
1.000V - 2.000V (+/- 500mV)
1.056V - 1.442V (+/- 180mV)
DAC range:
0.000V - 1.501V (0x00 - 0x74)
0.000V - 3.000V (0x00 - 0x74)
0.000V - 3.300V (0x00 - 0xFF)
VRef current:
+3.4mA - -3.4mA (- = sourced)
+61uA -
-61uA (- = sourced)
+6.0mA - -5.0mA (- = sourced)
DAC step size:
/ step @ output
8
7
4
1.51mV / step
SYNC_DATE=06/13/2011
PAGE TITLE
6
5 1.5V (DAC: 0x3A)
5
DESCRIPTION
D
D
8.59mV
QTY
114S0218
Margined target:
6
REFERENCE DES
5% 1/16W MF-LF 402
MEM VREG
7.69mV / step @ output
DESCRIPTION
2
VREFMRGN_FRAMEBUF_BUF_R
DDRVREF_DAC
R3442
B
QTY
116S0004
PART NUMBER
2
PCA9557D Pin: Nominal value
A1 A4
29 31
1K
A
Required zero ohm resistors when no VREF margining circuit stuffed
DDRVREF_DAC 1
UCSP
VREFDQ:M1_M3
2
MEM A VREF DQ
U3404 MAX4253
3
PLACE_NEAR=R3441.2:1mm
DAC Channel:
V+
A3
PP0V75_S3_MEM_VREFDQ_B 1
A
5% 1/16W MF-LF 402
B1 A2
2
VREFMRGN_MEMVREG_FBVREF_R
D
DDRVREF_DAC
R3413 100K
0
R3441
C3440 10% 16V X7R-CERM 0402
CRITICAL
R3416
VREFDQ:M1_M3
VREFMRGN_FRAMEBUF_BUF
DDRVREF_DAC
DDRVREF_DAC
PLACE_NEAR=Q3420.3:1mm
CRITICAL
31 26
NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step DDR3L (1.35V) 6.99mV per step
=PPDDR_S3_MEMVREF
NOTICE OF PROPRIETARY PROPERTY:
@ output
3
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
34 OF 109 SHEET
31 OF 86
1
A
8
7
6
5
4
2
3
1
PLACE_NEAR=J3501.15:2.54mm
C3531 1 2
PCIE_AP_R2D_C_P IN PCIE_AP_R2D_C_N IN
0.1UF
1 10%
2
1 0% 0.1UF
1X5R-CERM 6V 0201
16 81 16 81
1 X5R-CERM 6V 0201
C3530 PLACE_NEAR=J3501.17:2.54mm
D
D
R3510 0
1 5%1/20W
2
PCIE_AP_D2R_P PCIE_AP_D2R_N
MF 201
R3511
1 5%1/20W
R3500 6
1 AP_TEMP_SMB_SDA_R
0
5%1/16W
=AP_TEMP_SMB_SDABI
2 MF-LF 402
0
2
OUT
16 81
OUT
16 81
3V S3 WLAN FET
MF 201
1 AP_TEMP_SMB_SCL_R
0
5%1/16W
WIFI_EVENT_L_R
1 5%1/16W
0
P-TYPE
RDS(ON)
=AP_TEMP_SMB_SCLIN
2 MF-LF 402
20-30 MOHM @2.5V
LOADING
0.727 A (EDP)
48
R3502 6
TPCP8102
CHANNEL
48
R3501 6
MOSFET
CRITICAL WIFI_EVENT_L
2 MF-LF 402
OUT
Q3550
45 46
DMP2018LFK DFN2563-6 155S0367
FERR-120-OHM-3A 32 PP3V3_WLAN_F PP3V3_WLAN 1 2
606 MA NOMINAL MAX 81 6
PCIE_AP_R2D_P
46 6
MIN_NECK_WIDTH=0.4 mm MIN_LINE_WIDTH=1 mm
L3504
727 MA PEAK
D
C
81 6
C3522
PCIE_AP_R2D_N
1
0.1uF
J3501
81 6
PCIE_AP_D2R_PI_P
F-ST-SM
81 6
PCIE_AP_D2R_PI_N
31
C3520
3
402
20% 2 10V X5R 805
CRITICAL
1
R3550
P3V3WLAN_SS
2
33K
1
5% 1/16W MF-LF 2 402
PM_WLAN_EN_L
2
IN
73
5% 1/16W
10% 16V X5R 402-1
DLP11S
C
10K
10% 16V 2 X5R 402
0.1UF
AIRPORT
330-OHM-80MA L3501
R3551
0.033UF
C3550
32
1
C3551 1
PLACE_NEAR=Q3550.6:2.54mm
PLACE_NEAR=J3501.29:2.54mm
500913-0302 32
10V CERM 2
402
1
10UF
20%
10V CERM 2
CRITICAL
1
0.1uF
20%
516S0582
=PP3V3_S3_WLAN 7
G
C3521
1
2
S
4
MIN_LINE_WIDTH=1 mm 0603 MIN_NECK_WIDTH=0.2 mm
MF-LF 402
SYM_VER-1
2
1
4
3
85 6
6
5
85 6
8
7
12
11
14
13
16
15
18
17
10
PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N
4
3
PCIE_CLK100M_AP_P
IN
16 81
1
2
PCIE_CLK100M_AP_N
IN
16 81
PLACE_NEAR=J3501.11:2.54mm
9
20
PP3V3_S3RS4_BT_F 6
BLUETOOTH
19
22
21
80 6
24
23
80 6
26
25
28
30 34
27 29
32 6
PP3V3_S3RS4_BT_F
MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm
1
C3532 0.01UF
10% 16V 2 X7R-CERM
33
B
0402
1
R35181
R3517 15K
USB_BT_CONN_P USB_BT_CONN_N
1
VCC
L3505 BTPWR:S4 2
1
=PP3V3_S4_BT
15K
L3506 BTPWR:S3 1
=PP3V3_S3_BT
Y+
2
Y-
NOSTUFF
10 SEL
15K
M- 4
TQFN
D+ 7
BTPWR:S4
D- 6
USB_BT_P USB_BT_N
BI
8 80
BI
8 80
8
OE*
IN
1 PM_SLP_S4_L
5% 1/20W MF 201
2
1
G
R3512 1R3513 15K
15K
1% 1/20W MF 2201
1% 1/20W MF 2 201
Delay = 60 ms +/- 20%
C3511 1
= PP 3V 3 3_ _ S3 _ _W W LA N
32
SEL
OUTPUT 1
0.01UF
L
USB_BT_WAKE
16V X7R-CERM 2 0402
H
USB_BT
R3553 100K
1% 1/16W MF-LF 2 402
7 32
CRITICAL 1
1
R3554
VDD
232K
1% 1/16W MF-LF 2 402
U3540
0.1uF
+ -
518S0815 6
C3540
20% 10V 2 CERM 402
TDFN 0.7V
6 17 24
1
SLG4AP016V
P3V3WLAN_VMON 2
SENSE
OUT
DLY
AP_RESET_CONN_L
4 RESET*
CRITICAL
AP_RESET_L
MR* 3
J3502
819Q-3506-K281 6
8 6
6 5 4
80 6
3
A
80 6
2
PP5V_S3_ALSCAMERA_F =I2C_ALS_SCL =I2C_ALS_SDA USB_CAMERA_CONN_P USB_CAMERA_CONN_N
AP_CLKREQ_Q_L
IN BI
48
R3555
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=J3502.6:2.54MM
L3507 90-OHM
2 3
USB_CAMERA_P
BI
18 80
1
2
USB_CAMERA_N
BI
18 80
1
1
DRAWING NUMBER
=PP5V_S3_ALSCAMERA 7
Apple Inc.
C3552
R
0.1uF
PLACE_NEAR=J3502.2:2.54MM
5
SYNC_DATE=02/15/2011
X19/ALS/CAMERA CONNECTOR
0402-LF
4
6
16
PAGE TITLE
FERR-120-OHM-1.5A
SYM_VER-1 DLP0NS
7
5
SYNC_MASTER=K90I_MLB
L3508
CAMERA
CRITICAL
9
18 23 73
AP_CLKREQ_L
1% 1/16W MF-LF 2 402
206 mA nominal max
ALS
7
GND
100K
275 mA peak
48
PAD
24
IN OUT
(OD)
THRM 1
1
8
OUT 8
7 IN
IN
AP_PWR_EN
EN 6
F-RT-SM1
B
Supervisor & CLKFREG # ISolation
P P3 V V3 3 _W L LA AN N_ _F BTMUX_SEL NOSTUFF 10%
PCIE_WAKE_L
S 2
NOSTUFF
1
0
73 45 26 17 6
PLACE_NEAR=J3501.27:2.54mm
VESM
1% 1/20W MF 2201
USB_BT_WAKEP USB_BT_WAKEN
3
R3519
0402-LF
R3514
GND
BTPWR:S4
7
U3510
CRITICAL
1% 1/20W MF 2201
FERR-120-OHM-1.5A
M+ 5
46
OUT
D 3SSM3K15AMFVAPE
1
PI3USB102ZLE
15K
1% 1/20W MF 2201
0402-LF PLACE_NEAR=J3501.27:2.54mm
2
1
R3515 1R3516
7
FERR-120-OHM-1.5A
C3510
10% 6.3V 2 X5R 201
9
5% 1/20W MF 2012
Q3510
NOSTUFF
0.1UF
0
1% 1/20W MF 2201
NOSTUFF 1
BTPWR:S4 =BT_WAKE_L CRITICAL
32
BTPWR:S3
NOSTUFF
NOTICE OF PROPRIETARY PROPERTY:
20% 10V 2 CERM 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
35 OF 109 SHEET
32 OF 86
1
A
8
7
6
5
4
2
3
1
CRITICAL 81 8
IN
PCIE_T29_R2D_C_P<0>
C3600
81 8
IN
PCIE_T29_R2D_C_N<0>
C3601
1
81 8
IN
PCIE_T29_R2D_C_P<1>
10%
1
81 8
IN
PCIE_T29_R2D_C_N<1>
C3602
10%
PCIE_T29_R2D_C_P<2>
10%
1
81 8
IN
PCIE_T29_R2D_C_N<2>
C3604
10%
1
C3605
81 8
IN
PCIE_T29_R2D_C_P<3>
C3606
IN
PCIE_T29_R2D_C_N<3>
C3607
16V
X5R-CERM 0201
16V
X5R-CERM 0201
16V
X5R-CERM 0201
16V
X5R-CERM 0201
81 81
2
10%
1
81 81
2
10%
0.1UF 81 8
V19
PCIE_T29_R2D_P<0> PCIE_T29_R2D_N<0>
T19
PER_0_P
U3600
PET_0_P
T29
PET_0_N
PER_0_N
V21
81
T21
81
C3640
PCIE_T29_D2R_C_P<0> PCIE_T29_D2R_C_N<0>
1
2
10%
0.1UF 1
16V
X5R-CERM 0201
16V
X5R-CERM 0201
81 81
2
10%
0.1UF
P19
PCIE_T29_R2D_P<1> PCIE_T29_R2D_N<1>
M19
K19
PCIE_T29_R2D_P<2> PCIE_T29_R2D_N<2>
H19
F19
PCIE_T29_R2D_P<3> PCIE_T29_R2D_N<3>
D19
PER_1_N
E V I E C E R
PER_2_P PER_2_N
PER_3_P
PET_1_P T I M S N A R T
PET_1_N
P21 M21
81 81
C3642
PCIE_T29_D2R_C_P<1> PCIE_T29_D2R_C_N<1>
0.1UF
C3643
6
R36901 3.3K
5% 1/16W MF-LF 4022
1
R3691 3.3K
5% 1/16W MF-LF 2 402
C3690 1 1UF
R36921
R36231
5% 1/16W MF-LF 4022
5% 1/16W MF-LF 402 2
3.3K
10%
6.3V 2 CERM 402
8
CRITICAL OMIT_TABLE
10K
1
R3622 10K
PET_2_P PET_2_N
K21
81
H21
81
C3644
PCIE_T29_D2R_C_P<2> PCIE_T29_D2R_C_N<2>
PET_3_P
PER_3_N
PET_3_N
F21
81
D21
81
0.1UF
C3645
B21
TP_TBT_MONDC0
A20
TP_TBT_MONDC1
MONDC0
WAKE*
C
(T29_SPI_MOSI)
D
(T29_SPI_CLK)
6
C
U3690
(T29_SPI_MISO)
S_L
3
W_L
T29ROM_HOLD_L
7
HOLD_L
0.1UF
C3647
PERST*
OUT
R3693 3.3K
83
83
9
51
F1
1
0.1UF
C3621
1
0.1UF 83 8
IN
DP_T29SNK0_ML_C_P<1>
C3622
1
0.1UF
83 8
B
IN
DP_T29SNK0_ML_C_N<1>
C3623
1
0.1UF
2
DP_T29SNK0_ML_P<0>
33 83
DP_T29SNK0_ML_N<0>
33 83
2
83 33
5% 1/16W MF-LF 4022
10% 16V X5R-CERM 0201
83 33 83 33
83 33
10% 16V X5R-CERM 0201
83 33
DP_T29SNK0_ML_P<1>
2
83 33
33 83
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201
83 33
DP_T29SNK0_ML_N<1>
33 83 83 33 83 33
83 8
IN
DP_T29SNK0_ML_C_P<2>
C3624
1
0.1UF
83 8
C3625
IN
DP_T29SNK0_ML_C_N<2>
IN
DP_T29SNK0_ML_C_P<3>
C3626
IN
DP_T29SNK0_ML_C_N<3>
C3627
1
0.1UF 83 8
1
0.1UF
83 8
1
0.1UF 83 8
BI
DP_T29SNK0_AUXCH_C_P
C3628
BI
DP_T29SNK0_AUXCH_C_N
C3629
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201
DP_T29SNK0_ML_P<2>
33 83
8
E6
T29_RESET_L
E14
T29_RSENSE
IN
DP_T29SNK0_ML_N<2>
33 83
R36301 100K
DP_T29SNK0_ML_P<3>
33 83
DP_T29SNK0_ML_N<3>
33 83
1
0.1UF
2
10% 16V X5R-CERM 0201
5% 1/16W MF-LF 402 2
DP_T29SNK0_AUXCH_N
2
IN
83 8
IN
DP_T29SNK1_ML_C_N<0>
83 8
IN
DP_T29SNK1_ML_C_P<1>
C3632
83 8
IN
DP_T29SNK1_ML_C_N<1>
C3633
0.1UF
C3631
1
0.1UF 1
0.1UF 1
0.1UF
A
83 8
IN
DP_T29SNK1_ML_C_P<2>
C3634
1
0.1UF
83 8
IN
DP_T29SNK1_ML_C_N<2>
C3635
1
0.1UF 1
83
8
IN
DP_T29SNK1_ML_C_P<3>
83 8
IN
DP_T29SNK1_ML_C_N<3>
C3636 0.1UF C3637 1 0.1UF
83 8
BI
DP_T29SNK1_AUXCH_C_P
C3638
83 8
BI
DP_T29SNK1_AUXCH_C_N
C3639
1
0.1UF 1
0.1UF
8
10% 16V X5R-CERM 0201 2
33 83
2
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201
33 83
33 83
DP_T29SNK1_ML_N<1>
33 83
DP_T29SNK1_ML_P<2>
OUT
5% 1/16W MF-LF 402
83 75
OUT
83 75
OUT
83 75
IN
83 75
IN
2
75 33 83
OUT IN
33 83 83 75
2
OUT
8 81
PCIE_T29_D2R_N<1>
OUT
8 81
PCIE_T29_D2R_P<2>
OUT
8 81
PCIE_T29_D2R_N<2>
OUT
8 81
OUT
8 81
OUT
8 81
10%
16V
2
10%
X5R-CERM 0201
16V
2
10%
X5R-CERM 0201
16V
2
10%
X5R-CERM 0201
16V
2
X5R-CERM 0201
PCIE_T29_D2R_P<3>
10%
16V
X5R-CERM 0201
PCIE_T29_D2R_N<3>
2
10%
16V
X5R-CERM 0201
=PP3V3_T29_RTR 2 5%
1/20W
MF
7 33 34 35
201
35
1
E16
2
T29_RBIAS
THERM_DP
PCIE_CLKREQ_2* PCIE_CLKREQ_3*
EE_CS*
TEST_EN
P5
TEST_POINT_0 TEST_POINT_1
M5
TEST_POINT_2
L6
TEST_POINT_3
T E S E R N O R E W O P
C S I M
M O R P E E
E4 N6
T S E U Q E R K L C
K1
PCIE_RST_1*
J2
PCIE_RST_2* PCIE_RST_3* TDI G A T J
TMS TCK TDO
REFCLK_100_IN_P S K C O L C
T R O P T S E T
PCIE_RST_0*
Not used in host mode. TP_T29_PCIE_RESET0_L TP_T29_PCIE_RESET1_L TP_T29_PCIE_RESET2_L TP_T29_PCIE_RESET3_L
K3 J4 T3
JTAG_TBT_TDI JTAG_TBT_TMS JTAG_TBT_TCK JTAG_TBT_TDO
R4 R2 T1
PCIE_CLK100M_T29_P
H17 G16
REFCLK_100_IN_N XTAL_25_IN XTAL_25_OUT TMU_CLK_OUT TMU_CLK_IN
P17 R16 U2 E2
81
PCIE_CLK100M_T29_N SYSCLK_CLK25M_T29_R TP_T29_XTAL25OUT
6 6 6 6
IN
8 19
IN
16
IN
8
OUT
8
IN
16 81
IN
16 81
=PP3V3_T29_RTR
C
7 33 34 35
1
R3698 10K
5% 1/16W MF-LF
2 402
R3695 806 1
R36961
T29_TMU_CLK_OUT T29_TMU_CLK_IN
1K
2
SYSCLK_CLK25M_T29
DP_T29SNK1_ML_P<3>
2
DP_T29SNK1_ML_N<3>
2
10% 16V X5R-CERM 0201 2
10% 16V X5R-CERM 0201
OUT
83 75
OUT
83 75
IN
83 75
IN
33 83
DP_T29SNK1_AUXCH_P
33 83
DP_T29SNK1_AUXCH_N
33 83
7
IN
24 81
1% 1/16W MF-LF 402
5% 1/16W MF-LF 4022
NO STUFF
DP_T29SNK0_ML_P<3> DP_T29SNK0_ML_N<3>
AA4
DP_T29SNK0_ML_P<2> DP_T29SNK0_ML_N<2>
AA6
DP_T29SNK0_ML_P<1> DP_T29SNK0_ML_N<1>
AA8
DP_T29SNK0_ML_P<0> DP_T29SNK0_ML_N<0>
AA10 Y9
DPSNK0_ML_LANE_0N
DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N
V1
DPSNK0_AUX_CHP
W2
DPSNK0_AUX_CHN
Y3
Y5
Y7
V5
V9
DP_T29SNK1_ML_P<0> DP_T29SNK1_ML_N<0>
U10
U12 V15 U14
DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N
V7
DP_T29SNK1_HPD
U4
T29_R2D_C_P<0> T29_R2D_C_N<0>
A6
T29_D2R_P<0> T29_D2R_N<0>
C4
T29_LSEO<0> T29_LSOE<0>
J6
U6
5% 1/16W MF-LF 4022
DPSNK0_ML_LANE_3P DPSNK0_ML_LANE_3N DPSNK0_ML_LANE_2P DPSNK0_ML_LANE_2N DPSNK0_ML_LANE_1P DPSNK0_ML_LANE_1N DPSNK0_ML_LANE_0P
0 T R O P K N I S
Y A L P S I D
DPSNK1_ML_LANE_3P DPSNK1_ML_LANE_3N DPSNK1_ML_LANE_2P
DPSNK1_ML_LANE_1P DPSNK1_ML_LANE_1N DPSNK1_ML_LANE_0P DPSNK1_ML_LANE_0N
DPSRC0_ML_LANE_3N
0 T R O P E C R U O S
DPSNK0_HOT_PLUG_DET
DPSNK1_ML_LANE_2N
DPSRC0_ML_LANE_3P
AA18 Y17
DPSRC0_ML_LANE_2P
AA16
DPSRC0_ML_LANE_2N
Y15
DPSRC0_ML_LANE_1P DPSRC0_ML_LANE_1N DPSRC0_ML_LANE_0P DPSRC0_ML_LANE_0N
AA14 Y13
AA12 Y11
TP_DP_T29SRC_ML_CP<3> TP_DP_T29SRC_ML_CN<3> TP_DP_T29SRC_ML_CP<2> TP_DP_T29SRC_ML_CN<2> TP_DP_T29SRC_ML_CP<1> TP_DP_T29SRC_ML_CN<1> TP_DP_T29SRC_ML_CP<0> TP_DP_T29SRC_ML_CN<0>
6 6
6 6
B
6 6
6 6
W16
DPSRC0_AUX_CHP DPSRC0_AUX_CHN DPSRC0_HOT_PLUG_DET
1 T R O P K N I S
DP_ATEST DP_RES_0 DP_RES_1
U16
TP_DP_T29SRC_AUXCH_CP TP_DP_T29SRC_AUXCH_CN
V3
DP_T29SRC_HPD
Y19
T29_DP_ATEST
6 6
100pF SRF > 40MHz BYPASS=U3600.Y19::2mm BYPASS=U3600.Y19::5.08mm
Y21
AA20
C3685
T29_DP_RES
1
1
14.0K
DPSNK1_AUX_CHP
1% 1/16W MF-LF 402 2
DPSNK1_AUX_CHN DPSNK1_HOT_PLUG_DET
1
R3632 100K
2
5% 50V CERM 2 0402
C3686 0.01UF
100PF
R36851
10% 16V
2 X7R-CERM
0402
5% 1/16W MF-LF 402
A4
C2
K5 A10
T29_R2D_C_P<1> T29_R2D_C_N<1>
A8
PRT2_T29T_P
PRT0_T29T_P PRT0_T29T_N 0 T R PRT0_T29R_N O P
PRT0_T29R_P
T29_0_LSEO T29_0_LSOE PRT1_T29T_P
S T R O P
2 T R O P
PRT2_T29T_N PRT2_T29R_P PRT2_T29R_N T29_2_LSEO T29_2_LSOE
A14 A12 C12 C10 G4
T29_R2D_C_P<2> T29_R2D_C_N<2> T29_D2R_P<2> T29_D2R_N<2>
OUT
8 83
OUT
8 83
IN
8 83
IN
8 83
T29_LSEO<2> T29_LSOE<2>
OUT
8
IN
8
OUT
8 83
A16
T29_R2D_C_P<3> T29_R2D_C_N<3>
OUT
8 83
C16 C14
T29_D2R_P<3> T29_D2R_N<3>
IN
8 83
IN
8 83
G2
T29_LSEO<3> T29_LSOE<3>
H3
SYNC_MASTER=K90I_MLB
PRT1_T29T_N
PRT3_T29T_N
6
75
OUT
75
IN
83 48
BI
83 48
OUT
T29_D2R_P<1> T29_D2R_N<1>
C8 C6
PRT1_T29R_P
T29_LSEO<1> T29_LSOE<1>
G6
T29_1_LSEO
T29_3_LSEO
T29_1_LSOE
T29_3_LSOE
I2C_T29_SDA I2C_T29_SCL
F3
H5
F5
5
PRT1_T29R_N
1 T R O P
SYNC_DATE=02/15/2011
PAGE TITLE
PRT3_T29T_P
A18
T29 Host (1 of 2) DRAWING NUMBER
33 83
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
D
R36311
75
DP_T29SNK1_ML_N<2>
EE_CLK
A2
N2
Use B1 GND ball for THERM_DN
V13
100K
DP_T29SNK1_ML_P<1>
L2
TP_T29_THERM_DP
DP_T29SNK1_ML_P<1> DP_T29SNK1_ML_N<1>
83 33
8
EE_DO
U8
83 33
33 83
EE_DI
M1
L4
V11
83 33
DP_T29SNK1_ML_N<0>
T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L T29_SPI_CLK
P1
M3
DP_T29SNK1_ML_P<2> DP_T29SNK1_ML_N<2>
33 83
DP_T29SNK1_ML_P<0>
PCIE_CLKREQ_1*
DP_T29SNK1_ML_N<3>
83 33
10% 16V X5R-CERM 0201
N4
DP_T29SNK1_ML_P<3>
83 33
83 8
PCIE_CLKREQ_0*
83 33
83 33
10% 16V X5R-CERM 0201
SNK1 AC Coupling 2 DP_T29SNK1_ML_C_P<0> C3630 1
PCIE_T29_D2R_P<1>
1K
P3
83 33
83 33
DP_T29SNK0_AUXCH_P
R3655
MONOBSN
=T29_CLKREQ_L T29_GPIO<1> T29_GPIO<2> T29_RSVD
DP_T29SNK0_HPD
OUT
83 33
1
0.1UF
83 8
2
8 81
2
X5R-CERM 0201
X5R-CERM 0201
10K
83 33
0
SNK0 AC Coupling C3620
DP_T29SNK0_ML_C_P<0>
OUT
16V
R36991
R36291
DP_T29SNK0_ML_C_N<0>
8 81
16V
R36511
T29_PCIE_WAKE_L
1% 1/16W MF-LF 402
T29_TEST_EN TP_T29_TEST_POINT_0 TP_T29_TEST_POINT_1 TP_T29_TEST_POINT_2 T29_TEST_POINT_3
5% 1/16W MF-LF 2 402
IN
MONOBSP
2 402
0
IN
M17
RSENSE
RBIAS
R3625
83 8
TP_TBT_MONOBSN
83
THM PAD
4
1
OUT
PCIE_T29_D2R_N<0>
2
10%
10K
1
83 8
6
83
VSS
1
PCIE_T29_D2R_P<0>
2
10%
10K MONDC1
R3621
5% 1/16W MF-LF 2 402
MLP
1
K17
1
M95320-RMC6XG
T29ROM_WP_L
(T29_SPI_CS_L)
Q
6
TP_TBT_MONOBSP
1
35
2
1
C3646
PCIE_T29_D2R_C_P<3> PCIE_T29_D2R_C_N<3>
DEBUG: For monitoring clock
VCC 5
1
0.1UF
5% 1/16W MF-LF
5% 1/16W MF-LF
2 402
1
0.1UF
DEBUG: For monitoring current/voltage
=PP3V3_T29_RTR
1
0.1UF 6
35 34 33 7
1
0.1UF
2 N E G E I C P
PER_1_P
1
0.1UF
C3641
FCBGA
2
0.1UF
D
81 81
(SYM 1 OF 2)
0.1UF
IN
X5R-CERM 0201
X5R-CERM 0201
2
0.1UF 81 8
16V
16V
2
1
C3603
OMIT_TABLE
2
0.1UF
0.1UF
3 T R O P
PRT3_T29R_P PRT3_T29R_N
H1
OUT
8
IN
8
NOTE: All unused LSOE/EO pairs should be aliased together. Other signals okay to float (TP/NC).
T29_SDA T29_SCL
4
3
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
36 OF 109 SHEET
33 OF 86
1
A
8
7
6
5
4
D
2
3
OMIT_TABLE
C3700 1
1
10UF
20% 2 6.3V X5R 603
C3705
1
1UF
10% 2 6.3V CERM
402
C3706
1
1UF
6.3V 2 10% CERM 402
C3707
1
6.3V 2 10% CERM 402
C3708
1
6.3V 2 10% CERM 402
C3709
VCC1P0
H11
VCC1P0
H13
1UF
K9
6.3V 2 10% CERM 402
K11
1UF
1UF
H9
K13 M9 M11 M13
C3701 1 10UF 20%
6.3V 2 X5R 603
1
C3710 1UF 10%
2 6.3V CERM 402
1
C3711
6.3V 2 CERM 402
C3712
1
1UF
1UF 10%
1
10%
2 6.3V CERM 402
C3713
1
2 6.3V CERM 402
H15
10%
K15
1UF
1UF 10%
C3714
2 6.3V CERM 402
M15 E8
1UF
10% 2 6.3V CERM 402
C
1
C3721 1UF
10% 2 6.3V CERM 402
1
C3722
(SYM 2 OF 2)
VCC1P0
C3744 1
H7
1UF
M7
10%
K7
C3743 1 1UF 10%
C3745 1 1UF 10%
6.3V 2 CERM
6.3V 2 CERM
6.3V 2 CERM
C3753 1
C3752 1
C3751 1
402
402
402
1
C3746 10UF
20% 6.3V 2 X5R 603
VCC1P0
VCC3P3_DP_RX1
VCC1P0 VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE
VCC3P3_DP_RX1
C C V
VDD1P0_DP_RX1
VCC3P3_DP_TXRX
0402
10UF
20% 6.3V 2 X5R 603
VCC3P3_DP_TXRX
P7 R6 P9 P11
1UF 10%
6.3V 2 CERM 402
VDD3P3DP_PLL
1UF 10%
6.3V 2 CERM 402
1UF 10%
6.3V 2 CERM 402
C3750 1 1UF 10%
6.3V 2 CERM 402
P13
VDD1P0_DP_TXRX
C3760
VDD1P0_DP_TXRX
1
1UF
10% 2 6.3V CERM 402
10%
6.3V 2 CERM 402
L3730
2
C3747
G10 G12
C
L3770
FERR-120-OHM-1.5A 1
1
VCC1P0
G14
1UF
VCC3P3
VCC3P3_T29 VCC3P3_T29
VCC1P0
VCC1P0_PE
R12
VCC3P3
FCBGA
VCC1P0
E12
R8
C3720
T29
VCC1P0
E10
R10 1
U3600
VCC3P3
D
=PP3V3_T29_RTR 7 33 35 135 mA (Single-Port) 152 mA (Dual-Port) EDP: 200 mA
CRITICAL =PP1V05_T29_RTR 7 2100 mA (Single Port) 2250 mA (Dual Port) EDP: 3000 mA
1
FERR-120-OHM-1.5A R14
PP1V05_T29_VDD_DPPLL
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
1
VDD1P0_DP_PLL
VCC3P3_DP_TXRXBIAS
C3730 2.2UF 20%
6.3V 2 CERM
402-LF
J10 J14 L8 L10 L12 L14 N8 N10 N12 N14
VSSDP
VSS
B3 B5 B7 B9 B11 B13 B15 B17 B19
D1 D3 D5 D7 D9 D11 D13 D15 D17 E18 E20 F7
T9
402-LF
VSSDP VSSDP VSSDP
T11
VSS
VSSDP
T15
VSSDP
VSS
VSSDP
VSS
VSSDP
VSS
VSSDP
VSS
VSSDP
VSS
VSSDP
VSS
VSSDP
VSS
VSSDP
VSSPE VSSPE VSSPE VSSPE
D N G
V17 W4 W6 W8 W10 W12 W14 Y1
VSSDP
AA2
VSSDP_PLL
T13
VSSPE VSSPE
F9 F11 F13
VSSPE
VSSPE
F15
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE VSSPE
VSSPE VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
0402
T17
VSSPE
VSSPE
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
2
6.3V CERM 2
VSS
B
F17 G18 G20 J16 J18
C18 C20
2.2UF 20%
VSS
VSSDP B1
T5 T7
VSS
VSS
1
PP3V3_T29_DPBIAS
C3770 1 G8 J8 J12
B
P15
J20 L16 L18 L20 N16 N18 N20 R18 R20 U18 U20 W18 W20
A
S Y NC _ MA ST E R= K 90 I _M L B
S Y NC _ DA T E= 0 2/ 15 / 20 1 1
PAGE TITLE
T29 Host (2 of 2) DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY:
Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @
8
7
6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
90C.
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
37 OF 109 SHEET
34 OF 86
1
A
8
7
6
5
Page Notes CRITICAL T29BST:Y
Power aliases required by this page: - =PPVIN_SW_T29BST (8-13V Boost Input) - =PP18V_T29_REG (18V Boost Output) - =PP3V3_T29_P3V3T29FET (3.3V FET Input) - =PP3V3_T29_FET (3.3V FET Output) - =PP3V3_S0_T29PWRCTL - =PP1V05_T29_P1V05T29FET (1.05V FET Input) - =PP1V05_T29_FET (1.05V FET Output)
D
Q3880
8 7
SI8409DB
=PPVIN_SW_T29BST 8-13V Input Changes required for 2S. T29BST:Y
BGA
3
7
CRITICAL T29BST:Y
L3895
1
T29BST:Y
T29BST:Y
C3890 1
C3891 1
10% 25V X5R 2 805
10% 25V X5R 2 805
Voltage not specified here, add property on another page.
C3880
10% 25V 2 X5R 402
10UF
T29BST:Y
0.1UF
5% 1/16W MF-LF 4022
R38911
1
DIDT=TRUE
T29BST_SNS1 T29BST:Y 7 2
<R1>
25 EN/UVLO
T29BST_EN_UVLO
CRITICAL T29BST:Y
330K
T29BST_INTVCC T29BST_PWREN_L
Q3805
SSM3K15AMFVAPE
1 76 75
IN
C3892 1
TBT_A_HV_EN
1
S 2
T29BST:Y 1
R3892
1
0402
Open-Drain GPIO IN
IN OUT
VC
33
RT
32
1% 1/16W MF-LF 402
2 10 35
NC
1
0402
NO STUFF 1
SGND
10% 6.3V 2 CERM-X5R 402
3 4 7 4 2 2 3
K
PLACE_NEAR=C3897.1:2 mm
XW3895 SM
1
C3889 100PF
GND
5% 2 50V CERM
2 3 4 5 6 7 1 1 1 1 1 1
0402
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V
2
T29BST_VSNS
T29BST:Y
R38951 137K
1% 1/16W MF-LF 4022
<Ra>
T29BST_FBX T29BST:Y
31
C3894 0.33UF
1% 1/16W MF-LF 4022
5% 2 50V CERM
SS FBX
1
41.2K
C3888 22PF
34 SYNC
T29BST:Y
R3894
R38961 15.8K
1% 1/16W MF-LF 4022
<Rb>
=PP15V_T29_REG T29BST:Y
T29BST:Y 1
C3895
1
4.7UF
4.7UF
10% 2 50V X7R-CERM
10% 2 50V X7R-CERM
T29BST:Y
T29BST:Y
C3896
7 8
Vout = 18.3V Max Current = 0.8A Freq = 300KHz
1206
1206
C3898 1
1
4.7UF
4.7UF
10% 50V
10% 50V
X7R-CERM 2
X7R-CERM 2
1206
1206
SGND shorted to GND inside package, no XW necessary.
C3897
T29BST:Y 1
C3899
0.001UF
10% 50V 2 X7R-CERM
0402
Vout = 1.6V * (1 + Ra / Rb)
C
T29BST:Y
7 33 34
+ -
5% 1/16W MF-LF 402 1
R3807
SOT563
1 S
3 MR*
TBT_PWR_EN TBT_CLKREQ_L
6 EN
T29BST_SHDN_DIV 1
R3887
(OD)
B
T29_RESET_L
OUT
33
T29BST:Y 3 D
IN
33
THRM
=T29_CLKREQ_L T29_CLKREQ_ISOL_L
Q3888
SSM6N37FEAPE
5% 1/20W MF 2 201
DLY = 60 ms +/- 20%
IN 7
5
R3888
330K 5% 1/20W MF 2 201
330K
RESET* 4
GND
Max Vgs: 10V
T29BST:Y 1
T29BST:Y
0.7V
8 OUT
Pull-up provided by SB page.
G 2
7
SENSE 2
DLY
TBT_SW_RESET_L
Q3888
SSM6N37FEAPE
1
PP1V05_T29
TDFN
24
49.9K
GND_T29BST_SGND
1/16W MF-LF 2402
SLG4AP016V
10K
19
30
T29BST_RT
100K 5%
VDD
U3800
X5R 2 402
=T29_RESET_L
CRITICAL
1
10% 0.1UF 25V
R38032
16
R3890 2 1 T29BST_VSNS_RC
D
POWERDI-123
DFLS230L
T29BST_SNS2 T29BST:Y
1
T29BST_VC
T29BST_SS
6 D
C3800 1 Platform (PCIe) Reset IN
3
CRITICAL T29BST:Y
D3895
=PP3V3_S0_T29PWRCTL =PP3V3_T29_RTR
24
6
SNS2
36
1% 1/16W MF-LF 4022
UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)
Supervisor & CLKREQ# Isolation 7
C3893
10% 50V 2 X7R-CERM
<R2>
10K
T29BST_VC_RC T29BST:Y T29BST:Y 1 0.0033UF
1% 1/16W MF-LF 2 402
SNS1
QFN
NC
R38931
5% 2 50V CERM 402
10% 10V 2 X5R 805
G
C3887 47PF
4.7UF
73.2K
C
U3890
INTVCC
T29BST:Y
T29BST:Y D 3
VESM
T29BST:Y
28
A
0
5% 1/16W MF-LF 4022
SW
LT3957
5% 1/16W MF-LF 4022
R38891
8 9 0 1 8 2 2 3
VIN
R38811
T29BST_BOOST
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE
10UF
1% 1/16W MF-LF 4022
T29BST:Y
2
PCMB063T-100MS
200K
T29BST_PWREN_DIV_L
1
10UH-4A-68-MOHM
PPVIN_SW_T29BST
G
2
3
T29 15V Boost Regulator
-30V +/-12V -1.4V 46mOhm @ 4.5V Vgs 3.7A @ 70C
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm
D 2
T29BST:Y 1
470K
BOM options provided by this page: T29BST:Y - Stuffs 18V boost circuitry.
S
4
R38801
Signal aliases required by this page: - =T29_CLKREQ_L - =T29_RESET_L
4
SI8409DB: Vds(max): Vgs(max): Vgs(th): Rds(on): Id(max):
SOT563
4 S
G 5
SMC_DELAYED_PWRGD
IN
24 45 46
MAKE_BASE=TRUE
PAD
9
B
3.3V T29 Switch U3810 7
TPS22924
=PP3V3_S0_P3V3T29FET
CSP
A2 B2
VIN
=PP3V3_T29_FET A1
VOUT
7
Max Current = 2A (85C)
B1
U3810
CRITICAL
C3810 1
C2 ON
1UF
TPS22924C
Part
GND
10%
6.3V 2 CERM
1 C
Type
Load Switch
402
R(on)
18.3 mOhm Typ
@ 2.5V
24 mOhm Max
R38161 0
5% 1/16W MF-LF 4022
TBT_PWR_EN_RC
1.05V T29 Switch U3815
7
TPS22920
=PP1V05_S0_P1V05T29FET
CSP
A2 B2
VIN
A
C3815 1 1UF
CRITICAL D2 ON
10%
GND
402
1 D
6.3V 2 CERM
=PP1V05_T29_FET A1
VOUT
C2
7
Max Current = 4A (85C)
B1
U3815
C1
Part
TPS22920
Type
Load Switch
R(on)
8 mOhm Typ
@ 1.05V
11.5 mOhm Max
S Y NC _ MA ST E R= K 90 I _M L B
NO STUFF
T29 Power Support DRAWING NUMBER
Apple Inc.
C3816 1
R
1UF
NOTICE OF PROPRIETARY PROPERTY:
10%
6.3V CERM 2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
402
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REVISION
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BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below. If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY. If enabled:
VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_ENET_PHY
71
???mA (1000base-T, Caesar V) 71 36 24 7
=PP3V3_ENET_PHY
281mA (1000base-T max power, Caesar IV)
VDD for Card Reader I/O =PP3V3R1V8_ENET_LR_OUT 36 CRITICAL
1
2
D
ENET_SR_LX
71
ENET_SR_VFB
71
Internal 1.2V Switching Regulator pins.
L3900 FERR-600-OHM-0.5A
CRITICAL
L3920 PP3V3_S3_ENET_PHY_XTALVDDH
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
SM
C3921
2
1
1
10% 16V 2 X7R-CERM 0402
2
1
2
CRITICAL
10% 16V X7R-CERM 0402
C3926
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
SM
5% 1/16W MF-LF 402
R3940
1
1
2
2
4.7K 5% 1/16W MF-LF 402
=PP3V3_S0_ENETPHY
OUT
1
PCIE_ENET_D2R_N
1K 5% 1/16W MF-LF 402
2 2
10% 16V X7R-CERM 0402 81 16
OUT
1
1
1
PCIE_ENET_R2D_C_P
81 16
IN
81 16
C3956 1
OUT
0
=ENET_WAKE_L
1
(See note)
2
82 30
10% 16V X7R-CERM 0402
R3943 24
81 16
0.1UF
PCIE_ENET_R2D_C_N
2
16
WAKE#
2
10% 16V X7R-CERM 0402
C3931
R3941 5% 1/16W MF-LF 402
C3915
1
1
10% 6.3V X5R-CERM 2 603
2
4.7UF
10% 6.3V X5R-CERM 603
CRITICAL
L3930
2 8 4 4
10% 16V X7R-CERM 0402
7 3
H
AVDDH D D V S A I B
7 1
0 6 2 7 2 5 6
H D D V L A T X
VMAIN_PRSNT(IPD)
27
PCIE_TXD_N
81
PCIE_ENET_D2R_C_P
28
PCIE_TXD_P
81
PCIE_ENET_R2D_P
33
PCIE_RXD_P
81
PCIE_ENET_R2D_N
34
PCIE_RXD_N
IN
PCIE_CLK100M_ENET_P
31
PCIE_REFCLK_P
IN
PCIE_CLK100M_ENET_N
30
ENET_RESET_L
11
PERST*
(IPD)
ENET_CLKREQ_L
12
CLKREQ*
(OD)
ENET_WAKE_R_L
3
WAKE*
(OD)
ENET_LOW_PWR
4
LOW_PWR
(IPD)
BCM57765_SMB_CLK
6
BCM57765_SMB_DATA
If PHY is always powered then alias =ENET_WAKE_L to PCIE_WAKE_L.
VDDO
4 1
5 1
D D V _ R S
P D D V _ R S
6 1
3 1
X
L
_ R S
9 3
B F V _ R S
5 1 4 5
9 2 2 3
AVDDL
6 3
L D D V L L P _ E I C P
2
5 1 3 6
L D D V L L P _ Y H P G
4.7UF
SMB_DATA
66
SCLK_SPD1000LED*
36
BCM57765_MISO
64
36
BCM57765_MOSI
65
SO_LINKLED*
36
BCM57765_CS_L
63
CS*/EECLK
10% 6.3V X5R-CERM 603
2
18
SYSCLK_CLK25M_ENET
NC BCM57765_RDAC
19 38
1
1
10% 16V X7R-CERM 2 0402
2
0.1UF
C3935
LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
10UF
the card reader on-chip I/O.
10% 6.3V X5R 805
=PP3V3R1V8_ENET_LR_OUT
U3900
1
36
PP3V3R1V8_ENET_LR_OUT_REG
TRD0_P
40
ENET_MDI_P<0>
BI
37 82
QFN-8X8
TRD0_N
41
ENET_MDI_N<0>
BI
37 82
TRD1_P
44
ENET_MDI_P<1>
BI
37 82
TRD1_N
43
ENET_MDI_N<1>
BI
37 82
TRD2_P
46
ENET_MDI_P<2>
BI
37 82
TRD2_N
47
ENET_MDI_N<2>
BI
37 82
TRD3_P
50
ENET_MDI_P<3>
BI
37 82
TRD3_N
49
ENET_MDI_N<3>
BI
37 82
) D P I (
GPIO_0/CR_ACT_LED*
5
GPIO_1/LR_OUT
8
GPIO_2/MEDIA_SENSE
9
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V
1
C3970
1
C3971 0.1UF
4.7UF 2
1
10% 6.3V X5R-CERM 603
2
C3972 0.1UF
10% 16V X7R-CERM 0402
2
10% 16V X7R-CERM 0402
NC
to errata.
ENET_MEDIA_SENSE
OUT
24
SDCONN_DETECT_L
IN
30
CR_CMD
26
SDCONN_CMD
IN
30 82
OUT
30 82
SD_DETECTo1
(IPU)
(IPD)
CR_CLK
21
SDCONN_CLK
CR_DATA0
25
SDCONN_DATA<0>
BI
CR_DATA1
24
SDCONN_DATA<1>
BI
30 82
CR_DATA2
23
SDCONN_DATA<2>
SI/EEDATA
) U P I (
BI
30 82
CR_DATA3
22
SDCONN_DATA<3>
BI
30 82
CR_DATA4
52
SDCONN_DATA<4>
BI
SPD100LED*/SERIAL_DO
(OD)
TRAFFICLED*/SERIAL_DI
(OD)
) U P I (
30 82
CR_DATA5
53
SDCONN_DATA<5>
BI
30 82
CR_DATA6
54
SDCONN_DATA<6>
BI
30 82
SDCONN_DATA<7>
BI
XTALO
RDAC
30 82
B
55
CR_DATA7 ) U P I (
XTALI
MS_INS*
59
TP_CE_L_MS_INS_L
CR_LED*/CR_BUS_PWR
60
ENET_CR_PWREN
CR_WP*
57
SR_DISABLE
68
OUT
30
R3980
BDM57765_SR_DISABLE
30 82
No MS (Memory Stick) Insert feature needed. Control signal to light LED or control SD bus power. SDCONN_WP 1K
1
IN
30
2 5%
THRM_PAD
PHY Non-Volatile Memory
C
Connect only to U3900 pin 20.
BCM57765B0
67
TP_BCM57765_TRAFFICLED_L
C3936
VDDC
SMB_CLK
10
BCM57765_SCLK
IN
10% 16V X7R-CERM 2 0402
NOTE: "IPx" == Programmable pull-up/down
36
TP_BCM57765_SPD100LED_L
81 24
2 SM
C3930
PCIE_REFCLK_N
IN OUT
Standard
N-channel FET isolation suggested.
1
CRITICAL
0.1UF
58
IN
1
C3916
SD_DETECT can only be used active low due 30 24
1
0.1UF
2
PCIE_ENET_D2R_C_N
Must isolate from PCIe WAKE# if PHY
B
0.1UF
10% 16V X7R-CERM 0402
(IPx)
5% 1/16W MF-LF 402
is powered-down in S3/S5.
4.7UF
PP1V2_ENET_PHY_GPHYPLL
ENET_VMAIN_PRSNT
2
10% 16V X7R-CERM 0402
SM
C3925
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
81
0.1UF IN
2
C3911
2
10% 16V X7R-CERM 0402
C3955 81 16
1
Current Limiting Resistor
0.1UF 1
C3910 0.1UF
2
4.7K
C3951
PCIE_ENET_D2R_P
10% 16V X7R-CERM 2 0402
0.1UF
R3942
0.1UF 81 16
1
FERR-600-OHM-0.5A
R3910 4.7K
C3950
1
PP3V3_S3_ENET_PHY_AVDDH
2
2
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
L3910
1
L3925 1
PP1V2_ENET_PHY_PCIEPLL
C3905
FERR-600-OHM-0.5A
7
CRITICAL FERR-600-OHM-0.5A
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
0.1UF
C
10% 6.3V X5R-CERM 603
PP3V3_S3_ENET_PHY_BIASVDDH
SM
1
SM
C3920 4.7UF
0.1UF
L3905 FERR-600-OHM-0.5A 2
2
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
10% 16V X7R-CERM 0402
CRITICAL
1
PP1V2_ENET_PHY_AVDDL
1
0.1UF
1
D
FERR-600-OHM-0.5A
C3900
1/16W
MF-LF
402
9 6
R3965 1.24K
ROM contains MAC address, PCIe config info as well as code for Bonjour proxy. 2
Required for proper PHY operation.
1% 1/16W MF-LF 402
BCM57765 supports both active-levels for WP.
SR_DISABLE must be pulled down to use internal SR. IPD has a race condition.
(Required ROM size TBD) 71 36 24 7
=PP3V3_ENET_PHY
6
1
C3990 0.1UF
VCC
U3990
2
AT45DB011D
10% 16V X7R-CERM 0402
SOIC-8S1
A
36
BCM57765_SCLK
2
SCK
36
BCM57765_CS_L
4
CS*
5
3
OMIT
SI
1
BCM57765_MOSI
36
SO
8
BCM57765_MISO
36
S YN C_ MA ST ER =J 31 _M LB
ETHERNET PHY (CAESAR IV)
NOSTUFF 1
RESET*
R3990
1
7
2
5% 1/16W MF-LF 402
DRAWING NUMBER
R3997
Apple Inc.
4.7K
4.7K
GND
2
5% 1/16W MF-LF 402
other 3 SPI pins configures ENET for the
NOTICE OF PROPRIETARY PROPERTY:
Atmel AT45DB011D (1Mbit) ROM.
ROM is used then the straps must change.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
If a different
NOTE: ENETM requires SI pull-down instead of SO.
7
051-9058
REVISION
R
NOTE: Pull-down on SO plus internal pull-ups on
8
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WP*
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Page Notes Power aliases required by this page: (NONE)
Signal aliases required by this page: (NONE)
BOM options provided by this page: (NONE)
D
D
Place one of 0.1uf cap close to
each centertap pin of transformer
ENETCONN_CTAP 1
C4000
1
0.1UF
C4002 0.1UF
10% 2 16V X5R-CERM
10% 16V 2 X5R-CERM
0201
0201
1
C4004 0.1UF
10% 2 16V X5R-CERM
0201
1
C4006 0.1UF
10% 2 16V X5R-CERM
0201
OMIT_TABLE CRITICAL
T4000 82 36
BI
ENET_MDI_P<0>
1
82 36
BI
ENET_MDI_N<0>
2
SM
3
12
85
ENETCONN_P<0>
11
85
ENETCONN_N<0>
10
ENET_CTAP0
4
9
ENET_CTAP1
5
8
CRITICAL
J4000
RJ45-M97-3
TX
F-RT-TH
TLA-6T213HF
C 82 36
BI
ENET_MDI_P<1>
9
85
C
10
ENETCONN_P<1>
1 2
82 36
BI
6
ENET_MDI_N<1>
7
85
ENETCONN_N<1>
3
RX
4
OMIT_TABLE CRITICAL
5 6
T4001 82 36
82 36
BI
BI
ENET_MDI_P<3>
1
ENET_MDI_N<3>
2
7
SM
12 11
85
ENETCONN_P<3>
8
85
ENETCONN_N<3>
11 12
3
10
ENET_CTAP2
TX
514-0636
TLA-6T213HF
82 36
BI
ENET_MDI_N<2>
82 36
BI
ENET_MDI_P<2>
4
9
5
8
85
ENETCONN_N<2>
7
85
ENETCONN_P<2>
6
ENET_CTAP3
RX
Transformers should be mirrored on opposite sides of the board
R40001
R40011
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 4022
75
B
75
1
R4002 75
5% 1/16W MF-LF 2 402
1
R4003 75
CRITICAL
5% 1/16W MF-LF 2402
B
C4008 1000PF
ENET_BOB_SMITH_CAP MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
1
2 10% 2KV
CERM 1206
PART NUMBER 157S0084
QTY
2
DESCRIPTION
REFERENCE DES
XFMR,ISO,HALF-PORT,1000T,12P,SMD,HF
T4000,T4001
CRITICAL
BOM OPTION
CRITICAL
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
Ethernet Connector DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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REVISION
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40 OF 109 SHEET
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=PP3V3_FW_FWPHY
7 mA I/O
C4120
1
C4121
1UF
1UF
10% 6.3V CERM 2 402
10% 6.3V CERM 402
2
7 38 39 40
138 mA
C4122
1
1
1
C4123
1UF
1UF
10% 6.3V CERM 2 402
10% 6.3V CERM 402
1
C4124
2
10% 6.3V CERM 402
1
1UF 2
L4130
D
120-OHM-0.3A-EMI
D
114 mA FireWire PHY
C4130 1UF 10% 6.3V CERM 402
1
C4132
1UF
1UF
10% 6.3V CERM 2 402
10% 6.3V CERM 402
C4131
1
2
1
PP3V3_FW_FWPHY_VDDA MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
2
L4110 39 7
L4135
120-OHM-0.3A-EMI
=PP1V0_FW_FWPHY
1
135 mA
2
120-OHM-0.3A-EMI 17 mA PCIe SerDes
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
0402-LF
1
C4110
1
1UF
C4111
C4135
C4100
1
1UF
1UF
10% 6.3V 2 CERM 402
10% 6.3V CERM 402
2
10% 6.3V CERM 402
2
10% 6.3V CERM 402
1
C4105
1
C4106
10% 6.3V CERM 402
2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
1
2 0402-LF
2
0 mA VReg PWR
C4101
1
C4102
1
10% 6.3V CERM 402
2
10% 6.3V CERM 402
C4103
1
2
10% 6.3V CERM 402
C4104
1UF
1UF
1UF
1UF
1UF
1UF 2
C4136
1
1
PP3V3_FW_FWPHY_VP25
1UF
110 mA Digital Core
1
2 0402-LF
2
10% 6.3V CERM 402
10% 6.3V CERM 402
2
2
C4141
1UF
0.1UF
10% 6.3V CERM 402
20% 10V CERM 402
1
1
2
2
C4140 1UF 10% 6.3V CERM 402
C
C
PLACEMENT_NOTE=Place C4170 close to U1400 PLACEMENT_NOTE=Place C4171 close to U1400 1 1 A B
2 3 1 1 2 B C E
0 1 2 E H
2 1 2 1 H K L
2 1 3 M N
1 1 N
1 C
2 1 1 C F
2 1 G
1 3 J L
1 1 2 L M
2 1 A
5 6 8 D D D
5 L
0 1 L
C4170
2 1 K
6 9 L L
1
0.1UF
VDD10
VDDH
VDD33
VP
VP25
C4171
VREG_PWR
OMIT
NC NC NC
1
200K
1% 1/16W MF-LF 402
ATBUSN
=FW_PHY_DS0
F12
DS0 (IPD) NT-2
IN
=FW_PHY_DS1
E12
DS1 (IPD) NT-3
PCIE_FW_R2D_N PCIE_FW_R2D_P
PCIE_TXD0N
N5
81
PCIE_FW_D2R_C_N
PCIE_TXD0P
N6
81
PCIE_FW_D2R_C_P
REFCLKN
N9
PCIE_CLK100M_FW_N
IN
16 81
REFCLKP
N10
PCIE_CLK100M_FW_P
IN
16 81
NT-21 (IPU)TCK
M4
NT-20 (IPU)TDI
FW643E
IN
=FW_PHY_DS2
E13
BI
FW_P0_TPA_N
B8
82 40
BI
FW_P0_TPA_P
A8
82 40
BI
FW_P1_TPA_N
B5
TPA1N
82 40
BI
A5
TPA1P
BI
FW_P1_TPA_P FW_P2_TPA_N
B3
TPA2N
BI
FW_P2_TPA_P
A3
82 40
BI
FW_P0_TPB_N
B9
TPB0N
82 40
BI
FW_P0_TPB_P
A9
TPB0P
82 40
BI
FW_P1_TPB_N
B6
TPB1N
82 40
BI
FW_P1_TPB_P
A6
TPB1P
BI
FW_P2_TPB_N
40
BI
FW_P2_TPB_P
A4
TPB2P
40
BI
FW_P0_TPBIAS
B7
TPBIAS0
NT-12 (IPD)
VAUX_DISABLE
40 39
BI
FW_P1_TPBIAS
C3
TPBIAS1
NT-13
(OD) CLKREQN
BI
FW_P2_TPBIAS
A2
TPBIAS2
40
2
C4175
DS2 (IPD) NT-4
PCI EXPRESS PHY
2
0.1UF
10%
1
2
0.1UF
R4150
22PF 1
2 5% 50V CERM 0402
C4151
FW_CLK24P576M_XO CRITICAL 1
NC NC
2
Y4150
1
412
2
TPA0P
R0
FW643_TPCPS
B10
TPCPS
6
TP_FW643_TDI
6
M1
TP_FW643_TDO
M3
TP_FW643_TMS
NT-19 (IPU) TRST*
N1
FW643_TRST_L
C2
=FW_PME_L
D13
FW643_REGCTL
E1
FW643_VAUX_DETECT
D2
TP_FW643_VAUX_ENABLE
L2
=FW_CLKREQ_L
1394 PHY
1% 1/16W MF-LF 402
24.576MHZ
R4161
SM-3.2X2.5MM
4
1
1% 1/16W MF-LF 402
2
R4170 191
2.94K
3
22PF 1
1
2
2
WAKE* REGCLT
FIXME!!! - TYPO IN SYMBOL REGCTL
VAUX_DETECT
POWER MANAGEMENT
R4165 5% 1/16W MF-LF 402
OUT
8 39
OUT
39
1
R4164 10K
NT-16 (IPD)
6
5% 1/16W MF-LF 402
1
XO
FW_CLK24P576M_XI
G13
XI NT-9
TP_FW643_SE TP_FW643_SM
M13
SE (IPD)
2
SCIFCLK
G2
5% 1/16W MF-LF 402
CE (IPD) FW620* (IPU)
D1
TP_FW643_SCIFCLK
R4166 10K 5% 1/16W MF-LF 402
B
NOTE: FW_PME_L and FW_CLKREQ_L are
isolated for systems that use
1394B physical plug detect.
WITH PLUG DETECT: - Gate CLKREQ# based on PHY power
TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT
- TP (or NC) PME#
TP_FW643_SCIFMC
WITHOUT PLUG DETECT:
N12
FW643_SCL
M11
TP_FW643_SDA
N4
FW_RESET_L
- Alias both signals to drop = prefix
NT-7 SCL NT-6 SDA
6
MISCELLANEOUS
JASI_EN (IPD) NT-11
TP_FW643_AVREG
A10
AVREG
6
TP_FW643_VBUF
H13
VBUF
FW643_PU_RST_L
K13
FW_RESET*
NC
2
F2
(IPD) NT-1
L13 D12
TP_FW643_OCR10_CTL
2
H1
SERIAL EEPROM CONTROLLER
TP_FW643_JASI_EN
CHIP RESET
NT-5 PERST*
39
R4163 10K
J12
OCR_CTL_V10
J13
OCR_CTL_V12 (Reserved) 2 4 B D
IN 1
(IPU) NT-8
VSS
10% 6.3V CERM-X5R 402
1
SCIFMC
NAND tree order.
SM (IPD) MODE_A
1
NT-14 (IPD) SCIFDAIN NT-17 SCIFDOUT NT-15 (IPD)
NOTE: NT-xx notes show
TP_FW643_FW620_L
C4162
SCIF
NT-OUT
TP_FW643_CE
0.33UF 2
J2
NAND_TREE
REXT
6
6
1
470K
K1
F13
7 38 39 40
FW643_LDO
2
TP_FW643_NAND_TREE FW643_REXT
N13
16 81
=PP3V3_FW_FWPHY
6
10K
FW_CLK24P576M_XO_R
TP_FW643_MODE_A
1% 1/16W MF-LF 402
5% 50V CERM 0402
R4162
6
16 81
OUT
16V X7R-CERM 0402
PLACEMENT_NOTE=Place C4175 close to U4100 PLACEMENT_NOTE=Place C4176 close to U4100
(OD) NT-10 (IPD)
TPB2N
B11
TP_FW643_TCK
N2
(IPU)TDO
NT-18 (IPU)TMS
TEST CONTROLLER
TPA2P
FW643_R0
L8
16 81
TPA0N
G1
C4150
IN
OUT
16V X7R-CERM 0402
PCIE_FW_D2R_P 10%
16 81
16V X7R-CERM 0402
PCIE_FW_D2R_N
2
IN
16V X7R-CERM 0402
PCIE_FW_R2D_C_P 10%
1
C4176
BGA
40
10%
1
0.1UF
81
82 40
B4
81
N7
U4100
IN
40
R4160
B
A11
N8
PCIE_RXD0N PCIE_RXD0P
CRITICAL
40
40
=PPVP_FW_PHY_CPS
ATBUSB ATBUSH
40
40
40
B13 A13
PCIE_FW_R2D_C_N
2
7 9 0 D D 1 D
4 5 9 4 6 E E E F F
7 8 F F
0 1 F
4 6 G G
7 8 0 G G 1 G
4 6 7 8 0 H H H H 1 H
2
VREG_VSS 4 5 9 J J J
0 4 5 1 K K J
7 8 9 K K K
7 6 L K
0 1 K
5% 1/16W MF-LF 402
2 1 L
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
FireWire LLC/PHY (FW643E) DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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REVISION
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PAGE
41 OF 109 SHEET
38 OF 86
1
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8
7
6
5
4
Page Notes =PPBUS_S5_FWPWRSW
- =PPBUS_FW_FET
CRITICAL
(FW VP FET Input)
Q4260
(FW VP FET Output)
- =PP3V3_FW_FET
(3.3V FET Output)
- =PP3V3_FW_FWPHY
(PHY 3.3V Power)
CRITICAL
FDC638P_G
- =PP3V3_FW_P3V3FWFET (3.3V FET Input) =PPBUS_S5_FWPWRSW
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
5 4 2
- =PP3V3_S0_FWPWRCTL
D4260
1.1A-24V 6
7
CRITICAL
F4260
SM
- =PP3V3_S0_FWLATEVG
PPBUS_FW_FWPWRSW_F
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
=PPBUS_FW_FET
SM
PPBUS_FW_FWPWRSW_D
2
A
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
MINISMDC110H24
7
K
CRS08-1.5A-30V
1
- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)
D
1
FireWire Port Power Switch
Power aliases required by this page: -
2
3
- =PP1V0_FW_FET_R
(1.0V FET Output)
- =PP1V0_FW_FWPHY
(PHY 1.0V)
1
R4262
1
10K
- =PP1V05_FW_P1V0FWFET (1.0V FET Input)
2
2
FWPORT_FASTOFF_L_DIV
(SYM-VER2)
S
5
SOT-363
R4263
(NONE)
10% 25V X5R 402
D
3
2
Q4262
1
D
10 5% 1/16W MF-LF 402
1
0.1UF
FWPORT_PWREN_L_DIV
BSS8402DW
G
- =FW_CLKREQ_L
BOM options provided by this page:
C4260
5% 1/16W MF-LF 402
4
Signal aliases required by this page: - =FW_PME_L
R4260 300K
5% 1/16W MF-LF 402
3 2
FWPORT_FASTOFF_L 1
R4261
D 40 7
Q4262
=PP3V3_S0_FWLATEVG
2
BSS8402DW
G
2
(SYM-VER1)
5% 1/16W MF-LF 402 7
=PP3V3_S0_FWPWRCTL
FWPORT_PWREN_L
SOT-363
S
Q4261
1
D 3
C4261
G
10% 25V X5R 2 402
S 2
24
IN
10% 25V X5R 402
=FW_RESET_L 2
R4290 100K
SLG4AP016V
R4283
2
5% 1/16W MF-LF 402
=PP1V0_FW_FWPHY
+ -
10K
1
C
5% 1/16W MF-LF 402
39 24 16
SENSE
7 38
2
0.7V
DLY
FW_RESET_R_L
3
MR*
RESET*
FW_RESET_L
4
OUT
38
IN
38
C
DLY = 60 ms +/- 20%
IN
FW_PWR_EN
6
EN
OUT
FW_CLKREQ_L
8
OUT
=FW_CLKREQ_L IN
(OD)
Pull-up provided by another page.
GND 5
7
1
CRITICAL
1
VDD
U4290
2
TDFN
FWPORT_PWR_EN
IN
1
0.1UF 1
0.1UF
VESM
1
C4290
NO STUFF
SSM3K15AMFVAPE
40
Supervisor & CLKREQ# Isolation
470K
6
FW_CLKREQ_PHY_L
7
MAKE_BASE=TRUE
THRM PAD
9
=PP1V05_S0_FWPWRCTL
FireWire Port 5K Pull-Down Detect R4275
1
All FireWire devices require 5K pull-down on TPB pair.
1K
Host can detect as load on TPBIAS signal.
5% 1/16W MF-LF 402 2
Current source only active when FW_PWR_EN is low.
3.3V FW Switch
FW_PWR_EN_L
U4201 6
D
1
CRITICAL
Q4275 DMB53D0UV SOT-563
39 24
IN
FW_PWR_EN
2
2
G
R4271
R4270 330K
56K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
1
7
FW_5KPD_DET_L
3
2
5
B2
S 1
B
Q4270
6 5
BC847CDXV6TXG SOT563
Q4270
2
FWDET_MIRROR
Q4275
C4201
1
C2
10% 6.3V CERM 402
GND TPS22924C
Part
1 C
2
2
Type
Load Switch
R(on)
18 mOhm Typ
1
R4273
1K
12K 5% 1/16W MF-LF 402
2
Max Output: 2A
1.0V FW Switch
5% 1/16W MF-LF 402
U4202
1 7
TPS22924
=PP1V05_FW_P1V0FWFET
CSP
A2 B2
VIN
VOUT
PP1V05_FW_FET A1 B1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
2
LSI FireWire PHY requires 1.0V.
CRITICAL
PLACE_NEAR=C4360.1:2 mm
C4202
FW_P1_TPBIAS
1
10% 6.3V CERM 402
FireWire PHY WAKE# Support
C2
1
ON GND
1UF 2
1 C
2
R4202
To avoid an extra power supply,
0.549
1.05V is used with a series R to reduce voltage.
1% 1/16W MF 402
=PP1V0_FW_FET_R
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal. 40 38 7
B
50 mOhm Max
FWDET_EMIT
R4272
IN
U4201 & U4202
ON
1UF
4
7
B1
1
FW_P1_TPBIAS_R
40 38
=PP3V3_FW_FET EDP = 0.14A (85C)
A1
0.1UF 10% 16V X7R-CERM 0402
BC847CDXV6TXG SOT563
4
1
VOUT
CRITICAL
DMB53D0UV
C4270
CRITICAL
VIN
CRITICAL
SOT-563 3
CSP
A2
MAKE_BASE=TRUE
FW_5KPD_DET_RC CRITICAL
TPS22924
=PP3V3_FW_P3V3FWFET
=PP3V3_FW_FWPHY
7
Dual-purpose output: 1) 5K Pull-down Detect when FW_PWR_EN is low.
R4277
1
1
10K 5% 1/16W MF-LF 402
2) FW643 WAKE# (PME#) when PHY is powered.
R4276
FW_PME_L
100K
2
2
5% 1/16W MF-LF 402 5
FW_WAKE
6
D
38 8
IN
=FW_PME_L
8
FW643_WAKE_L
2
8 19
C4276
CRITICAL
Q4276 DMB53D0UV
NO STUFF
A
OUT
Pull-up provided on another page. 3
SOT-563
1
4
SYNC_MASTER=K90I_MLB
0.1UF 10% 16V X7R-CERM 0402
FireWire Port & PHY Power DRAWING NUMBER
G
MAKE_BASE=TRUE
Apple Inc.
CRITICAL
Q4276 S
R
DMB53D0UV
NOTICE OF PROPRIETARY PROPERTY:
SOT-563
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1
TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.
8
7
6
SYNC_DATE=06/23/2011
PAGE TITLE 2
5
4
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42 OF 109 SHEET
39 OF 86
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Page Notes - =PPVP_FW_PHY_CPS_FET (From Port)
2
3
Unused FireWire Ports
1
FireWire PHY Config Straps
FW643 has internal leakage path from TPCPS pin to VDD33.
Disabled per LSI instructions
Configures PHY for:
FET blocks current to TPCPS until VDD33 is powered.
(All unused port signals TP/NC)
- Port "1" Bilingual (1394B)
(To PHY)
40 39 38 7
- =PP3V3_FW_FWPHY
=PP3V3_FW_FWPHY
W D 2 ) 2 0 3 R 6 4 E V 3 8 - S M T Y O S S S B (
- =PP3V3_S0_FWLATEVG
0 0 3 4 Q
Signal aliases required by this page: - =FW_PHY_DS0 - =FW_PHY_DS1
D
4
FW643 TPCPS Leakage Protection
Power aliases required by this page: - =PPVP_FW_PORT1 - =PPVP_FW_PHY_CPS
5
7
- =FW_PHY_DS2
PPVP_FW_CPS
=PPVP_FW_PHY_CPS_FET 4
From Port
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
R4311 5% 1/16W MF-LF 402
S
1
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE
D 3
FW_P0_TPBIAS
82 38
BI
FW_P0_TPA_P
82 38
BI
FW_P0_TPA_N
BI
FW_P0_TPB_P
82 38
82 38
=PPVP_FW_PHY_CPS
G
470K
IN
38
38
BI
NC_FW0_TPAP
2
CPS_EN_L_DIV
(NONE)
1394b implementation based on Apple
R4312
1
330K 5% 1/16W MF-LF 402
1% 1/16W MF-LF 402
NO_TEST=TRUE
NC_FW0_TPAN MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBP
1
2
2
R4380 10K
6
MAKE_BASE=TRUE
1% 1/16W MF-LF 402
FWPHY_DS0
NO_TEST=TRUE 6
MAKE_BASE=TRUE
FWPHY_DS1
NO_TEST=TRUE
NC_FW2_TPBIAS
FW_P2_TPBIAS
38
IN
38
BI
FW_P2_TPA_P
38
BI
F W_ P2 _T PA _N
38
BI
FW_P2_TPB_P
38
BI
FW_P2_TPB_N
MAKE_BASE=TRUE
FWPHY_DS2
6
OUT
38
=FW_PHY_DS1
OUT
38
6
1
NO_TEST=TRUE 6
NC _ FW 2= _TTRP AN MAK E _ BA S E UE
OUT
38
6
NO_TEST=TRUE
NC_FW2_TPBN
R4381 10K 1%
NO_ TES T=T RUE
NC_FW2_TPBP MAKE_BASE=TRUE
=FW_PHY_DS2
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPAP MAKE_BASE=TRUE
D
=FW_PHY_DS0
MAKE_BASE=TRUE
NC_FW0_TPBN
FW_P0_TPB_N
1
10K
6
MAKE_BASE=TRUE
BOM options provided by this page:
FireWire Design Guide (FWDG 0.6, 5/14/03)
R4382
NO_TEST=TRUE
MAKE_BASE=TRUE
To FW643
5
NC_FW0_TPBIAS MAKE_BASE=TRUE
2
1/16W MF-LF 402
6
MAKE_BASE=TRUE
NO_TEST=TRUE
2
CPS_EN_L
6
D 40 39 38 7
Q4300
=PP3V3_FW_FWPHY 2
BSS8402DW
G
SOT-363
S
(SYM-VER1)
1
C
C CRITICAL
Cable Power
Termination
Place close to FireWire PHY
7
L4310 FERR-250-OHM
=PPVP_FW_PORT1
1 39 38
IN
2
FW_P1_TPBIAS
Note: Trace PPVP_FW_PORT1 must handle up to 5A PPVP_FW_PORT1_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V
SM 1
C4314 0.01UF
1
C4360
2
0.33UF 2
10% 6.3V CERM-X5R 402
10% 50V X7R 402
(FW_PORT1_TPA_P) (FW_PORT1_TPA_N)
"Snapback" & "Late VG" Protection SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1
2 82 38
82 38
B
R4360
R4361
56.2
56.2
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
39 7
PORT 1
=PP3V3_S0_FWLATEVG
BILINGUAL
1
PLACE_NEAR=U4350.1:2
CRITICAL
mm
C4350
J4310
1
10% 16V X7R-CERM 0402
BI
FW_P1_TPA_P
FW_PORT1_TPA_P
BI
FW_P1_TPA_N
FW_PORT1_TPA_N
MAKE_BASE=TRUE
1394B-M97
1
0.1UF 2
F-RT-TH
VCC
U4350
2
TPD4S1394 3
TP_FWLATEVG_VCLMP
LLP
VCLMP
MAKE_BASE=TRUE
82 38
BI
FW_P1_TPB_P
82 38
BI
FW_P1_TPB_N
FW_PORT1_TPB_P
39
MAKE_BASE=TRUE
OUT
4
FWPORT_PWR_EN
FW_PORT1_TPB_N SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1
2
R4362
R4363
56.2 1%
56.2 1%
1/16W MF-LF 402
1/16W MF-LF 402
R4350
MAKE_BASE=TRUE
D1-
7
CRITICAL
D2+
6
D2-
5
1
GND
(FW_PORT1_BREF)
9
(FW_PORT1_TPB_P)
2
NC
6
(FW_PORT1_TPA_N)
3
C4319
220PF 2
5% 25V C0G-CERM 0402
R4364
10% 50V X7R 603-1
1
4.99K 1% 1/16W MF-LF 402
OUTPUT
TPB+
B
VP
SC/NC
NC VG
TPA-
VG
TPATPA<R>
INPUT
TPA+ TPA(R) TPA+
10 PLACE_NEAR=J4310.5:2 mm
11
1
(FW_PORT1_TPB_P)
13 2
514S0605
1
R4319
(FW_PORT1_TPB_N)
1M
2
2
5% 1/16W MF-LF 402
CHASSIS GND
12
0.1uF
C4364
TPB<R>
VP
5 4
2
FW_PORT1_TPB_C
1
TPB(R) TPB-
TPB+
(FW_PORT1_TPA_P)
(PINS 5/6 AND 7/8 ARE SWAPPED FOR BETTER ROUTING)
2
TPB-
7
(GND)
FW_PORT1_AREF
5% 1/16W MF-LF 402
1
8
2
100K
1
FWPWR_EN
D1+
8
(FW_PORT1_TPB_N)
AREF needs to be isolated from all local grounds per 1394b spec When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue) BREF should be hard-connected to logic ground for speed signaling and connection
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
FireWire Connector DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED
8
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43 OF 109 SHEET
40 OF 86
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7
6
5
4
ODD Power Control =PP5V_S3_ODD
6
2
10% 10V
5% 1/16W MF-LF 4022
3
R4595
=PP3V3_S0_ODD
Q4596
1
100K
2
ODD_PWR_SS
1
5% 1/16W MF-LF 402
D 6
R4597
F-ST-SM
2 10% 16V
X7R-CERM 0402
SOT563
100K
5% 1/16W MF-LF 402 2
2 G
S 1
ODD_PWR_EN
1
4
3
6
5 7 9
12
11
14
13
16
15
S 4 45 6
OUT
SATA HDD Connector (Gen3)
41 7
SATA_ODD_D2R_C_N
C4526 1
SATA_ODD_D2R_C_P
C4525 1
=PP5V_S0_HDD
49.9K
1% 1/16W MF-LF 2 402
0603
=PP3V3_S0_HDD
PLACE_NEAR=J4501.9:6MM
2
41
7
IN
SSD_OOBD2R_FTL_L
1
3.3K 2
X5R-CERM 1206
2
2
NOSTUFF
X5R-CERM 1206
C4502 0.1UF
CERM
1
1
402
NOSTUFF
R4538 100K
CERM
Write:0xB6
5% 1/16W MF-LF 2402
402
PLACE_NEAR=L4500.1:2MM
PLACE_NEAR=L4500.2:2MM
R45371
SSD_OOBR2D_L
453 SSD_OOBD2R_L
L4539 1
SYS_LED_ANODE_R
R45311 C4531 1
4.7
SMC_SSD_OOBR2D_L
2 1%
1/16W
IN
MF-LF 402
L
L
0x96/0x97
L
H
0x98/0x99
2 SSD_OOBD2R_FTL_L FERR-220-OHM 0402 FERR-220-OHM 0402
H
L
0xB6/0xB7
H
H
0xB8/0xB9
5%
OUT
41
IN
46
SYS_LED_ANODE
2 1/16W
46
MF-LF 402
0.001UF 10% 50V
41 7
X7R-CERM 2
100K R4584 5% 1/16W MF-LF
2 402
ADD0
OUT
=PP1V5_S0_RDRVR
54722-0224
VALUE: 4.5 DB
R45361
2
3
4
5
6
GND_VOID
7
8
GND_VOID
9
10
2
68.1
11
12
GND_VOID
13
14
GND_VOID
15
16
17
18
19
20
21
22
SATA_HDD_D2R_C_P
CRITICAL
80 6
SATA_HDD_D2R_C_N
C4535 5.0PF
1
2
0201
NO STUFF
R45151 4.7K
5% 1/16W MF-LF 4022
41 7
SATARDRVR_I2C_ADDR0 SATARDRVR_I2C_ADDR1
1
GND_VOID=TRUE
2
0201
C4514
1
C4519
41
C4518 & C4517 Placement Note:
0.01UF
0.1UF
20% 16V 2 X7R-CERM
20% 2 10V CERM 402
It is critical that these two should be near to U1800 pin AM1 and AM3.
0402
B
PLACE_NEAR=U4510.16:2MM
PLACE_NEAR=U4510.6:2MM
PLACE_NEAR=U1800.AM1:5MM
80
2
C0G
SATA_HDD_D2R_RC_P
25V
GND_VOID=TRUE
+/-0.1PF
68.1
80
SATA_HDD_D2R_RC_N
25V
C4516 1 0.01UF
2
C4515 1 0.01UF
2
GND_VOID=TRUE
85
SATA_HDD_D2R_RDRIN_P
85
C4518 1
SATA_HDD_D2R_RDROUT_P
0.01UF
10% 16V X7R-CERM 0402 GND_VOID=TRUE
85
SATA_HDD_D2R_RDRIN_N
85
2
C4517 1
SATA_HDD_D2R_RDROUT_N
0.01UF
0402 10% 16V X7R-CERM
2
OUT
16 80
SATA_HDD_D2R_N
OUT
16 80
SATA_HDD_R2D_C_N
IN
16 80
SATA_HDD_R2D_C_P
IN
16 80
0402 10% 16V X7R-CERM PLACE_NEAR=U1800.AM3:5MM GND_VOID=TRUE
6 6 1
GND_VOID=TRUE
SATA_HDD_D2R_P
0402 10% 16V X7R-CERM
1% 1/20W MF 201
VDD
U4510 2
41.2 80 6
SATA_HDD_R2D_N
C4534
7 44
SATA_HDD_R2D_P
C4533 15PF
1
R4532 0
1
2
1
41.2
GND_VOID=TRUE
5% 25V 0201
2
80
SATA_HDD_R2D_RC_N
NP0-CERM
GND_VOID=TRUE
5% 25V 0201
R45331
5% 1/16W MF-LF 2402
PS8521A
GND_VOID=TRUE
1% 1/20W MF 201
15PF
80
SATA_HDD_R2D_RC_P
201
0.01UF
2
C4510 1
2
23 16
IN
41
IN
SATARDRVR_I2C_ADDR0
41
IN
SATARDRVR_I2C_ADDR1
GND_VOID=TRUE
85
SATA_HDD_R2D_RDROUT_N
1
A_INP
TQFN GND_VOID GND_VOID A_OUTP 15
2
A_INN
GND_VOID
0402 10% 16V X7R-CERM
0.01UF SATARDRVR_EN
NP0-CERM
2 GND_VOID=TRUE 1% 1/20W MF
C4511 1
GND_VOID=TRUE
85
SATA_HDD_R2D_RDROUT_P
PLACE_NEAR=U4510.12:5MM GND_VOID=TRUE
14 GND_VOID A_OUTN
4
B_OUTN GND_VOID
GND_VOID
5
B_OUTP GND_VOID
GND_VOID
85
0.01UF
B_INN 12 B_INP 11
7
EN
8
B_PRE0/I2C_ADDR0
A_PRE1/SCL_CTL
APRE0/I2C_ADDR1
B_PRE1/SDA_CTL
9
R2D Passive DeEmphasis
SATARDRVR_I2C_EN_L
10
I2C_EN*
VALUE: 3.0 DB
SATARDRVR_TEST
18
TEST
85
0.01UF
REXT
20
SATARDRVR_REXT
19
=SATARDRVR_I2C_SCL
17
=SATARDRVR_I2C_SDA
C4532 0.1UF
1
5% 1/16W MF-LF 402 2
0402 10% 16V X7R-CERM
2
10% 16V 0402 X7R-CERM PLACE_NEAR=U4510.11:5MM GND_VOID=TRUE
IN BI
48
48
SYNC_MASTER=YONAS_J30
R4512
1
SATA/IR/SIL Connectors
1% 1/16W MF-LF
2
DRAWING NUMBER
Apple Inc.
402
338S0907 CRITICAL
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
7
6
5
4
3
SYNC_DATE=11/08/2011
PAGE TITLE
3.74K
3 3 1 1 2
R4511 0
0402
2
C4512 1
SATA_HDD_R2D_RDRIN_P
GND THRM PAD
10% 16V 2 X7R-CERM
C4513 1
SATA_HDD_R2D_RDRIN_N
0402 10% 16V X7R-CERM
PP5V_S3_IR_R
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V
8
41
=PP1V5_S0_RDRVR
GND_VOID=TRUE
+/-0.1PF C0G
R45351
80 6
1
46
=PP1V5_S0_RDRVR
1% 1/20W MF 201
C4536 5.0PF
516S0687
6
OUT
GND_VOID=TRUE 80 6
R45341
=PP5V_S3_IR
SMC_SSD_OOBD2R_L
NOSTUFF
F-ST-SM 1
2
20% 2 10V CERM 402
5% 1/16W MF-LF 4022
5% 1/16W MF-LF 4022
D2R Passive DeEmphasis
0
C4584 0.1UF
4.7K
4.7K
J4501
1
5% 1/16W MF-LF 402
R45131
R45101
6 44
C
R4586
SMC_SSD_OOBD2R_R_L
41 7
1
IR_RX_OUT
1
5% 1/16W MF-LF 402
Address (R/W)
0402
B
SC70-5 4
GND 2
1
402
Read:0xB7
ADDR1 PLACE_NEAR=J4501.7:10MM PLACE_NEAR=J4501.7:10MM
6
SSD_OOBD2R_R_L1
5% 1/16W MF-LF
SATA Internally PDRedriver ~150K
1
20% 10V
1K
LMV331 VCC+
2
C4501 0.1UF 20% 10V
16 80
U4580
5
3
SSD_OOB1V0REF
1
20% 10V
16 80
OUT
R4585
2
PLACE_NEAR=U4580.8:2MM
R4582
7
CRITICAL
C4538 100UF
OUT
1
0.1UF
20% 10V 2 CERM 402
R4583
5% 1/16W MF-LF 2 402
2
C4580
1
L4500
20% 10V
SATA_ODD_D2R_N
GND_VOID=TRUE
2 GND_VOID=TRUE SATA_ODD_D2R_P 10% 16V X7R-CERM 0402
1
FERR-70-OHM-4A
C4537 100UF
0.01UF
2
10% 16V X7R-CERM 0402
=PP3V3_S0_SMC
100K
1
16 80
=PP1V5_S0_RDRVR
R4581
1
16 80
IN
Notes: OOBD2R was OOB_TEMP, from SSD, to SMC OOBR2D was TEMP_CTL, from SMC, to SSD
1
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.4MM VOLTAGE=5V
IN
2 GND_VOID=TRUE SATA_ODD_R2D_C_N 10% 16V X7R-CERM 0402
SATA OOB Comparator
SMC_ODD_DETECT
7
A
85 6
85 6
0.01UF
516S0616
Note: Indicates disc presence.
PP5V_S0_HDD_FLT
0.01UF
2 GND_VOID=TRUE SATA_ODD_R2D_C_P 10% 16V X7R-CERM 0402
D
8 10
5% 1/16W MF-LF 4022
5 G
6
0.01UF
33K
ODD_PWR_EN_L
C
C4520 1
R45901
SOT563
IN
2
=PP3V3_S0_ODD
D 3
SSM6N37FEAPE
19
C4521 1
SATA_ODD_R2D_N
CRITICAL 41 7
Q4596
SATA_ODD_R2D_P
80 6
J4500
54722-0164
C4596 0.01UF
SSM6N37FEAPE
1
80 6
G
X5R-CERM 2 0402
ODD_PWR_EN_LS5V_L 41 7
4
0.068UF
100K
D
PP5V_SW_ODD
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.4MM VOLTAGE=5V
D
1
C4595 1
R45961 Note: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.
S
1
SATA ODD Connector
DFN2563-6 7
2
3
Q4590 CRITICAL DMP2018LFK
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
45 OF 109 SHEET
41 OF 86
1
A
8
7
6
5
4
2
3
D
USB Port Power Switch
D
1
USB Port A (Front Port)
CRITICAL CRITICAL
U4600
L4605
TPS2561DR
FERR-120-OHM-3A
SON 7
2
=PP5V_S3_USB
3
23 23
OUT1 OUT2
9
FAULT1* ILIM
7
IN_0 IN_1
OUT
USB_EXTA_OC_L
10
OUT
USB_EXTB_OC_L
6
FAULT2*
4
EN1
5
EN2
73
=USB_PWR_EN
CRITICAL
C4690
1
1
1
C4691 0.1UF
10UF
20% 6.3V X5R 603
2
2
43
PAD
1
1 1
PP5V_S3_USB_A_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
1
0.01UF
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
20% 16V X7R-CERM 0402
CRITICAL
CRITICAL 2
J4600
L4600 90-OHM-100MA DLP11S
USB-3.0-J30 F-RT-TH
SYM_VER-1
THRM
GND
C4696
2 0603
C4605
PP5V_S3_USB_B_ILIM
USB_ILIM
R4600
1
23.2K 1% 1/16W MF-LF 402
220UF-35MOHM
20% 10V CERM 402
1
PP5V_S3_USB_A_ILIM MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
8
20% 2 6.3V POLY-TANT CASE-B2-SM1
2
C4695
1
10UF
C4617
1
80
USB_EXTA_MUXED_N
4
3
80
USB_EXTA_MUXED_P
1
2
1
10UF 20% 6.3V X5R 603
20% 6.3V 2 X5R 603
80
2
80
USB_EXTA_MUXED_F_N
2
USB_EXTA_MUXED_F_P
3 4
2 5 6 VBUS
Current limit per port (R4600): 2.18A min / 2.63A max
3
4
C O C O I N I N
USB3_EXTA_RX_F_N
5
80
USB3_EXTA_RX_F_P
6
80
USB3_EXTA_TX_F_N
8
80
USB3_EXTA_TX_F_P
9
7
1 GND
C
80
D4600
10
RCLAMP0582N
11
SLP1210N6
VBUS DD+ GND
STDA_SSRXSTDA_SSRX+ GND_DRAIN
STDA_SSTXSTDA_SSTX+
C
12
CRITICAL
13 14 15
SHIELD
16
GND_VOID=TRUE
17
CRITICAL
18
L4610 80OHM-25%-100MA 0504
L2
Mojo SMC Debug Mux
80 18
OUT
USB3_EXTA_RX_N
4
80 18
OUT
USB3_EXTA_RX_P
1
3
2
L1 7
=PP3V42_G3H_SMCUSBMUX MOJO:YES 1
MOJO:YES
C4650
1
46 45 46 45
IN
SMC_DEBUGPRT_RX_L
OUT
SMC_DEBUGPRT_TX_L
20% 10V CERM 2 402
R4650 10K
9
0.1UF
VCC 2 5
M+
Y+
1
4
M-
Y-
2
U4650
5% 1/16W MF-LF 402
PI3USB102ZLE
B
80 18
BI
USB_EXTA_P
7
D+
80 18
BI
USB_EXTA_N
6
D-
8
GND_VOID=TRUE
TQFN
CRITICAL
CRITICAL
L4620
MOJO:YES
OE*
SEL
SMC_DEBUGPRT_EN_L
10
GND
SEL=0 Choose SMC
3
SEL=1 Choose USB
SIGNAL_MODEL=MOJO_MUX
45
L2
0.1UF 80 18
IN
80 18
IN
USB3_EXTA_TX_N
1
2
80
USB3_EXTA_TX_C_N
4
80
USB3_EXTA_TX_C_P
1
3
C4621 10% X5R
USB3_EXTA_TX_P
6.3V 201
0.1UF 1
2
2
L1
R4651
10% X5R
0 2 5% 1/16W MF-LF 402
0504
GND_VOID=TRUE
C4620
MOJO:NO 1
B
80OHM-25%-100MA IN
6.3V 201
GND_VOID=TRUE
2
4
5
D4610
R4652 0
1
1
CRITICAL
MOJO:NO
PGTSLP91-XSON-COMBO
2 5% 1/16W MF-LF 402
ESD3V3U4ULC-IP4292CZ10 D N G
C N
3 6 7 8 9
A
S YN C_ MA ST ER =J 31 _M LB
S YN C_ DA TE =0 7/ 08 /2 01 1
PAGE TITLE
External A USB3 Connector DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
46 OF 109 SHEET
42 OF 86
1
A
8
7
6
5
4
2
3
1
D
USB Port B (Back Port)
D
CRITICAL
L4705 FERR-120-OHM-3A 42
1
PP5V_S3_USB_B_ILIM MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
2
PP5V_S3_USB_B_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V
0603
C4705
1
0.01UF 20% 16V X7R-CERM 0402
CRITICAL 2
CRITICAL
J4700
L4700
USB-3.0-J30
90-OHM-100MA DLP11S
F-RT-TH
SYM_VER-1
80 25
BI
USB_EXTB_MUX_N
4
80 25
BI
USB_EXTB_MUX_P
1
3
2
1
USB_EXTB_F_N
2
USB_EXTB_F_P
3
80 80
4 2 5 6 VBUS
3
4
C O C O N I N I
1 GND
C
80
USB3_EXTB_RX_F_N
5
80
USB3_EXTB_RX_F_P
6 7
80
USB3_EXTB_TX_F_N
8
80
USB3_EXTB_TX_F_P
9
D4700
10
RCLAMP0582N
11
SLP1210N6
VBUS DD+ GND
STDA_SSRXSTDA_SSRX+ GND_DRAIN
STDA_SSTXSTDA_SSTX+
C
12
CRITICAL
13 14 15
SHIELD
16
GND_VOID=TRUE CRITICAL
17
L4710
18
80OHM-25%-100MA 0504
L2 80 18
OUT
USB3_EXTB_RX_N
4
80 18
USB3_EXTB_RX_P
1
OUT
3
2
L1
GND_VOID=TRUE CRITICAL
B
B
L4720 80OHM-25%-100MA 0504
GND_VOID=TRUE
C4720
L2
0.1UF 80 18
IN
80 18
IN
USB3_EXTB_TX_N
1 10% X5R
USB3_EXTB_TX_P
2 6.3V 201
80
USB3_EXTB_TX_C_N
4
80
USB3_EXTB_TX_C_P
1
3
C4721 0.1UF 1
2
2
L1 10% X5R
6.3V 201
GND_VOID=TRUE
1
CRITICAL
2
4
5
D4710 PGTSLP91-XSON-COMBO
ESD3V3U4ULC-IP4292CZ10 D N G
C N
3 6 7 8 9
NOTE: Swapped pin4 and 5, pin6 and 7 for layout.
A
S YN C_ MA ST ER =J 31 _M LB
S YN C_ DA TE =0 7/ 08 /2 01 1
PAGE TITLE
External B USB3 Connector DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
47 OF 109 SHEET
43 OF 86
1
A
8
7
6
5
4
3
2
1
IR SUPPORT D
41 7
D
=PP5V_S3_IR
1
C4801 0.1UF
2
10% 16V X7R-CERM 0402 4 1
VCC
U4800 CY7C63803-LQXC QFN 80 8
BI
80 8
BI
DIFFERENTIAL_PAIR=USB2_TPAD
USB_IR_P
12
P1.0/D+
USB_IR_N
13
P1.1/D-
DIFFERENTIAL_PAIR=USB2_TPAD
IR_VREF_FILTER 15 P1.2/VREG
1
C4803 1UF
2
10% 10V X5R 402-1
P0.0
7
P0.1
6
INT0/P0.2 5
16
P1.3/SSEL
INT1/P0.3 4
17
P1.4/SCLK
INT2/P0.4 3
18
P1.5/SMOSI
TIO0/P0.5
2
19
P1.6/SMISO
TIO1/P0.6
1
8
R4800 1
IR_RX_OUT_RC
9
1 10
P/N 338S0633
2
IR_RX_OUT
IN
6 41
C4804 0.001UF
20 21
100 5% 1/16W MF-LF 402
CRITICAL OMIT
NC
2
10% 50V X7R-CERM 0402
22
C
C
23 24
THRML PAD 5 2
VSS 1 1
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Front Flex Support DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
48 OF 109 SHEET
44 OF 86
1
A
8
7
6
5
4
2
3
1
D
D U4900 LM4FSXAH5BB 81 47 16 6
BI
81 47 16 6
BI
81 47 16 6
BI
81 47 16 6
BI
81 24
IN
81 47 16 6
IN
24
IN
47 16 6
BI
47 17 6
OUT
47 17 6
IN
19
OUT
46
OUT
84 48
BI
84 48
BI
84 48
C
BI
84 48
BI
84 48 6
BI
84 48 6
BI
84 48
BI
84 48
BI
46
BI
46
BI
84 48 6
BI
84 48 6
BI
52
OUT
52
IN
46
OUT
46
IN
46
OUT
46
OUT
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK33M_SMC LPC_FRAME_L SMC_LRESET_L LPC_SERIRQ PM_CLKRUN_L LPC_PWRDWN_L SMC_RUNTIME_SCI_L SMC_WAKE_SCI_L SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_4_ASF_SCL SMBUS_SMC_4_ASF_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SMC_FAN_0_CTL SMC_FAN_0_TACH SMC_FAN_1_CTL SMC_FAN_1_TACH SMC_MPM5_LED_PWR SMC_MPM5_LED_CHG
(OD) (OD)
(OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) NC FOR ENG PKG NC FOR ENG PKG (OD) (OD)
BGA
B13 LPC0AD0 A13 LPC0AD1
(1 OF 2)
C12 LPC0AD2 D11 LPC0AD3
OMIT
AIN00
E2
AIN01
E1
AIN02
F2
AIN03
F1
H12 LPC0CLK D12 LPC0FRAME*
AIN04
B3
AIN05
A3
C13 LPC0RESET* H13 LPC0SERIRQ
AIN06
B4
AIN07
A4
G11 LPC0CLKRUN* F13 LPC0PD*
AIN08
B5
AIN09
A5
F12 LPC0SCI* B12 PK5
AIN10
B6
AIN11
A6
AIN12
C1
E10 I2C0SCL D13 I2C0SDA
AIN13
C2
AIN14
B1
M4 I2C1SCL N2 I2C1SDA
AIN15
B2
AIN16
G2
N8 I2C2SCL M8 I2C2SDA
OUT
46
OUT
46
BI
63 46 41 6
46 46
IN IN IN
IN OUT
SMC_SYS_KBDLED SMC_T25_EN_L SYS_TDM_ONEWIRE SYS_ONEWIRE HISIDE_ISENSE_OC SMC_ODD_DETECT
46 46
B
46 73 46
IN IN IN IN OUT
IN
46
OUT
55
IN
63 46
IN
46
IN
73 26 17 8 6
IN
73 32 26 17 6
IN
73 17
IN
53 46
IN
47 46 6 47 46 6
IN OUT
BI
80 8
BI
46
IN
46
IN
46
IN
46
IN
46
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
IN
46
IN
46
IN
46
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
H1 H2
AIN20
B7
N7 I2C4SCL M7 I2C4SDA
AIN21
A7
AIN22
B8
N4 I2C5SCL N3 I2C5SDA
AIN23
A8
C0-
K2
CPU_PROCHOT_L
C0+ C1-
K1 L2
SMC_VCCIO_CPU_DIV2 SMC_S5_PWRGD_VIN SPI_DESCRIPTOR_OVERRIDE_L OUT CPU_CATERR_L IN CPU_THRMTRIP_3V3 IN
PC5/C1+ L1
PK7/FAN0TACH1
T3CCP1/PJ5/C2- C5
PN2/FAN0PWM2
T3CCP0/PJ4/C2+ D5
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
1.2V FOR ENG PKG
IN
46
IN
=PP3V3_S5_SMC
7 46
L4901
30-OHM-1.7A 1
L11 PN4/FAN0PWM3 N12 N11 M11
C4902
1
1UF 20% 10V
2 CERM 603
C4903
1
2 CERM 402
1
20% 10V
2 CERM 402
C4905 0.1UF
0.1UF
0.1UF 20% 10V
C4904
20% 10V
2 CERM 402
1
(OD)
SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT
SSI0FSS/PA3 M3 SSI0RX/PA4 L4
PN6/FAN0PWM4 PN7/FAN0TACH4
SSI0TX/PA5 N1
C4 PECI0RX C6 PECI0TX
SMC_BIL_BUTTON_L SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_S4_WAKESRC_EN
M13 PP0/IRQ116 L12 M5 J12
NC NC
SMC_LID (OD)
U1RX/B0 F11 U1TX/PB1 E11 T0CCP0/PB6 F4 T0CCP1/PB7 F3
PP1/IRQ117
SSI1CLK/PF2 L10
PP2/IRQ118
SSI1FSS/PF3 K10
PP3/IRQ119
PF4
L9
PF5
K9
SPI_SMC_MISO NC FOR SPI_SMC_MOSI NC FOR SPI_SMC_CLK NC FOR SPI_SMC_CS_L NC FOR S5_PWRGD PM_PCH_SYS_PWROK
1M
0.1UF
2 CERM 402 64 47 46
46 32
1
C4907 0.1UF
20% 10V 2 CERM 402
1
C4908 0.1UF
20% 10V 2 CERM 402
1
IN
BI
C4909 0.1UF
20% 10V 2 CERM 402
SMC_RESET_L
G10
WIFI_EVENT_L(OD) SMC_WAKE_L NC_SMC_HIB_L
B11 PK4/RTCCLK N13 WAKE*
46
IN
SMC_CLK32K NC_SMC_XOSC1
M10 XOSC0 N10 XOSC1
SWCLK/TCK C10 A10 SWDIO/TMS A11
SWO/TDO
TDI B10
SMC_EXTAL SMC_XTAL
G12 OSC0 G13
VREFA+
OSC1
VREFA-
WT3CCP1/PH5 H4
PQ5/IRQ129 PQ6/IRQ130
WT4CCP0/PH6 H3 WT4CCP1/PH7 G4
17
OUT
24 35 46
OUT
46
46
D1
XW4900 SM
GND_SMC_AVSS
E3
2
1
PLACE_NEAR=U4900.A1:4MM
C7 D9
VDD
E5
J9
F9
J10
46
46
H5 GND
J1
PP1V2_S5_SMC_VDDC MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V
J6
46 81
D6
STACK BRD
OUT
STACK BRD
OUT
1
C4920
1
0.01UF
H9
10% 10V 2 X5R-CERM
J5 J8
0201
C4921 1UF 10% 10V
2 X5R 402
J11
VDDC
K11
46 81 46 81
IN
73
IN
17 23 24
OUT
42
IN
46
IN
23 24 73
B 1
C4910 1UF
OUT
46
OUT
17 23
OUT
17 24
OUT
PP3V3_S5_AVREF_SMC
D2
A1
E9
42 46
46
BI
GNDA
J7
OUT
C
6 46 47
E6
F10
42 46
6 46 47
50
E8
OUT
6 46 47
NC
C3 49 46
46
OUT
PM_PWRBTN_L PM_SYSRST_L MEM_EVENT_L (OD) SMC_ADAPTER_EN
WT3CCP0/PH4 J3
PQ4/IRQ128
A2
K12 VBAT
10 78
OUT
6 46 47
VDDA D3 46 46
24
STACK BRD
ALL_SYS_PWRGD SMC_THRMTRIP
WT2CCP1/PH1 K4
SMC_TCK SMC_TMS SMC_TDO SMC_TDI
OMIT
10 46 68 78
46
K13
WT2CCP0/PH0 K3
L6
RST*
M12 HIB*
46 81
D4 PQ0/IRQ124 E4 PQ1/IRQ125
0.1UF
BGA
NC
46
6 73
BI
C4901
20% 2 10V CERM 402
LM4FSXAH5BB (2 OF 2)
OUT
IN
1
U4900
5% 1/20W MF 2 201
20% 10V
IN
SMC_DEBUGPRT_EN_L SMC_GFX_OVERTEMP
M6
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V
R4902
STACK BRD
WT0CCP0/PG4 K7 WT0CCP1/PG5 L7
K5
10% 2 25V X5R 402
1
C4911 1UF
10% 2 25V X5R 402
1
C4912 1UF
10% 2 25V X5R 402
1
C4913 0.1UF
20% 2 10V CERM 402
1
C4914 0.1UF
20% 2 10V CERM 402
1
C4915 0.1UF
20% 2 10V CERM 402
1
C4916 0.1UF
20% 2 10V CERM 402
1
C4917 0.1UF
20% 2 10V CERM 402
NOSTUFF
27 29 46 17 46 73
PQ7/IRQ131
L3 U0RX M1
U0TX
USB_SMC_N USB_SMC_P
SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L SMC_SYS_LED SMC_GFX_THROTTLE_L
D8 PP6/IRQ122 K6 PP7/IRQ123
N6
SMC_RX_L SMC_TX_L
SSI1TX/PF1 N9
J13 PP4/IRQ120 L5 PP5/IRQ121
F5 PQ2/IRQ126 N5 PQ3/IRQ127
PP3V3_S5_SMC_VDDA
1
C4906
D7
PN5/FAN0TACH3
J4 PH2/FAN0PWM5 J2 PH3/FAN0TACH5
2
0402 1
D10 PN3/FAN0TACH2
NC FOR STACK BRD
SMC_OOB1_RX_L SMC_OOB1_TX_L SMC_IR_RX_OUT_RC BDV_BKL_PWM
T1CCP0/PJ0 C9 T1CCP1/PJ1 B9 T2CCP0/PJ2 A9 T2CCP1/PJ3 C8
80 8
46
IN
G1
G3
CPU_PECI_R SMC_PECI_L
ENET_ASF_GPIO SMS_INT_L SMC_BC_ACOK G3_POWERON_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L
46
IN
AIN17
C11 PK6/FAN0PWM1 A12
NC FOR ENG PKG 63 53 46
46
IN
AIN19
SSI1RX/PF0 M9 63 46 6
46
IN
AIN18
SSI0CLK/PA2 M2 54
IN
L8 I2C3SCL K8 I2C3SDA
H11 PM6/FAN0PWM0 L13 PM7/FAN0TACH0
NC FOR STACK BRD
SMC_ADC0 SMC_ADC1 SMC_ADC2 SMC_ADC3 SMC_ADC4 SMC_ADC5 SMC_ADC6 SMC_ADC7 SMC_ADC8 SMC_ADC9 SMC_ADC10 SMC_ADC11 SMC_ADC12 SMC_ADC13 SMC_ADC14 SMC_ADC15 SMC_ADC16 SMC_ADC17 SMC_ADC18 SMC_ADC19 SMC_ADC20 SMC_ADC21 SMC_ADC22 SMC_ADC23
E13 USB0DM E12 USB0DP
WT5CCP1/PM3 H10
SMC_BATLOW_L
NC FOR ENG PKG
IN
46
OUT
46
NC FOR ENG PKG
IN
46
NC FOR ENG PKG
OUT
46
OUT
46 73
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
A
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
S YN C_ MA ST ER =Y ON AS _J 30
S YN C_ DA TE =1 2/ 21 /2 01 1
PAGE TITLE
SMC DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
49 OF 109 SHEET
45 OF 86
1
A
8
7
6
5
SMC Reset "Button", Supervisor & AVREF Supply 46 45 7
7
C5020
1
1
53
IN
53 46 45
IN
VREF-3.3V-VDET-3.0V
C5001
0
2
MR1*
DFN (IPU) SN0903048
7
MR2*
(IPU)
4
DELAY
6
RESET*
5
CRITICAL REFOUT
8
OUT
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V
THRM 9
2
C5025 1 10uF
10%
16V 2 X7R-CERM 0402
20% 2 6.3V X5R 603
SILK_PART=SMC_RST
1
45 47 64
45
C5026 0.01UF
10% 16V 2 X7R-CERM
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.1MM VOLTAGE=0V
SMC_ONOFF_L OMIT
45 46 53
SMC_ADC6
45
SMC_ADC7
45
SMC_ADC8
45
SMC_ADC9
45
SMC_ADC10
45
SMC_ADC11
45
SMC_ADC12
45
SMC_ADC13
45
SMC_ADC14
45
SMC_ADC15
45
SMC_ADC16
45
SMC_ADC17
45
SMC_ADC18
45
SMC_ADC19
45
SMC_ADC20
45
0
5% 1/10W MF-LF 2603
SILK_PART=PWR_BTN PLACE_SIDE=BOTTOM
SMC_ADC5
45
SMC_ADC22 SMC_ADC23
SILK_PART=PWR_BTN PLACE_SIDE=TOP
SMC Crystal Circuit Note: ADC10 and ADC11 are shared with comparators on Stack Board.
SMC USB Clock require these crystal values:5,6,8,10,12,16,18,20,24,25 MHz
R5010 45
SMC_XTAL
2.49K
1
1% 1/20W MF 201
Y5010 3.2X2.5MM-SM 12.000MHZ-30PPM-10PF
45
SMC_EXTAL
1
NC 1
3 2
4
NC
CRITICAL
C5010
1
12PF
C5011 12PF
5% 50V 2 C0G-CERM
Note: Pull-up for SMC_PME_S4_DARK_L are in page33 (R3315).
5% 50V 2 C0G-CERM
0402
0402
B
78 68 45 10
SMC_DCIN_VSENSE
=PPVCCIO_S0_SMC
SMC_DCIN_ISENSE
50
SMC_PBUS_VSENSE
50
SMC_HDD_ISENSE
49
MAKE_BASE=TRUE MAKE_BASE=TRUE
SMC_BMON_ISENSE
CRITICAL
45
19
SMC_OTHER_HI_ISENSE
50
SMC_MEM_ISENSE
49
SMC_CPUVCCIO_ISENSE
49
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_AXG_VSENSE
OUT
IN
3
2
SMC_THRMTRIP
IN
R5054
MAKE_BASE=TRUE
NC_SMC_ADC16
46 45
MAKE_BASE=TRUE
OUT
CPU_THRMTRIP_3V3
45
CPU_PECI_R
OUT
Q5058
49
MAKE_BASE=TRUE
PM_THRMTRIP_B_L1
1
MMBT3904LP-7
NC_SMC_ADC19
DFN1006-3
MAKE_BASE=TRUE
3.3K
PM_THRMTRIP_L
2
R5020
IN
Series resistors are no stuffed until the topology of 2 SPI Masters are verified.
NC_SMC_ADC21
MAKE_BASE=TRUE
NC_SMC_ADC22 SMC_ADC23
45 46
MAKE_BASE=TRUE
SMC_GFX_THROTTLE_L
45
SMC_FAN_1_CTL
R5021 NO
NC_SMC_GFX_OVERTEMP
MAKE_BASE=TRUE
81 45
NO STUFF
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
81 45
NC_ENET_ASF_GPIO
ENET_ASF_GPIO
45
SMC_MPM5_LED_PWR
45
SMC_MPM5_LED_CHG
81 45
MAKE_BASE=TRUE
NO STUFF 81 45
MAKE_BASE=TRUE
SYS_TDM_ONEWIRE SMC_OOB1_RX_L
45
SMC_OOB1_TX_L
45
SMC_SSD_OOBR2D_L
41
SMC_BC_ACOK
CRITICAL
Q5020
A
45 46 63
DP_A_EXT_HPD
NC_SMBUS_SMC_4_ASF_SCL
53 46 45
MAKE_BASE=TRUE
SMBUS_SMC_4_ASF_SDA BDV_BKL_PWM
NC_BDV_BKL_PWM
45
SMC_PME_S4_DARK_L
SDCONN_STATE_CHANGE_SMC
45
SCM12 Eng Pkg Support
NC_SMBUS_SMC_4_ASF_SDA
MAKE_BASE=TRUE
63 53 45 47 45 6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
47 45 6 24 30 45
19
SMC_SCI_L
SMC_WAKE_SCI_L
45
SMC_T25_EN_L
NC_SMC_T25_EN_L
45
SMC_IR_RX_OUT_RC
NC_SMC_IR_RX_OUT_RC
PP1V2_S5_SMC_VDDC
45 42
1
R5099
2
PLACE_NEAR=U1800.N14:5MM
47 45 6
0
47 45 6
5% 1/16W MF-LF 2402
MAKE_BASE=TRUE
R5012 22
45 42
45
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_ADC23
47 45 6 47 45 6 63 45 6
SMC_PACKAGE:ENG SMC_CLK32K 5 % 1 / 20 W
OUT
MF 2 0 1
45
46 7
63 46 45
=PPVCCIO_S0_SMC
45
SMC_VCCIO_CPU_DIV2
45 29 27 46 45
2
1% 1/16W MF-LF 402
47
IN
=PSOC_WAKE_L
32
IN
=BT_WAKE_L
20
PLACE_NEAR=U6100.1:1MM
6
5
4
D
B
E
R5070 R5072 R5071 R5073 R5074 R5075 R5076 R5077 R5078 R5079 R5080 R5081 R5087 R5092
MEM_EVENT_L CPU_THRMTRIP_3V3
R5014 R5017
10K 10K
1 1
2
100K
1
2
10K
1
2
100K
10K
2
1
2
1
2
100K
1
2
10K 10K 10K 10K 10K
1
2
1
2
1
2
1
2
470K 100K
1
2
1
2
10K 100K
1 1
2 2
1
2
5%
1/20W
MF MF
201
5%
1/20W
5%
1/20W
MF
5%
1 /2 0W
MF
2 01
5%
1 /2 0W
MF
2 01
201
5%
1/20W
MF
201
5%
1/20W
201
MF
201
5%
1/20W
MF
201
5%
1 /2 0W
MF
2 01
5% 1/20W
MF
5%
1 /2 0W
MF
5%
1 /2 0W
MF
2 01
5%
1/20W
MF
201
MF
B
201 2 01
5%
1/20W
5%
1/20W
MF
201
5%
1/20W
MF
201
201
5% 1/20W
MF
SMC_ROMBOOT
SMC_ADAPTER_EN
1
2
SMC_DELAYED_PWRGD
R5086 R5085 R5091
10K
45 35 24
100K
1
2
73 45
SMC_S4_WAKESRC_EN
R5090
100K
46 45
SMC_THRMTRIP
10K
1
2
1
201
5%
1 /2 0W
MF
2 01
5%
1/20W
MF
201
5%
1 /2 0W
MF
2 01
2
PP3V3_WLAN
R50401 100K
SOT-563
5% 1/20W MF 2012
Q2 Q1 73 45
S
G
C
1
2
3
IN
SMC_BATLOW_L
CRITICAL
SMC_SYS_LED
6
10K
1
2
VESM
D
S
5
OUT
5% 1/16W MF-LF 402
41
4
MF
2 01
SYNC_DATE=01/02/2012
DRAWING NUMBER
PM_BATLOW_L
OUT
Apple Inc.
17
R
2
Internal 20K pull-up on PM_BATLOW_L in PCH.
R5041 SYS_LED_ANODE
1 /2 0W
SMC Support
G
0
5%
PAGE TITLE
SSM3K15AMFVAPE 1
1 IN
R5089
SYNC_MASTER=YONAS_J30
Q5040
3
45
45
WIFI_EVENT_L
CRITICAL
Q5030
SYS_LED_L
R5082 100K
7
=PP3V3_S5_SMC
46 45 7
SMC_ONOFF_L G3_POWERON_L SMC_LID SMC_TX_L SMC_RX_L SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BIL_BUTTON_L SMC_BC_ACOK SMC_S5_PWRGD_VIN
73 45 17
=PP3V3_SUS_SMC 7
=PP3V3_S5_SMCBATLOW
DMB54D0UV
7 46
OUT
47 56 81
1K
45 32
1% 1/20W MF 2012
SMC_PME_S4_WAKE_L
47 56 81
OUT
R5088
BATLOW# Isolation 7
1.47K
S 2
OUT
5% 1/20W MF 2 201
1% 1/16W MF-LF 2402
R50321
D 3
MAKE_BASE=TRUE
8
SPI_MLB_CS_L
C
1
1% 1/16W MF-LF 2402
R5030
5% 1/20W MF 2201 53
2
Notes: OOBD2R was OOB_TEMP, from SSD, to SMC OOBR2D was TEMP_CTL, from SMC, to SSD
MAKE_BASE=TRUE
45
1 IN
0
1
32 6
=PP3V3_S4_SMC 75
STUFF SPI_MLB_CLK
47 56 81
45
VESM
G
2
5% 1/16W MF-LF 402
SYS_LED_L_VDIV OUT
SSM3K15AMFVAPE
1
0
1
47 56 81
OUT
NC_HISIDE_ISENSE_OC
45
PM_CLK32K_SUSCLK_R1
R5023 NO
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
SMBUS_SMC_4_ASF_SCL
PLACE_NEAR=U6100.5:1MM
OUT
41
MAKE_BASE=TRUE
HISIDE_ISENSE_OC
SPI_SMC_CS_L
IN
NC_SYS_TDM_ONEWIRE
MAKE_BASE=TRUE
45
SPI_MLB_MOSI
R5024
MAKE_BASE=TRUE
SMC_SSD_OOBD2R_L
=CHGR_ACOK
2
STUFF SPI_MLB_MISO
PLACE_NEAR=U6100.2:1MM
PLACE_NEAR=U6100.6:1MM
NC_SMC_MPM5_LED_PWR
MAKE_BASE=TRUE
NC_SMC_MPM5_LED_CHG
2
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
SPI_SMC_CLK
IN
0
1
MAKE_BASE=TRUE
45
45
SPI_SMC_MOSI
IN
0
1
R5022
NC_SMC_FAN_1_TACH
SMC_FAN_1_TACH
45
SPI_SMC_MISO
IN
NC_SMC_GFX_THROTTLE_L
MAKE_BASE=TRUE
SYS_LED_ILIM
SMC_DP_HPD_L
10 19 78
MAKE_BASE=TRUE
1
100K
BI
From/To CPU/PCH.
10 19 78
R5096
5% 1/20W MF 2 201
CPU_PECI
SMC12 SPI Support
402
100K
1
2
402
5% 1/16W MF-LF
CRITICAL 2
NC_SMC_ADC20
MAKE_BASE=TRUE
43
5% 1/16W MF-LF
R5058
3
SMC_AXG_ISENSE
1
523
1
To SMC.
NC_SCM_ADC17
MAKE_BASE=TRUE
45
1% 1/20W MF 2012
NOSTUFF
45 46
NC_SMC_ADC15
=PP5V_S3_SYSLED
R50311
5% 1/16W MF-LF 402
2
S G 5
NC_SMC_ADC14
MAKE_BASE=TRUE
System (Sleep) LED Circuit
7 46
330
5% 1/16W MF-LF 402
100K
=PP3V3_S4_SMC
R5051
1.6K
2
CRITICAL 4
D
1
R5053
SOT563
NC_SMC_ADC13
S 2
1
SSM6N15AFE
MAKE_BASE=TRUE
G
SMC_PECI_L_R
5% 1/16W MF-LF
Q5059
D
R5097
7
0
1
402
1
S4 HPD SMC Wake Source
SMC_PECI_L
From SMC.
PM_THRMTRIP_L_R
49
MAKE_BASE=TRUE
1
R5052
50
MAKE_BASE=TRUE
SMC_GFX_OVERTEMP
IN
VESM
IN
45
SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
D 3
SSM3K15AMFVAPE
S G 2
SMC_PROCHOT
46 45
17
Q5050
SOT563
1
7 46
CRITICAL
SSM6N15AFE
50
MAKE_BASE=TRUE
Q5059
D
50
MAKE_BASE=TRUE
1
SMC12 PECI Support
CPU_PROCHOT_L
BI
6
MAKE_BASE=TRUE
45
64 50
SMC_XTAL_R
2
49
NC_SMC_ADC2
45
45
49
SMC_CPU_ISENSE
MAKE_BASE=TRUE
SMC_ADC21
45
SMC_CPU_VSENSE
MAKE_BASE=TRUE
2
3
MAKE_BASE=TRUE
SMC_ADC4
45
46 45
R5015
5% 1/10W MF-LF 6032
C
OUT
1
0
SMC_ADC3
45 49 50
Debug Power "Buttons" OMIT
45
0402
GND_SMC_AVSS
PLACEMENT_NOTE=Place R5001 on BOTTOM side
MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.
R50161
SMC_ADC2
PAD
GND 1
SMC_RESET_L PP3V3_S5_AVREF_SMC
0.01UF
5% 1/10W MF-LF 603
SMC_ADC1
45
45
5% 1/16W MF-LF 2 402
SMC_ADC0
45
100K
U5010
402
SMC_MANUAL_RST_L OMIT
R5001
R5000
VIN
10%
SMC_TPAD_RST_L SMC_ONOFF_L
1
1
3
V+
0.47UF
6.3V CERM-X5R 2
D
45
=PP3V3_S5_SMC =PPVIN_S5_SMCVREF Desktops: 5V Mobiles: 3.42V
4
2
NOSTUFF
3
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
50 OF 109 SHEET
46 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
LPC+SPI Connector CRITICAL LPCPLUS_CONN:YES
J5100 55909-0374 M-ST-SM 7
=PP3V3_S5_LPCPLUS
7
=PP5V_S0_LPCPLUS
81 45 16 6
BI
81 45 16 6
BI
31
LPC_AD<0> LPC_AD<1>
32
1
2
LPC_CLK33M_LPCPLUS
3
4
LPC_AD<2>
5
6
LPC_AD<3>
7
8
BI BI
47 6
IN
SPI_ALT_MOSI
9
10
SPIROM_USE_MLB
47 6
OUT
SPI_ALT_MISO
11
12
SPI_ALT_CLK
LPC_FRAME_L
13
14
45 17 6
OUT
PM_CLKRUN_L
15
16
46 45 6
OUT
SMC_TMS
17
18
LPC_PWRDWN_L
IN
LPCPLUS_RESET_L
19
20
SMC_TDI
46 45 6
OUT
SMC_TDO
21
22
TP_SMC_TRST_L
23
TP_SMC_MD1
25
26
46 45 6
IN
SMC_TX_L
27
28
29
30
LPCPLUS_GPIO
81 45 16 6
24 6
IN
C
OUT
SPI_ALT_CS_L LPC_SERIRQ
24
33
IN
6 24 81 6 16 45 81 6 16 45 81
6 19 56
IN
6 47
IN
6 47
BI IN
6 16 45 6 17 45
OUT
6 45 46
SMC_TCK
OUT
6 45 46
SMC_RESET_L
OUT
45 46 64
SMC_ROMBOOT
OUT
46
SMC_RX_L
OUT
6 45 46
OUT
6 19
C
34
516S0573
SPI Bus Series Termination SPI_ALT_MISO SPI_ALT_MOSI
LPCPLUS_R:YES
1
LPCPLUS_R:YES
1
R5128 0
2
PLACE_NEAR=U1800.AV3:5mm 81 16
IN
B
PLACE_NEAR=U1800.BA2:5mm 81 16
IN
81 16
81 16
IN
OUT
15 1
R5112 1
SPI_MOSI_R
1
R5111
SPI_CLK_R
PLACE_NEAR=U1800.AY1:5mm
15
2
1
R5126
2
15
2
5% 1/16W MF-LF 402
2
SPI_CS0_L
R5121 81
SPI_CLK
1
81
SPI_MOSI
R5123
SPI_MISO
47
1
5% 1/16W MF-LF 402
R5122
2
PLACE_NEAR=J5100.14:5mm PLACE_NEAR=J5100.12:5mm PLACE_NEAR=J5100.9:5mm PLACE_NEAR=J5100.11:5mm
5% 1/16W MF-LF 402
47
1
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
6 47 6 47
R5120 81
5% 1/16W MF-LF 402
2
R5125 47
47
5% 1/16W MF-LF 402
R5110
SPI_CS0_R_L
R5127 47
5% 1/16W MF-LF 402
6 47
SPI_ALT_CS_L LPCPLUS_R:YES
LPCPLUS_R:YES
1
6 47
SPI_ALT_CLK
1
15 5% 1/16W MF-LF 402
47 5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
SPI_MLB_CS_L
46 56 81
OUT
46 56 81
B SPI_MLB_CLK
2
OUT
PLACE_NEAR=R5125.2:5mm
PLACE_NEAR=R5126.2:5mm
2
SPI_MLB_MOSI
OUT
46 56 81
IN
46 56 81
PLACE_NEAR=R5127.2:5mm
SPI_MLB_MISO
2
PLACE_NEAR=U6100.2:5mm
A
S YN C_ MA ST ER =J 31 _M LB
S YN C_ DA TE =0 6/ 15 /2 01 1
PAGE TITLE
LPC+SPI Debug Connector DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
51 OF 109 SHEET
47 OF 86
1
A
8
7
6
5
PCH SMBus "0" Connections 48 7
D
1
1
1K 5% 1/16W MF-LF 402
(MASTER) 81 16
7
R5200
U1800
R5201
2
J2900
5% 1/16W MF-LF 402
=I2C_SODIMMA_SCL
SMBUS_PCH_CLK
27
(MASTER) 84 45
=I2C_SODIMMA_SDA
SMBUS_PCH_DATA
27
84 45
MAKE_BASE=TRUE
VRef DACs
R5251 4.7K 5% 1/16W MF-LF 402
2
2
=PP3V42_G3H_SMBUS_SMC_BSA
R5280
SMC
5% 1/16W MF-LF 402
(MASTER)
SMBUS_SMC_0_S0_SCL
84 45 6
Battery Charger
2.0K 5% 1/16W MF-LF 402
ISL6258 - U7000 (Write: 0x12 Read: 0x13)
SMBUS_SMC_5_G3_SCL
=SMBUS_CHGR_SCL
SMBUS_SMC_0_S0_SDA
84 45 6
SMBUS_SMC_5_G3_SDA
64
=SMBUS_CHGR_SDA
64
29
Margin Control
Battery
(See Table)
Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)
U9701
=I2C_PCA9557D_SCL
=I2C_BKL_1_SCL
77
=AP_TEMP_SMB_SCL
32
31
=I2C_PCA9557D_SDA
=I2C_BKL_1_SDA
77
=AP_TEMP_SMB_SDA
32
7
=PP3V3_S3_SMBUS_SMC_MGMT
R5290
Mikey (Write: 0x72 Read: 0x73) =I2C_MIKEY_SCL
58 62
58 62
SMC "2" SMBus Connections NOTE: SMC RMT bus remains powered and may
7
SATA_Redriver
84 45 6
=SATARDRVR_I2C_SDA
R5270
2
2
84 45
SMBUS_SMC_3_SCL
84 45
SMBUS_SMC_3_SDA
R5291 4.7K 5% 1/16W MF-LF 402
C
be active in S3 state
1
1
2
2
R5271
1K 5% 1/16W MF-LF 402
U4900
(MASTER)
41
1
=PP3V3_S3_SMBUS_SMC_A_S3
SMC
U4510
(Write: 0xB6 Read: 0xB7) =SATARDRVR_I2C_SCL
5% 1/16W MF-LF 402
(MASTER)
U6880
1
4.7K
U4900
=I2C_MIKEY_SDA
NO STUFF
NO STUFF
SMC
(MASTER)
63
(Write: 0x90 Read: 0x91)
31
J2500 & J2550
63
=SMBUS_BATT_SDA
SMC "3" SMBus Connections
(WRITE: 0x58 READ: 0x59)
XDP Connectors
=SMBUS_BATT_SCL
X19
LED BACKLIGHT
U3401
(Write: 0x30 Read: 0x31)
D
MAKE_BASE=TRUE
J6955
=I2C_SODIMMB_SDA
=SMBUS_XDP_SDA
R5281
Battery Manager - (Write: 0x16 Read: 0x17)
=I2C_VREFDACS_SDA
=SMBUS_XDP_SCL
2
Battery
29
23
2
J3100
=I2C_SODIMMB_SCL
23
1
MAKE_BASE=TRUE
(Write: 0xA4 Read: 0xA5)
=I2C_VREFDACS_SCL
C
1
2.0K
U4900
SO-DIMM "B"
U3400
31
1
5% 1/16W MF-LF 402
MAKE_BASE=TRUE
(Write: 0x98 Read: 0x99) 31
1
4.7K
MAKE_BASE=TRUE
MAKE_BASE=TRUE 81 16
7
R5250
U4900
(Write: 0xA0 Read: 0xA1)
1
SMC "5" SMBus Connections
=PP3V3_S0_SMBUS_SMC_0_S0
SMC
SO-DIMM "A"
1K
2
2
3
SMC "0" SMBus Connections
=PP3V3_S0_SMBUS_PCH
Cougar-Point
4
Trackpad
1K 5% 1/16W MF-LF 402
J5800
(Write: 0x90 Read: 0x91)
SMBUS_SMC_2_S3_SCL
=I2C_TPAD_SCL
54
=I2C_TPAD_SDA
54
MAKE_BASE=TRUE 41 84 45 6
SMBUS_SMC_2_S3_SDA
T29 I2C Connections
MAKE_BASE=TRUE
ALS 7
J3502
=PP3V3_S0_T29I2C
(Write: 0x72 Read: 0x73) =I2C_ALS_SCL
32
=I2C_ALS_SDA
32
U3600
(MASTER)
B
PCH "SMLink 0" Connections 48 7
Digital SMS
83 33
LIS331DLH: U5920
83 33
1
1
R5230
T29 IC
R5231
4.7K
4.7K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
I2C_T29_SDA
U1800
(MASTER) 81 16
1
1
R5211
8.2K
8.2K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
2
2
=I2C_SMC_SMS_SCL
55
=I2C_SMC_SMS_SDA
55
I2C_T29_SCL
SDRVI2C:MCU
75
=I2C_T29AMCU_SCL
75
B
SDRVI2C:MCU 1
R5234 0
R5235 0
5% 1/20W MF 201 2
5% 1/20W MF
2 201
For Compliance Testing SDRVI2C:SB
SML_PCH_0_CLK
R5236
MAKE_BASE=TRUE 81 16
U9330
=I2C_T29AMCU_SDA
MAKE_BASE=TRUE
1
R5210
T29 Plug uC (Write: 0x26 Read: 0x27)
MAKE_BASE=TRUE
(Write: 0x30 Read: 0x31)
=PP3V3_S0_SMBUS_PCH
Cougar-Point
Microcontroller abstracts actual CDR(s) in plug.
SML_PCH_0_DATA
0
1
2 5% MF
MAKE_BASE=TRUE
SMC "1" SMBus Connections 7
R5237
1/20W 201
DP Re-driver
I2C_DPSDRVA_SCL
U9310
MAKE_BASE=TRUE
(Write: 0x94 Read: 0x95)
SDRVI2C:SB
0
1
I2C_DPSDRVA_SDA
2 5% MF
1/20W 201
MAKE_BASE=TRUE
=PP3V3_S0_SMBUS_SMC_B_S0
=I2C_DPSDRVA_SCL
75
=I2C_DPSDRVA_SDA
75
PCH "SMLink 1" Connections R5260
SMC
84 45
U1800
84 45
1
2
2
4.7K
5% 1/16W MF-LF 402
U4900
(MASTER)
Cougar-Point
1
R5261
CPU Temp
4.7K 5% 1/16W MF-LF 402
EMC1414: U5511 (Write: 0x98 Read: 0x99)
SMBUS_SMC_1_S0_SCL
=I2C_CPUTHMSNS_SCL
51
=I2C_CPUTHMSNS_SDA
51
MAKE_BASE=TRUE
A
SMBUS_SMC_1_S0_SDA MAKE_BASE=TRUE
(Write: 0x88 Read: 0x89)
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE 81 16
SML_PCH_1_CLK
81 16
SML_PCH_1_DATA
SMBus Connections DRAWING NUMBER
Apple Inc. R
SMLink 1 is slave port to
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
access PCH & CPU via PECI.
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
52 OF 109 SHEET
48 OF 86
1
A
8
7
6
5
4
2
3
1
CPU VCCIO 1.05V Load Side Current Sense (IC1C) Gain: 100x, EDP: 20.1 A Rsense: 0.001 (R7640) V across Rsense: 20.1 mV Gain needed: 164.2x
7
CPU Core Load Side Current Sense (IC0C) 1
D
20% 10V 2 CERM 402
V+
U5360
85 70
IN
CPUVCCIOS0_CS_N
IN
CPUVCCIOS0_CS_P
PLACE_NEAR=R7640.3:5MM
PLACE_NEAR=R7640.4:5MM
5 IN-
C5360 0.1uF
3
85 70
Gain: 161.5x, EDP: 53 A Rsense: 2x of 0.00075 (R7510, R7520), Rsum: 0.000375 V across Rsense: 19.8 mV Gain needed: 166.1x
=PP3V3_S0_ISNS
SC70
OUT
4 IN+
D
LOADISNS:YES
INA214
R5345
R5369 4.53K
CPUVCCIO_IOUT
6
1
SMC_CPUVCCIO_ISENSE
2
1% 1/16W MF-LF 402
REF 1
IN
C5369 85 69 68
IN
LOADISNS:YES
85 69
IN
DDR 1.5V S3 (Memory) Current Sense (IM0C) =PP3V3_S3_ISNS
7
1
OUT
=PP1V5_S3_DDR_ISNS
2.74K
2
ISNS_1V5_S3_DDR_R_P
1% 1/16W MF-LF
1
3
402
+IN -IN
R5372
2 4 85
ISNS_1V5_S3_DDR_N
1
2.74K
2
V+
1
SMC_MEM_ISENSE 1
402 PLACE_NEAR=U4900.B6:5MM
7
B
OUT
=PP5V_S0_HDD_ISNS
OUT
1K
1% 1/20W MF
201
0.1%
SIGNAL_MODEL=EMPTY
C
6.3V
45 46 49 50
AXG Core Load Side Current Sense (IN0C)
ISNS_5V_S0_HDD_R_P
R5355
+IN
V+
-IN
V-
C5380
85 69
OPA330
4 ISNS_5V_S0_HDD_IOUT 1
4.53K
2
85 69
SMC_HDD_ISENSE
PLACE_NEAR=U4900.B4:5MM
1M
0402
OUT
IN
CPUIMVP_ISNS2G_P
R5384
20%
2
1M
1
85 69
6.3V
IN
X5R 402
CPUIMVP_ISNS1G_N
4.42K2
1
PLACE_NEAR=R7550.4:5MM
IN
CPUIMVP_ISNS2G_N
CPUIMVP_ISUMG_R_P
CPUIMVP_ISNSG_N
1.54K2
1
7
4.53K
CPUIMVP_ISUMG_IOUT1
4
9
LOADISNS:YES
OUT
46
C5359 0.22UF
6.3V 2 X5R 402
B
LOADISNS:YES
PLACE_NEAR=U4900.H1:5MM
1
R5354 715K
0402
SMC_AXG_ISENSE 1
20%
PLACE_NEAR=U4900.H1:5MM
R5351 715K
1
1/16W MF
2
1% 1/16W MF-LF 402
V-
CPUIMVP_ISUMG_R_N
LOADISNS:YES
4.42K2
R5359
DFN
V+ THRM
85
OPA2333
1% 1/16W MF-LF 402
0.1%
1/16W MF
0.1%
LOADISNS:YES
402
5 6
1
PLACE_NEAR=R7560.4:5MM 1% 1/16W MF-LF
85
0402
85 69
85
R5353
R5358 45 46 49 50
8
1% 1/16W MF-LF 402
0402
LOADISNS:YES
GND_SMC_AVSS
2
CPUIMVP_ISNSG_P
85
1.54K2 1
1/16W MF
R5357
0.22UF
CRITICAL
U5340
R5352
0.1%
PLACE_NEAR=R7560.3:5MM
46
C5389
PLACE_NEAR=U4900.B4:5MM
1% 1/16W MF-LF 2 402
LOADISNS:YES LOADISNS:YES
4.42K2 1
LOADISNS:YES 1
=PP3V3_S0_IMVPISNS
2
0.1%
1/16W MF
R5356
402
R5383
49 7
4.42K
1
PLACE_NEAR=R7550.3:5MM
1% 1/16W MF-LF
1
CPUIMVP_ISNS1G_P LOADISNS:YES
R5389
SC70-5
ISNS_5V_S0_HDD_R_N
IN
20% 2 10V CERM 402
2 85
0.1%
1/16W MF 402
715K
45 46 49 50
LOADISNS:YES
X5R 402
0.1UF
U5380
3
2
GND_SMC_AVSS
2
Gain: 190.6x, EDP: 46 A Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375 V across Rsense: 17.25 mV Gain needed: 191.3x
5
1
201
1
R5344
715K
46
PLACE_NEAR=U5380.5:3MM
R5382 ISNS_5V_S0_HDD_N
1 1
C5379
GND_SMC_AVSS
2
=PP5V_S0_ISNS
1% 1/20W MF
85
PLACE_NEAR=U4900.E1:5MM
2
PLACE_NEAR=U4900.B6:5MM
1M
R5381 85
LOADISNS:YES
R5341
R5374 1
=PP5V_S0_HDD_ISNS_R 2
6.3V 2 X5R 402
0402
20%
1M
7
1
46
20%
0.22UF 2
1
2 4
OUT
C5349 0.22UF
PLACE_NEAR=U4900.E1:5MM
0.1%
SMC_CPU_ISENSE 1
LOADISNS:YES
LOADISNS:YES
2
1% 1/16W MF-LF
V-
CRITICAL
1% 1W MF-1 0612
2
1% 1/16W MF-LF 402
9
CPUIMVP_ISUM_R_N
SIGNAL_MODEL=EMPTY
4.53K
HDD Current Sense (IHDC)
0.001
R5349 4.53K
CPUIMVP_ISUM_IOUT1
4
1/16W MF
0402
402
1K
1
V-
LOADISNS:YES
1/16W MF
1% 1/16W MF-LF
1 3 ISNS_5V_S0_HDD_P
V+
0.1UF
1/16W MF 2 402
R5373
Gain: 1000x, EDP: 2.5 A (12.5 W) Rsense: 0.001 (R5380) V across Rsense: 2.5 mV Gain needed: 1320x
2 85
DFN
C5340
R5379
1
1% 1/16W MF-LF 2 402
R5380
2.21K
1
0.1%
LOADISNS:YES
3
THRM
0.1UF
4 ISNS_1V5_S3_DDR_IOUT
ISNS_1V5_S3_DDR_R_N
402
IN
CPUIMVP_ISNS_N
4.42K
1
C5370
SC70-5
2 85
1% 1/16W MF-LF
7
85
0.1%
CPUIMVP_ISNS2_N
CPUIMVP_ISUM_R_P
2
20% 10V 2 CERM 402
OPA330
5 85
IN
PLACE_NEAR=U5370.5:3MM
U5370
R5371 1 3 ISNS_1V5_S3_DDR_P
0.001
7
2
1/16W MF
PLACE_NEAR=R7520.4:5MM
CRITICAL
C
4.42K
1
PLACE_NEAR=R7510.3:5MM
85 69
85
0402
8
1
20% 10V 2 CERM 402
U5340
OPA2333
0.1%
1/16W MF
R5343
0402
R5348
=PP1V5_S3_DDR_ISNS_R
1% 1W MF-1 0612
12.21K2
0.1%
1/16W MF
R5347 LOADISNS:YES
1
R5370
CPUIMVP_ISNS2_P 14.42K2 85 CPUIMVP_ISNS_P
0402
Gain: 364.9x, EDP: 9 A Rsense: 0.001 (R5370) V across Rsense: 9 mV Gain needed: 366.6x
IN
R5342
CPUIMVP_ISNS1_N
CRITICAL
LOADISNS:YES
0402
LOADISNS:YES
PLACE_NEAR=U5340.8:3MM
LOADISNS:YES
0.1%
1/16W MF
45 46 49 50
LOADISNS:YES
=PP3V3_S0_IMVPISNS
2
R5346 PLACE_NEAR=R7520.3:5MM
PLACE_NEAR=U4900.A6:5MM
GND_SMC_AVSS
49 7
4.42K
1
LOADISNS:YES
20%
CRITICAL
7
CPUIMVP_ISNS1_P
0.22UF
2 X5R 6.3V 402
2
LOADISNS:YES
85 69 68
46
PLACE_NEAR=R7510.4:5MM
1
LOADISNS:YES PLACE_NEAR=U4900.A6:5MM
GND
OUT
0.1%
1/16W 0.1% MF 402
2
GND_SMC_AVSS
45 46 49 50
LOADISNS:YES SIGNAL_MODEL=EMPTY
1/16W MF 2 402
LOADISNS:YES
SIGNAL_MODEL=EMPTY
CPU Core Voltage Sense (VC0C) PLACE_NEAR=R7510.2:5 MM
PLACE_NEAR=U4900.E2:5MM
XW5320
R5329
SM
7
=PPCPUVCORE_S0_VSENSE1
2
CPUVSENSE_IN
4.53K
1
SMC_CPU_VSENSE
2
1% 1/16W MF-LF 402
OUT
46
PART NUMBER
PLACE_NEAR=U4900.E2:5MM
1
C5329
116S0114
0.22UF
QTY 3
DESCRIPTION RES,MTL FLIM,100K,1/16W,0402,SMD,LF
REFERENCE DES
CRITICAL
BO M OPTION LOADISNS:NO
C5349,C5359,C5369
20%
6.3V 2 X5R 402
GND_SMC_AVSS
A
45 46 49 50
AXG Core Voltage Sense (VN0C)
=PPAXGVCORE_S0_VSENSE1
SM
2
DRAWING NUMBER
R5339 AXGVSENSE_IN
14.53K2 1% 1/16W MF-LF 402
SMC_AXG_VSENSE
OUT
Apple Inc.
46
R
PLACE_NEAR=U4900.C1:5MM
1
C5339
NOTICE OF PROPRIETARY PROPERTY:
0.22UF
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
20%
6.3V 2 X5R 402
GND_SMC_AVSS
8
SYNC_DATE=09/28/2011
PAGE TITLE
PLACE_NEAR=U4900.C1:5MM
XW5330 7
SYNC_MASTER=LINDA_J30
Power Sensors: Load Side
PLACE_NEAR=R7550.2:5 MM
7
45 46 49 50
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
53 OF 109 SHEET
49 OF 86
1
A
8
7
6
5
4
CPU High Side Current Sense (IC0R) Gain: 50x, EDP: 17.4 A Rsense: 0.003 (R5400) V across Rsense: 52.2 mV Gain needed: 63.2x
D
7
CRITICAL
Q5480
0.003 R5400 2% 0.5W
85
MF
0612 CRITICAL 7
IN
U5400
PLACE_NEAR=U5400.5:10MM
R5409
INA213
5 INISNS_HS_COMPUTING_N
SC70
OUT
4 IN+ ISNS_HS_COMPUTING_P
6
HS_COMPUTING_IOUT
4.53K
1
2
REF 1
1
=PBUSVSENS_EN
IN
2 CRITICAL
PBUSVSENS_EN_L
2
1
R5482
100K
G
1% 1/16W MF-LF 402
S
46
3
C5409 0.22UF
PLACE_NEAR=U4900.B5:5MM
GND
73
SMC_CPU_HI_ISENSEOUT
6
D
1
1% 1/16W MF-LF 402
2 4
=PPVIN_S5_HS_COMPUTING_ISNS_R PLACE_NEAR=U5400.4:10MM
D
SOT-963
N-CHANNEL
Enables PBUS VSense divider when in S0.
20% 10V 2 CERM 402
V+
=PPVIN_S5_HS_COMPUTING_ISNS 1 3 85
NTUD3169CZ
C5401 0.1UF
3
OUT
PBUS_S0_VSENSE
2
D
20%
6.3V 2 X5R 402
=PPBUS_S0_VSENSE
7
5
27.4K
G
1% 1/16W MF-LF 4022
S
4
GND_SMC_AVSS
SMC_PBUS_VSENSE
0.5W
85
MF
0612 CRITICAL 7
IN
0.22UF
20% 6.3V 2 X5R 402
GND_SMC_AVSS
ISNS_HS_OTHER_N
5 IN-
20% 10V 2 CERM 402
SC70
ISNS_HS_OTHER_P
4 IN+
C
R5419
INA214 OUT
6
HS_OTHER_IOUT
4.53K
1
2
1% 1/16W MF-LF 402
REF 1
2 4
PLACE_NEAR=U4900.A5:5MM
=PPVIN_S5_HS_OTHER_ISNS_R PLACE_NEAR=U5410.4:10MM
45 46 49 50
C5411
0.003 2%
46
C5489
PLACE_NEAR=U4900.A3:5MM
U5410
PLACE_NEAR=U5410.5:10MM
R5410
1% 1/16W MF-LF 4022
OUT
PLACE_NEAR=U4900.A3:5MM
1
0.1UF
V+
=PPVIN_S5_HS_OTHER_ISNS 1 3 85
5.49K
=PP3V3_S0_HS_OTHER_ISNS
3
OUT
1% 1/16W MF-LF 4022
PBUSVSENS_EN_L_DIV 1
7
R54891
100K
OTHER High Side Current Sense (IO0R)
C
Rthevenin = 4573 Ohms
P-CHANNEL
45 46 49 50
R54811
7
PLACE_NEAR=U4900.A3:5MM
R54881
PLACE_NEAR=U4900.B5:5MM
Gain: 100x, EDP: 8.8 A Rsense: 0.003 (R5410) V across Rsense: 26.4 mV Gain needed: 125x
1
PBUS Voltage Sense & Enable (VP0R)
=PP3V3_S0_HS_COMPUTING_ISNS 1
7
2
3
SMC_OTHER_HI_ISENSE OUT 1
46
C5419 0.22UF 20%
6.3V
2 X5R 402
GND
2 CRITICAL
PLACE_NEAR=U4900.A5:5MM
GND_SMC_AVSS
45 46 49 50
DC In Voltage Sense & Enable (VD0R) CRITICAL
Charger (BMON Production) Current Sense (IPBR) Charger Gain: 36x Rsense: 0.010 (R7050) Max Current Measured: 9.2 A
PLACE_NEAR=U4900.A4:5MM
IN
=CHGR_ACOK
CHGR_BMON
SOT-963
45.3K2 1 1% 1/16W MF-LF 402
B
SMC_BMON_ISENSE
R5493 1
MF
R5429 IN
NTUD3169CZ N-CHANNEL
NO STUFF 64 46
64
Q5490
Enables DC-In VSense divider when AC present.
OUT
46 73
IN
PM_SUS_EN
1
5% 1/20W 201
0
6
DCINVSENS_EN_L
D
R54921
2
DCIN_VSENSE_EN
2
100K
G
1% 1/16W MF-LF 4022
S
R5494 MF
1
0
1
2
3
5% 1/20W 201
C5429
DCIN_S5_VSENSE
D
20% 16V 2 CERM 402
7
=PPDCIN_S5_VSENSE
5
B
27.4K
G
1% 1/16W MF-LF 4022
S
4
PLACE_NEAR=U4900.A4:5MM
PLACE_NEAR=U4900.F1:5MM
R54981
0.022UF
Rthevenin = 4573 Ohms
P-CHANNEL
GND_SMC_AVSS
SMC_DCIN_VSENSE
R54911
45 46 49 50
R54991
100K
1% 1/16W MF-LF 4022
DC-In (AMON) Current Sense (ID0R)
5.49K
1% 1/16W MF-LF 4022
46
C5499 0.22UF
20% 6.3V 2 X5R 402
PDCINVSENS_EN_L_DIV
Charger Gain: 20x Rsense: 0.020 (R7020) Max Current Measured: 8.3 A
OUT
PLACE_NEAR=U4900.F1:5MM
1
GND_SMC_AVSS
45 46 49 50
PLACE_NEAR=U4900.F1:5MM
PLACE_NEAR=U4900.B3:5MM
R5439 64
IN
CHGR_AMON
4.53K2
1
1% 1/16W MF-LF 402
SMC_DCIN_ISENSE 1
OUT
46
C5439 0.22UF
20% 2 6.3V X5R 402
A
PLACE_NEAR=U4900.B3:5MM
GND_SMC_AVSS
SYNC_MASTER=YONAS_J30
SYNC_DATE=11/03/2011
PAGE TITLE
Power Sensors: High Side
45 46 49 50
DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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D
D
Thermal Sensor: CPU Proximity, Fin Stack, Memory Proximity, 5V/3.3V Proximity I2C Write, 0x98, I2C Read: 0x99
R5510 =PP3V3_S0_CPUTHMSNS
7
1
47
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
5% 1/16W MF-LF 402 85
Thermal Diode: Fin Stack
PLACE_NEAR=Q5520.3:5MM
Placement Note: Place Q5520 on BOTTOM side. Close to Fin Stack.
1
C5520 22PF
NOSTUFF
C
5% 50V 2 CERM
3
Q5520 SOT732-3
2
85
PLACE_NEAR=Q5510.2:5MM
1
C5510
Q5510
BC846BMXXH
22PF 5% NOSTUFF
PLACE_NEAR=Q5515.3:5MM
1 CRITICAL PLACE_SIDE=TOP
1
2 CERM
NOSTUFF
50V
2 CERM
Q5515 BC846BMXXH SOT732-3
0402
3
85
402
PLACE_NEAR=U5511.4:5MM
3
C5515 22PF 5%
0402
PLACE_NEAR=Q5510.3:5MM
10% 50V
CERM 2
THMSNS_D2_P
2
SOT732-3
50V
PLACE_NEAR=U5511.3:5MM
THMSNS_D1_N
2
C5512 1
1
0.0022uF 10%
SIGNAL_MODEL=EMPTY
CERM 2
CRITICAL
402
PLACE_NEAR=Q5515.2:5MM
THMSNS_D2_N
50V
PLACE_NEAR=U5511.5:5MM
Thermal Diode: 5V/3.3V Proximity
Thermal Diode: Memory Proximity
Placement Note: Place Q5510 on the TOP side, Next to 5V and 3.3V power supplies.
Placement Note: Place Q5515 on the EITHER side, on right of DIMM connectors.
R55111
U5511
0.0022uF SIGNAL_MODEL=EMPTY
CRITICAL
PLACE_NEAR=Q5520.2:5MM
85
0.1uF
C5511 1
1
C5513
20% 10V 2 CERM 402
1 VDD
PLACE_NEAR=U5511.2:5MM
BC846BMXXH
0402
1
THMSNS_D1_P
10K
5% 1/16W MF-LF 4022
1
R5512 10K
5% 1/16W MF-LF 2 402
EMC1414 DFN 7
2 DP1
THERM*/ADDR
3 DN1
ALERT*
8
CPUTHMSNS_ALERT_L
4 DP2
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
48
10
=I2C_CPUTHMSNS_SCL
BI
48
5
DN2
SMCLK GND
6
CPUTHMSNS_THM_L
C
THRM_PAD
11
PLACE_SIDE=BOTTOM
Thermal Sensor: CPU Proximity Placement Note: Place U5511 on bottom side under CPU
the
Thermal Sensor: T29 Die B
B 33
BI
TP_T29_THERM_DP
85
T29_THERMD_P MAKE_BASE=TRUE
1
R5520
5% 10K 1/16W MF-LF 2 402 1
2
85
T29_THERMD_N
XW5520 PLACE_NEAR=U3600.B1:2MM
NOSTUFF PLACE_SIDE=BOTTOM
SM
Note: Use GND pin B1 on U3600 for N leg.
A
SYNC_MASTER=YONAS_J30
SYNC_DATE=08/01/2011
PAGE TITLE
Thermal Sensors DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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D
7
=PP5V_S0_FAN_RT
7
=PP3V3_S0_FAN_RT CRITICAL
R5660 47K 5%
C 45
1/16W MF-LF 402
R5665 47K 2 1
SMC_FAN_0_TACH
6
1
J5601 M-RT-SM 5
2
FAN_RT_TACH
1
5V DC
2
TACH
5%
3
1/16W MF-LF
4
402
NC
R5661 100K 5% 1/16W MF-LF 402
1
Q5660
SMC_FAN_0_CTL
VESM
2 S
45
MOTOR CONTROL GND
6
518S0521
SSM3K15AMFVAPE 1 G
C
78171-0004 NC
2
D
6
FAN_RT_PWM
3
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Fan DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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6
5
PSOC USB CONTROLLER -
PLACE_SIDE=BOTTOM
54 53 7
D
2
1.5
PP3V3_S3_PSOC
1
1
1
100PF
220K
54 6 53 54 6 53 53
CURRENT
2
3
R_SNS
V_SNS
V+
10UA 80UA
2.55 KOHM
0.0255 V 0.204 V
POWER
3V3 LDO
VDD
60MA (MAX) 60MA (MAX)
10 OHM 0.2 OHM
0.6 0.012
V V
36E-3 W 0.72E-3 W
PSOC
VDD
8MA (TYP) 14MA (MAX)
1.5 OHM
0.012 0.021
V V
96E-6 W 294E-6 W
18V BOOSTER
VIN
4MA (MAX)
4.7 OHM
0.0188 V
75.2E-6 W
54 53 7 53 7
54 6
53 6 53 6
20% 6.3V 2 X5R 603
53 6 53 6 53 6
73
54 6 54 6 54 6 54 6
C
NC
TPAD_VBUS_EN Z2_DEBUG3 Z2_RESET PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK
IN
54 6 54 6 54 6 54 6 54 6 54 6
P2_1 3 P4_7 4 P4_5 5 P4_3 6 P4_1 7 P3_7 8 P3_5 9 P3_3 10 P3_1 11 P5_7 12 P5_5 13 P5_3 14 P5_1
WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6
P P P P V D D V P P P P P P
PAD
WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3
42 41 40 39 38 37 36 35 34 33 32 31 30 29
27 26 25 24 23
WS_KBD7 WS_KBD8 WS_KBD9 6 WS_KBD10 6 WS_KBD11 6 WS_KBD12 6 WS_KBD13 6 WS_KBD14 6 6 WS_KBD15_CAP 6 WS_KBD16_NUM WS_KBD17 6 WS_KBD18 6 WS_KBD19 6 WS_KBD20 6 WS_KBD21 6 WS_KBD22 6 WS_KBD23 6 6 WS_KBD_ONOFF_L
6 53 53
6 53 53
22 21
6 53
R5714
6 53 6 53
53
WS_KBD15_C
1
470
2
6 53
53
WS_KBD16N
1
10K
53
2
53
53 53 53
1% 1/16W MF-LF 402
53
53 53
1% 1/16W MF-LF 402
6 53
53
53 53
6 53
R5710
6 53 6 53 46 45
6 53
OUT
SMC_ONOFF_L
C5710 1
6 53
0.1UF
6 53
20% 10V CERM 2 402
6 53 6 53
1
1K
5% 1/16W MF-LF 402
2
53 53
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
53 6 53 6 53 6
WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
3 1
NC
6 53
TP_PSOC_SCL TP_PSOC_SDA TP_PSOC_P1_3 TP_ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL 1
24
FF14-30A-R11B-B-3H
J5713
CRITICAL WS_KBD4 WS_KBD5 WS_KBD6 TP_ISSP_SDATA_P1_0 ISSP SDATA/I2C SDA
2
85
Z2_CLKIN TP_P7_7
USB_TPAD_R_P
5% 1/16W MF-LF 402
1
24
518S0637
6 53 6 53 6 53
6 54
SMC Manual Reset & Isolation
(PP3V3_S3_PSOC) 1
R5702 USB_TPAD_N
80 8
2
85
USB_TPAD_R_N
C5702
1
5% 50V
10% 16V 2 X7R-CERM
100PF
2 CERM
5% 1/16W MF-LF 402
0402
31
F-RT-SM
6 53
57
R5701 USB_TPAD_P
80 8
C
2
PLACEMENT_NO TE=NEAR J5713
6 53
0 1 5 6 7 8 6 7 8 2 9 3 4 5 2 2 1 1 1 1 1 2 2 2 2 2 2 2
6
D
28
53 6
R5715
P2_2 CRITICAL P2_0 OMIT P4_6 P4_4 U5701 P4_2 CY8C24794 MLF P4_0 (SYM-VER2) P3_6 P3_4 337S2983 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 7 0 0 2 4 6 7 5 3 1 THRML _ 1 _ 7 _ 1 _ 1 _ 1 _ _ 1 _ 1 _ 1 _ S S + - D D 7 1
32
29
C5706
WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18
2
NC
53 6
5 7 1 3 5 7 S D 6 4 2 0 6 4 _ _ _ _ _ _ S D _ _ _ _ _ _ 2 2 0 0 0 0 V V 0 0 0 0 2 2 1 P P P P P P P2_3 P P P P P P
WS_CONTROL_KEY Z2_KEY_ACT_L
=PP3V3_S4_TPAD =PP3V42_G3H_TPAD
30
53 6
6 5 4 3 3 2 1 8 7 6 5 4 9 0 5 5 5 5 5 5 5 4 4 4 4 4 4 4
53
1
Keyboard Connector
0.255E-6 W 16.32E-6 W
4.7UF
0402
=PSOC_WAKE_L PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY
OUT
1
10% 2 16V X7R-CERM
0402
5% 1/16W MF-LF 4022
C5705 0.1UF
5% 50V 2 CERM
R57031
46
C5704
PIN NAME
VOUT
BYPASS=U5701.22:19:11 mm BYPASS=U5701.22:19:8 mm BYPASS=U5701.22:19:5 mm
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
5% 1/16W MF-LF 402
IC TMP102
USB INTERFACES TO MLB SPI HOST TO Z2 TRACKPAD PICK BUTTONS KEYBOARD SCANNER
R5704
=PP3V3_S4_TPAD
4
C5703 0.1UF 0402
1
C5701 4.7UF
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
20%
6.3V 2 X5R 603
Keys ANDed with MSP power to isolate when MSP is not powered. No IPD on OE input pin PP3V3_S4 (symbol error).
BYPASS=U5701.49:50:5 mm BYPASS=U5701.49:50:8 mm BYPASS=U5701.49:50:11 mm
53 7
=PP3V42_G3H_TPAD
B
1
B
C5750 0.1UF
10% 16V 2 X7R-CERM
CRITICAL 0 1
0402
VDD
U5750 SLG4AP021
TPAD Buttons Disable
TQFN
BUTTON_DISABLE
53
Q5701
54 53 7
D 3
PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON
MLB
SSM3K15AMFVAPE CRITICAL
1 63 46 45
IN
SMC_LID
G
S 2
4 OE (IPD)
53 6
WS_LEFT_SHIFT_KBD
1 IN_1
53 6
WS_LEFT_OPTION_KBD
2 IN_2
53 6
WS_CONTROL_KBD
3 IN_3
VESM
THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V
=PP3V3_S4_TPAD
OUT_1
9
OUT_2
8
OUT_3
7
(IPD)
(IPD)
WS_LEFT_SHIFT_KEY 53 WS_LEFT_OPTION_KEY 53 WS_CONTROL_KEY
53
(IPD)
Pull-up in U5010. OUT_ALL# 6
GND 5
SMC_TPAD_RST_L
OUT
46
THRM PAD 1 1
A
S Y NC _M A ST E R= J3 1 _M L B
S Y NC _ DA T E= 0 7/ 01 / 20 1 1
PAGE TITLE
WELLSPRING 1 DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
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REVISION
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57 OF 109 SHEET
53 OF 86
1
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8
7
6
5
4
2
3
1
BOOSTER +18.5VDC FOR SENSORS BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION
D
D
- RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS - R5812,R5813,C5818 MODIFIED TPAD:Z2
TPAD:Z2
CRITICAL
PP5V_S4_P18V5S5
TPAD:Z2
R5805
7
=PP5V_S5_TPAD
0 2
P18V5S4_SW
A
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE
VLF3010AT-SM-HF
B0520WSXG
C5818
1
1
5%
50V
VIN 1
CERM 0402
U5805
L
FB
2 2
TPAD:Z2
1
1
2
2
0.1UF X7R-CERM 0402
NC
3
Z2_BOOST_EN
5
TPAD:Z2SW D N G P
THRML
PAD
X5R 603
9
7
1
6 54
1
8
R5811 100K
D N G 6
2
25V X5R 603-1
2
1% 1/16W MF-LF 402
R5813
55560-0228 M-ST-SM
=PP3V3_S4_TPAD
53 7
C5815 1000PF 5% 25V NP0-C0G 402
2
2
71.5K
TPAD:Z2
CRITICAL
10%
16V
J5800 1
1
10%
TPAD:Z2
CTRL
DO
C5817 2.2UF
10%
16V
IPD Flex Connector
TPAD:Z2
TPAD:Z2 1UF
QFN-1
TPAD:Z2
6 54
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V
CRITICAL
1% 1/16W MF-LF 402
C5819
TPS61045
C5816
PP18V5_Z2
2
R5812
P18V5S4_FB
4
0
5% 1/16W MF-LF 402
TPAD:Z2
1M
39PF
2
1
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V
TPAD:Z2
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V
5% 1/16W MF-LF 402
PP18V5_S4_R
K
PP5V_S5_P18V5S5_VIN
1
R5806
D5802 SOD-323
2
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V
TPAD:Z2
CRITICAL
L5801 3.3UH-870MA 1
1% 1/16W MF-LF 402
6
1 3 5
53 6
Z2_CS_L
4
53 6
Z2_DEBUG3
6
PP18V5_Z2
6 54
Z2_KEY_ACT_L
6 53
Z2_RESET
6 53
53 6
Z2_MOSI
8
7
PSOC_F_CS_L
6 53
53 6
Z2_MISO
10
9
PICKB_L
53 6
Z2_SCLK
12
11
PSOC_MISO
6 53
54 6
Z2_BOOST_EN
14
13
PSOC_MOSI
6 53
53 6
Z2_HOST_INTN
16
15
PSOC_SCLK
6 53
18
17
=I2C_TPAD_SDA
48
20
19
=I2C_TPAD_SCL
48
22
21
PP5V_S5_CUMULUS VOLTAGE=5V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM
2
53 6
Z2_CLKIN
6 53
C
C 516S0689
TPAD:CUMULUS
L5800 FERR-120-OHM-1.5A 1
PIN 21 IS NC ON CUMULUS FLEX
2 0402-LF
PIN 18 IS NC ON Z2 FLEX
PLACE_NEAR=J5800.18:3MM
TPAD:CUMULUS 1
C5800 0.1UF
PLACE_NEAR=J5800.18:3MM
2
20% 10V CERM 402
Keyboard Backlight Driver & Detection 7
=PP5V_S0_KBDLED
Keyboard Backlight Connector
CRITICAL
B
L5850 =PP3V3_S0_KBDLED
1
2 1098AS-SM
R5853
1
C5850
470K 5% 1/16W MF-LF 402
45
BI
1
KBDLED_SW
1
tristate and read SMC_SYS_KBDLED:
1 6
6
2
STLA02
1
DFN6 VOUT 4 CRITICAL
6 EN/PWM
FB
5
R5852
1
GND 2
10K 5% 1/16W MF-LF 402
2
J5815 pin 1 is grounded on keyboard backlight flex
4
R5855 10
2
518S0691
1% 1/16W MF-LF 402
KBDLED_CAP
NO STUFF
grounded when KB BL flex connected.
KBDLED_ANODE
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
U5850 3 LX
5% 1/16W MF-LF 402
SMC_KDBLED_PRESENT_L
3
1
R5854 4.7K
R5853 always stuffed, R5854 only
F-RT-SM
2
VIN
If LOW, keyboard backlight present If HIGH, keyboard backlight not present
FF18-4A-R11AD-B-3H
10%
10V
SMC_SYS_KBDLED
To detect Keyboard backlight, SMC will
J5815
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE
1UF X5R 402-1
2
B
CRITICAL
10UH-0.58A-0.35OHM 7
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
THRM_PAD 7
1
C5855
1
0.47UF 50V CERM-X5R 0603
C5856 0.47UF
10% 2
2
10%
2
50V CERM-X5R 0603
(SMC_KBDLED_PRESENT_L)
A
SYNC_MASTER=JACK_J30
SYNC_DATE=09/28/2011
PAGE TITLE
WELLSPRING 2 DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
4
2
3
1
D
D
7
=PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm CRITICAL
C5926
1
1
2
2
C
20% 6.3V X5R 603
4 1
C5922 0.1UF
10UF
BYPASS=U5920.14:13:8 mm
R5924
1
NC NC
10K 5% 1/16W MF-LF 402
45
OUT
1
VDD
10% 16V X7R-CERM 0402
R5920
V D D_ I O
2 3
NC
PLACE_SIDE=TOP
U5920 LIS331DLH LGA
10 15
CS
8
SMS_I2C_SEL
SDO
7 6
SMS_ADDR_SELECT I2C_SMC_SMS_SDA_R
4
I2C_SMC_SMS_SCL_R
1
C
10K 5% 1/16W MF-LF 402
2
R5923 0 1
RESERVED
2
=I2C_SMC_SMS_SDA
BI
=I2C_SMC_SMS_SCL
IN
48
5%
2
SMS_INT_L
11 INT1
TP_SMS_INT2
9
SDA/SDI/SDO SCL/SPC
INT2
1/16W MF-LF 402
GND
R5921
5 2 3 6 1 1 1
1
5% 1/16W MF-LF 402
PLACEMENT_NOTE=See schematic for orientation.
R5922 0 1
10K
338S0687
2
2
48
5% 1/16W MF-LF 402
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd) SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
Desired orientation when placed on top-side:
NOTE: SDA and SCL have internal pull-ups to VDD_IO. +Y +X
Front of system
+Z (up)
B
B
Circle indicates pin 1 location when placed in correct orientation
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Digital
Accelerometer DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
4
3
2
1
D
D
C
C 7
=PP3V3_SUS_ROM
1
R6101 3.3K
2
81 47 46
IN
5% 1/16W MF-LF 402
C6100
8
1
20% 10V CERM 402
CRITICAL
VDD
0.1UF 2
U6100 64MBIT
SPI_MLB_CLK
6
SCK
SOIC
SI
5
SPI_MLB_MOSI
IN
46 47 81
SO
2
SPI_MLB_MISO
OUT
46 47 81
SST25VF064C 81 47 46
IN
47 19 6
IN
SPI_MLB_CS_L
1
SPI_WP_L
3
SPIROM_USE_MLB
7
CE* WP* HOLD*
OMIT
VSS
NOTE: If HOLD* is asserted ROM will ignore SPI cycles.
4
B
B
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
SPI ROM DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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AUDIO CODEC APPLE P/N 353S3199 as of July 2011
L6201
U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL
FERR-220-OHM 7
=PP1V8R1V5_S0_AUDIO
IN
1
=PP5V_S3_AUDIO
C6210
D
1
1
2
2
C6211
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V
=PP3V3R1V5_S0_AUDIO
20% 4V X5R-1 402
10% 16V X7R-CERM 0402
PP4V5_AUDIO_ANALOG
C6216 C6219
CRITICAL
IN
PP4V5_AUDIO_ANALOG
C6221
1
1
C6220
2
2
20% 10V X5R-CERM 0402-1
10UF 1
C6218
2.67K
2
VD
CS4206_FP CS4206_FN
60
OUT
AUD_GPIO_3
62
IN
AUD_SENSE_A CS4206_FLYC
1
1
20% 6.3V CERM 402-LF
0.1UF 10% 16V X7R-CERM 0402
2
2
IN
HDA_BIT_CLK
81 16
IN
HDA_SYNC
81 16
81 16
IN
81 16
IN
1
22
2
HDA_SDOUT
57 58 59
GND_AUDIO_HP_AMP GND_AUDIO_CODEC
57 62
AUD_HP_PORT_L
OUT
59 61
AUD_HP_PORT_R
OUT
59 61
MIN _LI N E _W I D TH= 0.3 0MM
MIN _NE CK_ W I DT H = 0.2 0MM
2
GPIO0/DMIC_SDA1 LINEOUT_L1+
35
TP_AUD_LO1_P_L
12
34
TP_AUD_LO1_N_L
14
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2 GPIO2 LINEOUT_R1+
36
AUD_LO1_P_R
OUT
60 85
15
GPIO3
LINEOUT_R1-
37
AUD_LO1_N_R
OUT
60 85
13
SENSE_A
LINEOUT_L2+
31
AUD_LO2_P_L
OUT
60 85
LINEOUT_L2-
30
AUD_LO2_N_L
OUT
60 85
LINEOUT_R2+
32
AUD_LO2_P_R
OUT
60 85
LINEOUT_R2-
33
AUD_LO2_N_R
OUT
60 85
MICBIAS
16
AUD_CODEC_MICBIAS
OUT
62
42
FLYN
3
VL_HD
1
VL_IF
U6201
VCOM
LINEIN_L+
BITCLK
HPAMP_REF
IN
58
FR SPKR AMP. SIG. SOURCE
LFT. SPKR AMP. SIG. SOURCE RT. SPKR AMP. SIG. SOURCE
C
28 CS4206_VCOM
21
LINEIN_C-
22
LINEIN_R+
23
NC NC NC
SYNC
8
SDI
MICIN_L+
18
AUD_MIC_INP_L
IN
62
5
SDO
MICIN_L-
17
AUD_MIC_INN_L
IN
62
MICIN_R+
19
AUD_MIC_INP_R
IN
62
MICIN_R-
20
AUD_MIC_INN_R
IN
62
VREF+_ADC
27
AUD_DMIC_CLK OUT
57
11
RESET*
EXT MIC CODEC INPUT BI MIC CODEC INPUT
HDA_RST_L
TP_AUD_SPDIF_IN AUD_SPDIF_OUT_CHIP
47
SPDIF_IN
48
SPDIF_OUT
CS4206_VREF_ADC
R6212 61
CRITICAL
20% 10V X5R-CERM 0402-1
39
VHP_FILT-
2.2UF
AUD_SDI_R
10UF
HPREF
10 81
2
MIN_NECK_WIDTH=0.10MM
FLYP
5% 1/16W MF-LF 402
2
0.1UF 10% 16V X7R-CERM 0402
2
TANT-POLY 2012-LLP
MIN_LINE_WIDTH=0.30MM
6
HDA_SDIN0
OUT
10% 16V X7R-CERM 0402
2
20% 16V
40
FLYC
R6211
10UF
HPOUT_R
VHP_FILT+
CRITICAL
81 16
D
6 57 62
C6213
MIN_NECK_WIDTH=0.10MM
43
20% 6.3V CERM 402-LF
10% 10V X5R 402-1
C6217
1
MIN_LINE_WIDTH=0.30MM
45
CS4206_FLYN
C
2
1
38
C6223
2.2UF
C6226
2
1
1
2
C6214
0.1UF
VA_REF VA_HP VA
QFN
C6222
10% 16V X7R-CERM 0402
5 2
CS4206B
=PP3V3_S0_AUDIO
IN
6 4
IN
1
VBIAS_DAC
CS4206_FLYP 62 61 57 7
C6215
HPOUT_L
41
TP_AUD_GPIO_2 GPIO3 = SPKR AMP SHDN CONTROL
29 44
OUT AUD_GPIO_0 TP_AUD_GPIO_1
57
4 2
9
VBIAS_DAC
CRITICAL
1% 1/20W MF 201
1
0.1UF
2
10UF
20% 10V X5R-CERM 0402-1
R6210
1
1UF
1
10UF 20% 16V TANT-POLY 2012-LLP
GND_AUDIO_HP_AMP
59 58 57
7
0.1UF
4.7UF
62 57 6
7 57
PP1V8R1V5_S0_AUDIO_DIG
2 0402
AUD_SPDIF_OUT
OUT
39
1
R6214 DMIC_SCL
2
5% 1/16W MF-LF 402
AUD_DMIC_SCL
4
9 4
22
2
5% 1/16W MF-LF 402
DGND THRM_PAD AGND 7
1
6 2
C6224
1
1
2
2
C6225
NOSTUFF
10UF
1UF 20% 16V TANT 0603-SM
GND_AUDIO_HP_AMP
1
20% 16V TANT-POLY 2012-LLP
100K
59 58 57
B
2
62 57
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
GND_AUDIO_CODEC
R6213 5% 1/20W MF 201
Digial Mic - Only for mock ups as of July 2011 57
AUD_DMIC_CLK
57
AUD_GPIO_0
B
TP_AUD_DMIC_CLK MAKE_BASE=TRUE
4.5V POWER SUPPLY FOR CODEC
TP_AUD_DMIC_SDATA MAKE_BASE=TRUE
APPLE P/N 353S2281 as of July 2011 NOTES ON J30 audio L6200
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=5V
FERR-220-OHM 57 7
IN
=PP5V_S3_AUDIO
1
2
TPS71745
6
IN
4V5_REG_EN
4
EN
0402
IN
=PP3V3_S0_AUDIO
2.21K 1
SON
OUT
1
PP4V5_AUDIO_ANALOG
BI
Codec HPamp used for Lineout/HPout. No external HPamp. 3 Spk amplifiers - 2 tweeters and a sub woofer No line input capability SPDIF out China headset support
6 57 62
CRITICAL
R6200 62 61 57 7
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=4.5V
U6200
4V5_REG_IN
NR/FB
3
NC
5
4V5_NR
2 1% 1/16W MF-LF 402
GND 1
1
C6200
R6203
1UF 2
5% 1/16W MF-LF 402
2
NC
2 1
100K
10% 10V X5R 402
1
C6202
C6201
2
1
10% 16V X7R-CERM 0402
10% 10V X5R 402
C6203 1UF
0.1UF
1UF
2 2
10% 10V X5R 402
GND_AUDIO_CODEC
XW6200
57 62
SM
A
1
2
S YN C_ MA ST ER =K AV IT HA _J 30
NOSTUFF
0
AUDIO: CODEC/REGULATOR
2
DRAWING NUMBER
5% 1/16W MF-LF 402
Apple Inc. R
XW6201 SM 1
8
7
S YN C_ DA TE =0 7/ 25 /2 01 1
PAGE TITLE
R6201 1
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V
2
6
NOTICE OF PROPRIETARY PROPERTY:
GND_AUDIO_HP_AMP
57 58 59
5
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
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D
EXTERNAL (HEADSET) MIC INPUT CIRCUITRY APN:353S3066 as of July 2011
L6400
PP_AUDIO_CHS
FERR-220-OHM 7
=PP3V42_G3H_AUDIO
1
2 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.42V
0402
1
C6403 10UF
20% 6.3V 2 CERM-X5R 0402-1
1
C6400 0.1UF
10% 16V 2 X7R-CERM 0402
1
C6405 10UF
20% 6.3V 2 CERM-X5R 0402-1
CHS_CLAMPI
1 A
VDD
R6403
U6400
RAMPO/CLAMPI
1.02K2
1
1% 1/16W MF-LF 402
C4
R6401
2.21K2
1
WCSP
RAMPI
R6402
2.21K2
TS3A8237A0YZPR
C
1
1% 1/16W MF-LF 402
EXT_MIC_BIAS
IN
62
C
1% 1/16W MF-LF 402
D4
EXT_MIC_P 61
IN
C6416
FROM HEADSET 61
IN
1
33PF
B1 MIC1 C1 MIC2
5% 50V C0G-CERM 2 0402
AUD_HS_MIC2 D N G D
GND
2 3 3 A C B 61
61
IN IN
59 57
OUT
CHS_CLAMP0
AUD_HS_MIC1 CLAMPO
D3
MIC
D2
REF
D1
SCL
A3
SDA
A4
CPO
B4
1
10UF
MIN_NECK_WIDTH=0.20MM
2 2 B C
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
C6401
TO MIKEY & FILTER
10UF
20% 6.3V 2 CERM-X5R 0402-1
EXT_MIC_N
OUT
62
R6404
1
NOSTUFF
0
1
F E R _ P A C _ S H C
2
5% 1/16W MF-LF 402
C6406
10% 50V 2 X7R-CERM 0402
AUD_HS_RET1
1
CPP
0.001UF
MIN_LINE_WIDTH=0.40MM
C6402
20% 6.3V 2 CERM-X5R 0402-1
2 1 D D N N G G
AUD_HS_RET2
62
NOSTUFF
CHS_SCL
R6406 1
0
2
=I2C_MIKEY_SCL
IN
48 62
5% 1/16W MF-LF 402
CHS_SDA
R6405
GND_AUDIO_HP_AMP
1
0
R6407
2
1
5% 1/16W MF-LF 402
0
2
=I2C_MIKEY_SDA
BI
48 62
5% 1/16W MF-LF 402
B
B
XW6400 SM 1
HPAMP_REF
2
OUT
57
I2C ADDRESSES: CHS uses SMBus 0 connections CHS CHS
U6400 U6400
READ WRITE
0111 0111
0111 0110
0x77 0x76
A
SYNC_MASTER=DIRK_J30
SYNC_DATE=02/16/2012
PAGE TITLE
AUDIO: DETECT/MIC BIAS DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
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REVISION
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64 OF 109 SHEET
58 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
61 57
IN
AUD_HP_PORT_L CRITICAL
C6500
1
0.1UF 10% 16V X7R-CERM
2
0402
AUD_HP_ZOBEL_L
C
R6500
C
1
39 5% 1/16W MF-LF 402
58 57
IN
2
GND_AUDIO_HP_AMP
R6510
1
39 5% 1/16W MF-LF 402
2
AUD_HP_ZOBEL_R CRITICAL
C6510
1
0.1UF 10% 16V X7R-CERM
2
0402
61 57
IN
AUD_HP_PORT_R
B
B
A
S YN C_ MA ST ER =K AV IT HA _J 30
S YN C_ DA TE =0 7/ 25 /2 01 1
PAGE TITLE
AUDIO: HEADPHONE FILTER DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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65 OF 109 SHEET
59 OF 86
1
A
8
7
6
5
SATELLITE
4
2
3
1
& SUB TWEETER AMPLIFIER Gain Pin
Gain dB
Connect to VDD
12
Connect to VDD through 100k
9
Not connected
6
Connect to GND through 100k
3
Connect to GND
0
APN:353S2888 as of July 2011
D
SATELLITE
FC=1.2kHz typical
SUB
FC= 172 HZ typical
GAIN
3DB with Rin=28k typical
D
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
60 7
=PP5V_S3_AUDIO_AMP
1
AUD_LO2_P_R
IN
C6607
CRITICAL
L6611
C6611
FERR-1000-OHM 85 57
SPKRAMP_INR_P
1
1
1 A
0.1UF 10%
0.0047UF
2
85
16V
2
X7R-CERM 0402
10%
L6610
U6610
CERM 402
FERR-1000-OHM 85 57
1
AUD_LO2_N_R
IN
2
85
C6610
0.0047UF 1
SPKRAMP_INR_N
2
MAX98300
CRITICAL
25V
1
PVDD
2
0402
2
85
SSM2315_R_P
85
SSM2315_R_N
WLP
A3 IN+ B3 IN-
OUT+ CRITICALOUT-
CRITICAL
C6601
MIN_LINE_WIDTH=0.30 mm
47UF
MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT
20% 6.3V TANT1 2012-LLP
6 61 85
BI
MIN_LINE_WIDTH=0.30 mm
B1 C1
MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_N_OUT
OUT
6 61 85
0402 10% 25V
CERM 402
NC 1
C 60
1
60 7
2
1
AUD_LO1_P_R
CRITICAL
85
2
SPKAMP1_GAIN
1
R6612 100K 5% 1/16W MF-LF
PGND
5% 1/16W MF-LF 402
2 A
C6608
C6621 1
1
C
2402
1 A
0.1UF
0.033UF SPKRAMP_INSUB_P
10%
2
16V
X7R-CERM 0402
0402
C6620
FERR-1000-OHM 1
AUD_LO1_N_R
85
2
MAX98300
X5R 402
0.033UF SPKRAMP_INSUB_N
1
85
2
85
A3 B3
SSM2315_SUB_P
SSM2315_SUB_N
CRITICAL
C6603
MIN_LINE_WIDTH=0.30 mm
100UF 2
U6620
16V
CRITICAL
L6620
1
PVDD
2
10%
IN
C3
MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0 .20MM
L6621
85 57
GAIN
=PP5V_S3_AUDIO_AMP
FERR-1000-OHM IN
85 57
2 5% 1/16W MF-LF 402
SPKRAMP_SHDN
ALIAS OF PP5VLT_S3,
NC
R6611
0
AUD_GPIO_3
IN
SHDN*
B2
100K
R6610 57
C2
WLP
IN+
OUT+
IN-
CRITICALOUT-
MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT
20% 6.3V TANT CASE-AL1
OUT
6 61 85
OUT
6 61 85
MIN_LINE_WIDTH=0.30 mm
B1 C1
MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_N_OUT
0402 10% 16V
X5R 402
NC
C2
SHDN*
B2
NC
GAIN
C3SPKAMP2_GAIN 1
R6622 100K 5% 1/16W MF-LF
PGND SPKRAMP_SHDN
60
2402
2 A
B
B ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 60 7
=PP5V_S3_AUDIO_AMP
C6609 CRITICAL
L6631 85 57
IN
AUD_LO2_P_L
1
85
2
16V
SPKRAMP_INL_P
X7R-CERM 0402
2
L6630
25V
CERM 402
FERR-1000-OHM 85 57
IN
AUD_LO2_N_L
1
85
2
SPKRAMP_INL_N
0402
PVDD
2
U6630
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT
20% 6.3V TANT1 2012-LLP
MAX98300
CRITICAL
C6630 0.0047UF 1
CRITICAL
C6605 47UF
2
0402 10%
1
1 A
10%
0.0047UF 1
1
0.1UF
C6631
FERR-1000-OHM
2
85
SSM2315_L_P
85
SSM2315_L_N
A3 B3
10% 25V
CERM 402
NC
WLP
IN+
OUT+
IN-
CRITICALOUT-
C2
SHDN*
B2
NC
GAIN
OUT
6 61 85
OUT
6 61 85
MIN_LINE_WIDTH=0.30 mm
B1 C1
MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT
C3SPKAMP3_GAIN 1
R6632 100K
PGND 60
SPKRAMP_SHDN
2 A
5% 1/16W MF-LF
2402
A
SYNC_MASTER=KAVITHA_J30
SYNC_DATE=07/25/2011
PAGE TITLE
AUDI0: SPEAKER AMP DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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1
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8
7
6
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4
AUDIO JACK:LO/HP CONNECTOR, SPDIF TX
L6701 1
AUD_HS_MIC1
2
OUT
58
0402
0 2 0 7 M S 6 W X 1
=PP3V3_S0_AUDIO
1
FERR-1000-OHM AUD_HS_MIC1_UNFILT
62 57 7
2
3
CRITICAL
L6703 FERR-120-OHM-2.0A 1
AUD_HS_RET2
2
OUT
58
OUT
58
OUT
58
0402
Place XW on/near Jack pin
L6702
D
FERR-1000-OHM
D
1
AUD_HS_MIC2_UNFILT
2
0402
Place XW on/near Jack pin
APN:514-0671 J6700
1 2 0 7 M S 6 W X 1
AUD_CONNJ1_USMIC
SPDIF-TXRX-K24
CRITICAL
L6706 FERR-120-OHM-2.0A
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM
F-RT-TH
1
MIC
6
DETECT
5
AUD_CONNJ1_USGND_DET
SWITCH
2
AUD_CONNJ1_TIPDET
LEFT
1
AUD_CONNJ1_TIP
RIGHT
3
AUD_CONNJ1_RING
GND
4
AUD_HS_RET1
2
AUD_CONNJ1_USGND
CRITICAL
AUD_HS_MIC2
0402
AUDIO A - VIN
7
B - VCC
8
C - GND
9
AUD_SPDIF_OUT
IN
57
OPERATING VOLTAGE 3.3
POF 1 10
SHELL PINS
L6704
ANALOG MIC CONNECTOR
FERR-120-OHM-2.0A
10% 2
12
SHIELD
CRITICAL
C6700 1UF
11
6.3V
CERM 402
1
2
13
AUD_HP_PORT_L BI
CRITICAL
APN:518S0520
57 59
J6701
0402
C
78171-0003
CRITICAL
C
M-RT-SM
L6705
4
FERR-120-OHM-2.0A 1
2
AUD_HP_PORT_R BI
57 59
0402
R6700 CRITICAL
DZ6705
2
2
6.8V-100PF 2
2
1
1
DZ6701
DZ6703
AUD_J1_SLEEVEDET_R
2
OUT
62
OUT
62
402
DZ6704
1
R6701
402
1
1
1 CRITICAL
DZ6700
1
2 ESDALC5-1BM2
62 6
BI_MIC_SHIELD
2
62 6
BI_MIC_HI
3
5
SOD882
C6701 100PF
4.7
AUD_J1_TIPDET_R
2
5% 1/16W MF-LF 402
2
CRITICAL
SPEAKER CONNECTOR
5%
J6702
50V
78171-0002
CERM 0402
M-RT-SM
APN:518S0519
GND_CHASSIS_AUDIO_JACK VOLTAGE=0V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM
1
CRITICAL
6.8V-100PF
6.8V-100PF 402
10K
BI_MIC_LO
5% 1/16W MF-LF 402
6.8V-100PF
402 CRITICAL
1
CRITICAL
62 6
CHASSIS GND STITCHES
XW6710 SM 1
3
85 60 6
IN
SPKRAMP_L_P_OUT
1
85 60 6
IN
SPKRAMP_L_N_OUT
2
2 4
XW6711
85 60 6
SM 1
IN
SPKRAMP_SUB_P_OUT
2
R6760
B
1
0
B
CRITICAL
J6703
2
78171-0004
5% 1/16W MF-LF 402
M-RT-SM 5
1 85 60 6
IN
SPKRAMP_SUB_N_OUT
2
85 60 6
IN
SPKRAMP_R_P_OUT
3 4
6
APN:518S0521
85 60 6
IN
SPKRAMP_R_N_OUT
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB
A
NOISE COUPLED ON SPKR LINES
SYNC_MASTER=DIRK_J30
SYNC_DATE=11/10/2011
PAGE TITLE
AUDIO: JACK DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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61 OF 86
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8
7
6
5
4
2
3
1
CODEC OUTPUT SIGNAL PATHS FUNCTION
VOLUME
CONVERTER
PIN COMPLEX
MUTE CONTROL
DET
HP/LINE OUT
0X02 (2)
0X02 (2)
0X09 (9,A)
N/A
0X09 (A)
PORT B LEFT(HEADSET MIC)
ASSIGNMENT
HP=80HZ, LP=8.82KHZ MIKEY
S AT EL LI TE S
0X04 (4)
0 X0 4 ( 4)
SUB SPDIF OUT
N/A
GPIO_3
0X0B (11)
L6880
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V
FERR-1000-OHM
0X03 (3)
0X03 (03)
0X0A (10)
GPIO_3
N/A
N/A
0X08 (8)
0X10 (16)
N/A
0X0D (B)
61 57 7
=PP3V3_S0_AUDIO
1
2
PP3V3_S0_AUDIO_F
WCSP MIKEY 1A
0402
CODEC INPUT SIGNAL PATHS
D
APN:353S2640
I2C addresses: Mikey uses SMBus 0 CONVERTER
FUNCTION
VREF
PIN COMPLEX
BUILT-IN MIC
0X06 (6)
0X0D
HEADSET MIC
0X06 (6)
0X0D (13,V22,B,LEFT)
(13,B,RIGHT)
DET
ASSIGNMENT
MIC_BIAS (80%)
N/A
MIKEY
MIKEY
CRITICAL MIKEY
1
MIKEY
U6880
READ
0111
0011
0x73
MIKEY
U6880
WRITE
0111
0010
0x72
R6885
C6880
100K 5%
1UF
1/16W
SYSTEM GPIO
FUNCTION
PANTHER_POINT GPIO16
N/A
AUD_I2C_INT_L
N/A
PANTHER_POINT GPIO5/PIRQH
58 48
IN
=I2C_MIKEY_SCL
58 48
BI
=I2C_MIKEY_SDA
WCSP
C3
MICBIAS C1
SCL
MIKEY
PANTHER_POINT GPIO3/PIRQH
N/A
U6880 CD3282A1
2
X5R 402
PULLUPS for I2C ON PCH PAGE
SYSTEM INTERRUPT
AUD_IPHS_SWITCH_EN
AUD_IP_PERIPHERAL_DET
AVDD
10V
2
SOUTHBRIDGE RESOURCES
D
MIKEY
10%
MF-LF 402
2 CRITICAL A
1
SDA
DETECT
INT*
BYPASS
18
OUT
AUD_I2C_INT_L
B3 D3
24
IN
AUD_IPHS_SWITCH_EN
A3
ENABLE
A1
HDET
B2
CS
62
TIPDET_UNFILT R6880
1
B1HS_SW_DET D1 HS_RX_BP
1
CRITICAL
C6882 2.2UF
2
20% 6.3V TANT 402-1
D N G D
100K
D N G A
MIKEY
1
GND_AUDIO_CODEC
57 62
C6881 0.01UF
5%
2 2 C D
1/16W MF-LF 402
16V
10%
MIKEY
2
0402X7R-CERM
R6881
2
1
1K 1%
62 57
GND_AUDIO_CODEC
1/16W
MIKEY CRITICAL
57
OUT
PORT A DETECT (HEADPHONES)
402
AUD_SENSE_A
57
OUT
AUD_MIC_INP_L
57
OUT
AUD_MIC_INN_L
1
MIKEY CRITICAL 1
PP4V5_AUDIO_ANALOG_FLT 62
R6804
2
C
Q6803
DMC2400UV
150K 5% 1/16W MF-LF 402
1 61
IN
SOT563
AUD_J1_SLEEVEDET_R
P-CH
62
3
2
AUD_J1_SLEEVEDET_R_INV
20.0K
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
2
1
HS_MIC_HI_RC
EXT_MIC_P
2
R6883
MF-LF 402
402
10% 2
1
C6802
5 G
0.01UF
C6885 27PF
25V
X7R-CERM0402 2
CRITICAL
5% CER M
50V
C
0 40 2 1
CRITICAL
402
R6812
SSM6N37FEAPE
220K
Q6801
D
CRITICAL 3
SSM6N37FEAPE
D
SOT563
1/16W MF-LF
4 S
0402
D
GND_AUDIO_CODEC
SOT563
2 402
6
5
62
6
Q6801
5%
10% 16V
G
S
4 2
AUD_J1_SLEEVEDET_R_BUF
G
NC
S
PORT B RIGHT(BUILT-IN MIC)
1
62
AUD_J1_SLEEVEDET_R_INV
2
2 G
62
58
MIKEY
1
0.0082UF
EXT_MIC_N
2 X7R-CERM
IN
MF-LF
C6884
5% 1/16W
2
MIKEY
1
100K
10% 25V
AUD_PORTB_DET_L
58
1/16W 1
X5R
2
X5R
AUD_PORTA_DET_L
IN
5%
MIKEY
25V 402
0.1UF 1
2
CRITICAL
1
62 57
D
R6805
39.2K
58
2.2K
10%
C6886
1
R6806
OUT
2
R6884
0.1UF
PORT B DETECT(SPDIF DELEGATE)
EXT_MIC_BIAS
MF-LF
MIKEY
C6883
57
220K
APN:376S1081 1
N-CH
IN
100
1
AUD_CODEC_MICBIAS
5% 1/16W MF-LF 402
1 S
R6851
R6850
AUD_J1_SLEEVEDET_R_BUF
R6803
2
2.4K MIC_BIAS_FILT
1
2
1%
1% 1/20W 1
MF 201
1/20W
CRITICAL
MF
C6852
201
2.2UF 20%
GND_AUDIO_CODEC
2
62 57
6.3V TANT 402-1
62 57
GND_AUDIO_CODEC
CRITICAL
CRITICAL
L6801 57 6
1
PP4V5_AUDIO_ANALOG
IN
57
62
OUT
1
AUD_MIC_INP_R
1
C6804
MIN_NECK_WIDTH=0.1MM
AUD_J1_DET_NMOS_DRN
VOLTAGE=5V
0.1UF
10V 402
0.1UF
OUT
1
AUD_MIC_INN_R
25V X5R
1
402
2
BI_MIC_HI
IN
6 61
MF-LF 2
IN
6 61
IN
6 61
1
C6853 0.001UF 50V 10% 0402 X7R-CERM
L6851
2
402
B
FERR-1000-OHM
R6853
X5R
1
GND_AUDIO_CODEC
CRITICAL
5% 1/16W
402
62 57
R6852 100K
2
10% 25V
20% 2 CERM
GND_AUDIO_CODEC
1
BI_MIC_HI_F
10%
C6851 57
2
0402
CRITICAL
PP4V5_AUDIO_ANALOG_FLT
MIN_LINE_WIDTH=0.1MM
62 57
FERR-1000-OHM
0.1UF
2 0402
B
L6850
C6850
FERR-1000-OHM
2.4K
BI_MIC_LO_F
1
2
BI_MIC_LO
2 0402
1% 1/20W
XW6851
APN:376S0634
1
MF 201
SM
4 1
2
BI_MIC_SHIELD
S
S 1
R6801
61
IN
AUD_J1_TIPDET_R
5% 1/16W MF-LF 402
1
100K
2
1
1
C6801 0.1UF 2
R6830 2
R6807
AUD_J1_DET_RC
NOSTUFF 0
Q6804
20% C ER M
10V 4 02
TIPDET_UNFILT
100K 5% 1/20W MF 201
Q6800
Q6804 SSM3K15AMFVAPE
HP=80HZ
D 3
VESM
6
3
AUD_J1_DET_RC2_INV
2
1
1 1
1
C6803 0.1UF 2
20% CER M
10V 402
R6808
R6809 220K
220K 5% 1/16W MF-LF
2
2 402
62
NTZD3152P
G D
D
R6802 5% 1/20W MF 201
1
G
AUD_J1_DET_RC2
220K
2
2
NTZD3152P
5
APN:376S1017
SOT-563-HF SOT-563-HF
62 57
G
S 2
AUD_J1_DET_NMOS_GATE
5% 1/16W MF-LF 402
GND_AUDIO_CODEC
5% 1/16W MF-LF 402
R6810 1
10K 5% 1/16W MF-LF 402
A
2
AUD_IP_PERIPHERAL_DET
OUT
18
EXTRACTION NOTIFICATION
SYNC_MASTER=DIRK_J30
SYNC_DATE=02/20/2012
PAGE TITLE
AUDIO:Jack Translators DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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68 OF 109 SHEET
62 OF 86
1
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7
6
5
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3
1
MagSafe DC Power Jack CRITICAL
J6900
CRITICAL
F6905
78048-0573 M-RT-SM
6AMP-24V
1
6
1
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
2 3 4
D
5
6
2
=PP18V5_DCIN_CONN
7 63
1206-1 1
C6905
=PP3V42_G3H_ONEWIREPROT
0.01UF
ADAPTER_SENSE
20% 50V 2 CERM 0603
2.0K
518S0656
402 MF-LF 1/16W 5%
2
45
1
VCC
4
A
B
MAX9940 SC70-5
4 INT
PLACE_NEAR=U6901.5:1mm
1 45 46
SMC_BC_ACOK
3
EXT 5
NC
GND 2
2
Y
U6900
SYS_ONEWIRE
BI
0.1UF
20% 2 10V CERM 402
U6901
TC7SZ08FEAPE5 SOT665
CRITICAL 1
D
C6908
1
CRITICAL SMC_BC_ACOK_VCC
R6929
7
3
NC
1-Wire OverVoltage Protection
BIL CONNECTOR 7
=PP3V42_G3H_BATT CRITICAL
J6955
CPB6312-0101F
C
C
F-ST-SM 14
63 48 63 48
BI BI
=SMBUS_BATT_SDA =SMBUS_BATT_SCL
46
TO SMC
45 6
SMC_BIL_BUTTON_L
C6952
1
47PF 5%
D6990
BAT30CWFILM
R6905 1
5.0
5% 1/3W MF-LF 0805
B
R6990 63 7
=PP18V5_DCIN_CONN 1
47
2
5% 1/3W MF 0805
PPVIN_G3H_P3V42G3H
3
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
2
P18V5_DCIN_CONN_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
5
8
7 9
NC 12
11
16
15
R6961 6
100
SMC_LID_R
1 1/16W
2 402
SMC_LID
45 46 53
5% MF-LF
NC
C6951
1
1
C6955
0.001UF
0.1UF
10% 2 50V X7R-CERM
20%
10V CERM 2
516S0523
402
0402
P3V42G3H_REF3
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V
3
6
Supply needs to guarantee 3.31V delivered to SMC VRef generator
SOT-323
PBUS_G3H_R
2
4
10
3.425V "G3Hot" Supply
CRITICAL CRITICAL
1
5% 50V CERM 2 402
0402
=PPBUS_G3H
402
47PF
10% 50V X7R-CERM 2
64 7
50V CERM 2
C6953 1
C6954 1
0.001UF
13
2
1
0.1UF
R6995 1.00M
C6990 4.7UF 10% 35V
1/8W
N I V
MF-LF 2805
P3V42G3H_TON
3
X5R-CERM 2 0805
TON
4 EN
P3V42G3H_FB
C6991 1
NC
8
VCC
2
FB
1
B
BYP 9
PM6640 DFN
CRITICAL
L6995
CRITICAL GND 5
353S2776
3 F E R
U6990
REF
1UF
10% 25V X5R 2 603-1
0 1
7
1%
1
C6996
10% 16V 2 X5R 402-1
1
THRM
33UH-20%-0.44A-0.455OHM P3V42G3H_SW
SW 6
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm
PAD
SWITCH_NODE=TRUE
1 1
1
=PP3V42_G3H_REG
7
2
Vout = 3.465
D52LC-SM
DIDT=TRUE
350mA max output
C6994 1
f = 470 kHz
0.1UF
10% 16V X5R 2 402-1
518-0375 CRITICAL
BATTERY CONNECTOR
J6950
1
C6999 22UF
20% 2 6.3V X5R-CERM-1 603
BAT-K90-K91-K92 M-RT-TH
P1 P2 P3 P4 P5 P6
A
P7 P8 P9
SHLD_PIN
1 2 3 4 5 6 7
=SMBUS_BATT_SCL SYS_DETECT_L =SMBUS_BATT_SDA 64 6 PPVBAT_G3H_CONN
8 9 10
SHLD_PIN
11
SHLD_PIN
12 13
SHLD_PIN
6
C6950 0.1UF
1
10% 25V X5R 2 402
C6960
1
48 63
48 63
CRITICAL
D6950 1
2
RCLAMP2402B
SYNC_MASTER=JACK_J30
DC-In & Battery Connectors DRAWING NUMBER
SIZE
3
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
SYNC_DATE=07/29/2011
PAGE TITLE
5% 1/16W MF-LF 4022
1UF
10% 25V X5R 2 603-1
R69501 10K
SC-75
7
6
5
4
3
2
051-9058 6.0.0
REVISION
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1
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8
7
6
5
4
2
3
1 R7091 0
1
Inrush Limiter
Reverse-Current Protection
7
=PPDCIN_S5_CHGR
AON6405L
1
S
D
2
NO STUFF
C7086
1
C7085
1
10% 25V
10% 2 25V X5R 402
2 X5R
603-1
R7085
D PPDCIN_G3H_INRUSH_FET 5
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V
3
470K
0.1UF
1UF
2
G
3
64
PPCHGR_DCIN_D
20
1
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V
1
0.047UF
C7002
BATT_3S 1% 1/16W MF-LF 4022 1
R7010 30.1K
SMC_RESET_L
IN
1% 1/16W MF-LF 2 402
48
IN
48
BI
73
IN
1
R7011 9.31K
2
1
R7015
84
100K
84
1% 1/16W MF-LF 2402
BATT_2S
R70131
1
1% 1/16W MF-LF 4022
B
1
6
C7015
5 2 6 L S I
CELL
3
ACIN
CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N
5
ICOMP
7
VCOMP
8
VNEG
18
CSOP
17
CSON
C7050
10% 16V 2 X5R 402
64
2 26 1 28 84
CSIN 27 84
Vout = 1.25V * (1 + Ra / Rb)
0.02
2
0.5% 1W MF RL1632W
PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
R70251
CASE-D2-SM
1
5% 1/16W MF-LF 4022
C7025 0.22UF 10% 10V
4
C7036 1UF
1
C7037
0.001UF
10% 50V 2 X7R-CERM
C
0402
PLACE_NEAR=C7036.1:3mm
Q7030
RJK03E1DNS
2 CERM 402
HWSON-8
PLACE_NEAR=U7000.25:2mm
36V/V BMON 15 (OD) ACOK 14 D N G P
L7030
4.7UH-9.5A 1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE
GATE_NODE=TRUE DIDT=TRUE
OUT
50
OUT
50
OUT
46 50
180
4
G
Q7035
CHGR_PHASE_RC
RJK03E1DNS
DIDT=TRUE
1
1W MF 0612-3
Q7055 DFN5X6
4
1
2
0
1
2
85
CHGR_CSO_R_P
85
CHGR_CSO_R_N
B
TO/FROM BATTERY
SYM-VER-2
OMIT 2
PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
3
S D
2 1
25V X5R 2 603-1
2.2
CRITICAL AON6403L
0.5%
C7055 1UF 10% R7051 R7052
0402
0.01
3
(CHGR_CSO_N)
0.001UF
CASE-D2-SM
R7050
C7039
(GND)
(CHGR_CSO_P)
C7045
10% 50V 2 X7R-CERM
20% 2 25V POLY-TANT
PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm
470PF
1
C7040 22UF
10% 2 50V CERM
XW7000 SM
CRITICAL 1
CRITICAL BATT_3S
NO STUFF 1
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
0402
C7016
7 63
1206
5% 1/10W MF-LF 6032
OMIT CRITICAL
1 2 3
10% 50V 2 CERM
=PPBUS_G3H
2
IHLP4040DZ-SM
R70391
D
2
TO SYSTEM
F7040
8AMP-24V 1
2
NO STUFF
5
2 353S2929 2
1
CRITICAL
CRITICAL
S
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm 1 2 3 GATE_NODE=TRUE DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm CHGR_LGATE MIN_LINE_WIDTH=0.6 mm
CHGR_BGATE CHGR_AMON CHGR_BMON =CHGR_ACOK
Max Current = 8A (L7030 limit) f = 400 kHz
OMIT CRITICAL
D G
CHGR_VNEG_R 1
1
10% 2 25V X5R 603-1
10% 2 25V X5R 603-1
5
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
0
0
MF-LF 4022
C7035 1UF
22UF
PLACE_NEAR=Q7030.5:1mm
470PF
1% 1/16W
1
C7031
20% 2 25V POLY-TANT
CASE-D2-SM
S
3.01K
CRITICAL 1
C7030
20% 2 25V POLY-TANT
HWSON-8
R70161
CRITICAL 1
22UF
MIN_LINE_WIDTH=0.2 mm
BGATE 16 20V/V AMON 9
D ) A D P N _ G M A R ( H T
PPCHGR_DCIN CHGR_SGATE CHGR_AGATE CHGR_CSI_P CHGR_CSI_N
R7042
5% 1/16W MF-LF 2402
R7020
C7021
5% 50V 2 COG 402
1
CHGR_CSI_R_N
10% 25V 2 X5R 402
MIN_NECK_WIDTH=0.2 mm CHGR_BOOT SWITCH_NODE=TRUE DIDT=TRUE CHGR_UGATE CHGR_PHASE
BOOT 25 UGATE 24 PHASE 23 LGATE 21
9 2
330PF
CHGR_CSI_R_P
85
4 2
CHGR_BOOT_R
VDDP
U7000
1UF
CHGR_VCOMP_R
1K
VDD
CHGR_ACIN
85
0.1UF
10% 25V X5R 2 402
10UF
0 2
12 VHSTCRITICAL DCIN 13 SMB_RST_N SGATE 11 SCL AGATE 10 SDA TQFN CSIP 9 4 VFRQ
CHGR_RST_L =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA CHGR_VFRQ CHGR_CELL
Float CELL for 1S
1% 1/16W MF-LF 402
9 1
1
0.1UF
10% 10V X5R 2 402
5% 1/16W MF-LF 2402
64
C7022 1
1
1UF
100K
0 2 R7000 1 5% 1/16W MF-LF 402
C7001
R7002
GND_CHGR_AGND 47 45 46
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
C7099
20% 10V 2 X5R 603
CRITICAL 3 1
5% 1/16W MF-LF 402
PP5V1_CHGR_VDDP
64
1
10% 10V X5R 2 402
1K
2
5% 1/16W MF-LF 402
NO STUFF
1UF
R70121
4.7
1
10
1
R7001
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V
1
10UF
1% 1/20W MF 2012
2
R7022
0402
PP5V1_CHGR_VDD
C
C7020
C7098
20% 10V 2 X5R 603
R70961
NO STUFF CRITICAL
1
200K
5% 1/16W MF-LF 402
10% 2 10V X5R-CERM
30mA max load
=PP3V42_G3H_CHGR
10
1
1
NO STUFF <Rb>
R7021
(CHGR_DCIN)
(Switcher limit)
NO STUFF CRITICAL
1/20W MF 201 2
P5V5G3H_FB
(CHGR_SGATE)
2
5% 1/16W MF-LF 402
200MA MAX OUTPUT NO STUFF
681K 1%
0201
D
Vout = 5.506V
<Ra>
22PF
64
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.5V
1 C7095 R7095
5% 50V 2 NP0-C0G-CERM
62K
Divider sets ACIN threshold at 13.55V
7
1
5% 1/16W MF-LF 2402
R7005 3
2
PPCHGR_DCIN
PP5V5_CHGR_VDDP
2
(CHGR_AGATE)
1
NO STUFF MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.5V
DP418C-SM
NO STUFF
PAD
9
10% 4.7UF 35V X5R-CERM 2 0805
R7081
1% 1/16W MF-LF 4022
SOT-323
Input impedance of ~40K meets sparkitecture requirements
1
THRM
GND 5
PP5V1_CHGR_VDDP 64
SWITCH_NODE=TRUE DIDT=TRUE
FB 1
C7090 1
1
332K
BAT30CWFILM
ACIN pin threshold is 3.2V, +/- 50mV
33UH-20%-0.39A-0.435OHM
402
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm
2
5% 1/16W MF-LF 402
L7095
P5V5G3H_SW
SW 4
CRITICAL
NO STUFF
CHGR_SGATE_DIV MIN_LINE_WIDTH=0.3 MIN_NECK_WIDTH=0.3 mm mm
0603
R70861
5% 1/16W MF-LF 2402
4
10%
10% 10V
CERM 2
BIAS 2
7 NC
NO STUFF CRITICAL
0.22UF
DFN
R7080
0
1
C7094 1
BOOST
8 SHDN*
1
G
4.7UF
2 25V X5R-CERM
NO STUFF
LT3470A
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V
2
R7092
DIDT=TRUE
NO STUFF
U7090
PPDCIN_G3H_INRUSH
1
S
P5V5G3H_BOOST
3
VIN
5
C7087
1
4
MIN_LINE_WIDTH=0.3 MIN_NECK_WIDTH=0.3 mm mm
D7005
6
100K
1% 1/16W MF-LF 402
CHGR_AGATE_DIV
CRITICAL
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V
OMIT
OMIT
1
PPCHGR_DCIN_D_R
2
DFN5X6
DFN5X6
D
0
5% 1/16W MF-LF 402
Q7080
Q7085 AON6405L
2
5% 1/16W MF-LF 402
R7093
PPCHGR_DCIN_D 1
64
CRITICAL
CRITICAL
FROM ADAPTER
5.5V "G3Hot" Supply
NO STUFF
NO STUFF
1
0.1UF C7056 10%
16V X5R 2 402-1
5
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V
1
0.01UF C7057 10%
1
6 63
G
16V
X7R-CERM 2 0402
4
5% 1/16WMF-LF 402
5% 1/16WMF-LF 402
0402
(PPVBAT_G3H_CHGR_R)
(PPVBAT_G3H_CHGR_R) (CHGR_BGATE)
CHGR_ICOMP_RC 1
C7011 1
C7042
0.068UF
1
10% 16V
10% 10V 2 X5R 402-1
X7R-CERM 2 0402
0402
C7000 1UF
0.01UF
10% 10V 2 X5R-CERM
C7026 1
C7005 1
0.001UF
0.22UF
10% 50V
20% 25V X5R 2 603 64
GND_CHGR_AGND
X7R-CERM 2 0402
TABLE_5_HEAD
P AR T#
QTY
D ES C RI P TI ON
REFERENCE
DESIGNATOR(S)
CRITICAL
BOM OPTION TABLE_5_ITEM
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
1 07 S0 12 91
R ES ,5 MO HM ,1 %, 1W ,0 61 2, 4- TER7050 RM
C RI TI CA LB AT T_ 2S
A
SYNC_MASTER=JACK_J30
PART NUMBER
QTY
DESCRIPTION
376S0927
2
FDMC3020DC
376S0966
2
RJK03E1DNS
REFERENCE DES
CRITICAL
BOM OPTION
QTY
DESCRIPTION
REFERENCE DES
Q7030,Q7035
CRITICAL
CHARGER_POWER_FET:FAIR
PART NUMBER 376S0761
1
SI7137DP
Q7055
CRITICAL CRITICAL
Q7030,Q7035
CRITICAL
CHARGER_POWER_FET:REN
376S0845 376S0845
1 1
SI7149DP SI7149DP
Q7080 Q7085
CRITICAL CRITICAL
BOM OPTION
PBus Supply & Battery Charger DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
8
7
6
5
4
3
SYNC_DATE=09/27/2011
PAGE TITLE
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
70 OF 109 SHEET
64 OF 86
1
A
8
7
6
5
4
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3
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System Agent Power Supply D
D
7 7
=PPVIN_S0_VCCSAS0 =PP5V_S0_VCCSAS0 CRITICAL 1
R71011
C7101
VCCSAS0_BOOT_RC
R7130
5% 1/10W MF-LF 6032
PP5V_S0_VCCSAS0_VCC 0 2
73
1.62K
12
IN
CPU_VCCSASENSE1
CPU_VCCSASENSE_DIV
2
1% 1/16W MF-LF 402
VCCSAS0_SREF 1
41.2K R7147 1%
1/16W MF-LF 2 402
R7153 VCCSAS0_RTN
1.62K2
73
1
R7103
10% 16V
X5R-X7R-CERM 2 0402
PLACE_NEAR=C1761.2:1mm 1
R7148
1% 1/16W MF-LF 2 402
B
1 1 R7152 C7106 R7154 4.64K 4.64K
10PF
1% 1/16W 2 C0G-CERM MF-LF 0402 2 402 5% 50V
1% 1/16W MF-LF 2 402
1
C7105 10PF 5% 50V
R _ T E S _ 0 S A S C C V
1
SET0
9
SET1
5
Q7100
2
GATE_NODE=TRUE DIDT=TRUE
CRITICAL
7
1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
2
FDV0630H-SM
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
VID1
4
6A Max Output
(ENDIAN SWAP)
GND
R71411
PGND
85
VCCSAS0_CS_P
85
VCCSAS0_CS_N
1K
2
C7140 1000PF 2
CPU_VCCSA_VID<1> CPU_VCCSA_VID<0>
1 5% 25V
NP0-C0G 402
499K
(VCCSAS0_OCSET)
1% 1/16W MF-LF 2 402
1
R7142 1K
1% 1/16W MF-LF 2 402
R7149
0402
7
VID0
1
2 C0G-CERM
=PPVCCSA_S0_REG 2
GATE_NODE=TRUE DIDT=TRUE
1% 1/16W MF-LF 4022
IN
MIN_LINE_WIDTH=0.6 mm 3 MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
1% 1W MF-1 0612
f = 300 kHz
82.5K2
IN
1
3 4 5
1
12
PPVCCSA_S0_REG_R
152S0913
SWITCH_NODE=TRUE DIDT=TRUE
C
0.001
L7100
1.0UH-7.7A
VCCSAS0_LL
VCCSAS0_DRVL
3
12
R7140
CRITICAL 1
C7102
10% 16V 2 X5R 603
1% 1/16W MF-LF 402
RJK0222DNS HWSON
VCCSAS0_DRVH MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
6
FSEL
8
2.2UF
R7150
PHASE 16
RTN
VCCSAS0_SET1
6
PLACE_NEAR=Q7100.2:1mm
PGOOD
4 13
UGATE 17
LGATE 1
VCCSAS0_SET0
5% 1/16W MF-LF 402 2
52.3K
14
1000PF
376S0944
DIDT=TRUE
18
BOOT
OMIT_TABLE SREF
12 VO
0
1
7
11 OCSET
VCCSAS0_FSEL
C7103 1
0.022UF
CRITICAL
10 FB
VCCSAS0_OCSET
VCCSAS0_RTN_DIV
1% 1/16W MF-LF 402 2
XW7101 SM
UTQFN
EN
VCCSAS0_VO
PVCCSA_PGOOD
OUT
1
1
15
=PVCCSA_EN
IN
C7122
5% 2 25V NP0-C0G 402
PLACE_NEAR=C7121.1:3mm
2 CERM 402
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
U7100 R7151
B1A-SM
10% 10V
VCCSAS0_VBST
ISL95870A
C
POLY
0.22UF
1
10% 25V X5R 2 603-1
20% 16V 2
C7130
CRITICAL
PVCC
VCC
1
1
1UF
39UF-0.027OHM 1
0
9 1
C7121
C7120 1
DIDT=TRUE
20% 10V 2 X5R 603
5% 1/16W MF-LF 4022
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
CRITICAL
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
10UF
2.2
B
OCP = R7141 x 8.5uA / R7140 OCP = 8.5A
(VCCSAS0_VO)
XW7100 SM VCCSAS0_AGND
1
2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
PLACE_NEAR=U7100.3:1mm
INTEL TABLE: VID1
VID0
353S3074
IC,ISL95870A,PWM,2BIT-VID,RMOT-SNSE,20P U7100 1
CRITICAL
Voltage
0
0
0.9V
1
0
0.8V
0
1
0.725V
1
1
0.675V
A
S Y NC _ MA ST E R= J AC K _J 3 0
S Y NC _ DA T E= 0 9/ 28 / 20 1 1
PAGE TITLE
System Agent Supply DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: .
8
7
6
5
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
3
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REVISION
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PAGE
71 OF 109 SHEET
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3
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5V_S3/3.3V_S5 POWER SUPPLY D
D
VOUT = (2 * RA / RB) + 2
VOUT = (2 * RC / RD) + 2
<RA> R7267 SM 2
<RB> R7268
21K
XW7203 5V_S3_VFB_XW7203
1
1% 1/16W MF-LF 402 1
1% 1/16W MF-LF 402 1
2
<RC> R7270
<RD> R7269 10K
13.7K
1% 1/16W MF-LF 402 1
2
6.49K 1% 1/16W MF-LF 402 1
2
XW7204 SM 2
3V3S5_VFB_R7270
PLACE_NEAR=L7260.1:1 MM
2
1
PLACE_NEAR=L7220.2:1 MM
XW7205 SM 73
C
C R7273
XW7202
1
SM
=PPVIN_S5_5VS3 CRITICAL
C7282
1
0.001UF
20% 50V 2 CERM 402
1
20%
10% 25V 2 X5R 603-1
1UF
82UF
2 16V
ELEC
B6S-SM
1
2
4
G
MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2
2
HWSON-8
DIDT=TRUE
MIN_LINE_WIDTH=0.6
S
L7260
2 1
MM MM
P5VS3_ENTRIP
OMIT CRITICAL
CRITICAL
D
C7291 220UF
VREG3
TONSEL
VREG5
U7200
0.1UF
DRVH1
19 24 2 1
DRVH2
QFN
LL1
LL2
5 2 1 1 5 S P T
DRVL1 VO1
VFB1 ENTRIP1
G
4
DRVL2 VO2
VFB2 ENTRIP2
PP5V_S5_LDO
9
P3V3S5_VBST
VCLK
R7271 115K
3 2 1
EN0
1% 1/16W MF-LF 2 402
S
5% 1/16W MF-LF 402 1
10
P3V3S5_DRVH DIDT=TRUE
11
P3V3S5_LL
12 7
P3V3S5_VFB
6
P3V3S5_ENTRIP
18
13
C7242
0.001UF
82UF
20% 2 50V CERM 402
20%
2 16V
ELEC
B6S-SM
PLACE_NEAR=C7241.1:3MM
CRITICAL
P3V3S5_VBST_R MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2
RJK0216DPA
MM MM
MIN_LINE_WIDTH=0.6
MM
MIN_NECK_WIDTH=0.2
MM
WPAK2
1
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2
CRITICAL
7
DIDT=TRUE
L7220
MM MM
2.2UH-14A
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2
P3V3S5_VO2
5
1
C7240
Q7220
P3V3S5_DRVL
MM MM
1
6
DIDT=TRUE
2
B
IHLP2525CZ-SM1
=PP3V3_S5_REG 7
3 4 5
NC
CRITICAL
5V3V3_REG_EN
1
C7273
5 2
GND_5V3V3S5_SGND
1
1
R7272
2
150UF
1% 1/16W MF-LF 402
1
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V
C7251
1
C7250 10UF
20% 6.3V 2 X5R 603
20% 2 6.3V POLY B1A-SM
78.7K
10UF
20% 6.3V 2 X5R 603
GND THRM_PAD 5 1
2
2
MIN_LINE_WI DTH=0.6 MM MIN_NECK_WI DTH=0.2 MM
PGOOD 23
1
10% 25V 2 X5R 603-1
CRITICAL 1
PLACE_NEAR=Q7220.2:1MM
0
17
DIDT=TRUE
RJK03E0DNS HWSON-8
20% 2 6.3V ELEC D1A-SM
SKIPSEL
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
Q7261
1
10UF C7290
20
P5VS3_VFB
5
20% 10V 2 X5R 603
21
P5VS3_VO1
PCMB104E4R7-SM
1
P5VS3_DRVH P5VS3_LL P5VS3_DRVL
DIDT=TRUE
2
=PP5V_S3_REG
4
8
C7241 1UF
10% 16V X7R-CERM 2 0402
P5VS3_VBST22 VBST1 CRITICALVBST2
MM MM
DIDT=TRUE
4.7UH-13A-15MOHM3 1
MIN_NECK_WIDTH=0.2 MIN_LINE_WIDTH=0.6 MIN_NECK_WIDTH=0.2
MM MM
1
1
R7220
VREF
DIDT=TRUE
MIN_LINE_WI DTH=0.6 MM MIN_NECK_WI DTH=0.2 MM
CRITICAL
=PPVIN_S5_3V3S5 7
C7220
3
VIN 14
0
5% 1/16W MF-LF 402
P5VS3_VBST_R 1
1
6 1
R7260
X7R-CERM 0402
D
Q7260
2 CERM 603
C7271 0.22UF
0.1UF 10% 16V
OMIT CRITICAL RJK03E1DNS
MAX CURRENT = 12.947A PWM FREQ. = 300 KHZ
20% 10V
10% 10V 2 CERM 402
C7260
5
0.001UF C7293
7
C7270 1UF
P5VP3V3_VREF
PLACE_NEAR=Q7260.5:1MM
20% 50V 2 CERM 402
=PP5V_S5_LDO
C7281
C7280
1
PLACE_NEAR=C7281.1:3MM
1
2
P5VP3V3_REG3 1
7
5% 1/16W MF-LF 402
10% 2 25V X5R 603-1
1
1
100K
C7272 1UF
2
PLACE_NEAR=C7291.1:1 MM
B
1
=PPVIN_S5_5VS3
66 7
66 7
2
=P5V3V3_REG_EN
1
C7253 0.001UF
20% 50V 2 CERM 402
MAX CURRENT = 7.45A PWM FREQ. = 375 KHZ
2
XW7201 SM
D 6
Q7221
PLACE_NEAR=U7200.25:1 MM
SSM6N37FEAPE
P5V3V3_PGOOD
SOT563
73
IN
=P5VS3_EN_L
2 G
S 1 D 3
73
Q7221 SSM6N37FEAPE SOT563
A
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION 73
376S0927
1
FDMC3020DC
Q7260
376S0928
1
FDMC2514SDC
Q7261
5V_S3_POWER_FET:FAIR
376S0966
1
RJK03E1DNS
Q7260
5V_S3_POWER_FET:REN
376S0895
1
RJK03E0DNS
Q7261
5V_S3_POWER_FET:REN
IN
=P3V3S5_EN_L
5 G
S 4
SYNC_MASTER=JACK_J30
SYNC_DATE=08/22/2011
PAGE TITLE
5V_S3_POWER_FET:FAIR
5V/3.3V SUPPLY DRAWING NUMBER
Apple Inc. SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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66 OF 86
1
A
8
7
6
5
4
2
3
1
D
D
=PPVIN_S3_DDRREG
7
TABLE_ALT_HEAD
CRITICAL
CRITICAL 1
1
C7330
39UF-0.027OHM
7
20% 2 16V POLY B1A-SM
=PPVIN_S0_DDRREG_LDO
C7332
1
1UF
39UF-0.027OHM
CRITICAL
C7333
1
0.001UF
P AR T N UM BE R
C7334
20% 2 16V POLY-TANT
2 X7R-CERM
0402
ALTERNATE FOR PART NUMBER
B OM O PT IO N
REF DES COMMENTS: TABLE_ALT_ITEM
33UF
10% 50V
10% 25V 2 X5R 603-1
20% 2 16V POLY B1A-SM
128S0299 128S0218
ALL
128S0093 128S0218
ALL
TABLE_ALT_ITEM
CASED2E-SM
NO STUFF PLACE_NEAR=Q7330.5:1mm
=PP5V_S3_DDRREG
7
1
C7331
PLACE_NEAR=C7332.1:3mm
C7301 1 10UF
20% 10V X5R 2 603
C7300 1 10UF
5
PLACE_NEAR=U7300.2:1mm
20% 10V X5R 2 603 PLACE_NEAR=U7300.12:1mm
C
R7325
MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm 402
VLDOIN 12 V5IN 31
DDRREG_FB =DDRVTT_EN =DDRREG_EN
IN
26 8
IN
73
IN
VTT Enable
17 S3
6 1
R7315
1
8
20.0K
0.1UF
DDRREG_MODE DDRREG_TRIP
1% 1/16W MF-LF 2402
10% 16V
X7R-CERM 2 0402 PLACE_NEAR=U7300.6:1mm
DDRREG_VBST DDRREG_DRVH DDRREG_LL
VBST 15 DRVH 14
U7300
SW 13
TPS51916
16 S5
VDDQ/VTTREF Enable
DDRREG_1V8_VREF
C7315
R7319
DRVL 11 PGOOD 20
VDDQSNS 9 VTT 3
19 MODE
7
2
3
Q7319 D
2
S
C7316 0.01UF
1% 1/16W MF-LF 2402
DDRREG_P1V35_L
NO STUFF
1
100K
R7317 1R7318
1
10% 16V 2 X7R-CERM
PLACE_NEAR=U7300.19:3mm
SSM3K15AMFVAPE
7
4
1
C
OMIT S
2
CRITICAL
L7330
1 2 3
10% 25V X5R 402
0.88UH-20%-19A-2.3MOHM 1
2
=PPDDR_S3_REG
DDRREG_VTTSNS
1
load
D
2 (DDRREG_DRVL)
4
CRITICAL
C7360 1 10UF 20%
1 2
6.3V 2 X5R 603
PLACE_NEAR=C3101.1:1mm
1
5
=PPVTT_S3_DDR_BUF max
MPCG1040LR88-SM
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
PLACE_NEAR=C7361.1:3mm
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2402
(DDRREG_LL)
DIDT=TRUE
66.5K
200K
0402
PLACE_NEAR=U7300.8:1mm
PLACE_NEAR=U7300.8:5mm
0 1
DDRREG_VBST_RC
DDRREG_DRVL DIDT=TRUE DDRREG_PGOOD OUT 8 DDRREG_VDDQSNS =PPVTT_S0_DDR_LDO XW7360
VTT THRM PGND GND GND PAD
R7316
1% 1/16W MF-LF 402
HVSON-3333
0.1UF
MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
RJK0225DNS
C7325
SM
VTTSNS 1
18 TRIP VTTREF 5
1
150K
Q7330
G
4
GATE_NODE=TRUE
PLACE_NEAR=U7300.8:5mm
1
MF-LF 1 /1 /1 6W 2
DIDT=TRUE
CRITICAL
REFIN
0
5% 1
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
SWITCH_NODE=TRUE
QFN
VREF
10mA
NO STUFF
CRITICAL
D (DDRREG_DRVH)
2
CRITICAL 1
C7361
(Q7335 limit) 1
C7341
OMIT
330UF
1
20% 2.0V 2 POLY-TANT CASE-B2-SM1
1 2 3
C7346
f = 400 kHz
0.001UF
CRITICAL
S
10UF
20% 2 6.3V X5R 603
14.1A max output
20% 2 2.0V POLY-TANT CASE-B2-SM1
Q7335 HVSON-333
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm
Vout = 1.5V
330UF
CRITICAL
RJK0226DNS
G
CRITICAL
C7340
1
C7345
10% 50V 2 X7R-CERM
0402
10UF
2
20% 6.3V 2 X5R 603
XW7301 SM
1
PLACE_NEAR=C7340.1:1mm
PLACE_NEAR=C3101.1:3mm
C7360, C7361 close to memory
2
PLACE_NEAR=U7300.18:3mm
XW7300
C7350 1
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm
0.22UF
SM
VESM
1
10%
10V CERM 2 402
PLACE_NEAR=U7300.21:1mm
G
1
B
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V
MEM_VDD_SEL_1V5_L
PART NUMBER
IN
QTY
B
23
DESCRIPTION
376S0979
1
FDMC0225
376S0874
1
FDMC0202S
REFERENCE DES
CRITICAL
BOM OPTION
Q7330
DDR_POWER_FET:FAIR
Q7335
DDR_POWER_FET:FAIR
A
SYNC_MASTER=JACK_J30
SYNC_DATE=07/28/2011
PAGE TITLE
1.5V DDR3 Supply DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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73 OF 109 SHEET
67 OF 86
1
A
8
7
6
5
4
2
3
=PP5V_S0_CPUIMVP
1
7 69
R7401 PP5V_S0_CPUIMVP_VCC
68
1
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V
D
10
7
2
5% 1/16W MF-LF 402
=PPVCCIO_S0_CPUIMVP
=PPVIN_S0_CPUIMVP 7 1
54.9 1%
1/16W MF-LF 4022
PLACE_NEAR=U7400.18:2mm
20% 10V
1
R7480
X5R-CERM 2
PLACE_NEAR=U7400.19:2mm PLACE_NEAR=U7400.29:2mm
A D D V
Note: value needs scrubbing
B D D V
OUT
CPUIMVP_AXG_PWM2 NC
13 37 45
CPU_PROCHOT_L
4
1
1
C7450 43PF
73
IN
78 12
IN
78 12
IN
78 12
IN
24
OUT
73
OUT
CPUIMVP_PGOOD CPUIMVP_AXG_PGOOD
CPUIMVP_VR_ON CPU_VIDSOUT CPU_VIDSCLK CPU_VIDALERT_L
R7468 5.76K
1% 1/16W MF-LF 2 402
1
R7466
1
OMIT
1
R7464
5.76K
R7462 196K
NOSTUFF
1% 1/16W MF-LF 2 402
NONE NONE NONE
1% 1/16W MF-LF 2 402
2 402
24
POKA
12
POKB EN
21
CPUIMVP_NTC CPUIMVP_NTCG
1
TONA
48
CPUIMVP_TONA
CRITICAL BSTA1
25
CPUIMVP_BOOT1 CPUIMVP_UGATE1 CPUIMVP_PHASE1 CPUIMVP_LGATE1 CPUIMVP_ISUM1_P
DRVPWMA
DHA1 27
VRHOT*
26
41
ALERT*
3 44
CSPA2
THERMA
32
DHA2
THERMB
33
LXA2
CPUIMVP_SLEW
38
SR
DLA2
CPUIMVP_IMAXA CPUIMVP_IMAXB
35
IMAXA
BSTB
36
IMAXB
DHB
31 14
R7460
8
215K
15 18
DLB
CSPBAVE
1% 1/16W MF-LF 2 402
CSPB2
1
CRITICAL
1
AGND
CRITICAL
R7467
1
100KOHM
100KOHM
0402
0402
1% 1/16W MF-LF 2 402
R7469 2
1
R7465
R7463
200K
2
137K
1% 1/16W MF-LF 2402
1
R7461
5 0 2 2
137K
7 9 0 4 3
69
OUT
69
R7407
2
1
1% 1/16W MF-LF 402
C7408 150PF 1
OUT
CPUIMVP_FBB
NO STUFF
1
XW7400 SM 2
2
CPUIMVP_ISNS2_P
IN
49 69 85
CPUIMVP_ISUM_R
69
10% 25V
IN
X7R-CERM 0201
69
PP5V_S0_CPUIMVP_VCC
C7409
68
1 69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
2
1
1
C
AXG_PHASE1
2
1
R7430
5% 1/20W MF 201
10% 16V
X7R-CERM 0201
OUT
68
R7410
1000PF
OUT
0
5% 1/16W MF-LF 2 402
CPUIMVP_ISUMG2_P
IN
69
CPUIMVP_ISUMG1_P
IN
69
CPUIMVP_ISUMG_N
IN
69 85
69
68
C7418 100PF
5% 25V 2 NP0-CERM 0201
1
1
NO STUFF
C7419 100PF
5% 25V 2 NP0-CERM 0201
1
NO STUFF NO STUFF NO STUFF
C7414 100PF
5% 25V 2 NP0-CERM 0201
1
C7415 100PF
5% 25V 2 NP0-CERM 0201
1
C7416 100PF
5% 25V 2 NP0-CERM 0201
1
NO STUFF
C7423 100PF
5% 25V 2 NP0-CERM 0201
NO STUFF
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
PLACE_NEAR=Q7550.1:1mm
2
200
5% 1/20W MF 201
NO STUFF
GND_CPUIMVP_SGND PLACE_NEAR=Q7510.1:1mm
B
49 69 85
IN
B D N G P 7 1
1% 1/16W MF-LF 2402
OUT
150K
CPUIMVP_ISNS1_P
11
6
FBB A M D D N R A G H P P T
69
2
10
CSNB B S D N G
69
OUT
9
CSPB1
A S D N G
CPUIMVP_BOOT1G CPUIMVP_UGATE1G CPUIMVP_PHASE1G CPUIMVP_LGATE1G
16
LXB
1
CPUIMVP_ISUM2_P CPUIMVP_BOOT2 CPUIMVP_UGATE2 CPUIMVP_PHASE2 CPUIMVP_LGATE2
34
BSTA2
OUT
200
5% 1/20W MF 201
R7402 1
CPUIMVP_ISUM CPUIMVP_ISUM_N CPUIMVP_FBA
43
FBA
CLK
22
40
42
CSNA
VDIO
23
39
28
DLA1 CSPA1
CSPAAVE
1
1% 1/16W MF-LF 402
CPUIMVP_TONB
TONB
DRVPWMB
47
182K2
1
LXA1
5% 50V 2 C0G-CERM 0402
C
QFN
CSPA3
R7406
R7403
U7400 MAX15119GTM
OUT
2.2UF
6 9 9 4 2 1
PLACE_NEAR=U7400.16:2mm
C C V
78 46 45 10
D 69
C7403
402
130 1% 1/16W MF-LF 2402
69
1
20% 2 10V X5R-CERM 402
20% 2 10V X5R-CERM 402
2.2UF
R74791
C7402 2.2UF
C7401 1
C7452 1
1
1000PF
10% 16V 2 X7R-CERM
0201
B
100PF
C7440 CPU_AXG_SENSE_R
10
1
2
CPU_AXG_SENSE_N
IN
2
5% 25V NP0-CERM 0201
R7440 12 78
1
C7412 1000PF 10% 16V
2 X7R-CERM
0201
69
IN
CPUIMVP_ISUMG_AVE_P
1/20W 5% MF 201
C7441 1 1000PF
10% 16V X7R-CERM 2
68
CPUIMVP_FBA
7.68K2 R7412 1
R7441
0201
CPU_VCCSENSE_R
C7442 1000PF
10% 16V 2 X7R-CERM
0201 PLACE HOLDER
10
2
CPU_VCCSENSE_N
IN
12 78
C7443
CPU_VCCSENSE_P
IN
12 78
C7422 1000PF
1/20W NO STUFF 1
10 2 R7413 R 1 7413 5% 1/20W MF 201
1
5%
NO STUFF 1
1
CPUIMVP_FBA_R
1% 1/20W MF 201
MF 201
R7422
1000PF
10% 16V 2 X7R-CERM
68
CPUIMVP_FBB
0201 PLACE HOLDER
8.25K2
1
1% 1/20W MF 201
C7462
10% 16V 2 X7R-CERM
R7423
0201
CPUIMVP_FBB_R
10
1
CPU_AXG_SENSE_P
2
IN
12 78
5% 1/20W MF 201
100PF 1
2
5% 25V NP0-CERM 0201
NO STUFF
A
SYNC_MASTER=JACK_J30
SYNC_DATE=08/03/2011
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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74 OF 109 SHEET
68 OF 86
1
A
8
7 69 68 7
6
3.3
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
C7511
D
IN
CPUIMVP_UGATE1
10% 16V 2 X5R-CERM
C7516
1
C7517 1UF
10UF 0805
1
C7518
1
CRITICAL
C7519
1
0.001UF
0.001UF
20% 2 16V POLY-TANT
0402
0402
C7540 33UF
10% 50V 2 X7R-CERM
10% 50V 2 X7R-CERM
10% 25V 2 X5R 402
10% 16V 2 X5R-CERM
0805
B6S-SM
CRITICAL
1
10UF
ELEC
CASED2E-SM
NOSTUFF
PLACE_NEAR=Q7510.1:1mm PLACE_NEAR=C7517.1:3mm
CRITICAL
Q7510
DIDT=TRUE
7
TGR
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V
SWITCH_NODE=TRUE
152S1271
D
0612
1
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V
FCUL1040-SM
SWITCH_NODE=TRUE
8 5
1% 1W MF
0.36UH-20%-35A-0.00081OHM PPVCORE_S0_CPU_PH1_L 1 2 PPVCORE_S0_CPU_PH1
VSW 6 4
0.00075
L7510
VIN 1
SON5X6
TG
R7510
CRITICAL
CSD58872Q5D 3
MIN_LINE_WIDTH=0.5 DIDT=TRUE MM GATE_NODE=TRUE MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE1
IN
68
1
376S1005
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
2
3
CRITICAL
CPUIMVP_UGATE1_R
2
5% 1/16W MF-LF 402
CPUIMVP_PHASE1
IN
68
C7515
1
20%
2 16V
0.22UF
10% 10V 2 CERM 402
DIDT=TRUE
1
1
MIN_LINE_WIDTH=0.5 DIDT=TRUE MM GATE_NODE=TRUE MIN_NECK_WIDTH=0.2 MM
CRITICAL
C7514
82UF
20% 2 16V ELEC B6S-SM
R7515 68
1
C7513 82UF
1
5% 1/16W MF-LF 4022
CPUIMVP_BOOT1
CRITICAL
CRITICAL 1
DIDT=TRUE
R75111
IN
4 THESE TWO CAPS ARE FOR EMC
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
PHASE 1
68
5
=PPVIN_S0_CPUIMVP CPUIMVP_BOOT1_RC
=PPVCORE_S0_CPU_REG7
2
3
69
4
CPUIMVP_ISNS1_N CPUIMVP_ISNS1_P
OUT
49 85
OUT
49 68 85
BG
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
1
1
10 R7514
46.4 R7513 1%
PGND 9
1% 1/20W MF 2201
1/20W MF 2012
CPUIMVP_ISUM_N
IN
68 69
IN
68
PLACE_NEAR=U7400.43:1mm 1
C7571 2200PF
69 68 7
5% 1/16W MF-LF 4022
CPUIMVP_BOOT2 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
20% 2 16V ELEC B6S-SM
C7521
IN
CPUIMVP_UGATE2
68
IN
68
IN
GATE_NODE=TRUE DIDT=TRUE
MIN_LINE_WIDTH=1.5 MIN_NECK_WIDTH=0.2 MM MM
1
20%
10% 2 16V X5R-CERM
10UF
82UF
2 16V
ELEC
0805
B6S-SM
1
C7526
C7527
1
1UF
10UF
10% 2 16V X5R-CERM
C7528
1
C7529
1
0.001UF
0.001UF
CPUIMVP_ISUM1_P
20% 2 16V POLY-TANT
0402
0402
CASED2E-SM
NOSTUFF
CRITICAL
Q7520
PPVCORE_S0_CPU_PH2_L
VSW 6
DIDT=TRUE SWITCH_NODE=TRUE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.5 MIN_NECK_WIDTH=0.25MM MM VOLTAGE=1.25V
8
CPUIMVP_LGATE2
152S1271
5 BG
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
PGND
0612
=PPVCORE_S0_CPU_REG
2
3
4
R75231
1
CPUIMVP_ISNS2_N CPUIMVP_ISNS2_P
7 69
OUT
49 85
OUT
49 68 85
R7524 10
46.4
Removed snubber with EMC’s comment
376S1005 9
1
MIN_LINE_WIDTH=0.5 MIN_NECK_WIDTH=0.25MM MM VOLTAGE=1.25V
FCUL1040-SM
C
1% 1W MF
0.36UH-20%-35A-0.00081OHM 1 2 PPVCORE_S0_CPU_PH2
DIDT=TRUE
7
4 TGR
0.00075
L7520
VIN 1
SON5X6
R7520
CRITICAL
CSD58872Q5D 3 TG
MIN_LINE_WIDTH=0.5 DIDT=TRUE MM GATE_NODE=TRUE MIN_NECK_WIDTH=0.25 MM
C7530 33UF
10% 2 50V X7R-CERM
10% 50V 2 X7R-CERM
10% 2 25V X5R 402
0805
1
CRITICAL
CPUIMVP_UGATE2_R
2
5% 1/16W MF-LF 402
CPUIMVP_PHASE2
C7525
C7524
PLACE_NEAR=Q7520.1:1mm PLACE_NEAR=C7527.1:3mm
DIDT=TRUE
1
1
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
1
CRITICAL
CRITICAL
CRITICAL
0.22UF
10% 10V 2 CERM 402
R7525 68
C7523 82UF
1
2.2
C
1
DIDT=TRUE
R75211
IN
0201
THESE TWO CAPS ARE FOR EMC
CRITICAL
CRITICAL
MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.25 MM MM
PHASE 2
68
10% 10V 2 X7R-CERM
=PPVIN_S0_CPUIMVP CPUIMVP_BOOT2_RC
1% 1/20W MF 2012
1% 1/20W MF 2 201
CPUIMVP_ISUM_N PLACE_NEAR=U7400.43:1mm 1
IN
68 69
IN
68
C7572 2200PF
10% 10V 2 X7R-CERM
0201
7
CPUIMVP_ISUM2_P
=PPVIN_S0_CPUAXG THESE TWO CAPS ARE FOR EMC
THESE TWO CAPS ARE FOR EMC
CRITICAL
CRITICAL 1
CPUIMVP_UGATE1G_R
B
CRITICAL
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
2.2
10% 10V
TG
4
TGR
5
BG
CERM 2 402
IN
MIN_NECK_WIDTH=0.2 DIDT=TRUE MM MIN_LINE_WIDTH=0.5 GATE_NODE=TRUE MM 68
IN
68
IN
1
1
2
SWITCH_NODE=TRUE DIDT=TRUE
CPUIMVP_PHASE1G
10% 25V 2 X5R 402
1
C7558
1
0.001UF
1
0.001UF
10% 50V 2 X7R-CERM
POLY-TANT
OUT
CPUIMVP_ISNS1G_P
R75531 46.4
1% 1/20W MF 201 2
9
DIDT=TRUE MIN_LINE_WIDTH=1.5 MM SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.2 MM
0612
CRITICAL
POLY-TANT
0805
CASED2E-SM
1
C7564
C7565
1
10% 16V 2 X5R-CERM
=PPVCORE_S0_AXG_REG
NOSTUFF
0402
CPUIMVP_ISNS1G_N
OUT
SON5X6
3 TG
VIN
1
VSW
1% 1/20W MF 2 201
OU T
CPUIMVP_ISNS2G_P AXG_PHASE2
CPUIMVP_ISUMG_N 1
IN
1AXG_PHASE2
1
IN
AXG_PHASE2
R7540
5
10K
A
5% 1/16W MF-LF 2402 68
AXG_PHASE2
VDD
CPUIMVP_SKIP
2 6
TQFN
PWN
R7542 0
5% 1/16W MF-LF 402 2
AXG_PHASE2 BST 1
CRITICAL DH 8
SKIP*
LX 7 DL 4 GND 3
THRM PAD
9
CPUIMVP_BOOT2G MIN_LINE_WIDTH=0.25 MM DIDT=TRUE MIN_NECK_WIDTH=0.2 MM
CPUIMVP_UGATE2G MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
0201
AXG_PHASE2 1
C7542
Note: value needs scrubbing
1
200
1% 1/20W MF 2201
DIDT=TRUE GATE_NODE=TRUE 5%
1/16W MF-LF 402
CPUIMVP_PHASE2G
CPUIMVP_UGATE2G_R
68
Note: value needs scrubbing
CPUIMVP_ISUMG_AVE_P
68
SYNC_DATE=07/28/2011
DRAWING NUMBER
0
DIDT=TRUE
Note: value needs scrubbing
10%
16V X7R-CERM 2 0201
CPUIMVP_ISUMG_N
R
CPUIMVP_ISUMG_AVE_R_P NOSTUFF
C7568 1 OUT
Apple Inc.
5% 1/20W MF 2201
GATE_NODE=TRUE
DIDT=TRUE GATE_NODE=TRUE
1
C7569 330PF
10% 16V 2 X7R 201
Note: value needs scrubbing
5
CPU IMVP7 & AXG VCore Output
R7566
DIDT=TRUE MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE
6
OUT
SYNC_MASTER=JACK_J30
1
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
1000PF
7
OUT
PAGE TITLE
2
85 69 68
8
CPUIMVP_ISUMG2_P
49 69 85
R7564
100
1% 1/20W MF 2012
R7567 1
OUT
AXG_PHASE2 1
R75631
0.22UF
10% 10V 2 CERM 402
CPUIMVP_LGATE2G
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
68 69 85
10% 10V 2 X7R-CERM
CPUIMVP_ISNS1G_P 1
U7542 CPUIMVP_AXG_PWM2
OUT
2200PF
68
AXG_PHASE2
10% 25V 2 X5R 402
MAX17491 IN
CPUIMVP_ISUMG_N
DIDT=TRUE
1UF
1
49 85
C7573 AXG_PHASE2
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
C7541
OUT
PLACE_NEAR=U7400.10:1mm
376S1005
CPUIMVP_BOOT2G_RC AXG_PHASE2 1
69
10
1% 1/20W MF 2201
0201PLACE_NEAR=U7400.10:1mm
=PP5V_S0_CPUIMVP
CPUIMVP_ISNS2G_N
R7562
PGND 9
=PPVCORE_S0_AXG_REG7
4
1
1% 1/20W MF 2012
5 BG
10% 10V 2 X7R-CERM
CPUIMVP_ISUMG1_P
2
3
46.4
68 69 85
C7574
B
1W MF
0612
1
R7561
8
CPUIMVP_LGATE1G
0402
6 7
4 TGR
0.001UF
CRITICAL
SWITCH_NODE=TRUE
85 49
10
C7567
10% 50V 2 X7R-CERM
R7560
MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM FCUL1040-SM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM 152S1271 VOLTAGE=1.05V
CSD58872Q5D Q7560
49 85
R7554
1
0.36UH-20%-35A-0.00081OHM 0.00075 1 2 PPVCORE_S0_AXG2_L 1% CPUIMVP_VSWG2
7 69
CRITICAL
1
10% 50V 2 X7R-CERM
AXG_PHASE2
AXG_PHASE2
L7560
AXG_PHASE2
C7566
0.001UF
10% 25V 2 X5R 402
0805
PLACE_NEAR=Q7560.1:1mm PLACE_NEAR=C7565.1:3mm
Reserve for acoustic noise
4
1
1UF
10UF
CRITICAL
2
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
AXG PHASE 2
10% 16V 2 X5R-CERM
2 16V
NOSTUFF
C7563 10UF
33UF
1% 1W MF
1
MIN_LINE_WIDTH=0.5 MM 3 MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.05V
1
C7562
CASED2E-SM
NOSTUFF
2200PF
68 7
2 16V
CASED2E-SM
R7550 CRITICAL
152S1271
1
20%
20%
20% 2 16V POLY-TANT
0402
C7561 33UF
33UF
10% 50V 2 X7R-CERM
0402 PLACE_NEAR=Q7550.1:1mm PLACE_NEAR=C7557.1:3mm
1
C7560
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C7559
0.00075
PGND
5% 1/16W MF-LF 402
0805
C7557 1UF
10% 16V 2 X5R-CERM
L7550
8
1
10UF
0.36UH-20%-35A-0.00081OHM 1 2 PPVCORE_S0_AXG_R
MIN_LINE_WIDTH=0.5 MM FCUL1040-SM MIN_NECK_WIDTH=0.25 MM
85 69 49
R7555
CPUIMVP_UGATE1G
C7556
CPUIMVP_VSWG
7
DIDT=TRUE MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.2 MM MM
68
0805
CRITICAL 1
CRITICAL
VSW 6
0.22UF
CPUIMVP_BOOT1G
IN
10% 16V 2 X5R-CERM
ELEC
B6S-SM
VIN 1
SON5X6
3
C7551 1
5% 1/16W MF-LF 4022
68
20%
10UF
2 16V
CSD58872Q5D
R75511
C7555
1
Q7550
DIDT=TRUE
CRITICAL
C7554 82UF
20% 2 16V ELEC B6S-SM
376S1005
CPUIMVP_BOOT1G_RC
AXG PHASE 1
1
C7553 82UF
MIN_NECK_WIDTH=0.25 DIDT=TRUE MM MIN_LINE_WIDTH=0.5GATE_NODE=TRUE MM
4
3
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
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1
A
8
7
6
5
4
2
3
1
D
D
CPU VCCIO (1.05V S0) Regulator
7 7
=PPVIN_S0_CPUVCCIOS0 =PP5V_S0_CPUVCCIOS0
CPUVCCIOS0_VBST_RC MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
20% 10V 2 X5R 603
5% 1/16W MF-LF 4022
C
78 12
CPU_VCCIOSENSE_P
78 12
CPU_VCCIOSENSE_N
C7601 1R7630 10UF
2.2
PP5V_S0_CPUVCCIOS0_VCC
1
1
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
4 1
3 1
1
C7621
5% 25V 2 NP0-C0G 402
C7630
2
1
C7624 1UF 10% 25V
2 X5R
603-1
PLACE_NEAR=Q7630.2:1mm
1UF
DIDT=TRUE
C7622 1000PF
39UF-0.027OHM
20% 2 16V POLY B1A-SM
20% 2 16V POLY B1A-SM
CPUVCCIOS0_VBST
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
1
C7620
39UF-0.027OHM
0
5% 1/16W MF-LF 2 402
CRITICAL
CRITICAL
DIDT=TRUE
1
R76011
PLACE_NEAR=C7624.1:3mm
10% 25V X5R 402
C
VCC PVCC
R76041 3.01K
1% 1/16W MF-LF 4022
1
R7644
U7600
3.01K
73
=CPUVCCIOS0_EN
IN
<Ra>
73
2.74K
1% 1/16W MF-LF 4022
3
UTQFN
EN
CRITICAL
OUT
1
R7645
1% 1/16W MF-LF 2 402
C7602 1 2.2UF
10% 16V X5R 2 603
<Rb>
47PF 5%
50V CERM 2 402
CPUVCCIOS0_VO
8
CPUVCCIOS0_OCSET
7
CPUVCCIOS0_PGOOD
9
CPUVCCIOS0_RTN
2
CPUVCCIOS0_FSEL
5
11 UGATE
SREF
PHASE 10 LGATE 15
VO
CPUVCCIOS0_DRVH
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
PHASE
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.2 mm
1
C7605 47PF
5% 50V 2 CERM 402
1
0.001
L7630
1%
0.68UH-18A-3.3MOHM 1 2 PPCPUVCCIO_S0_REG_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V
PCMB103T
SWITCH_NODE=TRUE DIDT=TRUE
CPUVCCIOS0_DRVL
PGOOD
GATE_NODE=TRUE DIDT=TRUE
6
2 3 4 5
FSEL
=PPCPUVCCIO_S0_REG 2
3
4
2.2
1000PF 5% 25V
CPUVCCSAS0_SNUB
1
5% 1/10W MF-LF 603
7
Vout = 1.05V
C7623 1
20.1A Max Output f = 300 kHz
NP0-C0G 2
DIDT=TRUE MIN_LINE_WIDTH=0.6 MM
402
MIN_NECK_WIDTH=0.2 MM
NOSTUFF
NOSTUFF 1
6 1
1
0
1W MF-1 0612
1
R7631
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
RTN
R7603
7
R7640
CRITICAL
FDMS3602S POWER56
1
GATE_NODE=TRUE DIDT=TRUE
CPUVCCIOS0_LL
OCSET
1
C7631
0.001UF
10% 2 50V X7R-CERM
5% 1/16W MF-LF 2 402
0402
C7603
0.047UF
10% 2 16V X7R-CERM
0402
XW7600 SM
CPUVCCIOS0_AGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V
B
BOOT 12
FB
GND PGND
2.74K
C7604 1
4
CRITICAL
Q7630
CRITICAL
6
CPUVCCIOS0_FB CPUVCCIOS0_SREF
R76051
2
ISL95870
1% 1/16W MF-LF 2 402
1
2
PLACE_NEAR=U7600.1:1mm
R76411
85 49
CPUVCCIOS0_CS_P
85 49
CPUVCCIOS0_CS_N
B
3.09K
1% 1/16W MF-LF 402 2
C7640 1000PF 2
1 5% 25V
NP0-C0G 402
(CPUVCCIOS0_OCSET)
1
R7642 3.09K
2
1% 1/16W MF-LF 402
(CPUVCCIOS0_VO)
OCP = R7641 x 8.5uA / R7640 OCP = 26.265A Vout = 0.5V * (1 + Ra / Rb)
A
SYNC_MASTER=JACK_J30
SYNC_DATE=09/28/2011
PAGE TITLE
CPUVCCIO (1.05V) Power Supply DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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7
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5
4
CAESAR IV 1.2V INT.VR CMPTS L7700
Cougar Point requires JTAG pull-ups to be powered at 1.05V in SUS. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
4.7UH-0.91A 36 24 7
=PP3V3_ENET_PHY
1
1
C7717 4.7UF
20% 6.3V 2 CERM 603
1
C7718
ENET_SR_LX
2
PLE031B-SM PLACE_NEAR=U3900.16:1mm
36
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V SWITCH_NODE=TRUE
D
CRITICAL XDP_PCH
DIDT=TRUE
0.1UF
10% 16V 2 X7R-CERM
1
1.05V SUS LDO
CRITICAL
D
2
3
XW7700
0402
SM 1
ENET_SR_VFB
2
PLACE_NEAR=C7725.1:1mm PLACE_NEAR=U3900.14:1mm PLACE_NEAR=U3900.14:3mm
TPS720105 U7740
=PP3V3_SUS_P1V05SUSLDO
7
36
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V
SON
=PP1V2_ENET_PHY
36
6 IN
OUT 1
3 EN
NC 2
XDP_PCH
C7740 1
PP1V2_S3_ENET_INTREG
C7725
1
10UF
20% 2 6.3V X5R 603-2
1
C7726 0.1UF
=PP1V05_SUS_LDO 7
4 BIAS
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V
GND 5
1UF
6
Vout = 1.05V Max Current = 0.35A
NC
XDP_PCH
THRM
1
PAD 7
C7741 2.2UF
10% 6.3V 2 X5R 402
10%
6.3V 2 CERM 402
10% 16V 2 X7R-CERM
0402
PLACE_NEAR=L7700.1:1mm PLACE_NEAR=L7700.1:3mm
C 7
1
C7760
1
20% 22UF 6.3V 2 CERM-X5R 805
C7761
10% 0.1UF 16V 2 X5R 402-1
1
C7768
10% 1UF 10V 2 X5R 402
=P1V8S0_EN
IN
P1V8S0_SS 1
C7764
R7765
0.022UF
U7760
PLACE_NEAR=U7760.A3:1mm
PLACE_NEAR=C7768.1:3mm
73
3.24K
10% 1 2 P1V8_S0_COMP_RC 16V 2 X5R-X7R-CERM 1% 0402 1/16W MF-LF 402
MAX15053EWL
CRITICAL
WLP B2
SKIP CRITICAL
IN A3
B3
EN
LX A2
C2
SS/REFIN
C1
FB
P1V8S0_COMP B1
PGOOD
L7760
1.0UH-20%-11A-0.013OHM 1
P1V8S0_SW
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
C3
DIDT=TRUE
=PP1V8_S0_REG
2
COMP
P1V8S0_PGOOD OUT
GND 1 A
73
1
1
R7767
R7760 1 C7766 20.0K
1% NOSTUFF 1/16W MF-LF 2 402
100PF
1% 1/16W MF-LF 2402
5% 50V 2 CERM
1
1
C7765
C7767
20% 2 6.3V X5R-CERM-1 603
1
C7772 22UF
1
C7763 0.1UF
10% 20% 16V 2 6.3V X5R-CERM-12 X5R 402-1 603
1
R7761
100PF
1500PF
C7762 22UF
0402
P1V8_S0_RC
10K
5% 50V 2 CERM NOSTUFF
10% 25V 2 X7R 402
7
PIC0503H-SM
10K
P1V8SO_FB 1
C
Vout = 1.8V MAX CURRENT = 2A F = 1MHZ
1.8V S0 Switcher
=PP3V3_S0_P1V8S0
1% 1/16W MF-LF 2402
0402
B
B
1.05V S0 LDO
1.5V S0 Switcher
CRITICAL =PP1V5_S0_REG 7
Vout = 1.5V MAX CURRENT = 0.3A F = 1MHZ
=PP3V3_S0_P1V5S0 1
C7770
CRITICAL
1
1
10uF
=P1V5S0_EN
3
FB EN
GND
A
2
SOT23-5
SW 5
1
U7780
TPS720105 SON
C7773
P1V5S0_SW
=PP3V3_S0_P1V05S0LDO
4 BIAS
7
=PP1V8_S0_P1V05S0LDO
6 IN
=1V05_S0_LDO_EN
3 EN
73
20% 6.3V 2 X5R 603
C7782 1 C7780 1 1UF 10%
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE
6.3V 2 CERM 402
DIDT=TRUE
2
7
=PP1V05_S0_LDO
1UF
10%
NC 2 GND 5
6.3V 2 CERM 402
THRM PAD 7
7
Vout = 1.05V Max Current = 0.35A
OUT 1
10uF
TPS62201 4
IN
PCAA031B-SM
U7770
603
73
L7770 CRITICAL 10UH-0.55A-330MOHM
VI
20%
6.3V 2 X5R
7
NC 1
C7781 2.2UF
10% 6.3V 2 X5R 402
SYNC_MASTER=JACK_J30 PLACE_NEAR=U7780.4:1mm
SYNC_DATE=07/28/2011
PAGE TITLE
Misc Power Supplies
PLACE_NEAR=U7780.6:1mm
DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
R7803 NO 0
1
4
2
3
1
STUFF
3.3V S0 FET
2
5%
CRITICAL
Q7830
1/10W
SIA427DJ
MF-LF 603
SC70-6L
3.3V S4 FET
CRITICAL
Q7800
7
=PP3V3_S0_FET
7
=PP3V3_S0_P3V3S0FET
S
4
SIA427DJ
D
D
7
3.3V S0 FET 1
=PP3V3_S4_P3V3S4FET
R7832
7
S
4
D
=PP3V3_S4_FET
1
Q7812
7
R7802
D 3
220K
SSM3K15AMFVAPE
1 73
IN
G
10% 16V X5R 402
P3V3S4_EN_L
S 2
=P3V3S4_EN
2
1
G
0.033UF
5% 1/16W MF-LF 2 402
VESM
SOT563
C7809
3.3V S4 FET MOSFET
C7800
15.1K2 R7800
0.01UF
P3V3S4_GATE
1
5% 1/16W MF-LF 402
CHANNEL
2
IN
5
=P3V3S0_EN
G
G 3
2
C7830
91K
1
1
P3V3S0_SS
2
D
MOSFET
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON)
0.01UF
26 mOhm @1.8V
2
3.2 A (EDP)
LOADING
5% 1/16W MF-LF
10% 16V
402
X7R-CERM 0402
3.3V_SUS FET Q7820
26 mOhm @1.8V
CRITICAL
1.35 A (EDP)
LOADING
10% 16V X5R 402
R7830
S 4
P-TYPE 8V/5V
RDS(ON)
10% 16V X7R-CERM 0402
73
SiA427
1
0.033UF
5% 1/16W MF-LF 402
P3V3S0_EN_L
3
2
C7831
10K
D 3
SSM6N37FEAPE 1
Q7803
7
1
SC70-6L
SIA427DJ SC70-6L 7
=PP3V3_S5_P3V3SUSFET
7
S
4
R7822
C7821 1
1
Q7822
D 6
100K 5%
SSM6N37FEAPE
SOT563
3.3V S3 FET
2
CRITICAL
Q7810 2 G
SIA427DJ 73 72
SC70-6L 7
S
4
R7812
1
Q7812
2
G
R7820 12K 1
10% 16V X5R 402
47K
1
=PP3V3_S3_FET
G
2
3
C7820 0.01UF
1
2
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON) LOADING
10% 16V X7R-CERM 0402
7
=PP5V_S5_P5VSUSFET
26 mOhm @1.8V 100? mA (EDP)
LOADING
C
7
Q7822
R7842
D 3
IN
=P5V_3V3_SUS_EN
P5VSUS_EN_L
R7840 3.3K 1
2
D
=PP5V_SUS_FET
1
7
5V SUS FET
G
10% 16V X5R 2 402
5% 1/16W MF-LF 2 402
S 4
S
0.033UF
220K
3
MOSFET
C7840 0.01UF
P5VSUS_SS
1
5% 1/16W MF-LF 402
SiA427 P-TYPE 8V/5V
CHANNEL
2
16 mOhm @4.5V
RDS(ON)
10% 16V X7R-CERM 0402
1.5V S3/S0 FET
LOADING
100? mA (EDP)
CRITICAL
5.0V S0 FET
=PP1V5_S3_P1V5S3RS0_FET
=PP5V_S5_P1V5DDRFET
Q7860
DMP2018LFK DFN2563-6
C7801
=PP5V_S0_FET
1
0.1UF 20% 10V CERM 402
1
2
7
VCC
TDFN
ON
CRITICAL
SHDN*
NO STUFF 1
C7802 4.7UF 10%
D
5
G
7
R7862
S
6
PG
8
1
P1V5S0FET_GATE
0
5% 1/16W MF-LF 2402
Q7801 4
2
SI7108DN
G
PWRPK-1212-8-HF
P1V5S0FET_GATE_R 5% 1/16W MF-LF 402
P5V0S0_EN_L
S
1
2
3
C7861
220K
CRITICAL
D
R7801
GND
=PP1V5_S3RS0_FET
4
5.0V S0 FET
4
G
1
7
D
B
MOSFET
TPCP8102
CHANNEL
P-TYPE
RDS(ON)
18 MOHM @4.5V
LOADING
1.678 A (EDP)
0.033UF 3
10% 16V X5R
R7860 1
10K
2
2
C7860
402
0.01UF
P5V0S0_SS
1
2
5% 1/16W
7
MF-LF
6.3V X5R-CERM 2 603
S
1
1
SLG5AP020 2 3
2
=PP5V_S3_P5VS0FET
APN 376S0928
5
U7801
B P1V5CPU_EN
P-TYPE 8V/5V
CRITICAL
C7841 1
1
73 72
IN
SiA427
CHANNEL
Q7840
4
31 mOhm @1.8V 1.608 A (EDP)
5 G
26
MOSFET RDS(ON)
SC70-6L
SOT563
7
2
10% 16V X7R-CERM 0402
5V_SUS FET
MOSFET
SSM6N37FEAPE
7
1
SIA413DJ 0.01UF
P3V3S3_SS
7
7
3.3V S3 FET C7810
5% 1/16W MF-LF 402
=P3V3S3_EN
1
=PP3V3_SUS_FET
1
3.3V SUS FET
P3V3SUS_SS
3
2
R7810
P3V3S3_EN_L
S 1
D
2
5% 1/16W MF-LF 402
1
0.033UF
5% 1/16W MF-LF 2402
SOT563
IN
C7811
100K
D 6
SSM6N37FEAPE
73
=P5V_3V3_SUS_EN
1/16W MF-LF 402
7
=PP3V3_S3_P3V3S3FET
C
IN
10% 16V 2 X5R 402
P3V3SUS_EN_L
S 1
D
G
0.033UF
THRM
Q7802
PAD
9
402
10% 16V X7R-CERM 0402
D 3
SSM3K15AMFVAPE
1.5V S3/S0 FET P1V5S3RS0_RAMP_DONE OUT
MOSFET
SI7108DN
CHANNEL
N-TYPE
RDS(ON)
6 mOhm @4.5V
LOADING
5 A (EDP)
VESM
1
8 73
IN
=P5VS0_EN
G
S 2
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
Power FETs DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
78 OF 109 SHEET
72 OF 86
1
A
8
7
6
5
4
3
2
73 7
73 7
C7940 1 0.1uF 20%
10V CERM 2 402
CRITICAL
R7941
VDD
343S0497
1
SLG4AP012
SMC_PM_G2_EN
IN
MAKE_BASE=TRUE
73 7
=PP3V3_S5_PWRCTL Threshold: ?? DLY > 10 ms S5PGOOD_DLY 1
2
IN_A
OUT_A*
(IPD)
(OD,IPU)
6
IN_B
(OD,IPU)
OUT_A
4 3
2:1 +
5% 2 25V C0G-CERM 0402
OUT_B
DLY
0.033UF
66
10% 16V 2 X5R 402
Run (S0)
1 1
1
1
1
1
1
0
1
1
0
0
1
0
0
0
0
0
0
Deep Sleep (S4)
Deep Sleep (S5)
0
Battery Off (G3Hot)
S5_PWRGD
8
(OD,IPU)
5
1
PM_SLP_S4_L
IN
MAKE_BASE=TRUE
2
1
C7970 10% 10V X5R-CERM 0201
S5_PWRGD (old name RSMRST_PWRGD)-->SMC SMC-->PM_DSW_PWRGD
5.1K
5% 1/16W MF-LF 402 1 PLACE_NEAR=Q7812.2:6mm 1 G
5% 1/16W MF-LF 402
PLACE_NEAR=U7300.16:6mm
U7970
6 45 17
PM_SLP_S5_L
IN
P3V3_S4_EN
3
S
2
74LVC1G32
2
MAKE_BASE=TRUE
SOT891
SSM3K15AMFVAPE VESM
P3V3S3_EN
=P3V3S3_EN
72
OUT
=TBTAPWRSW_EN
4
2
1
76
OUT
IN
2
S0 ENABLE
3
SMC_S4_WAKESRC_EN
73 45 26 17 8 6
IN
(PM_SLP_S3_R_L)
2
R7981 20K
2
33K
5% 1/16W MF-LF 402
PLACE_NEAR=U7400.7:5mm
R7987
2
5% 1/16W MF-LF 402
1
67
OUT
42
0.47UF
10% 6.3V CERM-X5R 402
2
10% 6.3V CERM-X5R 402
PLACE_NEAR=Q7812.2:6mm
MAKE_BASE=TRUE
2
OUT
=USB_PWR_EN
PM_SLP_S3_R_L
5% 1/16W MF-LF 402
R7919
68
100
1
PM_SLP_S3_L
5% 1/16W MF-LF 402
1
2
2
R7988
R7986 5.1K
39K
5% 1/16W
5% 1/16W MF-LF 402
1
1 MF-LF 402
PLACE_NEAR=U7600.3:6mm PLACE_NEAR=U7770.3:6mm
=P5VS0_EN
OUT
72
=P3V3S0_EN
OUT
72
=PBUSVSENS_EN
OUT
50
PLACE_NEAR=U7760.B3:6mm
PLACE_NEAR=U1800.G18:5mm
PLACE_NEAR=U7100.15:6mm
P1V8S0_EN
=P1V8S0_EN
OUT
71
=P1V5S0_EN
OUT
71
MAKE_BASE=TRUE 7 73
=PP3V42_G3H_PWRCTL
3.3V/5.0V Sus ENABLE
P1V5S0_EN
2
R7931 5% 1/16W MF-LF 402
PLACE_NEAR=U7940.1:2.3mm
C7943
S0 Rail PGOOD (BJT Version) 7
46 45
1% 1/16W MF-LF 402
1
R7951 15.0K
1K
1
2
R7952 7.15K
1K
1
B
1
IN
Q2
NC
MAKE_BASE=TRUE
1K
=PP1V05_S0_VMON 1
ASMCC0179
0
S0PGD_BJT_GND_R
Worst-Case
ENET Enable Generation
=PP3V3_S5_PWRCTL
A
100
20% 10V CERM 2 402
CRITICAL 6
5%
1/16W MF-LF 402
1
0.1uF
U7930 Sense input threhold is 3.07V
R7957
5 SENSE
=PP3V3_SUS_PWRCTL
U7930 RESET*
=PP3V3_S0_PWRCTL 1
R7967
IN
R7968
IN
P1V8S0_PGOOD
2
2
2 7
P5V3V3_PGOOD
IN
CPUVCCIOS0_PGOOD
65
IN
PVCCSA_PGOOD
VDD
15.0K
ISL88042IRTEZ
TDFN (IPU) 3 V2MON CRITICAL MR* 1 5
V3MON
6
V4MON
RST*
100
1
NC
8
PM_RSMRST_L
OUT
PM_ENET_EN_L
PM_RSMRST_L goes to U1800.C21
2
Q7925
WOL_EN
5
1
330
2
G
Q7921
D
3
S
2
2
2
1
10% 16V X7R-CERM 0402
PM_WLAN_EN_L 6
VESM
G
PM_SLP_S3_L
OUT
2N7002DW-X-G
G
SOT-363 2
AP_PWR_EN
IN
5% 1/16W MF-LF 402
(AC_EN_L)
AC_EN_L
Q7920
NO STUFF 1
R7929
D
0
IN
SMC_ADAPTER_EN
2
G
S
1 OUT
SYNC_DATE=02/15/2011
PAGE TITLE
6
SOT-363
ALL_SYS_PWRGD
SYNC_MASTER=K90I_MLB
2N7002DW-X-G
5% 1/16W MF-LF 402
23 24 45 73
5% 1/16W MF-LF 402
D
2N7002DW-X-G
DRAWING NUMBER
SOT-363 5
2
Power Control 1/ENABLE
3
Q7920
(PM_SLP_S3_L)
G
Apple Inc.
S
051-9058
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
79 OF 109
II NOT TO REPRODUCE OR COPY IT
5
4
3
2
D
6.0.0 BRANCH
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
6
SIZE
REVISION
R
4
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
7
18 23 32
1
2
SHEET
73 OF 86
IV ALL RIGHTS RESERVED
8
32
Q7925
D 1
IN
C7922 0.01UF
P3V3ENET_SS
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
S
SSM3K15AMFVAPE
73 45 26 17 8 6
1
402
WLAN Enable Generation
SOT-363
IN
S
100
7
10%
100K 2 1
D
2N7002DW-X-G 19
2
R7964 1
=PP3V3_ENET_FET
3
3
R7966 100
D
G
0.033UF
R7922 5% 1/16W MF-LF 402
4
1
S
C7921
2 16V X5R
5% 10K 1/16W MF-LF 4022
17
NC
46 45 17
4
9353S2310
SOT23-6 MR* 3 (90K IPU) GND
1
R79211
2
1
S0PGOOD_ISL
R7962
2
2
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
GND THRM_PAD
1% 1/16W MF-LF 402
NO STUFF
ALL_SYS_PWRGD_R
S0PGOOD_ISL
=PP3V3_S3_P3V3ENETFET
7
100K
5% 1/16W MF-LF 402
2
R7963
U7960
6.04K
P1V5_DIV_VMON
1/16W MF-LF 402
1
IN
70
5% 1/16W MF-LF 402
20% 10V CERM 2 402
1% 1/16W MF-LF 402 2
100
66
0.1uF
15.0K S0PGOOD_ISL R7961 R79711S0PGOOD_ISL P1V05_DIV_VMON 1% 10K R79731 1/16W MF-LF 1% 402
5% 1/16W MF-LF 402
C7931
20% 50V 2 CERM 402
2
R7965
C7960 1
P5V_DIV_VMON
S0PGOOD_ISL 1
100
1
CPUIMVP_AXG_PGOOD
P1V5S0_PGOOD from U7710 71
B
SOT-23-HF
1
R7933
0.001UF
10K
5% 1/16W MF-LF 402 2
NO STUFF
Version in development) 68
NTR4101P
VDD 2 73 7
=PP1V05_S0_VMON
1/16W MF-LF 402 2
2
3.3V ENET FET
=PP3V3_SUS_PWRCTL
C7930
No stuff C7931, 12ms Min delay time
Thresholds:
S0PGOOD_ISL
=PP1V5_S0_VMON
10% 6.3V CERM-X5R 402
Q7922
=PP3V3_S0_VMON
R7970S0PGOOD_ISL 10K R79721 1%
0.47UF
PLACE_NEAR=U7930.6:2.3mm
=PP5V_S0_VMON 73 7
C7986
2
CRITICAL 73 7
S0 Rail PGOOD Circuitry
1% 1/16W MF-LF 402
PLACE_NEAR=U7760.B3:6mm
1
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")
3.3V SUS Detect
353S2809
3
1
6.04K
2
10% 6.3V CERM-X5R 402
72
2
5% 1/16W MF-LF 402
7
R7960
2
C7988 0.47UF
10% 6.3V CERM-X5R 402
VFRQ Low: Fix Frequency
TPS3808G33DBVRG4
S0PGOOD_ISL 73 7 1 S0PGOOD_ISL 1
PLACE_NEAR=U7770.3:6mm
1
0.47UF
VFRQ High: Variable Frequency
S4_PGOOD_CT 4 CT
7
C7981
Q4
Q2: 0.XXXV Q3: 0.640V 3.3V w/Divider: 2.345V Q4: 0.660V
73 7
1
10% 6.3V CERM-X5R 402
2
R7917
1
Thresholds: (ISL VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V
C
NO STUFF
DFN2015H4-8
1
VMON_Q4_BASE
2
5% 1/16W MF-LF 402
OUT
65
CHGR VFRQ Generation
R7955 73 7
=P5V_3V3_SUS_EN
PM_SUS_EN
S
2
CRITICAL
2
50
C7987 0.47UF
G
70
OUT
C
Q3
1
B
PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm
1
GND
Q1
7
4
6
PM_SLP_SUS_L
4
8
NC
VMON_Q3_BASE
2
5% 1/16W MF-LF 402
PP1V5_S0
3
71
=PVCCSA_EN
64
3
VESM
A
Q7950
R7954 =PP1V5_S0_VMON
SMC_BATLOW_L
D
=1V05_S0_LDO_ENOUT =CPUVCCIOS0_EN OUT
MAKE_BASE=TRUE
SSM3K15AMFVAPE
Y 17
6
5
1% 1/16W MF-LF 2 402
Q7931
U7940
74AUP1G3208 SOT891 1
23 24 45 73
S0PGD_C
5% 1/16W MF-LF 402
1
73 7
ALL_SYS_PWRGD
VMON_Q2_BASE
2
PVCCSA_EN
2
R7953 VMON_3V3_DIV
IN
MAKE_BASE=TRUE
CHGR_VFRQOUT
VCC
402
SMC_BATLOW_L:100K pull up on SMC page
150K
CPUVCCIOS0_EN
5
20% 10V CERM 2
R79561
1% 1/16W MF-LF 2 402
1
1
0.1uF
=PP3V3_S5_VMON
=PP3V3_S0_VMON
MAKE_BASE=TRUE
10K
=PP3V3_S5_PWRCTL
73 7
73 7
72
OUT
=DDRREG_EN
C7912
PLACE_NEAR=U7300.16:6mm
R7978
0
C7910
1
0.47UF
1
1
C
D
Q7911
DDRREG_EN MAKE_BASE=TRUE
=P3V3S4_EN
NO STUFF
OUT
D
MAKE_BASE=TRUE
1
CPUVCORE ENABLE CPUIMVP_VR_ON
53
PLACE_NEAR=U5701.3:6mm
PLACE_NEAR=U7970.6:3mm
0.1UF
2
5% 1/16W MF-LF 402
OUT
10% 10V X5R-CERM 0402
TPAD_VBUS_EN
9.1K
=PP3V3_S5_PWRCTL
73 7
46 45
ALL_SYS_PWRGD
2
45
OUT
5
0
66
0.068UF
2
R7912
R7911
NC
R7974
3.3K
OUT
STUFF 1 NO C7913
5% 1/16W MF-LF 402
1
MAKE_BASE=TRUE
9
=P5VS3_EN_L
66
NC
73 45 24 23
45 32 26 17 6
2
P3V3S5_EN_L_R NO STUFF MAKE_BASE=TRUE P5V3V3_REG_EN MAKE_BASE=TRUE =P5V3V3_REG_EN OUT
THRM PAD
GND
220PF
=P3V3S5_EN_L OUT
P5VS3_EN_L MAKE_BASE=TRUE
R7914
PM_SLP_S3_L
3.3V S4 ENABLE
DLY_1C
C7941
C7942
-
1.3V
7
MAKE_BASE=TRUE
1
PM_SLP_S4_L
PM_SLP_S5_L
SMC_PM_G2_ENABLE
Slee p (S3)
P3V3S5_EN_L
2
5% 1/16W MF-LF 402
TDFN
45 6
100
2
5% 1/16W MF-LF 402
1
U7941
68K
1 =PP3V42_G3H_PWRCTL
=PP3V42_G3H_PWRCTL Internal pull-ups 100K +/- 20% State
D
1
R7913 3.3V,5V S3 ENABLE
S5 Rail Enables & PGOOD
1
A
8
7
6
5
4
2
3
1
D
D
LCD CONNECTOR LVDS 8
CONNECTOR:518S0787
LCD_IG_PWR_EN
CRITICAL
J9000
20525-130E-01 F-RT-SM
CRITICAL
C9015
U9000
0.001UF
FPF1009 1 ON 7
=PP3V3_S5_LCD
1
C9009
2
10% 16V X7R-CERM 0402
C
FERR-120-OHM-1.5A
VOUT_1 4
PP3V3_LCDVDD_SW
3 VIN_2
VOUT_2 5
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM
GND THRM PAD 6 7
0.1UF
L9004
MFET-2X2-8IN
2 VIN_1
1
C9011
1
2
10% 16V X7R-CERM
0402
10% 50V X7R-CERM 0402
31 2
1 2
6
L9008
MIN_NECK_WIDTH=0.20 MM
CRITICAL
VOLTAGE=3.3V
1
C9012
2 0402-LF
6
7
4
PP3V3_S0_LCD_F
VOLTAGE=3.3V MIN_LINE_WI DTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
=PP3V3_S0_LCD
5 6 7
6.3V
X5R 603
MIN_LINE_WID TH=0.30 MM
NC
20%
2
3
PP3V3_LCDVDD_SW_F
120-OHM-0.3A-EMI
10UF
0.1UF
1
0.001UF 2
2 0402-LF
MIN_NECK_WIDTH=0.20 MM 1
C9010
1
10% 50V X7R-CERM 0402
(LVDS DDC POWER)
80 17 6
LVDS_IG_A_DATA_N<0>
80 17 6
LVDS_IG_A_DATA_P<0>
C
8 9 10
1 1
R9008
R9009 10K
10K
8 6
LVDS_DDC_CLK
8 6
LVDS_DDC_DATA
1/16W MF-LF 402
LVDS_IG_A_DATA_N<1>
11 12
80 17 6
LVDS_IG_A_DATA_P<1>
80 17 6
LVDS_IG_A_DATA_N<2>
14
80 17 6
LVDS_IG_A_DATA_P<2>
15
5% 1/16W
5%
2
80 17 6
2
13
MF-LF 402
16
CRITICAL
L9080
90-OHM-100MA DLP11S SYM_VER-1
85 6
LVDS_CONN_A_CLK_F_N
85 6
LVDS_CONN_A_CLK_F_P
17
LVDS I/F
18 19
80 17
LVDS_IG_A_CLK_N
4
3
77 6
PPVOUT_SW_LCDBKLT
C9020 80 17
LVDS_IG_A_CLK_P
1
20
NC
1
21
0.001UF
2
10% 50V X7R-CERM 0402
22 2
23
NC
24
LED BKLT I/F
25 26 27 28
77 6
LED_RETURN_1
77 6
LED_RETURN_2
77 6
LED_RETURN_3
77 6
LED_RETURN_4
77 6
LED_RETURN_5
33
77 6
LED_RETURN_6
34
29 30
NC
B
B
35 36 37 38 39 40 41
32
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
LVDS CONNECTOR DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
90 OF 109 SHEET
74 OF 86
1
A
8
7
81 8
IN
DP_EXTA_ML_C_P<0>
C9300
81 8
IN
DP_EXTA_ML_C_N<0>
C9301
1
0.1UF
81 8
IN
DP_EXTA_ML_C_P<1>
C9302
81 8
IN
DP_EXTA_ML_C_N<1>
C9303
DP_EXTA_ML_C_P<2>
C9304
81 8
IN
DP_EXTA_ML_C_N<2>
C9305
D
IN
DP_EXTA_ML_C_P<3>
C9306
IN
DP_EXTA_ML_C_N<3>
C9307
10% 16V X5R-CERM 0201
10% 16V X5R-CERM 0201
2
10% 16V X5R-CERM 0201
10% 16V X5R-CERM 0201
75 81
DP_EXTA_ML_N<0>
75 81
2
1
2
1
0.1UF
BI
DP_EXTA_AUXCH_C_P
C9308
BI
DP_EXTA_AUXCH_C_N
C9309
OUT
75 81
DP_EXTA_ML_N<1>
75 81
DP_EXTA_ML_P<2>
75 81
DP_EXTA_ML_N<2>
75 81
2
DP_EXTA_ML_P<3>
75 81
DP_EXTA_ML_N<3>
75 81
R9309
2
1
2
1
=PP3V3_S0_DPSDRVA
2
5% MF
83 33
IN
83 33
IN
C9372
T29_R2D_C_N<0> T29_R2D_C_P<0>
75 81
DP_EXTA_AUXCH_N
75 81
R9308
1
5% MF
83 33
OUT
83 33
OUT
1
20% 6.3V CERM 402-LF
PS8301 I2C Addresses:
81 75 81 75
81 75
Note: Other Parade devices use 96/B6, so only 94/B4 are used for this part.
81 75
81 75 81 75
81 75
NO STUFF
81 75
1
R9310 8 8
IN BI 81 75 81 75
1
R9312
8
1K
OUT
5% 1/16W MF-LF 402
48
IN
48
BI
23 16
IN
B 2 SDRV_PD
1
R9318 0 5% 1/20W MF 201
R9319 4.22K
1% 1/16W MF-LF 2 402
1
10% 16V 2 X5R-CERM 0201
2
1
0.1UF
DP_EXTA_ML_P<0> DP_EXTA_ML_N<0> DP_EXTA_ML_P<1> DP_EXTA_ML_N<1>
83 33
IN
83 33
IN
C9382
T29_R2D_C_N<1> T29_R2D_C_P<1>
DP_EXTA_ML_P<2> DP_EXTA_ML_N<2> DP_EXTA_ML_P<3> DP_EXTA_ML_N<3>
1
2 5% MF
30
1
1/20W 201
R9350 30
1
2
R9351 30
1
2
5% MF
1/20W 201
5% MF
1/20W 201
5% MF
1/20W 201
30
83
2
IN_D0N
OUT_D0N
29
83
IN_D1P IN_D1N
OUT_D1P OUT_D1N
4
28
83
IN_D2N
OUT_D2N
24
83
9 IN_D3P 10 IN_D3N
OUT_D3P
23
83
OUT_D3N
22
83
IN_D2P
DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N
16 IN_AUXP 15 IN_AUXN 3
IN_HPD
12 REXT
OUT_AUXN_SDA
17
(IPD) OUT_HPD
31
CA_DET
CEXT
R9373
C9365
DP_A_PWRDWN_R
DP_A_CA_DET
C9360
76
IN
76
OUT
33
OUT
33
OUT
=I2C_T29AMCU_SCL =I2C_T29AMCU_SDA T29DPA_HPD T29_A_BIAS_R T29_LSOE<0> T29_LSOE<1>
18
OUT
TBT_PWR_REQ_L
48 48
IN BI
=TBT_WAKE_L
1
0.22UF
C9361
1
0.22UF 1
R9353
T29 Path Biasing
1
DP_SDRVA_ML_C_P<2> DP_SDRVA_ML_C_N<2>
C9367
10% 16V X5R-CERM 0201
1
0.1UF
20% 6.3V CERM 402-LF
GND 6 3 3
20% X5R
83
D9361
1
6.3V 0201
8 9 10
HVQFN25
DP_SDRVA_ML_P<2> DP_SDRVA_ML_N<2>
R/PIO1_1/AD2
PIO0_4/SCL(OD) PIO0_5/SDA(OD)
R9365 R9364
PIO1_6/RXD
PIO0_7/CTS# PIO0_8/MISO/CT16B0_MAT0
PIO1_7/TXD PIO1_8/CT16B1_CAP0
1
3
5% 1/16W MF-LF 402
VSS 1 2
1
17 18
24 6
83 83
83
1
R9393 51
5% 1/20W MF 2 201
C9331
4
1
31
DIN1_0+
30
DIN1_0-
DP_SDRVA_ML_N<1> DP_SDRVA_ML_P<1>
27 26
DIN1_1-
DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N
19
AUX1+
18
AUX1-
DP_SDRVA_HPD
17
HPD_1
1K
5% 1/16W MF-LF 2 402
1
5
2 2
5% MF
1/20W 201
5% MF
1/20W 201
DP_A_BIAS0
8
VOLTAGE=3.3V
5% MF
1/20W 201
5% MF
1/20W 201
R93631
5% 1/20W MF 2 01
5% 1/20W MF 201 2
DP_A_BIAS2
8
1
R9362
VOLTAGE=3.3V
R9336
C
51
5% 1/20W MF
51
2 201
C9358 0.1UF
5% 1/20W MF 201
DIN2_0-
(T29_A_LSX_P2R) (T29_A_LSX_R2P)
DIN2_1+
22
DIN2_1-
T29_D2R1_BIASP T29_D2R1_BIASN
15 14
AUX2+
13
HPD_2
DP_A_PWRDWN T29_A_BIAS
R9334
76
1
10K
10
TBT_A_HV_EN
2
OUT
35 76
5% 1/16W MF-LF 402
2
P2R = Plug to Receptacle R2P = Receptacle to Plug
2
20% 10V
R9339
2
CBTL04DP081 HVQFN
1
20% 10V
CERM
402
T29DPA_ML_N<3> T29DPA_ML_P<3> T29: Unused
DOUT_0+ DOUT_0- 2
OUT
76 83 76 83
BI
T29DPA_ML_N<1> 76 83 BI T29DPA_ML_P<1> OUT 76 83 T29: LSX_A_R2P/P2R (P/N)
AUX+ 6
DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N
AUX- 7
BI
76 83
BI
76 83
B
T29: RX_1 Bias Sink DP_A_EXT_HPD
HPD_IN 8
IN
46 75
1
R9398 100K
GPU_SEL AUX_SEL
11
NC
5% 1/20W MF 2201
LO=Port A HI=Port B
THMPAD GND 3 3
8 1 2 2
SIGNAL_MODEL=T29DP_MUX
U9390 ML/HPD defaults to T29 mode so that DP/T29 Display can detect host T29 support using I2C pull-ups on ML<3>. U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s detection of DP Source. SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
DRAWING NUMBER
5% 1/16W MF-LF 402
Apple Inc. R
5% 1/16W MF-LF 2 402
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
4
0.1UF
5% 1/20W MF 2201
U9390
1M
0x26/0x27 (Wr/Rd)
C9391
DisplayPort/T29 A MUXing
33
10K
1
2
CERM
402
100K
VDD
AUX2-
32
Note:
R9399
DOUT_1- 5 DIN2_0+
CBTL04DP081 (353S3151) and PI3vEDP212 (353S3055) are footprint-compatible parts with similar pinouts. NXP uses pin 10 for ML and HPD, Pericom uses pin 10 for ML and pin 11 for HPD.
5% 1/16W MF-LF 402 2
76
75 76 8
1
DOUT_1+ 4
23
C9390 0.1UF
3
CRITICAL
24
NC
1K
2 SWDIO T29_A_UC_ADDR 75 R9330 provides pads for programming/debug of MCU, please make accessible. If project has space for 10-pin programming header it should be used.
6
DIN1_1+
25
1
10K
20% 10V 2 CERM 402
R9335
PAD
5 2
76 83
PP3V3_SW_TBTAPWR
DP_SDRVA_ML_N<3> DP_SDRVA_ML_P<3>
R9397
R93381
0.1UF
IN
76 83
OUT
10% 16V X7R-CERM 0402
83
10% 16V X5R-CERM 0201
T29_A_LSX_P2R T29_A_LSX_R2P T29_LSEO<1>
23
OUT
DP_A_BIAS
83
T29DPA_CONFIG1_RC IN T29DPA_CONFIG2_RC IN TBT_A_HV_EN_R T29_A_UC_ADDR 75 DP_A_EXT_HPD 46 75
16
76 83
Both R’s must connect to C in star topology.
1
I2C Addr: XTALIN
2 2
76 83
IN
DP/T29 A Low-Speed MUX
1
THRM
1 1
IN
1 4 SC70
2
SWCLK/PIO0_10/SCK/CT16B0_MAT2(OD)
15 R/PIO0_11/AD0 (OD)
1.5K 1.5K
9 0 6 2
1
20% 10V 2 CERM 402
1/20W 201
GND_VOID=TRUE
R9384 1.5K 1 GND_VOID=TRUE R9385 1.5K 1
74LVC1G04DBDCK
1K
0.1UF
1/20W 201
5% MF
GND_VOID=TRUE (D9361.2)
TSLP-2-7
U9359
5
10% 16V X5R-CERM 0201
PIO0_9/MOSI/CT16B0_MAT1
SWCLK
K
CRITICAL
5% 1/20W MF 201
PIO1_4/AD5/WAKEUP
PIO0_6/SCK
12 14
R/PIO1_2/AD3
A
DP Path Biasing R9361 1.5K 1 2 5% 1/20W MF 2 01 R9360 1.5K 1 2
1
DP_A_PWRDWN
port power
C9330
D 5% MF
GND_VOID=TRUE (D9382/D9383)
(D9360/D9361) 83 83
R9396
(IPU) SWDIO/PIO1_3/AD4 19 20
11 13
R/PIO1_0/AD1
PIO0_2/SSEL/CT16B0_CAP0
TSLP-2-7
(D9382/D9383)
T29_A_RSVD_N T29_A_RSVD_P
1
PIO0_1/CLKOUT
TSLP-2-7 K
CKPLUS_WAIVE=NdifPr_badTerm
OMIT_TABLE
2
T29: TX_1 T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>
K
SIGNAL_MODEL=T29PIN
20% 6.3V X5R 0201
83
2 2
2
1
GND_VOID=TRUE (D9360.2)
SIGNAL_MODEL=EMPTY
2
2
1
GND_VOID=TRUE
TSLP-2-7
2 2 1 1 9 OMIT_TABLE
51
RESET#/PIO0_0
K
BAR90-02LRH
2 2
7
A
76 75
5% 1/20W MF 201 2
VDD
D9383
BAR90-02LRH
5% 1/20W MF 201
DP_SDRVA_ML_P<0> DP_SDRVA_ML_N<0>
2
Must be 3.3V DP A
D9382
A
6.3V 0201
20% X5R
76 83
Must be 3.3V DP A port power
1 4
PP3V3_SW_TBTAPWR
A
BAR90-02LRH
2
R9383
83
2
76 83
OUT
GND_VOID=TRUE
R9374 1.5K R9375 1.5K
10% 16V X5R-CERM 0201
THMPAD
0
7
1
D9360
BAR90-02LRH
201
GND_VOID=TRUE
2
0.1UF
C9368
75
MF
2
C9369
IN
83
IC supports input high while Vcc = 0V.
2
1
(DP_SDRVA_HPD) DP_A_CA_DET
CRITICAL (All 4 D’s)
CRITICAL (All 4 D’s) 6.3V 0201
OUT
GND_VOID=TRUE (D9365.2)
TSLP-2-7
D9372/D9373: SIGNAL_MODEL=T29PIN
T29_R2D_P<1> T29_R2D_N<1>
83
1.5K
2
20% X5R
76 83
GND_VOID=TRUE (D9372/D9373)
3
10% 16V X5R-CERM 0201
AUXCH Snoop Port, used by PS8301 during training.
DPSDRVA_CEXT
20% 4V CERM-X5R-1 201 2
2
1
0.1UF
75
10% 16V X5R-CERM 0201
(DP_SDRVA_AUXCH_P) (DP_SDRVA_AUXCH_N)
11
TSLP-2-7
2
0.1UF
C9366
DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N
32
2
76 83
IN
T29_D2R_C_P<1> T29_D2R_C_N<1>
R9382 1.5K 1 2
2
1
0.1UF
DP_SDRVA_ML_C_P<3> DP_SDRVA_ML_C_N<3>
TSLP-2-7 K
K
BAR90-02LRH
GND_VOID=TRUE 5% 1/20W
10% 16V X7R-CERM 2 0402
0.1UF
C9362
A
A
D9364/D9365: SIGNAL_MODEL=EMPTY
0.1UF
DP_SDRVA_ML_C_P<1> DP_SDRVA_ML_C_N<1>
D9373
D9365
T29: TX_0 T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>
K
20% 4V CERM-X5R-1 201
C9359
DP_SDRVA_ML_C_P<0> DP_SDRVA_ML_C_N<0>
A
IN
GND_VOID=TRUE (D9364.2)
TSLP-2-7
BAR90-02LRH
5% 1/20W MF 201
=PP3V3_S0_DPSDRVA
75 7
270
5% 1/20W MF 2 201
R93921
2
T29_LSEO<0>
1
K
BAR90-02LRH
2
2.2UF
39 AUXDDC_OFF (IPD)
IN
1
0.22UF
DP_SDRVA_ML_R_P<2> DP_SDRVA_ML_R_N<2>
LPC1112A
8
1
C9319 1
34 PD (IPD)
75
OMIT
D9372
GND_VOID=TRUE
PLACE_NEAR=U9310.11:2 mm
DP_AUXCH_ISOL
PS8301 has internal ~150K pull-down on PD pin. Okay to drive this pin even when VCC=0V per Parade (pin is 5V-tolerant).
83
18
36 I2C_ADDR0 (IPD) 35 I2C_ADDR1 (IPD)
DPSDRVA_REXT
83
19
DPSDRVA_I2C_CTL_EN
38 SCL_CTL 37 SDA_CTL
20
AC_AUXN
DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR1
83
AC_AUXP
OUT_AUXP_SCL
26 I2C_CTL_EN (IPU)
=I2C_DPSDRVA_SCL =I2C_DPSDRVA_SDA
83 83
C9363 83
OUT_D2P
8
14 IN_SCL 13 IN_SDA
DP_EXTA_HPD
27 25
DP_A_PWRDWN
R93301
83
A
BAR90-02LRH
2
1
0.22UF
270
CRITICAL OUT_D0P
C9364
DP_SDRVA_ML_R_P<0> DP_SDRVA_ML_R_N<0>
5% 1/20W MF 201 2
IN_D0P
7
83 83
2
VDD
DP_EXTA_DDC_CLK DP_EXTA_DDC_DATA
33
OUT
83
1.5K
20% 4V CERM-X5R-1 GND_VOID=TRUE201
30
D9364
5% 1/20W MF 201
T29_R2D_P<0> T29_R2D_N<0>
20% 4V CERM-X5R-1 201 2 20% 4V CERM-X5R-1
20% 4V CERM-X5R-1 201
1
0.47UF
R9355
U9330
17
R9372 1 2
2
1
0.47UF
C9383
R93521
1
5
1
0.47UF
1 0 2 4
10% 16V 2 X5R-CERM 0201
5
Desktops use PCIe WAKE# Mobiles use S4 WAKE#
1
T29_A_BIAS_R2DP1 T29_A_BIAS_R2DN1
Port A MCU
=TBT_WAKE_L:
2
0.47UF
C9312
CRITICAL
A
IN
R9308/R9309 maintain bias on C9308/C9309 to prevent spikes when U9310 AUXDDC_OFF transitions from high to low.
1/20W 201
76 75
75
IN
8
C9380
QFN
5% 1/16W MF-LF 2 402
8
C9381
PS8301TQFN40GTR-A2
1K
1
GND_VOID=TRUE
U9310
Addr (W/R) 0x96/0x97 0xB6/0xB7 0x94/0x95 0xB4/0xB5
2
C9311 0.1UF
2.2UF
5% 1/16W MF-LF 402 2
1.5K
201 GND_VOID=TRUE
T29_D2R_N<1> T29_D2R_P<1>
DP A Super-Driver C9310 1
1K
T29_D2R_C_P<0> T29_D2R_C_N<0> GND_VOID=TRUE
20% 4V CERM-X5R-1 201
GND_VOID=TRUE
2
1M
=PP3V3_S0_DPSDRVA
R93111
2
20% 4V CERM-X5R-1 201 2
1
0.47UF
C9373
R9354
A0 0 1 0 1
1
0.47UF
C9371
1/20W 2 01
DP_EXTA_AUXCH_P
If GPU uses common pins for AUX_CH and DDC, alias nets together at GPU.
A1 0 0 1 1
C9370
(C9370/C9371)
T29_D2R_N<0> T29_D2R_P<0>
1
T29 A High-Speed Signals
T29_A_BIAS_R2DP0 T29_A_BIAS_R2DN0
7 75
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF
C
IN
T29 signals are P/N-swapped after AC caps to improve layout.
10% 16V X5R-CERM 0201
16V 10% X5R-CERM 0201
1
0.1UF
75 7
IN
GND_VOID=TRUE
DP_EXTA_ML_P<1>
1M
81 8
OUT
83 33
2
3 8
GND_VOID=TRUE 8
(C9380/C9381)
0.1UF
81 8
83 33
4
0.47UF
2
DP_EXTA_ML_P<0>
5
0.47UF
2
1
0.1UF
81 8
2
1
0.1UF
81 8
10% 16V X5R-CERM 0201
1
0.1UF IN
10% 16V X5R-CERM 0201
1
0.1UF
81 8
1
0.1UF
6
2
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
93 OF 109 SHEET
75 OF 86
1
A
8
7
6
5
4
2
3
1
3.3V/HV Power MUX V3P3 must be S4 to support wake from Thunderbolt devices.
=PP3V3_S4_TBTAPWRSW
7
CRITICAL
C9480 1
D
1
6.3V X5R-CERM-1 2 603
930mA (assumes 15V, 12W minimum) 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
V3P3
20
C9410
4.7UF
1
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V
14
C9485 0.1UF
CRITICAL
U9410
0.1UF
10% 50V 2 X7R 603-1
1
1
20% 10V 402
QFN
C9486 10UF
20% 6.3V 2 X5R 603
CERM 2
CD3210A0RGP 16 RSVD
1
TBTAPWRSW_ISET_V3P3
73
IN
=TBTAPWRSW_EN
IN
TBT_A_HV_EN
11 HV_EN
ISET_S0 10
TBTAPWRSW_ISET_S0
8
IN
=TBT_S0_EN
17 S0
ISET_S3 9
TBTAPWRSW_ISET_S3 TBTHV:P15V
5 EN
ISET_V3P3 8
GND
1 2 3 4 3 1
THRM
12V: See
R9414
1% 1/20W MF 2201
1
R9412 36.5K
1% 1/20W MF 2201
<RV3P3>
Single-fault protection requires two R’s per HV ISET_Sx with CD3210. Single R on ISET_V3P3 OK.
22.6K
1% 1/20W MF 2201
1% 1/20W MF 2012
<RHVS3>
DESCRIPTION
22.6K
1% 1/20W MF 2012
1
22.6K
For 12V systems:
R9411
22.6K
below
TBTAPWRSW_ISET_S3_R TBTAPWRSW_ISET_S0_R TBTHV:P15V
R94131
C
TBTHV:P15V 1
R94101
PAD
1 2
TBTHV:P15V
QTY
C9411 0.1UF
10% 50V 2 X7R 603-1
RSVD 15
75 35
PART NUMBER
75
PPHV_SW_TBTAPWR
12 OUT
VHV
7
10% 25V X5R-CERM 2 0603
D
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
V3P3OUT 18
6
C9415
Max 1200mA
830mA 830mA
PP3V3_SW_TBTAPWR
20V Max 1
Min 1030mA
890mA 890mA
19
=PPHV_SW_TBTAPWRSW
7
1100mA
IHVS0 IHVS3
20% 10V 2 CERM 402
20%
20%
6.3V 2
POLY-TANT
CASE-B2-SM
C9481 0.1UF
22UF
100UF
Nominal
IV3P3
CRITICAL
C9487 1
C
ILIM = 40000 / RISET
<RHVS0>
REFERENCE DES
CRITICAL
BOM OPTION
114S0338
2
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
R9410,R9413
TBTHV:P12V
114S0338
2
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
R9411,R9414
TBTHV:P12V
L9400
Nominal
IHVS0/S3
1120mA
Min
2
Max
1090mA
Thunderbolt Connector A
FERR-120-OHM-3A 1
C9400
PP3V3RHV_SW_DPAPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V
0603
1170mA (12W minimum)
1
C9405
0.01UF
IN
T29_A_BIAS_R 0.1UF 1
0.01UF
10% 50V X7R 2 402
C9490
75
For J9400 T29 SMT pads (3, 5, 17 & 19): GND_VOID=TRUE
2
T29 Dir 10% 16V
X7R-CERM 0402
83 75
OUT
83 75
OUT
T29_D2R_C_P<0> T29_D2R_C_N<0>
J9400
1
R9494
51
1K
5% 1/20W MF 2012
T29_A_BIAS
5% 1/20W MF 2012 OUT
SIGNAL_MODEL=EMPTY
8 75
83 75
8
IN
8
IN
83 75
T29_A_BIAS_D2RN1 T29_A_BIAS_D2RP1
GND_VOID=TRUE
5% 2.2K
1/20W MF 201 GND_VOID=TRUE 2
R9495 1K
5% 1/20W MF 2 201
2 4
SIGNAL_MODEL=EMPTY
6
T29DPA_ML_P<3> BI T29DPA_ML_N<3> BI T29: Unused
10 12 14 18
83 75
OUT
83 75
OUT
L9498
1
R9499
T29_D2R_C_P<1> T29_D2R_C_N<1>
D9498
A
BAR90-02LRH
D9499
A
K
TSLP-2-7
83 83
BI BI
1
T29DPA_CONFIG1_RC
75
OUT
T29DPA_CONFIG2_RC 1
R9452 1M
5% 1/16W MF-LF 4022
8
7
5% 1/16W MF-LF 2402
C9499 30PF
DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).
1
R9451 1M
1 C9494 330PF 10% 50V
X7R-CERM 2 0402
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP AUX_CHN DP_PWR
ML_LANE2P ML_LANE2N RETURN
1
C9495 330PF
10% 50V 2 X7R-CERM
0402
1
7
2
75 83
IN
75 83
10% 25V X5R-CERM 0201
T29DPA_ML_P<1> T29DPA_ML_N<1>
IN
75 83
T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>
IN
75 83
IN
75 83
R9471
R9470
470K
470K
5% 1/20W MF 2201
5% 1/20W MF 2 201
BI
B
75 83
17 19
(Both C’s)
C9472
C9473
GND_VOID=TRUE
470K
1
10% 10V X5R-CERM 2 0201
1
C9401
12
5% 1/20W MF 201
4V
CERM-X5R-1 2 20%
201 4V
CERM-X5R-1 201
GND_VOID=TRUE 1
R9473 470K
5% 1/20W MF 2201
5% 1/20W MF 2 201
2
2 20%
1
0.47UF
R9472
1
1
0.47UF
T29DPA_ML_P<2> T29DPA_ML_N<2>
1
R9401
470k R’s for ESD protection on AC-coupled signals.
0.01UF
10% 2 50V X7R 402
SYNC_MASTER=K90I_MLB 1
SYNC_DATE=02/15/2011
PAGE TITLE
R9441
Thunderbolt Connector A
100K 5% 1/16W MF-LF
DRAWING NUMBER
Apple Inc.
2 402
Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V
6
IN
T29: LSX_R2P/P2R (P/N)
83
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V
0.01UF
T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>
1
1
9 13 15
T29: TX_1
C9402
201
11
1
5% 50V 2 CERM 402
402
T29DPA_HPD
ML_LANE0N
5
4V
4V
CERM-X5R-1
GND_VOID=TRUE
GND_VOID=TRUE
0.01UF
GND_DPACONN_7_C MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
83
DPACONN_20_RC
5% 50V
OUT
CONFIG2
ML_LANE0P
3
2 20% 2 20%
CERM-X5R-1
1
0.47UF
201
C9406 1
L9499
CERM 2
OUT
CONFIG1
GND
T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N
2
30PF
75
C9471
22 21
GND_VOID=TRUE 0603 SIGNAL_MODEL=EMPTY
DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N
C9498 1
75
SM P IN S
HOT_PLUG_DETECT
650NH-5%-0.430MA-0.52OHM
(Both L’s)
83 75
T OP R OW
T H P IN S
CRITICAL
GND_VOID=TRUE SIGNAL_MODEL=T29PIN
83 75
B OT R OW
1
0.47UF
SHIELD PINS
0603 SIGNAL_MODEL=EMPTY
K
GND_VOID=TRUE
(Both C’s)
C9470
GND_VOID=TRUE
1 GND_VOID=TRUE
2
BAR90-02LRH TSLP-2-7 CRITICAL
A
20
650NH-5%-0.430MA-0.52OHM
5% 2.2K 1/20W MF 2201 GND_VOID=TRUE
83
2
T29DPA_ML_P<0> T29DPA_ML_N<0>
T29: TX_0
CRITICAL
R9498
83
1
16 1
1
10% 25V X5R-CERM 0201
T29 Dir
F-RT-THSM
8
B
DP Dir
DSPLYPRT-M97-1
GND_VOID=TRUE
R94911
VOLTAGE=3.3V
CRITICAL
DP Dir
GND_DPACONN_1_C
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
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PAGE
94 OF 109 SHEET
76 OF 86
1
A
8
7
6
5
4
2
3
1
PPBUS S0 LCDBkLT FET
CRITICAL
Q9706
MOSFET
FDC638APZ
CHANNEL
P-TYPE
RDS(ON)
43 mOhm @4.5V
LOADING
0.715 A (EDP)
FDC638APZ_SBMS001 SSOT6-HF
F9700
D
1
=PPBUS_S0_LCDBKLT
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
6
3AMP-32V-467 7
PPBUS_SW_LCDBKLT_PWR 5
2
603-HF
1
BOTTOM
R9788
PPBUS_SW_LCDBKLT_PWR
2
AND
1
C9782
10% 16V 2 X7R-CERM 0402
1% 1/16W MF-LF 402
*PPBUS_SW_LCDBKLT_PWR_ SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
ON THE SENSOR PAGE
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
7
3
PLACE_NEAR=L9701.2:3mm
=PP5V_S0_BKL
L9701 D9701 SOD-123
33UH-1.8A-110MOHM LCDBKLT_EN_DIV 8
=PPBUS_SW_BKL
1
C9712
R9789
2
CRITICAL 1
1
10% 25V X5R 805
1% 1/16W MF-LF 402
1217AS-2SM
C9713
2
2
A
PPBUS_SW_LCDBKLT_PWR_SW MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=40V
10% 25V X5R 402
K
1
C9796
1
220PF 2
PLACE_NEAR=L9701.1:3mm
PLACE_NEAR=L9701.1:4mm
PLACE_NEAR=U9701.A5:3mm
PPVOUT_SW_LCDBKLT CRITICAL
CRITICAL RB160M-60G
SWITCH_NODE=TRUE DIDT=TRUE
0.1UF
10UF
147K
2
CRITICAL
CRITICAL
2
1
D
*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS
PPBUS_SW_BKL
1
0.1UF
301K
8 77
THERE IS A SENSE RESISTOR BETWEEN
4
PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
C9797
1
2
C9799
6 74
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V
10UF
10UF
10% 50V X7R-CERM 0402
10% 50V X5R 1210-1
2
10% 50V X5R 1210-1
PLACE_NEAR=D9701.2:5mm
LCDBKLT_EN_L PLACE_NEAR=D9701.2:3mm
Q9707
D 3
SSM6N15AFE SOT563
PLACE_NEAR=U9701.D1:5mm
PLACE_NEAR=U9701.D1:3mm
C9710
1
1
2
2
1UF 5 8
IN
G
10% 25V X5R 603-1
S 4
LCD_BKLT_EN
LCDBKLT_DISABLE
Q9707
SM
0.01UF
PPVOUT_SW_LCDBKLT_FB
10% 16V X7R-CERM 0402
VOLTAGE=40V MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM
1
2
PLACE_NEAR=C9797.1:5mm
D 6 7
SSM6N15AFE
=PP3V3_S0_BKL_VDDIO
SOT563
C
XW9720
C9714
PLACE_NEAR=U9701.C4:4mm
C9711
C
1
0.1UF 2 24
IN
G
10% 16V X7R-CERM 0402
S 1
BKLT_PLT_RST_L
2
R9755 10K
1
4 C
48
Addr:
IN
=I2C_BKL_1_SCL
1
48
BI
=I2C_BKL_1_SDA
1
0
2
2
5% 1/16W MF-LF 402
1
PPBUS_SW_LCDBKLT_PWR
77 8
2
R9731 301K
B
1% 1/16W MF-LF 402
R9704 8
IN
LCD_BKLT_PWM
1
33
2
5% 1/16W MF-LF 402
1
25-BUMP-MICRO D2
VSYNC
BKL_FLTR
C2
FILTER
BKL_ISET
B3
ISET
BKL_FSET
B4
FSET
SW_0 SW_1 0 5 5 8 P L
FB
B1
BKLT:PROD
B2
R9717 PLACE_NEAR=U9701.E5:10mm
A5
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
D3
BKL_SDA
D4
SDA
BKL_PWM
A4
PWM
BKL_EN
A3
EN
C3
FAULT
TP_BKL_FAULT
2
R9715
SCLK
1% 1/16W MF-LF 402
S _ D N G 5 B
C9704
L _ D N G 4 E
OUT1
E5
BKL_ISEN1
OUT2
D5
BKL_ISEN2
OUT3
C5
BKL_ISEN3
OUT4
E3
BKL_ISEN4
OUT5
E2
BKL_ISEN5
OUT6
CRITICAL
PLACE_SIDE=BOTTOM
100K
1
BKL_SCL
E1
BKL_ISEN6
1
1
90.9K
Fpwm=9.62kHz see spec for others
1% 1/16W MF-LF 402
2
0
2
LED_RETURN_2 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
5% 1/16W MF-LF 402
6 74
OUT
6 74
OUT
6 74
OUT
6 74
OUT
6 74
OUT
6 74
B
R9719 PLACE_NEAR=U9701.C5:10mm
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
1 2 A A
0
2
LED_RETURN_3 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
5% 1/16W MF-LF 402
BKLT:PROD
R9714
R9720
16.2K
2
OUT
BKLT:PROD
W W S S _ _ D D N N G G
I_LED=22.7mA
R9716
LED_RETURN_1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
R9718 1
BOTTOM
BOTTOM
5% 50V C0G-CERM 0402
2
BKLT:PROD
PLACE_NEAR=U9701.D5:10mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
33PF 2
0 5% 1/16W MF-LF 402
BOTTOM
5% 1/16W MF-LF 402
R9757
0x58(Wr)/0x59(Rd)
0
2
5% 1/16W MF-LF 402
R9753
VIN
U9701 BKL_VSYNC_R
10K
1 C
VDDIO VLDO
R9741 1
1 D
2
5% 1/16W MF-LF 402
PLACE_NEAR=U9701.E3:10mm
1% 1/16W MF-LF 402
1
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins) MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
XW9710 SM
GND_BKL_SGND
1
0
2
LED_RETURN_4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
5% 1/16W MF-LF 402
BOTTOM
2
BKLT:PROD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V
R9721 PLACE_NEAR=U9701.E2:10mm
I_LED=369/Riset
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
(EEPROM should set EN_I_RES=1)
0
2
LED_RETURN_5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
5% 1/16W MF-LF 402
BOTTOM
BKLT:PROD
R9722 PLACE_NEAR=U9701.E1:10mm
1
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BOTTOM
A
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
0
2
5% 1/16W MF-LF 402
LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
SYNC_MASTER=J31_MLB
10 3S0 19 8
3 R ES ,T HI N F LI M, 1/ 16 W, 10 .2 O HM ,0 .1, 04 02 ,S MR9717,R9718,R9719
B KL T:E NG
10.2 ohm resistors for current
10 3S0 19 8
3 R ES ,T HI N F LI M, 1/ 16 W, 10 .2 O HM ,0 .1, 04 02 ,S MR9720,R9721,R9722
B KL T:E NG
measurement on LED strings.
LCD Backlight Driver DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
SYNC_DATE=07/08/2011
PAGE TITLE
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
97 OF 109 SHEET
77 OF 86
1
A
8
7
6
5
CPU Signal Constraints
4
2
3
1
CPU Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CPU_50S
*
=50_OHM_SE
= 5 0_ O HM _ SE
= 5 0_ O HM _ SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
DMI_S2N
PCIE_85D
PCIE_PCH_TX
DMI_S2N_P<3:0>
9 17
DMI_S2N
PCIE_85D
_PCH_TX PCIE
DMI_S2N_N<3:0>
9 17
DMI_N2S
PCIE_85D
_PCH_RX PCIE
DMI_N2S_P<3:0>
9 17
DMI_N2S
PCIE_85D
_PCH_RX PCIE
DMI_N2S_N<3:0>
9 17
FDI_DATA
PCIE_85D
PCIE_PCH_RX
FDI_DATA_P<7:0>
9 17
FDI_DATA
PCIE_85D
_PCH_RX PCIE
FDI_DATA_N<7:0>
9 17
TABLE_PHYSICAL_RULE_ITEM
CPU_55S
*
CPU_27P4S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
7 MIL
7 MIL
TABLE_PHYSICAL_RULE_ITEM
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
D
CPU_AGTL
*
=STANDARD
?
8 MIL
?
CPU_50S
CPU_AGTL
FDI_FSYNC<1..0>
9 17
CPU_50S
CPU_AGTL
FDI_LSYNC<1..0>
9 17
CPU_50S
CPU_AGTL
FDI_INT
9 17
CPU_PECI
CPU_50S
CPU_COMP
CPU_PECI
10 19 46
PM_SYNC
CPU_50S
CPU_AGTL
PM_SYNC
10 17
PM_MEM_PWRGD
CPU_50S
CPU _AGTL
CPU_50S
CPU_ITP
XDP_DBRESET_L
10 23 24
CPU_50S
CPU_ITP
XDP_CPU_PRDY_L
10 23
CPU_50S
CPU_ITP
XDP_CPU_PREQ_L
10 23
CPU_50S
CPU_AGTL
PM_EXT_TS_L<0>
CPU_50S
CPU_AGTL
PM_EXT_TS_L<1>
CPU_SM_RCOMP
CPU_27P4S
CPU_COMP
CPU_SM_RCOMP<0>
CPU_SM_RCOMP
C P U _ 2 7 P 4 S
TABLE_SPACING_RULE_ITEM
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
D
TABLE_SPACING_RULE_ITEM
CPU_8MIL
*
TABLE_SPACING_RULE_ITEM
CPU_COMP
*
20 MIL
*
=2:1_SPACING
*
25 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_ITP
? TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE
?
PM_MEM_PWRGD
10 17 26
Most CPU signals with impedance requirements are 50-ohm single-ended. Some signals require 27.4-ohm single-ended impedance. SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7
PCI-Express TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM NECK WIDTH
MINIMUM LINE WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
PCIE_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
*
=90_OHM_DIFF
=90_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
10
TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE_90D
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
CPU_SM_RCOMP<1>
CP U _ C O M P CPU_COMP CPU_ITP
CPU_50S
CPU _AGTL
CPU_50S
CPU_AGTL
CPU_VCCIO_SEL
8 12
CPU_PROCHOT_L
CPU_50S
CPU _AGTL
CPU_PROCHOT_L
10 45 46 68
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_PWRGD
10 19 23
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
PM_THRMTRIP_L
10 19 46
DMI_CLK100M
CLK_PCIE_90D
CLK_PCIE
DMI_CLK100M_CPU_P
10 16
DMI_CLK100M
C LK _P CI E_ 90 D
C LK _P CI E
DMI_CLK100M_CPU_N
10 16
ITPCPU_CLK100M
CLK_PCIE_90D
IE CLK_PC
ITPCPU_CLK100M_P
10 16
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
WEIGHT CPU_CATERR_L
CPU_SM_RCOMP<2>
10
CPU_27P4S CPU_50S
CPU_SM_RCOMP TABLE_SPACING_RULE_HEAD
CPU_CFG<11..0> CPU_CATERR_L
10
9 23 10 45
TABLE_SPACING_RULE_ITEM
*
CLK_PCIE
20 MIL
?
TABLE_SPACING_RULE_HEAD
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE_PCH_TX2TX
C
*
=3X_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
PCIE_PCH_TX2TX
TOP,BOTTOM
=4X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
*
PCIE_PCH_TX2RX
=4X_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
PCIE_PCH_TX2RX
TOP,BOTTOM
=5X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
P CI E_ PC H_ RX 2R X
*
= 3x _D IE LE CT RI C
?
PCIE_PCH_RX2TX
*
=4x_DIELECTRIC
?
P CI E_ PC H_ 2O TH ER
*
= 3x _D IE LE CT RI C
?
PCIE_PCH_RX2RX
TOP,BOTTOM
=4x_DIELECTRIC
?
PCIE_PCH_RX2TX
TOP,BOTTOM
=4x_DIELECTRIC
?
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PCIE_PCH_2OTHER
NET_SPACING_TYPE2
AREA_TYPE
10 16
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
ITPXDP_CLK100M_P
16 23
I126
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
ITPXDP_CLK100M_N
16 23 23
I127
I T P C P U _C L K 1 0 0 M
C L K_ P C I E _ 90 D
CLK_PCIE
I128
I T P C P U _C L K 1 0 0 M
C L K_ P C I E _ 90 D
CLK_PCIE
XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N
CPU_27P4S
CPU_COMP
EDP_COMP
9
C P U _ 2 7 P 4 S
CP U _ C O M P
CPU_PEG_COMP
9
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO
CPU_50S
CPU_ITP
XDP_CPU_TDI XDP_CPU_TDO
XDP_TMS
CPU_50S
CPU_ITP
XDP_CPU_TMS
10 23
XDP_TCK
CPU_50S
CPU_ITP
XDP_CPU_TCK
10 23
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_CPU_TRST_L
10 23
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L<3..0>
10 23
XDP_BPM_R_L
CPU_50S
CPU _ITP
CPU_CFG<15..12>
9 23
(FSB_CPURST_L)
CPU_50S
CPU_ITP
XDP_CPURST_L
23
CPU_VCCSENSE_P
12 68
CPU_VCCSENSE_N
12 68
I121
SPACING_RULE_SET
ITPCPU_CLK100M_N
I125
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
C
TABLE_SPACING_RULE_ITEM
23
TABLE_SPACING_ASSIGNMENT_ITEM
P CI E_ PC H_ TX
* _P CH _T X
*
P CI E_ PC H_ TX 2T X
PCIE_PCH_TX
* _P CH _R X
*
P CI E_ PC H_ TX 2R X
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
*
P CI E_ PC H_ RX
* _P CH _R X
P CI E_ PC H_ RX
* _P CH _T X
*
P CI E_ PC H_ RX 2T X
PCIE_PCH_TX
*
*
PCIE_PCH_2OTHER
P CI E_ PC H_ RX 2R X
*
*
PCIE_PCH_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
10 23 10 23
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_RX
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
B
C PU _ 2 7P 4 S
CPU_VCCAXG_SENSE
C PU _ 2 7P 4 S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCIOSENSE_P
12 70
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCIOSENSE_N
12 70
CPU_VCCAXG_SENSE
CP U _V C CS E NS E CP U _V C CS E NS E
CPU_ VCCSENSE
CPU_AXG_SENSE_P
12 68
CPU_VCCSENSE
CPU_AXG_SENSE_N
12 68
CP U _V C CS E NS E
CPU_VDDQ_SENSE_P
12
CPU_VCCSENSE
CPU_VDDQ_SENSE_N
12
CPU_AXG_VALSENSE_P
9
CPU_VCCAXG_SENSE
CPU_27P4S
CPU_VCCAXG_SENSE
CPU_27P4S
I115
CPU_VALSENSE
C PU _ 2 7P 4 S
I116
CPU_VALSENSE
CPU_27P4S
I117
CPU_VALSENSE
C PU _ 2 7P 4 S
I118
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I119
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I120
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I122
CPU_SVIDALERT_L
CPU_50S
CPU_COMP
CP U _V C CS E NS E
CPU_AXG_VALSENSE_N CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N
CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>
B
9 9 9
CPU_VIDALERT_L I123
CPU_SVIDSCLK
CPU_50S
CPU_COMP
I124
CPU_SVIDSOUT
CPU_50S
CPU_COMP
12 68
CPU_VIDSCLK
12 68
CPU_VIDSOUT
12 68
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
CPU Constraints DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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8
7
6
5
Memory Bus Constraints
4
2
3
1
Memory Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_37S
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=STANDARD
=STANDARD
NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK_P<5..0>
MEM_A_CLK
MEM_72D
MEM_CLK
MEM_A_CLK
MEM_72D
MEM_CLK
MEM_A_CLK_N<5..0>
11 27
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CKE<3..0>
11 27
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CS_L<3..0>
11 27
11 27
11 27
TABLE_PHYSICAL_RULE_ITEM
MEM_40S
*
MEM_72D
*
= 40 _O HM _S E
= 40 _O HM _S E
= 40 _O HM _S E
=40_OHM_SE
=STANDARD
=STANDARD
=72_OHM_DIFF
=72_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
MEM_50S
TOP,BOTTOM
Y
MEM_85D
TOP,BOTTOM
Y
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
= 85 _O HM _D IF F
= 85 _O HM _D IF F
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_ODT<3..0>
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_A<15..0>
11 27
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_BA<2..0>
11 27
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_RAS_L
11 27
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CAS_L
11 27
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_WE_L
11 27
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
D
MEM_50S
N
ISL10
=50_OHM_SE
=50_OHM_SE
=STANDARD
=50_OHM_SE
=STANDARD TABLE_PHYSICAL_RULE_ITEM
MEM_85D
ISL10
=85_OHM_DIFF
N
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
D
TABLE_PHYSICAL_RULE_ITEM
MEM_50S
Y
ISL3,ISL4,ISL9
=50_OHM_SE
=50_OHM_SE
=STANDARD
=50_OHM_SE
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
ISL3,ISL4,ISL9
=85_OHM_DIFF
Y
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
MEM_A_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_A_DQ<7..0>
11 28
MEM_A_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_A_DQ<15..8>
11 28
MEM_A_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_A_DQ<23..16>
11 28
MEM_A_DQ_BYTE3
MEM_50S
MEM _DATA
MEM_A_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_A_DQ<31..24> MEM_A_DQ<39..32>
MEM_A_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_A_DQ<47..40>
11 28
MEM_A_DQ_BYTE6
MEM_50S
MEM_A_DQ<55..48>
11 28
MEM_A_DQ_BYTE7
MEM_50S
MEM_A_DQ<63..56>
11 28
MEM_A_DQS_P<0>
11 28
MEM_A_DQS0
TABLE_SPACING_RULE_HEAD
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
WEIGHT
MEM_DATA
MEM_85D
MEM_DATA
MEM_DQS
11 28 11 28
MEM_DQS
MEM_A_DQS_N<0>
11 28
MEM _DQS
MEM_A_DQS_P<1>
11 28
MEM_DQS
MEM_A_DQS_N<1>
11 28
MEM_DQS
MEM_A_DQS_P<2>
11 28
MEM_DQS
MEM_A_DQS_N<2>
11 28
MEM_85D
MEM_DQS
MEM_A_DQS_P<3>
11 28
MEM_A_DQS3
MEM_85D
MEM_DQS
MEM_A_DQS_N<3>
11 28
MEM_A_DQS4
MEM_85D
MEM_DQS
MEM_A_DQS_P<4>
11 28
MEM_A_DQS4
MEM_85D
MEM_DQS
MEM_A_DQS_N<4>
11 28
MEM_A_DQS0
C
MEM_85D
MEM_A_DQS1
MEM_85D
MEM_A_DQS1
MEM_85D
MEM_A_DQS2
MEM_85D
MEM_A_DQS2
MEM_85D
MEM_A_DQS3
MEM_A_DQS5
MEM_85D
MEM_A_DQS5
MEM_85D
MEM_A_DQS6
MEM_85D
MEM_A_DQS6
MEM_85D
MEM_DQS
MEM_A_DQS_P<5>
11 28
MEM_DQS
MEM_A_DQS_N<5>
11 28
MEM_DQS
MEM_A_DQS_P<6>
11 28
MEM_DQS
MEM_A_DQS_N<6>
11 28
C
TABLE_SPACING_RULE_ITEM
*
MEM_CLK2MEM
=4:1_SPACING
? TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=3:1_SPACING
?
*
=2.5:1_SPACING
?
MEM_A_DQS7
MEM_85D
MEM_DQS
MEM_A_DQS_P<7>
11 28
MEM_A_DQS7
MEM_85D
MEM_DQS
MEM_A_DQS_N<7>
11 28
MEM_B_CLK
MEM_72D
MEM_CLK
MEM_B_CLK_P<5..0>
TABLE_SPACING_RULE_ITEM
MEM_B_CLK
MEM_72D
MEM_CLK
TABLE_SPACING_RULE_ITEM
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CKE<3..0>
11 29
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CS_L<3..0>
11 29
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_ODT<3..0>
11 29
TABLE_SPACING_RULE_ITEM
MEM_CTRL2MEM
TABLE_SPACING_RULE_ITEM
*
M EM _C MD 2C MD
?
= 1. 5: 1_ SP AC IN G
MEM_CMD2MEM
*
=3:1_SPACING
?
M EM _D AT A2 DA TA
*
= 1. 5: 1_ SP AC IN G
?
MEM_B_CLK_N<5..0>
11 29 11 29
TABLE_SPACING_RULE_ITEM
ME M_ DA TA 2M EM
= 3: 1_ SP AC IN G
*
? TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
? TABLE_SPACING_RULE_ITEM
MEM_2OTHER
25 MILS
*
NET_SPACING_TYPE1
SPACING_RULE_SET
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
*
MEM_CTRL
*
MEM_B_CMD
MEM_40S
MEM_CLK2MEM
MEM_CMD
MEM_CLK
*
MEM_CMD
MEM _CTRL
*
MEM_CMD2MEM
MEM_CLK2MEM
MEM_CMD2MEM
MEM_CMD
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
*
MEM_CLK2MEM
MEM_CMD
MEM _CMD
*
MEM_CMD
MEM_DATA
*
MEM_CMD
MEM_B_RAS_L
11 29
MEM_CMD
MEM_B_CAS_L
11 29
MEM_B_CMD
MEM_40S
MEM_CMD
MEM_B_WE_L
11 29
MEM_B_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_B_DQ<7..0>
11 28
MEM_B_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_B_DQ<15..8>
11 28
MEM_50S
MEM_DATA
MEM_B_DQ<23..16>
11 28
MEM_B_DQ<31..24>
11 28
MEM_B_DQ<39..32>
*
MEM_CLK2MEM
11 28
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM _CLK
*
MEM_CTRL2MEM
MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
MEM_DATA
C ME M_ TR L
*
M EM _D AT A2 ME M
MEM_DATA
MEM _CMD
*
MEM_DATA2MEM
MEM_DATA
ME M_ DAT A
*
M EM _D ATA 2D AT A
MEM_DATA
MEM_DQS
*
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
* *
MEM_CMD
*
MEM_DATA
MEM_B_DQ_BYTE5
MEM_50S
MEM_B_DQ<47..40>
11 28
MEM_B_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_B_DQ<55..48>
11 28
MEM_B_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_B_DQ<63..56>
11 28
MEM_B_DQS_P<0>
11 28
MEM_B_DQS0
MEM_85D
MEM_DQS
MEM_B_DQS_N<0>
11 28
MEM_B_DQS1
MEM_85D
MEM_DQS
MEM_B_DQS_P<1>
11 28
MEM_B_DQS1
MEM_85D
MEM_DQS
MEM_B_DQS_N<1>
11 28
MEM_85D
MEM_DQS
MEM_B_DQS_P<2>
11 28
MEM_85D
MEM_DQS
MEM_B_DQS_N<2>
11 28
MEM_B_DQS3
MEM_85D
MEM_DQS
MEM_B_DQS_P<3>
11 28
MEM_B_DQS3
MEM_85D
MEM_DQS
MEM_B_DQS_N<3>
11 28
MEM_B_DQS4
MEM_85D
MEM_DQS
MEM_B_DQS_P<4>
11 28
MEM_B_DQS4
MEM_85D
MEM_DQS
MEM_B_DQS_N<4>
11 28
MEM_B_DQS5
MEM_85D
MEM_DQS
MEM_B_DQS5
MEM_85D
MEM_DQS
MEM_B_DQS_P<5> MEM_B_DQS_N<5>
MEM_B_DQS6
MEM_85D
MEM_DQS
MEM_B_DQS_P<6>
MEM_B_DQS6
MEM_85D
per Huron River SFF DG rev1.0 (#438297).
MEM_B_DQS7
MEM_85D
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
MEM_B_DQS7
MEM_85D
MEM_CTRL
MEM_DQS
*
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2MEM
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
*
MEM_CLK
MEM_B_DQS0
MEM_85D
MEM_CLK
MEM_DQS2MEM
*
*
MEM_B_DQS2
MEM_2OTHER
MEM_B_DQS2
MEM_CTRL
*
MEM_CTRL
MEM_DQS2MEM
*
*
MEM_CMD
*
MEM_CMD
MEM_DQS2MEM
*
*
TABLE_SPACING_ASSIGNMENT_ITEM
M EM _D QS
M EM _D AT A
MEM_DQS
MEM_DQS
*
MEM_DQS2MEM
*
MEM_DQS2MEM
MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
*
*
MEM_2OTHER
MEM_DQS
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Need to support MEM_*-style wildcards!
DDR3:
MEM_DQS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_DQS
B
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM
A
MEM_DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_50S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DATA
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_CTRL
MEM_50S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
11 29
MEM_40S MEM_40S
MEM_B_DQ_BYTE4
MEM_CMD2CMD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
11 29
MEM_B_BA<2..0>
MEM_B_CMD
MEM_B_DQ_BYTE3
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CMD
MEM_B_CMD
MEM_B_DQ_BYTE2
B
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CMD
MEM_B_A<15..0>
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_HEAD
AREA_TYPE
NET_SPACING_TYPE2
MEM_40S
?
Memory Bus Spacing Group Assignments NET_SPACING_TYPE1
MEM_B_CMD
Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines
MEM_DQS
MEM_DQS
MEM_B_DQS_N<6> MEM_B_DQS_P<7>
MEM _DQS
MEM_B_DQS_N<7>
11 28 11 28 11 28 11 28
SYNC_MASTER=K90I_MLB 11 28
Memory Constraints DRAWING NUMBER
DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].
Apple Inc.
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm. CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.
R
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm.
NOTICE OF PROPRIETARY PROPERTY:
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm. SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5
8
7
SYNC_DATE=02/15/2011
PAGE TITLE
11 28
DQ to DQS matching per byte lane should be within 0.127mm.
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Digital Video Signal Constraints PHYSICAL_RULE_SET
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
2
3
DIFFPAIR NECK GAP
1
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
DP_85D
4 PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
LVDS_90D
=90_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
SPACING_RULE_SET
WEIGHT
LAYER
LINE-TO-LINE
SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
DP_PCH
*
DP_PCH_TX
*
=3x_DIELECTRIC
DP_PCH
TOP,BOTTOM
=4x_DIELECTRIC
?
DP_PCH_TX
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
= 3x _D IE LE CT RI C
*
LVDS_IG_A_CLK_P
17 74
L V DS _ 9 0 D
L V D S _ P C H _ T X
LVDS_IG_A_CLK_N
17 74
LVDS_IG_A_DATA
L V DS _ 9 0 D
L V D S _ P C H _ T X
LVDS_IG_A_DATA_P<2..0>
6 17 74
LVDS_IG_A_DATA_N<2..0>
6 17 74
LVDS_IG_A_DATA
LVDS_PCH_TX
LVDS_90D
LVDS_PCH_TX
LVDS_90D
LVDS_PCH_TX
LVDS_90D
LVDS_PCH_TX
I213
LVDS_90D
LVDS_PCH_TX
I214
L V DS _ 9 0 D
L V D S _ P C H _ T X
I215
L V DS _ 9 0 D
L V D S _ P C H _ T X
I216
L V DS _ 9 0 D
L V D S _ P C H _ T X
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
L VD S_ PC H_ TX
LVDS_90D
LVDS_IG_A_CLK
TABLE_SPACING_RULE_ITEM
?
=3x_DIELECTRIC
LVDS_IG_A_CLK
LVDS_PCH_TX
?
TOP,BOTTOM
=4x_DIELECTRIC
?
SATA Interface Constraints
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3> LVDS_IG_B_DATA_P<3..0> LVDS_IG_B_DATA_N<3..0> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N
8 17 8 17
D
8 17 8 17 8 17 8 17
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
SATA_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=90_OHM_DIFF
=90_OHM_DIFF
SATA_HDD_R2D
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_C_P
16 41
SATA_HDD_R2D
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_C_N
16 41
SATA_HDD_R2D_CONN
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_CONN
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_P SATA_HDD_R2D_N
SATA_HDD_D2R
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_P
16 41
SATA_HDD_D2R
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_N
16 41
SATA_HDD_D2R_CONN
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_C_P
6 41
SATA_HDD_D2R_CONN
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_C_N
6 41 16 41
TABLE_PHYSICAL_RULE_ITEM
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
SPACING_RULE_SET
WEIGHT
LAYER
LINE-TO-LINE
SPACING
WEIGHT
SATA_PCH_TX
*
=3x_DIELECTRIC
S AT A_ PC H_ TX
?
TOP,BOTTOM
= 4x _D IE LE CT RI C
?
TABLE_SPACING_RULE_ITEM
S AT A_ PC H_ RX
= 3x _D IE LE CT RI C
*
6 41 6 41
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S AT A_ PC H_ RX
?
TOP,BOTTOM
= 4x _D IE LE CT RI C
?
TABLE_SPACING_RULE_ITEM
SATA_ICOMP
8 MIL
*
?
LAYER
LINE-TO-LINE
SPACING
WEIGHT
= 4X _D IE LE CT RI C
*
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
S AT A3 _P CH _T X2 TX
?
TOP,BOTTOM
= 5X _D IE LE CT RI C
*
=5X_DIELECTRIC
?
*
= 4x _D IE LE CT RI C
?
S AT A3 _P CH _T X2 RX
TOP,BOTTOM
= 6X _D IE LE CT RI C
?
SATA3_PCH_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
*
=5x_DIELECTRIC
?
*
=4x_DIELECTRIC
?
SATA3_PCH_RX2TX
TOP,BOTTOM
=6x_DIELECTRIC
? TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SATA3_PCH_2OTHER
16 41
SATA_ODD_R2D
SATA_90D
SATA_PCH_TX
SATA_ODD_R2D_P
6 41
SATA_ODD_R2D
SATA_90D
SATA_PCH_TX
SATA_ODD_R2D_N
6 41
SATA_ODD_D2R
SATA_90D
SATA_PCH_RX
SATA_ODD_D2R_P
16 41
SATA_ODD_D2R
SATA_90D
SATA_PCH_RX
SATA_ODD_D2R_N
16 41
SATA_HDD_R2D_CONN
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_RC_P
41
SATA_HDD_R2D_CONN
SATA_90D
3_PCH_TX SATA
SATA_HDD_R2D_RC_N
41
S AT A _ HD D _ D2 R _ CO N N
S AT A _ 90 D
SATA3_PCH_RX
SATA_HDD_D2R_RC_P
41
S AT A _ HD D _ D2 R _ CO N N
S AT A _ 90 D
SATA3_PCH_RX
SATA_HDD_D2R_RC_N
41
PCH_SATAICOMP
16
SATA3_PCH_2OTHER
=5x_DIELECTRIC
TOP,BOTTOM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
PCH_SATA_ICOMP
?
SPACING_RULE_SET
SATA_ICOMP USB_85D
USB
USB_HUB_UP_P
18 25
USB_85D
USB
USB_HUB_UP_N
18 25
USB_EXTA
USB_85D
USB
USB_EXTA_P
18 42
USB_EXTA
USB_85D
USB
USB_EXTA_N
18 42
USB_EXTB
USB_85D
USB
USB_EXTB_MUX_P
25 43
USB_85D
USB
USB_EXTB_MUX_N
25 43
USB_85D
USB
USB_EXTA_MUXED_F_P
42
USB_HUB1_UP
C
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SATA3_PCH_RX2TX
SATA_PCH_TX
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S AT A3 _P CH _R X2 RX
SATA_90D
SATA_ODD_R2D_C_N
?
TABLE_SPACING_RULE_ITEM
SATA3_PCH_TX2RX
SATA_ODD_R2D
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
S AT A3 _P CH _T X2 TX
SATA_PCH_TX
SATA_ODD_R2D_C_P
SATA_ODD_R2D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
SATA_90D
C
TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_TX
*_PCH_TX
SATA3_PCH_TX2TX
*
TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_TX
*_PCH_RX
I219
SATA3_PCH_TX2RX
*
*_PCH_RX
*
SATA3_PCH_RX2RX
*_PCH_TX
*
SATA3_PCH_RX2TX
USB_EXTA_MUXED_F_N
42
I221
USB_85D
USB
USB_EXTB_F_P
43
I222
USB_85D
USB
USB_EXTB_F_N
43
I223
USB_85D
USB
USB_EXTA_MUXED_P
42
I224
USB_85D
USB
USB_EXTA_MUXED_N
42
I225
USB_85D
USB
USB_EXTD_XHCI_P
8 18
I226
USB_85D
USB
USB_EXTD_XHCI_N
8 18
I247
USB_85D
USB
USB_EXTB_EHCI_P
18 25
I248
USB_85D
USB
USB_EXTB_EHCI_N
18 25
I250
USB_85D
USB
USB_EXTB_XHCI_P
18 25
I249
USB_85D
USB
USB_EXTB_XHCI_N
18 25
USB_85D
USB3_PCH_RX
USB3_EXTA_RX_P
18 42
USB_85D
USB3_PCH_RX
USB_85D
USB3_PCH_TX
USB3_EXTA_TX_P
18 42
USB_85D
USB3_PCH_TX
USB3_EXTA_TX_N
18 42
USB_85D
USB3_PCH_RX
USB3_EXTB_RX_P
18 43
USB_85D
USB3_PCH_RX
USB3_EXTB_RX_N
18 43
USB3_PCH_TX
USB3_EXTB_TX_P
18 43
USB_85D
USB3_PCH_TX
USB3_EXTB_TX_N
18 43
USB_85D
USB3_PCH_RX
USB3_EXTA_RX_F_P
42
USB_85D
USB3_PCH_RX
USB3_EXTA_RX_F_N
42
USB3_EXTA_TX_F_P
USB_85D
I220
TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_RX SATA3_PCH_RX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_TX
*
*
SATA3_PCH_RX
*
*
SATA3_PCH_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_2OTHER
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
I228
USB3_EXT_RX
I227
USB 2.0 Interface Constraints
I229
USB3_EXT_TX
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
I230
DIFFPAIR NECK GAP
I231
TABLE_PHYSICAL_RULE_ITEM
PCH_USB_RBIAS
=STANDARD
*
8 MIL
8 MI L
= ST AND AR D
=STANDARD
=STANDARD
I232 TABLE_PHYSICAL_RULE_ITEM
USB_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
USB3_EXT_RX
I234
=85_OHM_DIFF
USB3_EXT_TX
SPACING_RULE_SET
B
LAYER
SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE
WEIGHT
SPACING
*
?
=2x_DIELECTRIC
I236
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
USB
I235
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_HEAD
WEIGHT
USB
TOP,BOTTOM
=4x_DIELECTRIC
?
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
USB 3.0 Interface Constraints MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
*
USB_85D
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LAYER
SPACING_RULE_SET
LINE-TO-LINE
WEIGHT
SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE
WEIGHT
SPACING
TABLE_SPACING_RULE_ITEM
*
USB3_PCH_TX2TX
=4X_DIELECTRIC
*
=5X_DIELECTRIC
?
USB3_PCH_TX2TX
TOP,BOTTOM
=5X_DIELECTRIC
*
= 4x _D IE LE CT RI C
I237
USB_85D
USB3_PCH_TX
USB3_EXTA_TX_F_N
42
I240
USB_85D
USB3_PCH_RX
USB3_EXTB_RX_F_P
43
I239
USB_85D
USB3_PCH_RX
USB3_EXTB_RX_F_N
43
USB3_EXTB_TX_F_P
43
I241
USB_85D
USB3_PCH_TX
I242
USB_85D
USB3_PCH_TX
I244
USB_85D
USB3_PCH_TX
USB3_EXTB_TX_F_N USB3_EXTA_TX_C_P
I243
USB_85D
USB3_PCH_TX
USB3_EXTA_TX_C_N
I246
USB_85D
USB3_PCH_TX
USB3_EXTB_TX_C_P
I245
USB_85D
USB3_PCH_TX
USB_EXTA
USB_85D
U SB 3_ PC H_ TX 2R X
TOP,BOTTOM
= 6X _D IE LE CT RI C
USB3_PCH_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
*
=5x_DIELECTRIC
?
=4x_DIELECTRIC
?
NET_SPACING_TYPE2
AREA_TYPE
A
* _P C H_ TX
*
43
8 45
USB_SMC_N
8 45
USB
USB_EXTC_P
8 18
USB
USB_EXTC_N
8 18
USB_85D
USB
USB_CAMERA_P
18 32
USB_85D
USB
USB_CAMERA_N
18 32
USB_85D
USB
USB_CAMERA_CONN_P
6 32
USB_85D
USB
USB_CAMERA_CONN_N
6 32
USB_BT
USB_85D
USB
USB_BT_P
8 32
USB_BT
USB_85D
USB
USB_BT_N
8 32
I253
USB_BT
USB_85D
USB
USB_BT_CONN_P
6 32
I254
USB_BT
USB_85D
USB
USB_BT_CONN_N
6 32
USB_TPAD
USB_85D
USB
USB_TPAD_P
8 53
USB_85D
USB
USB_85D
USB
USB_TPAD_N USB_IR_P
USB_85D
USB
USB_IR_N PCH_USB_RBIAS PCIE_CLK100M_PCH_P
? TABLE_SPACING_RULE_ITEM
USB3_PCH_RX2TX
TOP,BOTTOM
=6x_DIELECTRIC
U SB 3_ PC H_ 2O TH ER
TOP,BOTTOM
= 5x _D IE LE CT RI C
? TABLE_SPACING_RULE_ITEM
USB_CAMERA
?
SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM
U S B3 _ PC H _T X
43
USB_SMC_P
USB_85D
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
42
TABLE_SPACING_RULE_ITEM
?
TABLE_SPACING_RULE_ITEM
*
42
USB3_EXTB_TX_C_N
USB_85D
USB_EXTC
USB_CAMERA
USB3_PCH_RX2TX
USB
43
USB
?
TABLE_SPACING_RULE_ITEM
USB3_PCH_2OTHER
B
42
USB_85D
I252
TABLE_SPACING_RULE_ITEM
?
18 42
USB3_PCH_TX
?
TABLE_SPACING_RULE_ITEM
U SB 3_ PC H_ RX 2R X
USB3_EXTA_RX_N
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
USB3_PCH_TX2RX
USB_85D
I251
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_HEAD
I238
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE ON LAYER?
LAYER
PHYSICAL_RULE_SET
USB_85D
I233
LINE-TO-LINE
USB
USB3_PCH_TX2TX TABLE_SPACING_ASSIGNMENT_ITEM
U S B3 _ PC H _T X
* _P C H_ RX
*
USB3_PCH_TX2RX
U S B3 _ PC H _R X
* _P C H_ RX
*
USB3_PCH_RX2RX
TABLE_SPACING_ASSIGNMENT_ITEM
USB_IR
8 53 8 44
S YN C_ MA ST ER =K 90 I_ ML B
U S B3 _ PC H _R X
* _P C H_ TX
*
USB3_PCH_RX2TX
P C H_ U S B _ R BI A S
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
*
*
USB3_PCH_2OTHER
USB3_PCH_RX
*
*
USB3_PCH_2OTHER
P C H_ U S B _ R BI A S
PCH Constraints 1
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
7
6
5
DRAWING NUMBER
PCH_DIFFCLK_UNUSED_
C LK _P CI E_ 90 D
C LK _P CI E
CLK_PCIE_90D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
PCIE_CLK100M_PCH_N PCH_CLK96M_DOT_P
PCH_DIFFCLK_UNUSED_
C LK _P CI E_ 90 D
C LK _P CI E
PCH_CLK96M_DOT_N
16
PCH_DIFFCLK_UNUSED_
C LK _P CI E_ 90 D
C LK _P CI E
PCH_CLK100M_SATA_P
16
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
PCH_CLK100M_SATA_N
16
CPU_50S
CLK_PCIE
PCH_CLK14P3M_REFCLK
16
CPU_50S
CLK_PCIE
LPC_CLK33M
8
18
PCH_DIFFCLK_UNUSED_
TABLE_SPACING_ASSIGNMENT_ITEM
4
PCH_CLK33M_PCIIN
3
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
8 44
TABLE_SPACING_ASSIGNMENT_ITEM
SIZE
16
Apple Inc.
16 16
16 24
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
2
051-9058 6.0.0
REVISION
D
BRANCH
PAGE
102 OF 109 SHEET
80 OF 86
1
A
8
7
6
5
LPC Bus Constraints
4
PHYSICAL_RULE_SET
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
1
Chipset Net Properties
NET_TYPE
DIFFPAIR NECK GAP
2
3
PCH Net Properties TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
SPACING
TABLE_PHYSICAL_RULE_ITEM
LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM
CLK_LPC_50S
LPC_AD
LPC_50S
LPC
LPC_AD<3..0>
6 16 45 47
LPC_FRAME_L
LPC_50S
LPC
LPC_FRAME_L
6 16 45 47
LPC_RESET_L
LPC_50S
LPC
LPC_RESET_L
24
LAYER
LINE-TO-LINE
SPACING
WEIGHT LPC_CLK33M
CLK_LPC_50S
CLK_LPC
LPC
*
6 MIL
*
8 MIL
? TABLE_SPACING_RULE_ITEM
LPC_CLK33M
CLK_LPC_50S
LPC_CLK33M
CLK_LPC_50S
SMBUS_PCH_CLK
SMB_50S
I251
DP_EXTA_ML
DP_85D
DP_PCH_TX
SMBUS_PCH_DATA
SMB_50S
D
SMBUS_PCH_0_CLK
SMB_50S
SMB
SMBus Interface Constraints
SMBUS_PCH_0_DATA
SMB_50S
SMB
SMBUS_SMC_B_S0_SCL
SMB_50S
DP_PCH_TX
DP_EXTA_ML_C_N<3..0>
8 75
I253
DP_85D
DP_PCH_TX
DP_EXTA_ML_P<3..0>
75
DP_85D
DP_PCH_TX
18 24
I255
CLK_LPC
LPC_CLK33M_SMC
24 45
I254
DP_EXTA_AUXCH
DP_85D
DP_PCH
CLK_LPC
LPC_CLK33M_LPCPLUS
6 24 47
I256
DP_EXTA_AUXCH
DP_85D
DP_PCH
SMB
SMBUS_PCH_CLK
I257
DP_85D
DP_PCH
16 48
DP_PCH
16 48
I258
DP_85D
SMB
SMBUS_PCH_DATA
DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N
SML_PCH_0_CLK
16 48
SML_PCH_0_DATA
16 48
PCIE_85D
PCIE_T29_RX
?
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
DP_EXTA_ML_C_P<3..0>
DP_85D
LPC_CLK33M_SMC_R
TABLE_SPACING_RULE_ITEM
CLK_LPC
SPACING
DP_EXTA_ML
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
PHYSICAL
I252
8 75
DP_EXTA_ML_N<3..0>
75
DP_EXTA_AUXCH_C_P
8 75
DP_EXTA_AUXCH_C_N
8 75 75
D
75
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SMB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
SMBUS_SMC_B_S0_SDA HDA_BIT_CLK
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT HDA_SYNC
SMB_50S
SML_PCH_1_CLK SML_PCH_1_DATA
SMB SMB
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC
16 48 16 48
16 57 16 16 57
TABLE_SPACING_RULE_ITEM
*
SMB
HDA_SYNC_R
16
HDA
HDA_RST_R_L
16
HDA_50S
HDA
HDA_RST_L
16 57
HDA_50S
HDA
HDA_SDIN0
16 57
HDA
AUD_SDI_R
57
HDA_50S
HDA
HDA_SDOUT
16 57
HDA_50S
HDA
HDA_SDOUT_R
PM_SUS_CLK
CLK_SLOW_55S
CLK_SLOW
SPI_CLK
SPI_50S
SPI
SPI_CLK_R
16 47
SPI_50S
SPI
SPI_CLK
SPI_50S
SPI
SPI_50S
SPI
SPI_MISO
SPI_50S
SPI_CS0
?
=2x_DIELECTRIC
HDA_RST_L
HD Audio Interface Constraints
HDA_SDIN0
HDA_50S
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE ON LAYER?
LAYER
PHYSICAL_RULE_SET
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
HDA_SDOUT
TABLE_PHYSICAL_RULE_ITEM
*
HDA_50S
= 50 _O HM _S E
= 50 _O HM _S E
= 50 _O HM _S E
=STANDARD
=50_OHM_SE
=STANDARD
16 24
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
*
_T29_RX PCIE
47
I276
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
SPI_MOSI_R
16 47
I275
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
PCIE_T29_D2R_N<3..0>
8 33
SPI_MOSI
47
I277
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
PCIE_T29_D2R_C_P<3..0>
33
SPI
SPI_MISO
16 47
I278
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
PCIE_T29_D2R_C_N<3..0>
33
SPI_50S
SPI
SPI_CS0_R_L
16 47
PCIE_CLK100M_T29
SPI_50S
SPI
SPI_CS0_L
C LK _P CI E_ 90 D
47
SPI_50S
SPI
SPI_MLB_CLK
PCIE_CLK100M_T29
I288
C LK _P CI E_ 90 D
46 47 56
I289
SPI_50S
SPI
SPI_MLB_CS_L
46 47 56
I290
SPI_50S
SPI
SPI_MLB_MOSI
46 47 56
I291
SPI_50S
SPI
SPI_MLB_MISO
46 47 56
I292
SPI_50S
SPI
SPI_SMC_MISO
45 46
I293
SPI_50S
SPI
SPI_SMC_MOSI
45 46
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
C
CLK_SLOW_55S
=55_OHM_SE
*
=55_OHM_S E
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
*
CLK_SLOW
?
8 MIL
I295
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
SPI_50S
*
= 50 _O HM _S E
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
= 50 _O HM _S E
= 50 _O HM _S E
= 50 _O HM _S E
=STANDARD
=STANDARD
SPI
PCIE_ENET_R2D
I279
SPI_SMC_CLK
45 46
SPI_50S
SPI
SPI_SMC_CS_L
45 46
PCIE_85D
PCIE_PCH_TX
PCIE_ENET_R2D_P
36
PCIE_85D
PCIE_PCH_TX
PCIE_ENET_R2D_N
36
SPI_50S
I294
SPI Interface Constraints ALLOW ROUTE ON LAYER?
P C I E _ P C H _ T X
PCIE_ENET_R2D_C_P
16 36
PCIE_85D
PCIE_PCH_TX
PCIE_ENET_R2D_C_N
16 36
PCIE_85D
PCIE_PCH_RX
PCIE_ENET_D2R_P
16 36
PCIE_85D
PCIE_PCH_RX
PCIE_ENET_D2R_N
16 36
PCIE_85D
PCIE_PCH_RX
PCIE_ENET_D2R_C_P
36
P C I E _ 8 5D
P C I E _ P C H _ R X
PCIE_ENET_D2R_C_N
36
PCIE_AP_R2D_P
6 32
PCIE_AP_R2D_N
6 32
PCIE_AP_R2D_C_P
16 32
PCIE_AP_R2D_C_N
16 32
PCIE_AP_D2R_P
16 32
PCIE_AP_D2R_N
16 32
PCIE_FW_R2D_P
38
PCIE_FW_R2D_N
38
P C I E _ 8 5D
I280
PCIE_ENET_D2R TABLE_SPACING_RULE_HEAD
LAYER
LINE-TO-LINE
SPACING
WEIGHT
PCIE_T29_R2D_P<3..0>
33
PCIE_T29_R2D_N<3..0>
33
PCIE_T29_D2R_P<3..0>
8 33
C LK _P CI E
PCIE_CLK100M_T29_P
16 33
C LK _P CI E
PCIE_CLK100M_T29_N
16 33
C
Clock Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
CLK_SLOW_55S
OW CLK_SL
SYSCLK_CLK32K_RTC
16 24
CLK_25M_55S
CLK_25M
SYSCLK_CLK25M_SB
16 24
I283
CLK_25M_55S
CLK_25M
SYSCLK_CLK25M_SB_R
16
I284
CLK_25M_55S
CLK_25M
SYSCLK_CLK25M_ENET
24 36
I285
CL K _2 5 M _5 5 S
C LK _ 25 M
SYSCLK_CLK25M_ENET_R
CL K _ 2 5M _ 5 5 S
C L K_ 2 5M
SYSCLK_CLK25M_T29
24 33
CL K _2 5 M _5 5 S
C LK _ 25 M
SYSCLK_CLK25M_T29_R
33
I281
SYSCLK_CLK32K_RTC
I282
SYSCLK_CLK25M_SB
TABLE_PHYSICAL_RULE_ITEM
SPACING_RULE_SET
8 33
PCIE_T29_RX
SIO Signal Constraints LAYER
8 33
PCIE_T29_R2D_C_N<3..0>
_T29_RX PCIE
PCIE_85D PCIE_85D
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
PHYSICAL_RULE_SET
PCIE_T29_R2D_C_P<3..0>
PCIE_85D
PCIE_T29_R2D
SPI_MOSI
ALLOW ROUTE ON LAYER?
PCIE_T29_R2D PCIE_T29_R2D
I274
?
=2x_DIELECTRIC
PCIE_T29_R2D
I272
WEIGHT TABLE_SPACING_RULE_ITEM
HDA
I271 I273
PM_CLK32K_SUSCLK
TABLE_SPACING_RULE_HEAD
I286 I287
S Y S C L K _ C L K 2 5 M_ T 2 9
TABLE_SPACING_RULE_ITEM
SPI
8 MIL
*
?
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D PCIE_AP_R2D
PCIE_AP_D2R
PCIE_FW_R2D
B
PCI-Express Signal Constraints
PCIE_FW_D2R
LAYER
LINE-TO-LINE
SPACING
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE_T29_TX2TX
*
TABLE_SPACING_RULE_ITEM
?
=3X_DIELECTRIC
P CI E_ T2 9_ TX 2T X
TOP,BOTTOM
= 4X _D IE LE CT RI C
?
TABLE_SPACING_RULE_ITEM
*
PCIE_T29_TX2RX
=4X_DIELECTRIC
?
*
=3x_DIELECTRIC
?
*
= 4x _D IE LE CT RI C
?
TABLE_SPACING_RULE_ITEM
P CI E_ T2 9_ TX 2R X
TOP,BOTTOM
= 5X _D IE LE CT RI C
?
P CI E_ T2 9_ RX 2R X
TOP,BOTTOM
= 4x _D IE LE CT RI C
?
P CI E_ T2 9_ RX 2T X
TOP,BOTTOM
= 4x _D IE LE CT RI C
?
TABLE_SPACING_RULE_ITEM
PCIE_T29_RX2RX
*
P CI E_ T2 9_ 2O TH ER
TOP,BOTTOM
= 4x _D IE LE CT RI C
? PCIE_CLK100M_ENET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
_PCH_TX PCIE
PCIE_FW_R2D_C_P
16 38
PCIE_85D
PCIE_PCH_TX
PCIE_FW_R2D_C_N
16 38
PCIE_PCH_RX
PCIE_FW_D2R_P
16 38
PCIE_85D
PCIE_PCH_RX
PCIE_FW_D2R_N
16 38
PCIE_85D
PCIE_PCH_RX
PCIE_FW_D2R_C_P
38
PCIE_85D
PCIE_PCH_RX
PCIE_FW_D2R_C_N
38
PCIE_AP_D2R_PI_P
6 32
PCIE_85D
B
PCIE_85D
PCIE_85D
PCIE_PCH_RX PCIE_PCH_RX
PCIE_AP_D2R_PI_N PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N
PCIE_PCH_RX
6 32
PCIE_85D
PCIE_PCH_RX
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D CLK_PCIE_90D C LK _P CI E_ 90 D
C LK _P CI E
CLK_PCIE_90D
CLK_PCIE
PCIE_CLK100M_AP_P
16 32
CLK_PCIE_90D
CLK_PCIE
PCIE_CLK100M_AP_N
16 32
CLK_PCIE_90D
CLK_PCIE
PCIE_CLK100M_FW_P
16 38
CLK_PCIE_90D
CLK_PCIE
PCIE_CLK100M_FW_N
16 38
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
PCIE_CLK100M_EXCARD_N
8 16
CPU_COMP
PCH_VSS_NCTF<1>
6
PCH_VSS_NCTF<2>
6
PEG_CLK100M_P
8 16
CLK_PCIE
PEG_CLK100M_N
8 16
IE CLK_PC
PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N
TABLE_SPACING_RULE_ITEM
?
=3x_DIELECTRIC
PCIE_85D
PCIE_85D PCIE_AP_R2D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PCIE_T29_2OTHER
PCIE_AP_D2R
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
P CI E_ T2 9_ RX 2T X
PCIE_PCH_TX PCIE_PCH_TX
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
PCIE_85D PCIE_85D
SPACING_RULE_SET MCP_PE1_REFCLK
16 36 16 36
TABLE_SPACING_ASSIGNMENT_ITEM
*_T X
PCIE_T29_TX
*
PCIE_T29_TX2TX TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_T29_TX
*_R X *_
*
MCP_PE2_REFCLK
PCIE_T29_TX2RX TABLE_SPACING_ASSIGNMENT_ITEM
*_R X
PCIE_T29_RX
*
PCIE_T29_RX2RX TABLE_SPACING_ASSIGNMENT_ITEM
*_T X
PCIE_T29_RX
*
PCIE_T29_RX2TX
PCIE_CLK100M_EXCARD_P
8 16
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_T29_TX
*
*
PCIE_T29_2OTHER
I235
CPU_27P4S
I236
C P U _ 2 7 P 4 S
C P U _ CO M P
I237
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<5>
I238
CPU_27P4S
CPU_COMP
TP_PCH_VSS_NCTF<7>
I239
C P U _ 2 7 P 4 S
C P U _ CO M P
I240
C P U _ 2 7 P 4 S
C P U _ CO M P
I241
C P U _ 2 7 P 4 S
C P U _ CO M P
I242
CPU_27P4S
CPU_COMP
I243
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<12> PCH_VSS_NCTF<15>
I244
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<17>
I245
C P U _ 2 7 P 4 S
C P U _ CO M P
I246
CPU_27P4S
CPU_COMP
I247
C P U _ 2 7 P 4 S
I248
C P U _ 2 7 P 4 S
C P U _ CO M P
PCH_VSS_NCTF<22> PCH_VSS_NCTF<25>
6
I249
CPU_27P4S
CPU_COMP
PCH_VSS_NCTF<27>
6
I250
CPU_27P4S
CPU_COMP
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_T29_RX
*
*
PCIE_T29_2OTHER
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
A
System Clock Signal Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
CLK_SLOW_55S
*
=55_OHM_SE
=55_OHM_SE
= 5 5_ O HM _ SE
= 5 5_ O HM _ SE
=STANDARD
=STANDARD
*
=55_ OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
CLK_25M_55S
TABLE_SPACING_RULE_HEAD
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
WEIGHT
PCH_VSS_NCTF<9> PCH_VSS_NCTF<9> PCH_VSS_NCTF<11>
PCH_VSS_NCTF<19> PCH_VSS_NCTF<21>
C P U _ CO M P
PCH_VSS_NCTF<29>
6
6 81 6 81 6 6
SYNC_MASTER=K90I_MLB
6
PCH Constraints 2
6
DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY:
6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
*
=2x_DIELECTRIC
?
*
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
CLK_25M
8
NOTE: 25MHz system clocks very sensitive to noise.
7
6
5
4
SIZE
6
TABLE_SPACING_RULE_ITEM
CLK_SLOW
SYNC_DATE=02/15/2011
PAGE TITLE
6
3
2
051-9058 6.0.0
REVISION
D
BRANCH
PAGE
103 OF 109 SHEET
81 OF 86
1
A
8
7
6
5
4
2
3
1
Ethernet Net Properties
CAESAR IV (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE PHYSICAL
ELECTRICAL_CONSTRAINT_SET
SPACING
TABLE_PHYSICAL_RULE_ITEM
ENET_50S
ENET_3X
ENET_50S
ENET_3X
ENET_50S
ENET_3X
BCM5764_CLK25M_XTALI
ENET_100D
ENET_MDI
ENET_MDI_P<3..0>
36 37
ENET_100D
ENET_MDI
ENET_MDI_N<3..0>
36 37
BCM5764_CLK25M_XTALO
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT
ENET_RESET_L
30 36
TABLE_SPACING_RULE_ITEM
*
ENET_3X
?
=3:1_SPACING
ENET_MDI
SOURCE: Broadcom 5764-DS04-RDS Page 38 TABLE_SPACING_RULE_HEAD
D
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
WEIGHT
I166
CR_DATA
ENET_50S
ENET_CR_DATA
ENET_CR_DATA<7..0>
I167
CR_DATA
ENET_50S
ENET_CR_DATA
ENET_CR_CMD
I168
CR_CLK
ENET_50S
ENET_CR_DATA
ENET_CR_CLK
TABLE_SPACING_RULE_ITEM
*
ENET_CR_DATA
8MIL
?
CAESAR IV (Ethernet PHY) Constraints TABLE_PHYSICAL_RULE_HEAD
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_100D
*
=100_OHM_DIFF
= 1 00 _ OH M _D I FF
= 1 00 _ OH M _D I FF
= 1 00 _ OH M _D I FF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
D
I169
CR_DATA
ENET_CR_DATA
SDCONN_DATA<7..0>
30 36
I170
CR_DATA
ENET_50S
ENET_CR_DATA
SDCONN_CMD
30 36
I171
CR_CLK
ENET_50S
ENET_CR_DATA
SDCONN_CLK
30 36
I172
CR_CLK
ENET_50S
ENET_CR_DATA
SDCONN_CLK_L
ENET_50S
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE
SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
*
ENET_MDI
?
0.6 MM
SOURCE: Broadcom 5764-DS04-RDS Page 38
C
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
C
FireWire Net Properties
FireWire Interface Constraints
NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FW_110D
*
SPACING_RULE_SET
LAYER
=110_OHM_DIF F
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
= 11 0_ OH M_ DI FF
= 11 0_ OH M_ DI FF
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE
SPACING
WEIGHT
I158
FW_P0_TPA
FW_110D
FW_P0_TPA_P
38 40
I159
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPA_N
38 40
I160
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB_P
38 40
I161
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB_N
38 40
I162
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA_P
38 40
I163
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA_N
38 40
I164
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB_P
38 40
I165
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB_N
38 40
TABLE_SPACING_RULE_ITEM
*
FW_TP
=3:1_SPACING
?
_TP FW
Port 2 Not Used
B
B
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
Ethernet/FW Constraints DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
051-9058 6.0.0
REVISION
SIZE
D
BRANCH
PAGE
104 OF 109 SHEET
82 OF 86
1
A
8
7
6
5
DisplayPort Signal Constraints
4
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
T29_I2C_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE
SPACING
WEIGHT
T 2 9D P _8 0 D
T 2 9D P
I2
T29_R2D0
T 2 9D P _8 0 D
T 2 9D P
I3
T29_R2D1
T 2 9D P _8 0 D
T 2 9D P
I4
T29_R2D1
T 2 9D P _8 0 D
T 2 9D P
I5
T 2 9D P _8 0 D
T 2 9D P
I7
T 2 9D P _8 0 D
T 2 9D P
T29DP_100D
T29DP
T29_I2C
*
=2x_DIELECTRIC
I6
?
T29 SPI Signal Constraints
T29_D2R0
I8
T29_D2R0
T29DP_100D
T29DP
I9
T29_D2R1
T29DP_100D
T29DP
I10
T29_D2R1
T29DP_100D
T29DP
I11
T29DP_100D
T29DP
I12
T29DP_100D
T29DP
I13
T29DP_80D
T29DP
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
T29_SPI_55S
*
=55_OHM_SE
SPACING_RULE_SET
LAYER
LINE-TO-LINE
=55 _OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD I15
TABLE_SPACING_RULE_HEAD
SPACING
WEIGHT
I14
TABLE_SPACING_RULE_ITEM
*
T29_SPI
I17
?
=2x_DIELECTRIC
T29/DP Connector Signal Constraints LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
*
T29DP_80D
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
T 2 9D P _8 0 D
T 2 9D P
I18
DP_SDRVA_ML_EVEN
T29DP_80D
T29DP
I19
DP_SDRVA_ML_ODD
T29DP_80D
T29DP
I20
DP_SDRVA_ML_ODD
T29DP_80D
T29DP T 2 9D P
I21
DP_SDRVA_AUXCH
T 2 9D P _8 0 D
I22
DP_SDRVA_AUXCH
T 2 9D P _8 0 D
T 2 9D P
I23
T 2 9D P _8 0 D
T 2 9D P
I24
T29DP_80D
T29DP
I25
T29DP_80D
T29DP
I26
T29DP_80D
T29DP
I27
T 2 9D P _8 0 D
T 2 9D P
I28
T 2 9D P _8 0 D
T 2 9D P
I30
T29DP_80D
T29DP
I29
T29DP_80D
T29DP
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE
WEIGHT
SPACING
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
T29DP
=5x_DIELECTRIC
*
?
T29DP
TOP,BOTTOM
=7x_DIELECTRIC
?
SOURCE: Bill Cornelius’s T29 Routing Notes
T29_R2D2
T29DP_80D
T29_R2D2 T29_R2D3
T29DP_80D
T29DP
I34
T29DP_80D
T29DP
I33
T29_R2D3
T29DP_80D
T29DP
I31 I32
C
T29DP_80D
T29DP
I36
T29DP_80D
T29DP
T29_D2R2
T29DP_100D
T29DP
T 29 _D 2R 2
T 29 DP _1 00 D
T 29 _D 2R 3 T29_D2R3
T 29 DP _1 00 D T29DP_100D
T29DP T29DP
I41
T29DP_100D
T29DP
I42
T29DP_100D
T29DP
I43
T 2 9D P _8 0 D
T 2 9D P
I44
T 2 9D P _8 0 D
T 2 9D P
I46
T 2 9D P _8 0 D
T 2 9D P
I45
T 2 9D P _8 0 D
T 2 9D P
I39 I38 I40
NET_TYPE ELECTRICAL_CONSTRAINT_SET
DP_SDRVB_ML_EVEN
T29DP_80D
T29DP
I48
DP_SDRVB_ML_EVEN
T29DP_80D
T29DP
DP_SDRVB_ML_ODD DP_SDRVB_ML_ODD
T29DP_80D
I50
T29DP_80D
T29DP
I51
DP_SDRVB_AUXCH
T29DP_80D
T29DP
I52
DP_SDRVB_AUXCH
T29DP_80D
D P_ P PC C H_ TX
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML
DP P_ _ 85 D DP_ _8 85 5D D
D P_ P PC C H_ TX D P_ P PC C H_ TX
I64
DP_T29SNK0_ML
DP_ _8 85 5D D
D P_ P PC C H_ TX
I65
DP P_ _ 85 D
D P_ PC H
I66
DP P_ _ 85 D
D P_ PC H
DP_T29SNK0_ML_C_N<3..0> DP_T29SNK0_ML_P<3..0> DP_T29SNK0_ML_N<3..0> DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N
DP P_ _ 85 D
I61
I67
DP_T29SNK0_AUXCH
DP P_ _ 85 D
D P_ PC H
I68
DP_T29SNK0_AUXCH
DP P_ _ 85 D
D P_ PC H
I69
DP P_ _ 85 D
D P_ P PC C H_ TX
I70
DP_85D
DP_PCH_TX
I71
DP_T29SNK1_ML
DP_85D
DP_PCH_TX
I72
DP_T29SNK1_ML
DP_ _8 85 5D D
D P_ P PC C H_ TX
I74
DP P_ _ 85 D
D P_ PC H
I73
DP P_ _ 85 D
D P_ PC H
DP P_ _ 85 D
D P_ PC H
DP_85D
DP_PCH
I77
DP_85D
DISPLAYPORT
I78
DP_85D
DISPLAYPORT
I79
DP_85D
DISPLAYPORT
I80
DP_85D
DISPLAYPORT
I75
DP_T29SNK1_AUXCH
I76
DP_T29SNK1_AUXCH
I81 I82
T29_I2C_55S
T29_I2C
T29_I2C_55S
T29_I2C
T29_SPI_55S
T29_SPI
DP_T29SNK1_ML_C_P<3..0> DP_T29SNK1_ML_C_N<3..0> DP_T29SNK1_ML_P<3..0> DP_T29SNK1_ML_N<3..0> DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N
T29DP
I53
T29DP_80D
T29DP
I54
T29DP_80D
T29DP
I55
T29DP_80D
T29DP
I56
T29DP_80D
T29DP
I57
T29DP_80D
T29DP
I58
T29DP_80D
T29DP
I59
T 2 9D P _8 0 D
T 2 9D P
I60
T 2 9D P _8 0 D
T 2 9D P
I2C_T29_SCL I2C_T29_SDA
T29_SPI_MOSI
T29_SPI_55S
T29_SPI
I85
T29_SPI_MISO
I86
T29_SPI_CS_L
T29_SPI_55S T29_SPI_55S
T29_SPI T29_SPI
T29_SPI_MISO T29_SPI_CS_L
I87
T29DP_80D
T29DP
I88
T29DP_80D
T29DP
I89
T29DP_100D
T29DP
I90
T29DP_100D
T29DP
T29_R2D_C_P<3..0> T29_R2D_C_N<3..0> T29_D2R_P<3..0> T29_D2R_N<3..0>
T29_SPI_CLK
I84
8
DP_SDRVA_ML_C_P<3..0> DP_SDRVA_ML_C_N<3..0> DP_SDRVA_ML_R_P<3..0> DP_SDRVA_ML_R_N<3..0> DP_SDRVA_ML_P<2..0:2> DP_SDRVA_ML_N<2..0:2> DP_SDRVA_ML_P<3..1:2> DP_SDRVA_ML_N<3..1:2> DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N T29DPA_ML_P<3..0> T29DPA_ML_N<3..0> T29DPA_ML_C_P<3..0> T29DPA_ML_C_N<3..0> DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N
75 75 75 75
75 76
D
75 76 75 76 75 76 76 76
75 75 75 75 75 83 75 83 75 75 75 75 75 75
75 76 75 76 75 76 75 76 75 76 75 76
T29_R2D_P<2> T29_R2D_N<2> T29_R2D_P<3> T29_R2D_N<3> T29_R2D_C_F_P<3..2> T29_R2D_C_F_N<3..2> T29_D2R_C_P<2> T29_D2R_C_N<2>
C
T29_D2R_C_P<3> T29_D2R_C_N<3> T29DPB_D2R3_AUXCH_P T29DPB_D2R3_AUXCH_N DP_SDRVB_ML_C_P<3..0> DP_SDRVB_ML_C_N<3..0> DP_SDRVB_ML_R_P<3..0> DP_SDRVB_ML_R_N<3..0> DP_SDRVB_ML_P<2..0:2> DP_SDRVB_ML_N<2..0:2> DP_SDRVB_ML_P<3..1:2> DP_SDRVB_ML_N<3..1:2> DP_SDRVB_AUXCH_P DP_SDRVB_AUXCH_N DP_SDRVB_AUXCH_C_P DP_SDRVB_AUXCH_C_N
Only used on dual-port hosts. 83 83
T29DPB_ML_P<3..0> T29DPB_ML_N<3..0> T29DPB_ML_C_P<3..0> T29DPB_ML_C_N<3..0> DP_B_EXT_AUXCH_P DP_B_EXT_AUXCH_N
B
8 33 8 33 33 33
8 33 8 33 33 33
8 33 8 33 33 33
8 33 8 33 33 33
DP_T29SRC_ML_C_P<3..0> DP_T29SRC_ML_C_N<3..0> DP_T29SRC_AUXCH_C_P DP_T29SRC_AUXCH_C_N
T29_SPI_CLK T29_SPI_MOSI
I83
T29DP
T29_R2D_P<0> T29_R2D_N<0> T29_R2D_P<1> T29_R2D_N<1> T29_R2D_C_F_P<1..0> T29_R2D_C_F_N<1..0> T29_D2R_C_P<0> T29_D2R_C_N<0> T29_D2R_C_P<1> T29_D2R_C_N<1> T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N
SPACING
I63
I62
A
PHYSICAL
T29DP
I47
I49
T29 IC Net Properties
T29DP
I35
I37
B
T29DP T29DP T29DP
DP_SDRVA_ML_EVEN
TABLE_PHYSICAL_RULE_ITEM
T29DP_100D
T29DP_80D T29DP_80D T29DP_80D
I16
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
SPACING
T29_R2D0
TABLE_SPACING_RULE_ITEM
D
PHYSICAL
I1
TABLE_PHYSICAL_RULE_ITEM
LAYER
1
NET_TYPE ELECTRICAL_CONSTRAINT_SET
T29 I2C Signal Constraints
SPACING_RULE_SET
2
3
T29/DP Net Properties
7
Only used on hosts supporting T29 video-in
33 48
SYNC_MASTER=K90I_MLB 33 48
SYNC_DATE=02/15/2011
PAGE TITLE
T29 Constraints
33
DRAWING NUMBER
SIZE
33
Apple Inc.
33 33
R
NOTICE OF PROPRIETARY PROPERTY: 8 33 75
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8 33 75 8 33 75 8 33 75
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REVISION
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83 OF 86
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8
7
6
5
4
2
3
1
SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
*
=STANDARD
=STANDARD
= ST AN DA RD
= ST AN DA RD
0.1 MM
0.1 MM
NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
1TO1_DIFFPAIR
D
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_A_S3_SCL
SMB_50S
SMB
SMBUS_SMC_A_S3_SDA
SMB_50S
SMB
SMBUS_SMC_2_S3_SDA
6 45 48
SMBUS_SMC_B_S0_SCL
SMB_50S
SMB
SMBUS_SMC_1_S0_SCL
45 48
SMBUS_SMC_B_S0_SDA
SMB_50S
SMB
SMBUS_SMC_1_S0_SDA
45 48
SMBUS_SMC_0_S0_SCL
SMB_50S
SMB
SMBUS_SMC_0_S0_SCL
45 48
SMBUS_SMC_0_S0_SDA
SMB_50S
SMB
SMBUS_SMC_0_S0_SDA
45 48
SMBUS_SMC_BSA_SCL
SMB_50S
SMBUS_SMC_BSA_SDA
6 45 48
SMB
SMBUS_SMC_5_G3_SCL
6 45 48
SMB_50S
SMB
SMBUS_SMC_5_G3_SDA
6 45 48
S MB U S _S M C _M G M T_ S CL
S MB _ 5 0S
SMB
SMBUS_SMC_3_SCL
45 48
S MB U S _S M C _M G M T_ S DA
S MB _ 5 0S
SMB
SMBUS_SMC_3_SDA
45 48
D
SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
CHGR_CSO
SPACING
CHGR_CSI_P
64
1TO1_DIFFPAIR
CHGR_CSI_N
64
1TO1_DIFFPAIR
CHGR_CSO_P
64
1TO1_DIFFPAIR
CHGR_CSO_N
64
1TO1_DIFFPAIR
C
C
B
B
A
S YN C_ MA ST ER =K 90 I_ ML B
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
SMC Constraints DRAWING NUMBER
Apple Inc. R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
8
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REVISION
SIZE
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PAGE
106 OF 109 SHEET
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1
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6
5 TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
= 55 _O HM _S E
=55_OHM_SE
=1:1_DIFFPAIR
DIFFPAIR NECK GAP
=1:1_DIFFPAIR
4
2
3
J30 Specific Net Properties
1
J30 Specific Net Properties NET_TYPE
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
SENSE_1TO1_55S
*
=1:1_DIFFPAIR
=55_OHM_SE
THERM_1TO1_55S
*
=1:1_DIFFPAIR
= 55 _O HM _S E
ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM
PHYSICAL
SPACING
ELECTRICAL_CONSTRAINT_SET
E NE T_ 10 0D
E NE TC ON N
ENETCONN_P<3..0>
37
ENET_100D
ENETCONN
ENETCONN_N<3..0>
37
SATA_90D
SATA_PCH_RX
SATA_ODD_D2R_C_P
6 41
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
=1:1_DIFFPAIR
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
SATA_PCH_RX
SATA_ODD_D2R_C_N
6 41
S A TA 3 _P C H_ R X
SATA_HDD_D2R_RDROUT_P
41
S A TA _ 9 0 D
S A TA 3 _P C H_ R X
SATA_HDD_D2R_RDROUT_N
41
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_RDRIN_P
41
S A TA _ 9 0 D
S A TA 3 _P C H_ T X
I295
S A TA _ 9 0 D
S A TA 3 _P C H_ T X
SATA_HDD_D2R_RDRIN_P
41
I298
S A TA _ 9 0 D
S A TA 3 _P C H_ T X
SATA_HDD_D2R_RDRIN_N
41
I297
S A TA _ 9 0 D
S A TA 3 _P C H_ T X
SATA_HDD_R2D_RDROUT_P
41
I296
S A TA _ 9 0 D
S A TA 3 _P C H_ T X
SEN SE_ DIF FPA IR
THE RM_ 1TO 1_5 5S
THERM
THMSNS_D1_P
51
THERM_1TO1_55S
THERM
THMSNS_D1_N
51
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
THMSNS_D2_P
51
THERM_1TO1_55S
THERM
THMSNS_D2_N
51
SATA_90D S A TA _ 9 0 D
PCIE_CLK100M_AP TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
D
SENSE
=2:1_ SPACING
*
CPU_COMP
GND
? TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
THERM
*
=2:1_ SPACING
?
AUDIO
*
=2:1_ SPACING
?
CPU_VCCSENSE
GND
GND_P2MM
*
CLK_PCIE_90D
CLK_PCIE
C LK _P CI E_ 90 D
C LK _P CI E
TABLE_SPACING_RULE_ITEM
SATA_HDD_R2D_RDRIN_N
SATA_HDD_R2D_RDROUT_N
PCIE_CLK100M_AP_CONN_P
6 32
PCIE_CLK100M_AP_CONN_N
6 32
1TO1_DIFFPAIR
CHGR_CSI_R_P CHGR_CSI_R_N
64
1TO1_DIFFPAIR
CHGR_CSO_R_P
64
1TO1_DIFFPAIR
GND_P2MM
*
41
CHGR_CSO_R_N
1TO1_DIFFPAIR
64
D
64
41
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
ENETCONN
25 MILS
*
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
ENET_MDI
GND
*
SPACING_RULE_SET
I287 I288
? TABLE_SPACING_ASSIGNMENT_ITEM
SEN SE_ DIF FPA IR
THE RM_ 1TO 1_5 5S
THERM
T29_THERMD_P
51
THERM_1TO1_55S
THERM
T29_THERMD_N
51
GND_P2MM
TABLE_SPACING_RULE_HEAD
LAYER
SPACING_RULE_SET
LINE-TO-LINE
SPACING
WEIGHT
SEN SE_ DIF FPA IR
TABLE_SPACING_RULE_ITEM
GND
=STANDARD
*
TABLE_SPACING_ASSIGNMENT_HEAD
?
NET_SPACING_TYPE1
NET_SPACING_TYPE2
GND
CLK_PCIE
AREA_TYPE
SPACING_RULE_SET
*
GND_P2MM
THE RM_ 1TO 1_5 5S
THERM
T29THMSNS_D2_P
THERM_1TO1_55S
THERM
T29THMSNS_D2_N
SEN SE_ 1TO 1_5 5S
SENSE
SENSE_1TO1_55S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
GND
PCIE*
*
GND
SATA*
*
SEN SE_ DIF FPA IR
LINE-TO-LINE
SPACING
ISNS_HS_COMPUTING_N
50
SENSE
ISNS_HS_COMPUTING_P
50
SENSE_1TO1_55S
SENSE
ISNS_HS_OTHER_N
50
SENSE_1TO1_55S
SENSE
ISNS_HS_OTHER_P
50
SPKRAMP_L_P_OUT
6 60 61
SEN SE_ 1TO 1_5 5S
SENSE
CPUVCCIOS0_CS_N
49 70
SPK_OUT
DIFFPAIR
AUDIO
SPKRAMP_L_N_OUT
6 60 61
SENSE_1TO1_55S
SENSE
CPUVCCIOS0_CS_P
49 70
SPK_OUT
DIFFPAIR
AUDIO
SPKRAMP_SUB_P_OUT
SPK_OUT
DIFFPAIR
AUDIO
GND_P2MM
TABLE_SPACING_RULE_HEAD
LAYER
SPACING_RULE_SET
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
GND_P2MM
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
GND_P2MM
*
0.20 MM
TABLE_SPACING_ASSIGNMENT_ITEM
1000 GND
USB*
GND_P2MM
*
TABLE_SPACING_RULE_ITEM
PWR_P2MM
0.20 MM
*
SEN SE_ DIF FPA IR
SPK_OUT
SB_POWER
CLK_PCIE
*
PWR_P2MM
SB_POWER
SATA*
*
PWR_P2MM
SB_POWER
SATA*
*
PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CLK
GND
*
DIFFPAIR
AUDIO
TABLE_SPACING_ASSIGNMENT_ITEM
1000
SPACING_RULE_SET
SPK_OUT
DIFFPAIR
AUDIO
SPK_OUT
DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
6 60 61
SPKRAMP_SUB_N_OUT
6 60 61
SPKRAMP_R_P_OUT
6 60 61
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
SEN SE_ 1TO 1_5 5S
SEN SE
CPUIMVP_ISNS1_P
49 68 69
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1_N
49 69
I299
SEN SE_ 1TO 1_5 5S
SENSE
CPUIMVP_ISNS2_P
SEN SE_ 1TO 1_5 5S
SEN SE
GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
GND
MEM_CTRL
GND
MEM_DATA
GND
GND_P2MM
*
SEN SE_ DIF FPA IR TABLE_SPACING_ASSIGNMENT_ITEM
C
*
GND_P2MM
*
GND_P2MM
SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
GND
*
TABLE_SPACING_ASSIGNMENT_ITEM
GND_P2MM GND
LVDS*
*
GND_P2MM
I317
S EN SE _D IF FP AI R
I318 SENSE_DIFFPAIR
SEN SE_ DIF FPA IR
I322
SENSE_DIFFPAIR
I321 SENSE_DIFFPAIR
I249
SENSE_DIFFPAIR
I250 I252
I253
PHYSICAL_RULE_SET
LAYER
MEM_40S OVER RIDE
OVERRI DE
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
OV OVERRI DE
O VERRID E
0.09 MM OVE RRIDE
400 MIL OVE RRIDE
OVE RRIDE
OVER RIDE
I256
I300
SSM2315_SUB_P
49 69
I302
CPUIMVP_ISNS1G_P
49 69
I301
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
CPUIMVP_ISNS1G_N
49 69
I304
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
SSM2315_R_N
60
S EN SE _1 TO 1_ 55 S
S EN SE
CPUIMVP_ISNS2G_P
49 69
I303
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
SSM2315_R_P
60
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS2G_N
49 69
I305
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_LO2_N_R
57 60
CPUIMVP_ISUM_R_P
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
SENSE_1TO1_55S
SENSE
49
I307
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUM_R_N
49
I306
SEN SE_ 1TO 1_5 5S
SENSE
CPUIMVP_ISUMG_R_P
49
I310
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUMG_R_N
49
I308
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNSG_P
49
I309
SEN SE_ 1TO 1_5 5S
SEN SE
CPUIMVP_ISNSG_N
49
I311
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS_P
49
I312
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS_N
49
I313
SENSE_1TO1_55S
SENSE
VCCSAS0_CS_P
65
I314
SENSE_1TO1_55S
SENSE
VCCSAS0_CS_N
65
I315
I281
*
MEM_72D OVER RIDE
OVERRI DE
OV OVERRI DE
0.09 MM OVE RRIDE
O VERRID E
400 MIL OVE RRIDE
OVER RIDE
I283
*
OVERRI DE
OV OVERRI DE
0.09 MM OVE RRIDE
400 MIL OVE RRIDE
OVE RRIDE
OVER RIDE
0.09 MM OVE RRIDE
400 MIL OVE RRIDE
OVE RRIDE
OVER RIDE
57 60
AUD_LO1_N_R
57 60
AUD_LO1_P_R
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
SPKRAMP_INL_P
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
SPKRAMP_INL_N
60
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
SPKRAMP_INR_P
60
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
SPKRAMP_INR_N
SPKRAMP_INSUB_P SPKRAMP_INSUB_N
AUDIO
USB_85D
USB USB
SENSE_DIFFPAIR
57 60
AUDIO AUDIO
USB_85D
USB_TPAD_R_P USB_TPAD_R_N
S EN SE
ISNS_5V_S0_HDD_N
49
SENSE
ISNS_5V_S0_HDD_P
49
SB_POWER
SENSE_1TO1_55S
SENSE
ISNS_5V_S0_HDD_R_N
49
SB_POWER
SEN SE_ 1TO 1_5 5S
SEN SE
ISNS_5V_S0_HDD_R_P
49
SB_POWER
SEN SE_ 1TO 1_5 5S
SEN SE
ISNS_LCDBKLT_N
SEN SE_ 1TO 1_5 5S
SEN SE
ISNS_LCDBKLT_P
SENSE_1TO1_55S
57 60
AUD_LO2_P_L
1TO1_DIFFPAIR
1TO1_DIFFPAIR
8 9
S EN SE _1 TO 1_ 55 S
57 60
AUD_LO2_N_L
AUD_DIFF AUD_DIFF
8 9
I284
O VERRID E
O VERRID E
AUD_LO2_P_R
AUDIO AUDIO
68 69
SENSE_DIFFPAIR
C
1TO1_DIFFPAIR
CPU_THERMD_P
S EN SE _D IF FP AI R
60
1TO1_DIFFPAIR
CPUIMVP_ISUMG_N
I316
60
SSM2315_L_P
AUD_DIFF
CPU_THERMD_N
SEN SE
SSM2315_L_N
AUD_DIFF
S EN SE
TABLE_PHYSICAL_RULE_ITEM
MEM_37S OVER RIDE
AUDIO AUDIO
SEN SE
I282
OVE RRIDE
CPUIMVP_ISUMG_P
1TO1_DIFFPAIR 1TO1_DIFFPAIR
SEN SE_ 1TO 1_5 5S SEN SE_ 1TO 1_5 5S
SEN SE
AUD_DIFF AUD_DIFF
SEN SE_ 1TO 1_5 5S
I255
60
49 68 69
CPUIMVP_ISNS2_N
S EN SE _1 TO 1_ 55 S
TABLE_PHYSICAL_RULE_ITEM
60
SENSE
TABLE_PHYSICAL_RULE_ITEM
*
SSM2315_SUB_N
SEN SE
SENSE_DIFFPAIR
I254
SENSE_1TO1_55S
S EN SE _D IF FP AI R
I251
TABLE_PHYSICAL_RULE_HEAD
6 60 61
SEN SE_ 1TO 1_5 5S
TABLE_SPACING_ASSIGNMENT_ITEM
SPKRAMP_R_N_OUT
PP3V3_S5
60
60 60 60
53 53
6 7
PP3V3_S0
6 7
PP1V5_S3RS0
6 7
GND
GND
TABLE_PHYSICAL_RULE_ITEM
B
MEM_85D OVER RIDE
*
OVERRI DE
OV OVERRI DE
TABLE_PHYSICAL_RULE_ITEM
*
PCIE_85D OVER RIDE
OVERRI DE
USB_85D OVER RIDE
TOP OVERRI DE
C PU _2 7P 4S OVER RIDE
T OP OVERRI DE
CLK_PCIE_90D OVER RIDE
TOP OVERRI DE
O VERRID E
0.076 MM OVE RRIDE
10 mm OVE RRIDE
OV OVERRI DE
O VERRID E
0.1 MM OVE RRIDE
500 MIL OVE RRIDE
OVE RRIDE
OVER RIDE
OV OVERRI DE
O VERRID E
0.09 MM OVE RRIDE
400 MIL OVE RRIDE
OVE RRIDE
OVER RIDE
O VERRID E
0.09 MM OVE RRIDE
400 MIL OVE RRIDE
OVE RRIDE
OVER RIDE
OV OVERRI DE
SENSE
ISNS_1V5_S3_DDR_P
49
SENSE_1TO1_55S
SENSE
ISNS_1V5_S3_DDR_N
49
SEN SE_ 1TO 1_5 5S
SEN SE
ISNS_1V5_S3_DDR_R_P
49
SENSE_1TO1_55S
SENSE
ISNS_1V5_S3_DDR_R_N
49
I293
LVDS_90D
LVDS_PCH_TX
LVDS_CONN_A_CLK_F_N
6 74
I294
LVDS_90D
LVDS_PCH_TX
LVDS_CONN_A_CLK_F_P
6 74
I292
SENSE_DIFFPAIR
I291
OVE RRIDE
OVER RIDE TABLE_PHYSICAL_RULE_ITEM
I319 I320
SENSE_DIFFPAIR
SENSE_1TO1_55S
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
A
OV OVERRI DE
Memory Constraint Relaxations
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
Project Specific Constraints
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE ON LAYER?
PHYSICAL_RULE_SET
LAYER
MEM_72D
BOTTOM
0.127 MM
6.35 MM
MEM_85D
TOP
0.1 MM
6.35 MM
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DRAWING NUMBER
DIFFPAIR NECK GAP
SIZE
TABLE_PHYSICAL_RULE_ITEM
Apple Inc. TABLE_PHYSICAL_RULE_ITEM
R
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
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REVISION
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K90i Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS (MIL or MM)
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
ALLEGRO VERSION 16.2
TABLE_PHYSICAL_RULE_HEAD
LAYER
PHYSICAL_RULE_SET
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH =50_OHM_SE
10 MM
0 MM
0 MM
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
DEFAULT
*
Y
=50_OHM_SE
STANDARD
*
Y
=DEFAULT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE
SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
*
*
AREA_TYPE
SPACING_RULE_SET
BGA
BGA_P1MM
*
BGA
BGA_P2MM
*
BGA
BGA_P2MM
BGA
BGA_P2MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
DEFAULT
*
0.1 MM
TABLE_SPACING_ASSIGNMENT_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
D
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM NECK WIDTH
MINIMUM LINE WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
STANDARD
=DEFAULT
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
?
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
50_OHM_SE
TOP,BOTTOM
Y
0.110 MM
0.090 MM
50_OHM_SE
*
Y
0.080 MM
0.080 MM
TABLE_PHYSICAL_RULE_ITEM
BGA_P1MM
*
=DEFAULT
?
TABLE_PHYSICAL_RULE_ITEM
BGA_P2MM
*
=DEFAULT
?
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
TABLE_SPACING_RULE_ITEM
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.165 MM
40_OHM_SE
ISL10
N
0.126 MM
0.126 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
LAYER
SPACING_RULE_SET
*
2:1_SPACING
*
LINE-TO-LINE
SPACING
WEIGHT
0.15 MM
?
0.2 MM
?
ISL3,ISL4,ISL9
0.126 MM
Y
0.126 MM
=STANDARD
=STANDARD
=STANDARD
*
=STANDARD
N
=STANDARD
=STANDARD
=STANDARD
2.5:1_SPACING
SPACING
WEIGHT TABLE_SPACING_RULE_ITEM
*
0.140 MM
?
*
0.210 MM
?
0.25 MM
*
4X_DIELECTRIC
*
0.280 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
? TABLE_SPACING_RULE_ITEM
3:1_SPACING
=STANDARD
LINE-TO-LINE
2X_DIELECTRIC 3X_DIELECTRIC TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
LAYER
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
1.5:1_SPACING TABLE_PHYSICAL_RULE_ITEM
*
TABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
*
0.3 MM
TABLE_SPACING_RULE_ITEM
5X_DIELECTRIC
?
0.350 MM
*
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
37_OHM_SE
TOP,BOTTOM
Y
0.190 MM
0.1 MM
37_OHM_SE
ISL10
N
0.145 MM
0.1 MM
D
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_SLOW
=STANDARD
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
4:1_SPACING
*
0.4 MM
TABLE_SPACING_RULE_ITEM
?
6X_DIELECTRIC
*
0.420 MM
7X_DIELECTRIC
*
0.490 MM
? TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
?
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
37_OHM_SE
ISL3,ISL4,ISL9
Y
0.145 MM
0.1 MM
=STANDARD
=STANDARD
=STANDARD
37_OHM_SE
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.2 MM
27P4_OHM_SE
*
Y
0.235 MM
0.2 MM
=STANDARD
= ST AN DA RD
= ST AN DA RD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
C
C
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
TOP,BOTTOM
Y
0.090 MM
0.090 MM
55_OHM_SE
*
Y
0.070 MM
0.070 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
72_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
= ST AN DA RD
= ST AN DA RD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
*
Y
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
1:1_DIFFPAIR
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
ISL3,ISL4,ISL9
Y
72_OHM_DIFF
ISL10
N
0.140MM
72_OHM_DIFF
TOP,BOTTOM
Y
0.175 MM
0.175 MM
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
*
N
=STANDARD
=STANDARD
72_OHM_DIFF
0.140 MM
0.140 MM
0.190 MM
0.190 MM
0.190 MM
0.190 MM
0.200 MM
0.200 MM
TABLE_PHYSICAL_RULE_ITEM
0.140 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
85_DIFF_BGA
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
= 8 5_OH M _DI F F
=8 5 _OHM _ DIF F
TABLE_PHYSICAL_RULE_ITEM
85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
85_OHM_DIFF
ISL3,ISL4
0.101 MM
Y
0.1 MM
0.170 MM
TABLE_PHYSICAL_RULE_ITEM
85_DIFF_BGA
0.170 MM
ISL3,ISL4
0.075 MM
Y
0.075 MM
0.12 5 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
85_DIFF_BGA
85_OHM_DIFF
ISL9,ISL10
Y
0.101 MM
0.1 MM
0.170 MM
0 . 170 MM
85_OHM_DIFF
TOP,BOTTOM
Y
0.125 MM
0.1 MM
0.190 MM
0 . 190 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
ISL9,ISL10
0.075 MM
Y
0.075 MM
0.12 5 MM
0.125 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner
layers.
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
90_DIFF_BGA
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
90_DIFF_BGA
ISL3,ISL4
Y
0.075 MM
90_DIFF_BGA
ISL9,ISL10
Y
0.075 MM
TABLE_PHYSICAL_RULE_ITEM
B
TABLE_PHYSICAL_RULE_ITEM
=90_OHM_DIFF
=90_OHM_DIFF
0.075 MM
0.125 MM
0.125 MM
0.075 MM
0.125 MM
0.125 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=1 0 0 _ O H M_ D I F F
= 1 00 _ O H M_DI FF
0.12 5 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
ISL3,ISL4
0.091 MM
Y
0.091 MM
0.180 MM
0 . 180 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
ISL9,ISL10
0.091 MM
Y
0.091 MM
0.180 MM
0 . 180 MM
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
TOP,BOTTOM
Y
0.111 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
100_OHM_DIFF
*
N
0.111 MM
0.200 MM
0 . 200 MM
NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner
layers.
TABLE_PHYSICAL_RULE_HEAD
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
100_DIFF_BGA
*
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
Y
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
= 10 0_ OH M_ DI FF
= 10 0_ OH M_ DI FF
= 10 0_ OH M_ DI FF
0.075 MM
0.075 MM
MINIMUM LINE WIDTH
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
ISL3,ISL4
Y
0.076 MM
0.076 MM
0.250 MM
0.250 MM
T ABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
ISL9,ISL10
Y
0.076 MM
0.076 MM
0.250 MM
100_DIFF_BGA
0.250 MM
ISL9,ISL10
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
TOP,BOTTOM
0.085 MM
Y
0.085 MM
0.200 MM
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
0.200 MM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
=STANDARD
=STANDARD
=STANDARD
0.068 MM
0.068 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
0.250 MM
0.250 MM
Y
0.068 MM
0.068 MM
0.250 MM
0.250 MM
Y
0.081 MM
0.081 MM
0.250 MM
0.250 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
110_OHM_DIFF
*
110_OHM_DIFF
ISL3,ISL4
110_OHM_DIFF
ISL9,ISL10
110_OHM_DIFF
TOP,BOTTOM
N
TABLE_PHYSICAL_RULE_ITEM
Y
NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers. TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
NOTE: These are Intel recommended impedances for PEG, unused on K90i. TABLE_PHYSICAL_RULE_HEAD
A
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
48_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.165 MM
MAXIMUM NECK LENGTH
TABLE_PHYSICAL_RULE_ITEM
S YN C_ MA ST ER =K 90 I_ ML B
48_OHM_SE
*
Y
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
80_OHM_DIFF
*
N
0.090 MM
0.090 MM
PCB Rule Definitions
=STANDARD
=STANDARD
=STANDARD
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
S YN C_ DA TE =0 2/ 15 /2 01 1
PAGE TITLE
TABLE_PHYSICAL_RULE_ITEM
DRAWING NUMBER
SIZE
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
R TABLE_PHYSICAL_RULE_ITEM
80_OHM_DIFF
ISL3,ISL4
Y
80_OHM_DIFF
ISL9,ISL10
Y
8 0 _O H M_ D IF F
T O P, B OT T OM
0.115 MM
0.115 MM
0.115 MM
0.115 MM
0.140 MM
0.140 MM
0.180 MM
0.180 MM
0.180 MM
0.180 MM
0.190 MM
0.190 MM
NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
8
Y
7
6
5
4
3
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REVISION
D
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109 OF 109 SHEET
86 OF 86
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