AXI Compliant DDR3 Controller
Content
2010 Second International Conference on Computer Modeling and Simulation
AXI Compliant DDR3 Controller
Vikky Lakhmani, M.Tech(Sequential) Student
Department of Electrical & Electronics Engineering,
Uttar Pradesh Technical University,
Lucknow (Uttarpradesh), INDIA
Email: [email protected]
Nusrat Ali
Project Manager (VLSI Division),
HCL Technologies, Noida,INDIA
Email: [email protected]
Dr. Vijay Shankar Tripathi
Department of Electronics & Communication
Motilal Nehru National Institute of Technology,
(MNNIT), Allahabad (U.P), INDIA
Email: [email protected]
Abstract—This paper describes the implementation of AXI
compliant DDR3 memory controller. It discusses the overall
architecture of the DDR3 controller along with the detailed
design and operation of its individual sub blocks, the pipelining
implemented in the design to increase the design throughput. It
also discusses the advantage of DDR3 memories over DDR2
memories and the AXI protocol operation
Write Address
Write Response
AXI
Interface
Read Data
AXI
Interface
Storage
Control
Burst
Manager
Address
Control
AXI Access
Manager
INTRODUCTION
The AXI compliant DDR3 Controller permits access of
DDR3 memory through AXI Bus interface[1-4]. The DDR3
controller works as an important bridge between the AXI
host and DDR3 memory. It takes care of the DDR3
initialization and various timing requirements of the DDR3
memory. The DDR3 controller performs multiple schemes
to increases the effective memory throughput[3]. These
schemes include combining and reordering the Read/Write
commands. For attaining the maximum throughput from the
memory, It operates all the memory banks in parallel and
minimizes the effect of precharge/refresh and other DDR3
internal operations [2].
Power
Down
Control
Refresh
Control
Address
Control
Central
Bank
Manager
Bank
Manag
DDR3
Memory
Command
Control
Initialization
Control
AXI Compliant DDR3 Controller Architecture
The architecture of the design is shown in the fig.1. The
design consists of following blocks• AXI interface
• AXI access Manager
• DDR3 Controller
978-0-7695-3941-6/10 $26.00 © 2010 IEEE
DOI 10.1109/ICCMS.2010.291
AXI-IF
Read Address
Keywords- DDR3 memory, AXI Interface, AXI access
Manager, DDR2 memories, AXI protocol operation
I.
Control
Write Data
DDR3 Controller
Fig.1 AXI compliant DDR3 controller
A.
AXI Interface:
AXI-Interface block interacts with HOST
processor and AXI access manager. It is
responsible for accepting and interpreting the
AXI commands issued by the processor and
responding to Read / Write requests in AXI
protocol as requested by processor. It also
maintains an arbiter block which is responsible
for arbitrating between Read/Write commands.
Arbitration is required between the commands
387
391
burst. The AXI access manager combines the
command wherever possible to improve the
performance and passes the final command to
DDR3 controller. To insure maximum
throughput it pre-fetches the commands from
AXI interface converts into memory transactions
and maintains locally. These stored commands
are supplied to the DDR3 Controller whenever
DDR3 Controller is not busy in the very next
clock.
because of parallel/independent Read/Write
command received at the AXI interface.
It maintains asynchronous FIFO’s to store the
command and the data. The Read command gets
stored in (Read Command Block), Write
command gets stored in (Write Command
block), Read data gets stored in (Read Data
block), and Write data gets stored in (Write Data
Block). The stored commands are supplied to the
AXI access manager whenever AXI access
manager is free. Now since the storage can have
both Read and Write commands in the respective
block hence it maintains an arbiter which
arbitrates between Read/Write command and
whenever Burst Manager is free one of the
present command is supplied to the Burst
Manager.
Read Address Channel
Read
Command
Block
Write Address Channel
Write
Command
Block
Read Data Channel
Read Data
Block
Write Data Channel
Write Data
Block
Write Response Channel
The AXI-IF block interacts with the AXI
interface block and receives commands. The
received commands are stored in the Storage
control block. The Burst Manager converts the
AXI command into DDR3 burst. The address
control block is responsible for generation of
address. The overall operation of various blocks
in the AXI access manager is controlled by the
Control Logic. The fig.3 shows the AXI Access
Manager BlockControl Logic
AXI-IF
Arbiter Block
Storage Control
Burst
Manager
Address
Control
Fig.3 AXI Access Manager Block
Write
Response
Block
C. DDR3 Controller :
The main function of DDR3 controller is to interact
with the DDR3 memory. This is the heart of the
AXI compliant DDR3 controller and responsible
for understanding the DDR3 protocol and
communicating with the DDR3 memory [4]. DDR3
Controller also issues Refresh, Power down, Selfrefresh command along with the read or write
command as per the user configuration [1].
The internal blocks of DDR3 controller are shown
in the fig.4-
Fig.2 AXI Interface Block
B. AXI Access Manager:
The main function of the AXI-Access Manager
is to convert the AXI commands into memory
access commands for maximum utilization of the
DDR3 Band Width. The DDR3 memory takes
command only in burst 4 or 8 mode whereas the
AXI command could be a smaller or longer
392
388
Power Down
Control
Central Bank
Manager
Feature
Refresh Control
Data Rate
Burst
Length
No. of
Bank
Address
Control
Fig.4
Bank
Manager
II
400-800
Mbps
BL=4,8
4 banks
800-1600 Mbps
BL=4,8
15/15/15 ns
12/12/12 ns
Bidirectional
DQS
(single
ended
Default)
2.5+/- 0.2 V
Bi-directional
DQS
(Single/Diff.
Default)
Bi-directional DQS
(Differential
Default)
1.8+/- 0.1 V
1.5+/- 0.075 V
Reset
No
No
Yes
ODT
No
Yes
Yes
Vdd/Vddq
:
4
512Mb/1 Gb : 8
Banks
2 bits
DDR3 Controller Block
The Power Down Control Block takes care of
generating the power down command to the DDR3
memory whenever the host commands it to go to
Power saving mode. The refresh control block
takes care of refreshing the DDR3 memory as per
the user supplied configuration. The initialization
control blocks take care of initializing the DDR3
memory after reset. To control the timings of
individual DDR3 banks it contains Bank manager
which track the timing requirements for the
individual DDR3 banks. The address control block
is responsible for generating the address to the
DDR3 memory. The Command control block
interacts with the DDR3 memory and based on the
Bank manager inputs drives the DDR3 bus. It is
also responsible for receiving the data during the
Read operation. The Central Bank manager coordinates between the individual Bank Mangers
and maintains the overall timing requirement of
DDR3 memory.
200-400
Mbps
BL=2,4,8
DDR3
15/15/15 ns
CL/tRCD/
tRP
Source
sync.
Command
Control
DDR2
512Mb
Banks
1 Gb
Banks
4 bits
Prefetch
Initialization
Control
DDR
: 8
8 bits
Table 1: DDR3 feature Comparison
III
SIMULATION, TESTING & VERIFICATION
Verification is important part of complete design process. It
takes almost 60% of design process flow so to minimize
time to market in complete design we do verification
process in parallel with design process. The verification of
AXI compliant DDR3 controller is accomplished by
sending the AXI transaction through the AXI Bus
Functional Model. The response from the AXI compliant
DDR3 controller is received by the AXI Bus Functional
Model and is passed to the Checker. The checker also picks
the expected response from the Local memory and
compares it based on the comparison the environment prints
passed and failed messages and the associated data
mismatch if any. The verification environment for AXI
compliant DDR3 controller is shown in fig.5.
DDR FEATURES COMPARRISON:
DDR3
offers
a
substantial
performance
improvement over previous DDR2 & DDR
memory systems. New DDR3 features, all
transparently implemented in the memory
controller,
improve
the
signal
integrity
characteristics of DDR3 designs so that higher
performance is achieved without an undue burden
for the system designer. If proper consideration is
given to any new DDR2 memory design, it can be
a relatively easy upgrade to support DDR3 in the
next generation design.
393
389
DDR3
Controller
Design
AXI
BFM
Checker
DDR3
Memory
Pass/Fail
Local
Memor
Fig.5 Verification of DDR3
Controller
FIG6.2- BL8, RANDOM READ/WRITE
The AXI Bus Functional Model consists of generator, driver,
monitor and scoreboard. The generator generates AXI
transactions. Driver is used to drive the DUT (Device under
Test) here DUT is AXI interface. The AXI transaction is
also passed to the local memory which prepares the
expected response which is passed to the checker whenever
the checker asks for it. Upon receiving the response from
the DDR3 memory checker commands the local memory to
give back the stored expected response and compares the
DDR3 controller response with the expected response.
IV: SIMULATION RESULTS:
Fig6.3- AL0 , BL4
The below figures are showing snapshot of the DDR3
controller operation in various modes. The design has been
coded in “Verilog HDL” language. The functional
simulation tool used in IUS6.1 from Cadence.
Fig6.4- BL4 , AL0
V: CONCLUSION
The design has been verified by the exhaustive functional
verification. We examined the performance of the design by
generating different type of AXI commands and noting
down the time taken by the DDR3 controller in finishing
them. In most of the scenario the throughput of the design is
close to the theoretical max. The latency of the design is
between 10 to 35 clocks based on the command generated
and the internal DDR state.
FIG6.1- AL0,BL4
394
390
VI: FUTURE IMPROVMENTS
Future improvements in AXI interface block is to add more
features like fixed address mode, address wrapping mode
and write response signal generation other than OKEY
response. In fixed burst, the address remain all the same for
every transfer in the burst. This burst type is for every
repeated accesses to the same location such as when loading
or emptying a peripheral FIFO and wrapping burst is similar
to an incrementing burst, in that the address for each transfer
in the burst is an increment of the previous transfer address.
However in wrapping burst the address wraps around to a
lower address when a wrap boundary is reached. The write
response signal other then OKEY are EXOKAY SLVERR
and DECERR. Future Improvement in DDR3 Controller is
to add Reorder block in between AXI Access Manager and
DDR3 Controller block. The Reorder block will enhance the
performance of complete DDR3 Controller because it sends
same row address command first then sends other row
address commands. When we switch the transaction from
Row address X to other Row address Y first we have to
close Bank corresponding to that Row address X means
precharge that Bank and it take tRP time to precharge the
particular bank. So to achieve high performance we have to
order the same row address command with coming data
from AXI Interface block. But at this time we are not
implementing this block because this is applicable when we
are firing random row address command means that depend
on open the customer requirements because this reorder
block increase cost and size of the chip.
REFERENCES
Churoo (Chul-Woo) Park, HoeJu Chung, Yun-Sang
Lee, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, KiWhan Song, Kyu-Hyoun Kim,Jung-Bae Lee,
Changhyun Kim, Senior Member, IEEE, and Soo-In
Cho.” A 512-Mb DDR3 SDRAM Prototype and SelfCalibration Techniques” Proc. IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VOL. 41,NO.4, APRIL
2006
nd
[2] K. Kim et al, “ A 1.4 Gb/s DLL using 2 order chargepump scheme with low phase/duty error for high-speed
DRAM application ,” in IEEE Int. Solid-state Circuits
Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 212-523.
[3] S.Lee et al, “ A. 1.6 Gbs/pin double data rate SDRAM
with wavepiplined CAS latency control,” in IEEE Int.
Solid-State Circuits conf. (ISSCC) Dig. Tech. Papers,
2004, pp.210-213.
[4] H. Song et al, “ A 1.2 Gbs/pin double data rate SDRAM
with on die-termination,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, 2003, pp.
314-496.
[1]
395
391
AXI Compliant DDR3 Controller
Vikky Lakhmani, M.Tech(Sequential) Student
Department of Electrical & Electronics Engineering,
Uttar Pradesh Technical University,
Lucknow (Uttarpradesh), INDIA
Email: [email protected]
Nusrat Ali
Project Manager (VLSI Division),
HCL Technologies, Noida,INDIA
Email: [email protected]
Dr. Vijay Shankar Tripathi
Department of Electronics & Communication
Motilal Nehru National Institute of Technology,
(MNNIT), Allahabad (U.P), INDIA
Email: [email protected]
Abstract—This paper describes the implementation of AXI
compliant DDR3 memory controller. It discusses the overall
architecture of the DDR3 controller along with the detailed
design and operation of its individual sub blocks, the pipelining
implemented in the design to increase the design throughput. It
also discusses the advantage of DDR3 memories over DDR2
memories and the AXI protocol operation
Write Address
Write Response
AXI
Interface
Read Data
AXI
Interface
Storage
Control
Burst
Manager
Address
Control
AXI Access
Manager
INTRODUCTION
The AXI compliant DDR3 Controller permits access of
DDR3 memory through AXI Bus interface[1-4]. The DDR3
controller works as an important bridge between the AXI
host and DDR3 memory. It takes care of the DDR3
initialization and various timing requirements of the DDR3
memory. The DDR3 controller performs multiple schemes
to increases the effective memory throughput[3]. These
schemes include combining and reordering the Read/Write
commands. For attaining the maximum throughput from the
memory, It operates all the memory banks in parallel and
minimizes the effect of precharge/refresh and other DDR3
internal operations [2].
Power
Down
Control
Refresh
Control
Address
Control
Central
Bank
Manager
Bank
Manag
DDR3
Memory
Command
Control
Initialization
Control
AXI Compliant DDR3 Controller Architecture
The architecture of the design is shown in the fig.1. The
design consists of following blocks• AXI interface
• AXI access Manager
• DDR3 Controller
978-0-7695-3941-6/10 $26.00 © 2010 IEEE
DOI 10.1109/ICCMS.2010.291
AXI-IF
Read Address
Keywords- DDR3 memory, AXI Interface, AXI access
Manager, DDR2 memories, AXI protocol operation
I.
Control
Write Data
DDR3 Controller
Fig.1 AXI compliant DDR3 controller
A.
AXI Interface:
AXI-Interface block interacts with HOST
processor and AXI access manager. It is
responsible for accepting and interpreting the
AXI commands issued by the processor and
responding to Read / Write requests in AXI
protocol as requested by processor. It also
maintains an arbiter block which is responsible
for arbitrating between Read/Write commands.
Arbitration is required between the commands
387
391
burst. The AXI access manager combines the
command wherever possible to improve the
performance and passes the final command to
DDR3 controller. To insure maximum
throughput it pre-fetches the commands from
AXI interface converts into memory transactions
and maintains locally. These stored commands
are supplied to the DDR3 Controller whenever
DDR3 Controller is not busy in the very next
clock.
because of parallel/independent Read/Write
command received at the AXI interface.
It maintains asynchronous FIFO’s to store the
command and the data. The Read command gets
stored in (Read Command Block), Write
command gets stored in (Write Command
block), Read data gets stored in (Read Data
block), and Write data gets stored in (Write Data
Block). The stored commands are supplied to the
AXI access manager whenever AXI access
manager is free. Now since the storage can have
both Read and Write commands in the respective
block hence it maintains an arbiter which
arbitrates between Read/Write command and
whenever Burst Manager is free one of the
present command is supplied to the Burst
Manager.
Read Address Channel
Read
Command
Block
Write Address Channel
Write
Command
Block
Read Data Channel
Read Data
Block
Write Data Channel
Write Data
Block
Write Response Channel
The AXI-IF block interacts with the AXI
interface block and receives commands. The
received commands are stored in the Storage
control block. The Burst Manager converts the
AXI command into DDR3 burst. The address
control block is responsible for generation of
address. The overall operation of various blocks
in the AXI access manager is controlled by the
Control Logic. The fig.3 shows the AXI Access
Manager BlockControl Logic
AXI-IF
Arbiter Block
Storage Control
Burst
Manager
Address
Control
Fig.3 AXI Access Manager Block
Write
Response
Block
C. DDR3 Controller :
The main function of DDR3 controller is to interact
with the DDR3 memory. This is the heart of the
AXI compliant DDR3 controller and responsible
for understanding the DDR3 protocol and
communicating with the DDR3 memory [4]. DDR3
Controller also issues Refresh, Power down, Selfrefresh command along with the read or write
command as per the user configuration [1].
The internal blocks of DDR3 controller are shown
in the fig.4-
Fig.2 AXI Interface Block
B. AXI Access Manager:
The main function of the AXI-Access Manager
is to convert the AXI commands into memory
access commands for maximum utilization of the
DDR3 Band Width. The DDR3 memory takes
command only in burst 4 or 8 mode whereas the
AXI command could be a smaller or longer
392
388
Power Down
Control
Central Bank
Manager
Feature
Refresh Control
Data Rate
Burst
Length
No. of
Bank
Address
Control
Fig.4
Bank
Manager
II
400-800
Mbps
BL=4,8
4 banks
800-1600 Mbps
BL=4,8
15/15/15 ns
12/12/12 ns
Bidirectional
DQS
(single
ended
Default)
2.5+/- 0.2 V
Bi-directional
DQS
(Single/Diff.
Default)
Bi-directional DQS
(Differential
Default)
1.8+/- 0.1 V
1.5+/- 0.075 V
Reset
No
No
Yes
ODT
No
Yes
Yes
Vdd/Vddq
:
4
512Mb/1 Gb : 8
Banks
2 bits
DDR3 Controller Block
The Power Down Control Block takes care of
generating the power down command to the DDR3
memory whenever the host commands it to go to
Power saving mode. The refresh control block
takes care of refreshing the DDR3 memory as per
the user supplied configuration. The initialization
control blocks take care of initializing the DDR3
memory after reset. To control the timings of
individual DDR3 banks it contains Bank manager
which track the timing requirements for the
individual DDR3 banks. The address control block
is responsible for generating the address to the
DDR3 memory. The Command control block
interacts with the DDR3 memory and based on the
Bank manager inputs drives the DDR3 bus. It is
also responsible for receiving the data during the
Read operation. The Central Bank manager coordinates between the individual Bank Mangers
and maintains the overall timing requirement of
DDR3 memory.
200-400
Mbps
BL=2,4,8
DDR3
15/15/15 ns
CL/tRCD/
tRP
Source
sync.
Command
Control
DDR2
512Mb
Banks
1 Gb
Banks
4 bits
Prefetch
Initialization
Control
DDR
: 8
8 bits
Table 1: DDR3 feature Comparison
III
SIMULATION, TESTING & VERIFICATION
Verification is important part of complete design process. It
takes almost 60% of design process flow so to minimize
time to market in complete design we do verification
process in parallel with design process. The verification of
AXI compliant DDR3 controller is accomplished by
sending the AXI transaction through the AXI Bus
Functional Model. The response from the AXI compliant
DDR3 controller is received by the AXI Bus Functional
Model and is passed to the Checker. The checker also picks
the expected response from the Local memory and
compares it based on the comparison the environment prints
passed and failed messages and the associated data
mismatch if any. The verification environment for AXI
compliant DDR3 controller is shown in fig.5.
DDR FEATURES COMPARRISON:
DDR3
offers
a
substantial
performance
improvement over previous DDR2 & DDR
memory systems. New DDR3 features, all
transparently implemented in the memory
controller,
improve
the
signal
integrity
characteristics of DDR3 designs so that higher
performance is achieved without an undue burden
for the system designer. If proper consideration is
given to any new DDR2 memory design, it can be
a relatively easy upgrade to support DDR3 in the
next generation design.
393
389
DDR3
Controller
Design
AXI
BFM
Checker
DDR3
Memory
Pass/Fail
Local
Memor
Fig.5 Verification of DDR3
Controller
FIG6.2- BL8, RANDOM READ/WRITE
The AXI Bus Functional Model consists of generator, driver,
monitor and scoreboard. The generator generates AXI
transactions. Driver is used to drive the DUT (Device under
Test) here DUT is AXI interface. The AXI transaction is
also passed to the local memory which prepares the
expected response which is passed to the checker whenever
the checker asks for it. Upon receiving the response from
the DDR3 memory checker commands the local memory to
give back the stored expected response and compares the
DDR3 controller response with the expected response.
IV: SIMULATION RESULTS:
Fig6.3- AL0 , BL4
The below figures are showing snapshot of the DDR3
controller operation in various modes. The design has been
coded in “Verilog HDL” language. The functional
simulation tool used in IUS6.1 from Cadence.
Fig6.4- BL4 , AL0
V: CONCLUSION
The design has been verified by the exhaustive functional
verification. We examined the performance of the design by
generating different type of AXI commands and noting
down the time taken by the DDR3 controller in finishing
them. In most of the scenario the throughput of the design is
close to the theoretical max. The latency of the design is
between 10 to 35 clocks based on the command generated
and the internal DDR state.
FIG6.1- AL0,BL4
394
390
VI: FUTURE IMPROVMENTS
Future improvements in AXI interface block is to add more
features like fixed address mode, address wrapping mode
and write response signal generation other than OKEY
response. In fixed burst, the address remain all the same for
every transfer in the burst. This burst type is for every
repeated accesses to the same location such as when loading
or emptying a peripheral FIFO and wrapping burst is similar
to an incrementing burst, in that the address for each transfer
in the burst is an increment of the previous transfer address.
However in wrapping burst the address wraps around to a
lower address when a wrap boundary is reached. The write
response signal other then OKEY are EXOKAY SLVERR
and DECERR. Future Improvement in DDR3 Controller is
to add Reorder block in between AXI Access Manager and
DDR3 Controller block. The Reorder block will enhance the
performance of complete DDR3 Controller because it sends
same row address command first then sends other row
address commands. When we switch the transaction from
Row address X to other Row address Y first we have to
close Bank corresponding to that Row address X means
precharge that Bank and it take tRP time to precharge the
particular bank. So to achieve high performance we have to
order the same row address command with coming data
from AXI Interface block. But at this time we are not
implementing this block because this is applicable when we
are firing random row address command means that depend
on open the customer requirements because this reorder
block increase cost and size of the chip.
REFERENCES
Churoo (Chul-Woo) Park, HoeJu Chung, Yun-Sang
Lee, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, KiWhan Song, Kyu-Hyoun Kim,Jung-Bae Lee,
Changhyun Kim, Senior Member, IEEE, and Soo-In
Cho.” A 512-Mb DDR3 SDRAM Prototype and SelfCalibration Techniques” Proc. IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VOL. 41,NO.4, APRIL
2006
nd
[2] K. Kim et al, “ A 1.4 Gb/s DLL using 2 order chargepump scheme with low phase/duty error for high-speed
DRAM application ,” in IEEE Int. Solid-state Circuits
Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 212-523.
[3] S.Lee et al, “ A. 1.6 Gbs/pin double data rate SDRAM
with wavepiplined CAS latency control,” in IEEE Int.
Solid-State Circuits conf. (ISSCC) Dig. Tech. Papers,
2004, pp.210-213.
[4] H. Song et al, “ A 1.2 Gbs/pin double data rate SDRAM
with on die-termination,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, 2003, pp.
314-496.
[1]
395
391
