CAN BASED COLLISION AVOIDANCE DOCUMENT

Chapter 1 INTRODUCTION

1.1 OVERVIEW
Cars on the same direction in highway usually keep a safe distance one another with similar speed. However, due to the driver‟s distraction, long-time driving fatigue, flake out, or even a sudden deceleration of the previous car, a serious collision accident may occur if the driver can not react in time to brake. On the other hand, drivers need the mirrors to know other approaching cars from two-side or from the rear end. Even the driver check around carefully, he cannot take an immediate respond, except push the horn, to a sudden approaching car and an accident is thus unavoidable. Therefore, developing a front-obstacle warning system and a rear end collision avoidance system subject to all directions are important in collision avoidance. For the front-end collision avoidance subsystem, Collision avoidance sensor is adopted to measure the distance with respect to the previous car. For rear-end end collision avoidance subsystem, the currently available collision avoidance sensors for vehicles are adopted for approaching cars with relatively low speed. While the rough reading of distance data cannot be applied directly, an intelligent approach is proposed to process the raw distance readout of sensors to produce appropriate warning signals.

1.2 PROJECT OBJECTIVE
• This project Can based collision avoidance system is intended for secure and smooth journey. •

If the driver himself is not concentrating on driving or any other parameters, which may cause damage to vehicle as well a life, this intelligent car/ vehicle warn the driver regarding the danger ahead.

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Chapter 2 LITERATURE SURVEY

2.1 EXISTING SYSTEM
The present automobile safety constitutes of • • • Power train management system Antilock braking system (ABS) Acceleration skid control (ASC) system, etc,

The functionality and wiring of these electric control units (ECU) are getting more complicated.

2.2 PROPOSED SYSTEM
In 198Os, a Germany car component provider Robert Bosch Co. introduced an in-car network; the controller area network (CAN) bus, to replace the complex and expensive traditional in-car wiring. In this project, a high-level protocol CAN open is adopted to interconnect those CAN nodes with reliable communications among sensors. Today the CAN bus is also used as a field bus in general automation environments; primarily due to the low cost of some CAN Controllers and processors.

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2.3 ADVANTAGES
 Collision Mitigation by Braking

 Crash avoidance  Road Safety  Injury and Accident Prevention  Commercially marketable technical systems  Low cost  Product Excellence due to Minimum Requirements  High Alert system

2.4 DISADVANTAGES



The technical challenges for current collision avoidance systems lie in achieving high detection rates given an acceptable false alarm rate, under real-life driving situations.

 The problem with curved roads is that sensors might mistake a car running in the opposite direction for a hazard on the lane where the CAS equipped vehicle is driving.

Cars Equipped with sensors running in the opposite direction

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2.5 APPLICATIONS

 Used as a Warning System to avoid Collision in National Highways.  Used by Police to Track the speed of the approaching vehicles.  Used to detect an object in Extreme conditions like Fog and misty areas.  Can be implemented in Robotic Applications.  Can be used in large vehicles like Trucks and buses.  Can be implemented in Aircraft and aerospace electronics.  Can be used in Passenger and cargo trains.  Can be implemented in Maritime electronics.

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Chapter 3 INTRODUCTION TO EMBEDDED SYSTEMS

3.1 INTRODUCTION:
Each day, our lives become more dependent on 'embedded systems', digital information technology that is embedded in our environment. More than 98% of processors applied today are in embedded systems, and are no longer visible to the customer as 'computers' in the ordinary sense. An Embedded System is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few pre-defined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass-produced, benefiting from economies of scale. The increasing use of PC hardware is one of the most important developments in high-end embedded systems in recent years. Hardware costs of high-end systems have dropped dramatically as a result of this trend, making feasible some projects which previously would not have been done because of the high cost of non-PC-based embedded hardware. But software choices for the embedded PC platform are not nearly as attractive as the hardware. Typically, an embedded system is housed on a single microprocessor board with the programs stored in ROM. Virtually all appliances that have a digital interface -- watches, microwaves, VCRs, cars -- utilize embedded systems. Some embedded systems include an operating system, but many are so specialized that the entire logic can be implemented as a single program. Physically, Embedded Systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. In terms of complexity embedded systems can range from very simple with a single microcontroller chip, to very complex with multiple units, peripherals and networks mounted inside a large chassis or enclosure.

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3.2 DEFINITION OF AN EMBEDDED SYSTEM:
An Embedded system is defined as, for a particular/specific application implementing the software code to interact directly with that particular hardware what we built. Software is used for providing features and flexibility, Hardware = {Processors, ASICs, Memory...} is used for Performance (& sometimes security). (Or) An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, often with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. (Or) An embedded system is a single-purpose computer built into a larger system for the purposes of controlling and monitoring the system. A computer system that is part of a larger system or machine. There are many definitions of embedded system but all of these can be combined into a single concept. An embedded system is a special purpose computer system that is used for particular task.

3.3 FEATURES OF AN EMBEDDED SYSTEM:
The versatility of the embedded computer system lends itself to utility in all kinds of enterprises, from the simplification of deliverable products to a reduction in costs in their development and manufacture. Complex systems with rich functionality employ special operating systems that take into account major characteristics of embedded systems. Embedded operating systems have minimized footprint and may follow real-time operating system specifics. The special computers system is usually less powerful than general-purpose systems, although some expectations do exist where embedded systems are very powerful and complicated. Usually a low power consumption CPU with a limited amount of memory is

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used in embedded systems. Many embedded systems use very small operating systems; most of these provide very limited operating system capabilities. Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale. Some embedded systems have to operate in extreme environment conditions such as very high temperature & humidity. For high volume systems such as portable music players or mobile phones, minimizing cost is usually the primary design consideration. Engineers typically select hardware that is just “good enough” to implement the necessary functions. For low volume or prototype embedded systems, general purpose computers may be adapted by limiting the programs or by replacing the operating system with a real-time operating system.

3.4 CHARACTERISTICS OF AN EMBEDDED SYSTEM:
An Embedded computing systems generally exhibit rich functionality complex functionality is usually the reason for introducing CPUs into the design. However, they also exhibit many non-functional requirements that make the task especially challenging: • Real-time deadlines that will cause system failure if not met; • Multi-rate operation; • In many cases, low power consumption; • Low manufacturing cost, which often means limited code size. Workstation programmers often concentrate on functionality. They may consider the performance characteristics of a few computational kernels of their software, but rarely analyze the total application. They almost never consider power consumption and manufacturing cost. The need to juggle all these requirements makes embedded system programming very challenging and is the reason why embedded system designers need to understand computer architecture.
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3.5 OVERVIEW OF AN EMBEDDED SYSTEM ARCHITECTURE:
Every Embedded system consists of a custom-built hardware built around a central processing unit. This hardware also contains memory chips onto which the software is loaded.

Application Operating System H/W

Software

Figure 1 : Overview of embedded system architecture The operating system runs above the hardware and the application software runs above the operating system. The same architecture is applicable to any computer including desktop computer. However these are significant differences. It is not compulsory to have an operating system in every embedded system. For small applications such as remote control units, air conditioners, toys etc.

3.6 APPLICATIONS OF EMBEDDED SYSTEMS:
Some of the most common embedded systems used in everyday life are

Small embedded controllers:

8-bit CPUs dominate, simple or no operating system (e.g., thermostats)

Control systems:

Often use DSP chip for control computations (e.g., automotive engine control)

Distributed embedded control: Mixture of large and small nodes on a real-time Embedded networks (e.g., cars, elevators, factory automation) System on chip: ASIC design tailored to application area (e.g., consumer electronics, set-top boxes)
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Network equipment:

Emphasis on data movement/packet flow (e.g., network switches; telephone switches)

Critical systems:

Safety and mission critical computing (e.g., pacemakers, automatic trains)

Signal processing:

Often use DSP chips for vision, audio, or other signal Processing (e.g., face recognition)

Robotics:

Uses various types of embedded computing (especially Vision and control) (e.g., autonomous vehicles)

Computer peripherals: Wireless systems:

Disk drives, keyboards, laser printers, etc. Wireless network-connected “sensor networks” and “Motes” to gather and report information

Embedded PCs: Command and control:

Palmtop and small form factor PCs embedded into Equipment Often huge military systems and “systems of systems” (e.g., a fleet of warships with interconnected Computers)

Home Appliances, intercom, telephones, security systems, garage door openers, answering machines, fax machines, home computers, TVs, cable TV tuner, VCR, camcorder, remote controls, video games, cellular phones, musical instruments, sewing machines, lighting control, paging, camera, pinball machines, toys, exercise equipment Office Telephones, computers, security systems, fax machines, microwave, copier, laser printer, color printer, paging Auto Trip computer, engine control, air bag, ABS, instrumentation, security system, transmission control, entertainment, climate control, cellular phone, keyless entry.

3.7 TYPES OF EMBEDDED SYSTEMS:
Based on functionality and performance embedded systems categorized as 4 types

1. Stand alone embedded systems 2. Real time embedded systems
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3. Networked information appliances 4. Mobile devices

Stand alone embedded systems: As the name implies, stand alone systems work in standalone mode. They take i/p, process them and produce the desire o/p. The i/p can be an electrical signal from transducer or temperature signal or commands from human being. The o/p can be electrical signal to drive another system an led or LCD display Ex digital camera, microwave oven, CD player, Air conditioner etc

Real time embedded systems: In this type of an embedded system a specific work has to be complete in a particular period of time. Hard Real time systems: - embedded real time used in missiles Soft Real time systems: - DVD players

Networked information appliances: Embedded systems that are provided with n/w interfaces and accessed by n/w's such as local area n/w or internet are called Network Information Appliances. Ex: A web camera is connected to the internet. Camera can send pictures in real time to any computers connected to the internet Mobile devices: Actually it is a combination of both VLSI and Embedded System. Mobile devices such as Mobile phone, Personal digital assistants, smart phones etc are special category of embedded systems.

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CHAPTER 4 HARDWARE IMPLEMENTATION OF THE PROJECT

4.1 BLOCK DIAGRAM

NODE 1

LCD
GP2D12
ATMEGA 32

MCP 2515

MCP 2551

NODE 2 L293D
ATMEGA 32

LCD

DC MOTOR

MCP 2515

MCP 2551

Fig 2: Block diagram of the project

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4.1.1 PROJECT METHODOLOGY
This project is designed by following blocks:        ATMEGA 16 (AVR CONTROLLER) MCP2515 MCP2551 16X2 LCD GP2D12 L293D DC MOTOR

Here we (AVR

are

having

two

nodes (CAN

each node contains CONTROLLER),

AT MEGA 16 MCP2551 (CAN

CONTROLLER),

MCP2515

TRANSRECEVER). In first node we are interfacing GP2D12 to find the object, in second node contains DC motor. Initially motor is rotating with maximum speed. If any object is found in front of GP2D12 in node1 motor will stop in node2 by using CAN protocol.

4.2 POWER SUPPLY

Power supply is a reference to a source of electrical power. A device or system that supplies electrical or other types of energy to an output load or group of loads is called a power supply unit or PSU. The term is most commonly applied to electrical energy supplies, less often to mechanical ones, and rarely to others

This power supply section is required to convert AC signal to DC signal and also to reduce the amplitude of the signal. The available voltage signal from the mains is 230V/50Hz which is an AC voltage, but the required is DC voltage(no frequency) with the amplitude of +5V and +12V for various applications.

In this section we have Transformer, Bridge rectifier, are connected serially and voltage regulators for +5V and +12V (7805 and 7812) via a capacitor (1000µF) in parallel are connected parallel as shown in the circuit diagram below. Each voltage regulator output is again is connected to

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the capacitors of values (100µF, 10µF, 1 µF, 0.1 µF) are connected parallel through which the corresponding output (+5V or +12V) are taken into consideration.

230V O/P
TRANSFORMER

RECTIFIER

FILTER

REGULATOR

FIG 3 : POWER SUPPLY BLOCK DIAGRAM

Transformer
A transformer is an electrical device which is used to convert electrical power from one electrical circuit to another without change in frequency. Transformers convert AC electricity from one voltage to another with little loss of power. Transformers work only with AC and this is one of the reasons why mains electricity is AC. Step-up transformers increase in output voltage, step-down transformers decrease in output voltage. Most power supplies use a step-down transformer to reduce the dangerously high mains voltage to a safer low voltage. The input coil is called the primary and the output coil is called the secondary. There is no electrical connection between the two coils; instead they are linked by an alternating magnetic field created in the soft-iron core of the transformer. The two lines in the middle of the circuit symbol represent the core. Transformers waste very little power so the power out is (almost) equal to the power in. Note that as voltage is stepped down current is stepped up. The ratio of the number of turns on each coil, called the turn‟s ratio, determines the ratio of the voltages. A step -down transformer has a large number of turns on its primary (input) coil which is connected to the high voltage mains supply, and a small number of turns on its secondary (output) coil to give a low output voltage.

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Figure 4 : Transformer

Bridge Rectifier
A diode bridge or bridge rectifier is an arrangement of four diodes in a bridge configuration that provides the same polarity of output voltage for any polarity of input voltage. When used in its most common application, for conversion of alternating current (AC) input into direct current (DC) output, it is known as a bridge rectifier. A bridge rectifier provides full-wave rectification from a two-wire AC input, resulting in lower cost and weight as compared to a center-tapped transformer design, but has two diode drops rather than one, thus exhibiting reduced efficiency over a center-tapped design for the same output voltage.

Basic Operation
When the input connected at the left corner of the diamond is positive with respect to the one connected at the right hand corner, current flows to the right along the upper colored path to the output, and returns to the input supply via the lower one.

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When the right hand corner is positive relative to the left hand corner, current flows along the upper colored path and returns to the supply via the lower colored path.

FIG 5 : OPERATION OF RECTIFIER In each case, the upper right output remains positive with respect to the lower right one. Since this is true whether the input is AC or DC, this circuit not only produces DC power when supplied with AC power: it also can provide what is sometimes called "reverse polarity protection". That is, it permits normal functioning when batteries are installed backwards or DC input-power supply wiring "has its wires crossed" (and protects the circuitry it powers against damage that might occur without this circuit in place). Prior to availability of integrated electronics, such a bridge rectifier was always constructed from discrete components. Since about 1950, a single four-terminal component containing the four diodes connected in the bridge configuration became a standard commercial component and is now available with various voltage and current ratings

FILTER
A Filter is a device, which removes the a.c component of rectifier output but allows the d.c component to reach the load.

Capacitor Filter
We have seen that the ripple content in the rectified output of half wave rectifier is 121% or that of full-wave or bridge rectifier or bridge rectifier is 48% such high percentages of ripples is not acceptable for most of the applications. Ripples can be removed by one of the following methods of filtering:
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(a) A capacitor, in parallel to the load, provides an easier by –pass for the ripples voltage though it due to low impedance. At ripple frequency and leave the d.c.to appears the load. (b) An inductor, in series with the load, prevents the passage of the ripple current (due to high impedance at ripple frequency) while allowing the d.c (due to low resistance to d.c) (c) various combinations of capacitor and inductor, such as L-section filter section

filter, multiple section filter etc. which make use of both the properties mentioned in (a) and (b) above. Two cases of capacitor filter, one applied on half wave rectifier and another with full wave rectifier.

Fig 6: capacitor filter Filtering is performed by a large value electrolytic capacitor connected across the DC supply to act as a reservoir, supplying current to the output when the varying DC voltage from the rectifier is falling. The capacitor charges quickly near the peak of the varying DC, and then discharges as it supplies current to the output. Filtering significantly increases the average DC voltage to almost the peak value (1.4 × RMS value). To calculate the value of capacitor(C),

C = ¼*√3*f*r*Rl
Where, f = supply frequency, r = ripple factor, Rl = load resistance Note: In our circuit we are using 1000microfarads.
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Voltage Regulator
Voltage regulator ICs is available with fixed (typically 5, 12 and 15V) or variable output voltages. The maximum current they can pass also rates them. Negative voltage regulators are available, mainly for use in dual supplies. Most regulators include some automatic protection from excessive current ('overload protection') and overheating ('thermal protection'). Many of the fixed voltage regulator ICs have 3 leads and look like power transistors, such as the 7805 +5V 1A regulator shown on the right. The LM7805 is simple to use. You simply connect the positive lead of your unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the Common pin and then when you turn on the power, you get a 5 volt supply from the output pin.

Fig 7 : A Three Terminal Voltage Regulator

78XX:
The Bay Linear LM78XX is integrated linear positive regulator with three terminals. The LM78XX offer several fixed output voltages making them useful in wide range of applications. When used as a zener diode/resistor combination replacement, the LM78XX usually results in an effective output impedance improvement of two orders of magnitude, lower quiescent current. The LM78XX is available in the TO-252, TO-220 & TO263packages

Features:
• Output Current of 1.5A • Output Voltage Tolerance of 5%

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• Internal thermal overload protection • Internal Short-Circuit Limited • No External Component • Output Voltage 5.0V, 6V, 8V, 9V, 10V, 12V, 15V, 18V, 24V • Offer in plastic TO-252, TO-220 & TO-263 • Direct Replacement for LM78XX

4.3 ATMEGA32 CONTROLLER

4.3.1 OVERVIEW:

The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designed to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega32 provides the following features: 32K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 1024 bytes EEPROM, 2K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while
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allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel‟s high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed insystem through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By Combining an 8-bit RISC CPU with InSystem Self-Programmable Flash on a monolithic chip, the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.

4.3.2 FEATURES:   High-performance, Low-power AVR® 8-bit Microcontroller Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier
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

High Endurance Non-volatile Memory segments – 32K Bytes of In-System Self-programmable Flash program memory – 1024 Bytes EEPROM – 2K Byte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write

Operation – Programming Lock for Software Security  JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support –Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface  Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC - 8 Single-ended Channels -7 Differential Channels in TQFP Package Only
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-2 Differential Channels with Programmable Gain at 1x, 10x, or 200x – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator  Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby  I/O AND PACKAGES: – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF  OPERATING VOLTAGES: – 2.7 - 5.5V for ATmega32L – 4.5 - 5.5V for ATmega32  SPEED GRADES: – 0 - 8 MHz for ATmega32L – 0 - 16 MHz for ATmega32  Power Consumption at 1 MHz, 3V, 25°C for ATmega32L – Active: 1.1 mA
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– Idle Mode: 0.35 mA - Power-down Mode: < 1 μA

4.3.3 PIN DIAGRAM AND DESCRIPTION:

Figure 8 : PIN configuration VCC GND Port A (PA7-PA0) :Digital supply voltage. :Ground. :Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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Port B (PB7-PB0): Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C (PC7-PC0): Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. The TD0 pin is tri-stated unless TAP states that shift out data are entered. Port D (PD7-PD0): Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. RESET: Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. XTAL1: Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2: Output from the inverting Oscillator amplifier. AVCC: AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. AREF: AREF is the analog reference pin for the A/D Converter.

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4.3.4 AVR CPU CORE: This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 9 : AVR CPU core In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.

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4.3.5 ALU – ARITHMETIC LOGIC UNIT: The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format.

Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as:

Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
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Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a half carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. Bit 4 – S: Sign Bit, S = N ⊕V The S-bit is always an exclusive or between the Negative Flag N and the Two‟s Complement Overflow Flag V. Bit 3 – V: Two’s Complement Overflow Flag The Two‟s Complement Overflow Flag V supports two‟s complement arithmetic. Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation.

4.3.6 GENERAL PURPOSE REGISTER FILE: The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
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• One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input

Figure 10 : AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

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THE X-REGISTER, Y-REGISTER AND Z-REGISTER: The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5.

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details).

4.3.7 INSTRUCTION EXECUTION TIMING: This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock, directly generated from the selected clock source for the chip. No internal clock division is used. Figure shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

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1 The Parallel Instruction Fetches and Instruction Executions Below figure shows the internal timing concept for the Register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Single Cycle ALU Operation:

2 Single Cycle ALU Operation Figure 11 : Instruction Execution Timing

4.3.8 AVR ATmega32 MEMORIES: This section describes the different memories in the ATmega32. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega32 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

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In-System Reprogrammable Flash Program Memory The ATmega32 contains 32K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega32 Program Counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The operation of Flash Programming in SPI, JTAG or Parallel Programming mode. Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory Instruction Description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on above.

SRAM DATA MEMORY: The below fig shows the ATmega32 SRAM Memory is organized. The lower 2144 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 2048 locations address the internal data SRAM.

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The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect Addressing Pointer Registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register-indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of internal data SRAM in the ATmega32 are all accessible through all these addressing modes.

4.3.9 DATA MEMORY ACCESS TIMES: This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in below figure.

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4.3.10 REGISTER DESCRIPTION FOR I/O PORTS:

Port A Data Register – PORTA:

Port A Data Direction Register – DDRA:

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Port A Input Pins Address –PINA:

Port B Data Register – PORTB:

Port B Data Direction Register – DDRB:

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Port B Input Pins Address – PINB:

Port C Data Register – PORTC:

Port C Data Direction Register – DDRC:

Port C Input Pins Address – PINC:

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In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push- Pull Zero Output. The port pins assumes their initial value, even if the clock is not running. Note that the DDRC and PINC Registers are available in ATmega103

compatibility mode, and should not be used for 100% back-ward compatibility.

Port D Data Register – PORTD:

Port D Data Direction Register – DDRD:

Port D Input Pins Address – PIND:

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4.3.11 ARCHITECTURE OF ATMEGA32:

FIGURE 12 : ARCHITECTURE OF ATMEGA32
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4.4 COLLISION AVOIDANCE SENSOR

4.4.1 INTRODUCTION: The sensor is based on the principle of Infrared Reflection. It makes use of Infrared rays modulated at 38 kHz and then receiving the reflected rays. The circuit is built around the popular NE555 timer IC operating in Astable Multivibrator mode. A continuous beam of IR rays modulated at 38k Hz is emitted by the IR LED connected to the O/P pin of the 555 (pin-3). The receiver used is TSOP1738 from Vishay; it has a built-in filter and gain-amplifier. When there‟s an Obstacle in front of the module, the IR rays are reflected back and fall on the receiver (TSOP1738), making its output LOW, which is otherwise HIGH. The LED indicator should not be confused with Active High o/p. The LED is connected across the +Vcc and Data pin of TSOP with a 1K resistor in series. QUICK REFERENCE: Obstacle No Obstacle : LED Glow : LED Off : Output is 0.0 - 0.2V : Output is 5.0 - 5.2 V

4.4.2 DIAGRAM:

Figure 13: Collision avoidance sensor GP2D12

4.4.3 THEORY OF OPERATION: The basic concept of IR (infrared) obstacle detection is to transmit the IR signal (radiation) in a direction and a signal is received at the IR receiver when the IR radiation bounces back from a surface of the object.

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Here in the figure the object can be anything which has certain shape and size, the IR LED transmits the IR signal on to the object and the signal is reflected back from the surface of the object. The reflected signal is received by an IR receiver. The IR receiver can be a photodiode / phototransistor or a readymade module which decodes the signal. In order to implement the IR obstacle detection, we need to understand the following 1. How to transmit IR signal using commercially available electronic components. 2. The IR receiver. The main focus in this document is to explain the implementation of IR based obstacle detection in detail. IR Transmitter In general, the basic building block of any IR transmitter is modulation of the information signal with carrier signal, because the receiver modules which are available off-the-shelf are made for a particular carrier frequency. So it is clear that when you chose a particular IR receiver module, you also need to transmit the modulated wave with the same carrier frequency of that of an IR receiver module. Modulating a 38 Khz carrier signal

ON state = 10ms OFF state = 90ms The figure above explains the modulation process, this is similar to OOK(ON-OFF Keying) modulation, where the carrier signal is ON for certain period of time. When transmitting a signal for obstacle detection, it is necessary that the carrier signal is transmitted for a short while and remains OFF for longer period of time. If the transmission of the carrier signal is prolonged, in other words, instead of having a short transmission period(10 milliseconds in our case, as explained in the figure) of carrier signal, if we have it for a long period of time then the receiver module will treat it as a noise and ignores receiving the transmitted signal.

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The implementation of IR transmitter can be done in various ways; in this document we will discuss two ways 1. Using 7555(compatible with 555) timer IC to generate a 38 kHz carrier signal. 2. Using Micro controller(Atmel atmega8535) inbuilt wave generation module.

IR TRANSMITTER USING 7555 TIMER IC:

Here in the figure 5k ohms pot is used instead of 1200 ohms resister, so that it can be adjusted for 38 kHz frequency. This adjustment is required because of the tolerance value of the components used in the circuit. The best way to overcome this is to connect the circuit to the oscilloscope and trim the pot to get 38 kHz. In case you don‟t have an access to oscilloscope, still you can check it with IR receiver circuit. Secondly you can trim the 500 ohms pot depending on the distance you intend to operate the sensor. It is observed that, by adjusting the 500 ohms pot to 200 ohms, it is possible to detect obstacles with in 50 cms of range from the sensor. IR Receiver It is quite simple to construct a IR receiver with readily available off-the-shelf modules. These modules are nothing but the IC packages, referred as TSOP(Thin small-outline package). In this document, the receiver is designed for 38 kHz carrier signal; hence the IC selected should work for the same frequency. The IC TSOP4838 will serve as a receiver module, which is compatible with both TTL and CMOS logic. This means that we can directly get digital signal from the receiver module and then connect it to the microcontroller.

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IMPLEMENTATION OF IR RECEIVER USING AN LED AS AN INDICATOR:

Here in the circuit the LED blinks whenever the TSOP4838 module receives a signal from the transmitter. Once the transmitter and receiver is complete, both should be placed at a certain angle, so that the obstacle detection happens in a proper way. This angle is nothing but the directivity of the sensor, which is generally +/- 45 degrees. Also remember, that a thick enclosure is necessary for both IR transmitter and IR receiver, because the IR radiation may bounce back from the surrounding objects which may not help when you want to detect obstacle in one direction. Sometimes, if you don‟t have a thick enclosure then the signal may directly reach the receiver even without having an obstacle. The enclosure can be made out of plastic or even metal materiel which is painted black in color.

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4.5 CONTROL AREA NETWORK

Controller Area Network (CAN) is an advanced serial bus system that efficiently supports distributed control system with a very high level of security. Robert Bosch, Germany initially developed it for the use in motor vehicles in the late 1980‟s.It‟s domain of application ranges from high-speed network to low cost multiplex wiring. To improve the behavior of the vehicle, it was necessary for the different control system (and their sensor) to exchange information. This was usually done by discrete interconnection of the different system (i.e. point -to - point wiring). The requirement for the information exchange has then grown to such an extent that a cable network with a length up to several miles and many connectors were required. This leads to growing problems concerning material cost, production time and reliability. The solution to this problem was the connection of the Control system via a serial bus system. With the use of CAN, point - to - point wiring is replaced by one serial bus connecting to all control systems. This is accomplished by adding some CAN specific hardware to each control unit that provides the “rules " or the protocol for transmitting and receiving information via the bus. The CAN protocol uses the data link layer and the physical layer in the ISO_OSI model.

4.5.1 OVERVIEW of CAN PROTOCOL: CAN is a multi - master bus with an open, linear structure with one logic bus line. The number of nodes is not limited by the protocol. In CAN protocol, two versions are available. They are version 2.0A CAN and version 2.0B CAN. Version 2.0A is original CAN specifications specify an 11 bit identifier which allows 2^11(=2048) different message identifiers and is known as standard CAN. Version 2.0B CAN contain 29 bit identifiers which allows 2^29 (over 536 million) message identifiers.

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CAN has the following properties:       Prioritization of messages. Guarantee of latency times. Configuration flexibility. Multicast reception with time synchronization. System wide data consistency. Error detection and error signaling.

The CAN protocol handle bus accesses according to the concept called “Carrier Sense Multiple Access with arbitration on message priority ". This arbitration Concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss.

If two or more bus nodes start their transmission at the same time after having found the bus to be idle, collision of the messages is avoided by bitwise arbitration. Each node sends the bits of its message identifier and monitors the bus level.

4.5.2 BASIC CONCEPTS: Some of the basic concepts which are necessary to understand the CAN operation. They are as follows. Messages : Information on the bus is sent in fixed format messages of different but limited length. When the bus is free any connected unit may start to transmit a new message. Information routing : In CAN systems a can node does not make use of any information about the system configuration (e.g. station addresses).this has several important consequences. System flexibility : Nodes can be added to the CAN network without requiring any change in the software or hardware of any node and application layer. Message routing :The content of a message is named by an IDENTIFIER. The identifier does not indicate the destination of the message but describes the meaning of the data ,so that

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all nodes in the network are able to decide by message filtering whether the data is to be acted upon by them or not. Multicasting : As a consequence of the concept of message filtering any number of nodes can receive and simultaneously act upon the same message. Data consistency : Within a CAN network it is guaranteed that a message is simultaneously accepted either by all nodes or by no node. Thus data consistency of a system is achieved by the concepts of multicast and by error handling. Bit rate : The speed of CAN may be different in different systems. However, in a given system the bit rate is uniform and fixed. Priorities : The identifier defines a static message priority during bus access. Remote data request : By sending a remote frame a node requiring data may request another node to send the corresponding data frame. The data frame and the corresponding remote frame named by the same identifier. Multimaster : When the bus is free any may start to transmit a message. The unit with the message of highest priority to be transmitted gains bus access. Arbitration : Whenever the bus is free, any unit may start to transmit a message. If two or more units start transmitting messages at the same time, the bus access conflict is resolved by bit wise arbitration using the identifier. The mechanism of arbitration grantees that neither information nor time is lost. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame. During arbitration every transmitter compares the level of the bit transmitted with the level that is monitored on the bus. If these levels are equal the unit may continue to send. When a „recessive‟ level is sent and a „dominant‟ level is monitored, the unit has lost arbitration and must withdraw without sending one more bit.

4.5.3 BUS CHARACTERISTICS:

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There are two bus states, called "dominant" and "recessive". The bus logic uses a "WiredAND" mechanism, that is, "dominant bits" (equivalent to the logic level "Zero") overwrite the "recessive" bits (equivalent to the logic level "One”). Bus access and arbitration The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbitration on Message Priority”. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss.

In the picture above you see the trace of the transmit pins of three bus nodes called A, B and C, and the resulting bus state according to the wired-AND principle.

If two or more bus nodes start their transmission at the same time after having found the bus to be idle, collision of the messages is avoided by bitwise arbitration. Each node sends the bits of its message identifier and monitors the bus level.

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At a certain time nodes A and C send a dominant identifier bit. Node B sends a recessive identifier bit but reads back a dominant one. Node B loses bus arbitration and switches to receive mode. Some bits later node C loses arbitration against node A. This means that the message identifier of node A has a lower binary value and therefore a higher priority than the messages of nodes B and C. In this way, the bus node with the highest priority message wins arbitration without losing time by having to repeat the message. Nodes B and C automatically try to repeat their transmission once the bus returns to the idle state. Node B loses against node C, so the message of node C is transmitted next, followed by node B‟s message. It is not permitted for different nodes to send messages with the same identifier as arbitration could fail leading to collisions and errors

4.5.4 MESSAGE TRANSFER: Message transfer is manifested and controlled by two frame types. A data frame Here data from a transmitter to the receivers. It is composed of seven different bit fields. Start of frame, Arbitration field, control field, data field, crc field, Ack field, End of frame. A Remote frame It is transmitted by a bus unit to request the transmission of the data frame with the same identifier. It is composed of six different bit fields. Start of frame, Arbitration field, control field, crc field, Ack field, End of frame. A "Data Frame" is generated by a CAN node when the node wishes to transmit data. The Standard CAN Data Frame is shown above. The frame begins with a dominant Start of Frame bit for hard synchronization of all nodes.

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Figure 14 : Data Frame The Start of Frame bit is followed by the Arbitration Field consisting of 12 bits. The 11-bit Identifier, which reflects the contents and priority of the message, and the Remote Transmission Request bit. The Remote transmission request bit is used to distinguish a Data Frame (RTR = dominant) from a Remote Frame (RTR = recessive).The next field is the Control Field, consisting of 6 bits. The first bit of this field is called the IDE bit (Identifier Extension) and is at dominant state to specify that the frame is a Standard Frame. The following bit is reserved and defined as a dominant bit. The remaining 4 bits of the Control Field are the Data Length Code (DLC) and specify the number of bytes of data contained in the message (0 - 8 bytes).

The data being sent follows in the Data Field which is of the length defined by the DLC above (0, 8, 16, 56 or 64 bits).The Cyclic Redundancy Field (CRC field) follows and is used to detect possible transmission errors. The CRC Field consists of a 15 bit CRC sequence, completed by the recessive CRC Delimiter bit.

The next field is the Acknowledge Field. During the ACK Slot bit the transmitting node sends out a recessive bit. Any node that has received an error free frame acknowledges the correct reception of the frame by sending back a dominant bit (regardless of whether the node is configured to accept that specific message or not). From this it can be seen that CAN
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belongs to the "in-bit-response" group of protocols. The recessive Acknowledge Delimiter completes the Acknowledge Slot and may not be overwritten by a dominant bit. Seven recessive bits (End of Frame) end the Data Frame.

Figure 14 : Remote Frame Generally data transmission is performed on an autonomous basis with the data source node (e.g. a sensor) sending out a Data Frame. It is also possible, however, for a destination node to request the data from the source by sending a Remote Frame. There are 2 differences between a Data Frame and a Remote Frame. Firstly the RTR-bit is transmitted as a dominant bit in the Data Frame and secondly in the Remote Frame there is no Data Field. In the very unlikely event of a Data Frame and a Remote Frame with the same identifier being transmitted at the same time. The Data Frame wins arbitration due to the dominant RTR bit following the identifier. In this way, the node that transmitted the Remote Frame receives the desired data immediately.

4.5.5 CAN CONTROLLER OPERATION: The CAN controller having error detection and handling capacity in efficient way, it also makes sleep mode of operation and produces interrupts Error Handling The CAN Controllers count and handle transmit and receive errors as specified in CAN Spec 2.0B. The Transmit and Receive Error Counters are incremented for each detected error and are decremented when operation is error-free. If the Transmit Error counter contains 255 and another error occurs, the CAN Controller is forced into a state called Bus-Off. In this
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state, the following register bits are set: BS in CANSR, BEI and EI in CANIR if these are enabled, and RM in CANMOD. RM resets and disables much of the CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit Error Counter will count down 128 occurrences of the Bus Free condition (11 consecutive recessive bits). Software can monitor this countdown by reading the Tx Error Counter. When this countdown is complete, the CAN Controller clears BS and ES in CANSR, and sets EI in CANSR if EIE in IER is 1. The Tx and Rx error counters can be written if RM in CANMOD is 1. Writing 255 to the Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANSR) is 1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software clears RM in CANMOD thereafter, only one Bus Free condition (11 consecutive recessive bits) is needed before operation resumes.

Sleep Mode

The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN Interrupt Enable register to enable an interrupt on any wake-up condition. The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up in response to bus activity, is not able to receive an initial message, until after it detects Bus free (11 consecutive recessive bits). If an interrupt is pending or the CAN bus is active when software sets SM, the wakeup is immediate.

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Interrupts

Each CAN Controller produces 3 interrupt requests, Receive, Transmit, and “other status”. The Transmit interrupt is the OR of the Transmit interrupts from the three Tx Buffers. Each Receive and Transmit interrupt request from each controller is assigned its own channel in the Vectored Interrupt Controller (VIC), and can have its own interrupt service routine. The “other status” interrupts from all of the CAN controllers, and the Acceptance Filter LUTerr condition, are OR-ed into one VIC channel.

Transmit Priority

If the TPM bit in the CANMOD register is 0, multiple enabled Tx Buffers contend for the right to send their messages based on the value of their CAN Identifier (TID). If TPM is 1, they contend based on the PRIO fields in bits 7:0 of their CANTFS registers. In both cases the smallest binary value has priority. If two (or three) transmit-enabled buffers have the same smallest value, the lowest-numbered buffer sends first. The CAN controller selects among multiple enabled Tx Buffers dynamically, just before it sends each message.

4.6 MCP 2515 & MCP 2551 µCHIPS

4.6.1 MCP 2515:
DESCRIPTION & PIN DIAGRAM: Microchip Technology‟s MCP2515 is a stand-alone Controller Area Network (CAN) controller that implements the CAN specification, version 2.0B. It is capable of transmitting and receiving both standard and extended data and remote frames. The MCP2515 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCUs overhead. The MCP2515 interfaces with microcontrollers (MCUs) via an industry standard Serial Peripheral Interface (SPI).

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FEATURES: • Implements CAN V2.0B at 1 Mb/s: - 0 – 8 byte length in the data field - Standard and extended data and remote frames • Receive buffers, masks and filters: - Two receive buffers with prioritized message storage - Six 29-bit filters - Two 29-bit masks • Data byte filtering on the first two data bytes(applies to standard data frames) • Three transmit buffers with prioritization and abort features • High-speed SPI Interface (10 MHz): - SPI modes 0,0 and 1,1 • One-shot mode ensures message transmission is attempted only one time • Clock out pin with programmable prescaler: - Can be used as a clock source for other device(s) • Start-of-Frame (SOF) signal is available for monitoring the SOF signal: - Can be used for time-slot-based protocols and/or bus diagnostics to detect early bus degradation • Interrupt output pin with selectable enables • Buffer Full output pins configurable as: - Interrupt output for each receive buffer - General purpose output • Request-to-Send (RTS) input pins individually configurable as: - Control pins to request transmission for each transmit buffer
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- General purpose inputs • Low-power CMOS technology: - Operates from 2.7V – 5.5V - 5 mA active current (typical) - 1 μA standby current (typical) (Sleep mode) • Temperature ranges supported: - Industrial (I): -40°C to +85°C - Extended (E): -40°C to +125°C DEVICE OVERVIEW: The MCP2515 is a stand-alone CAN controller developed to simplify applications that require interfacing with a CAN bus. A simple block diagram of the MCP2515. The device consists of three main blocks: 1. The CAN module, which includes the CAN protocol engine, masks, filters, transmit and receive buffers. 2. The control logic and registers that are used to configure the device and its operation. 3. The SPI protocol block. CAN MODULE: The CAN module handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate message buffer and control registers. Transmission is initiated by using control register bits via the SPI interface or by using the transmit enable pins. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against the userdefined filters to see if it should be moved into one of the two receive buffers.

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Fig 15 : CAN module

CONTROL LOGIC: The control logic block controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control. Interrupt pins are provided to allow greater system flexibility. There is one multi-purpose interrupt pin (aswell as specific interrupt pins) for each of the receive registers that can be used to indicate a valid message has been received and loaded into one of the receive buffers. Use of the specific interrupt pins is optional. The general purpose interrupt pin, as well as status registers (accessed via the SPI interface), can also be used to determine when a valid message has been received. Additionally, there are three pins available to initiate immediate transmission of a message that has been loaded into one of the three transmit registers. Use of these pins is optional, as initiating message transmissions can also be accomplished by utilizing control registers, accessed via the SPI interface. SPI PROTOCOL BLOCK: The MCU interfaces to the device via the SPI interface. Writing to, and reading from, all registers is accomplished using standard SPI read and write commands, in addition to specialized SPI commands.

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4.6.2 MCP 2551:
DEVICE OVERVIEW: The MCP2551 is a high-speed CAN, fault-tolerant device that serves as the interface between a CANprotocol controller and the physical bus. The MCP2551 provides differential transmit and receive capability for the CAN protocol controller and is fully compatible with the ISO11898 standard, including 24V requirements. It will operate at speeds of up to 1 Mb/s. Typically, each node in a CAN system must have a device to convert the digital signals generated by a CAN controller to signals suitable for transmission over the bus cabling (differential output). It also provides a buffer between the CAN controller and the highvoltage spikes that can be generated on the CAN bus byoutside sources (EMI, ESD, electrical transients, etc.). PIN DIAGRAM:

Figure 16 : MCP2551 FEATURES: • Supports 1 Mb/s operation • Implements ISO-11898 standard physical layer requirements • Suitable for 12V and 24V systems • Externally-controlled slope for reduced RFI emissions • Detection of ground fault (permanent dominant) on TXD input • Power-on reset and voltage brown-out protection • An unpowered node or brown-out event will not disturb the CAN bus • Low current standby operation • Protection against damage due to short-circuit conditions (positive or negative battery voltage) • Protection against high-voltage transients
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• Automatic thermal shutdown protection • Up to 112 nodes can be connected • High noise immunity due to differential bus implementation • Temperature ranges: - Industrial (I): -40°C to +85°C - Extended (E): -40°C to +125°C

BLOCK DIAGRAM:

TRANSMITTER FUNCTION: The CAN bus has two states: Dominant and Recessive. A dominant state occurs when the differential voltage between CANH and CANL is greater than a defined voltage (e.g.,1.2V). A recessive state occurs when the differential voltage is less than a defined voltage (typically 0V). The dominant and recessive states correspond to the low and high state of the TXD input pin, respectively. However, a dominant state initiated by another CAN node will override a recessive state on the CAN bus. MAXIMUM NUMBER OF NODES: The MCP2551 CAN outputs will drive a minimum load of 45Ω, allowing a maximum of 112 nodes to be connected (given a minimum differential input resistance of 20 kΩ and a nominal termination resistor value of 120Ω).

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RECEIVER FUNCTION: The RXD output pin reflects the differential bus voltage between CANH and CANL. The low and high states of the RXD output pin correspond to the dominant and recessive states of the CAN bus, respectively.

INTERNAL PROTECTION: CANH and CANL are protected against battery short circuits and electrical transients that can occur on the CAN bus. This feature prevents destruction of the transmitter output stage during such a fault condition. The device is further protected from excessive current loading by thermal shutdown circuitry that disables the output drivers when the junction temperature exceeds a nominal limit of 165°C. All other parts of the chip remain operational and the chip temperature is lowered due to the decreased power dissipation in the transmitter outputs. This protection is essential to protect against bus line short-circuit-induced damage.

OPERATING MODES:

The RS pin allows three modes of operation to be selected: • High-Speed • Slope-Control • Standby When in High-speed or Slope-control mode, the drivers for the CANH and CANL signals are internally regulated to provide controlled symmetry in order to minimize EMI emissions. Additionally, the slope of the signal transitions on CANH and CANL can be controlled with a resistor connected from pin 8 (RS) to ground, with the slope proportional to the current output at RS, further reducing EMI emissions.

HIGH-SPEED: High-speed mode is selected by connecting the RS pin to VSS. In this mode, the transmitter output drivers have fast output rise and fall times to support high-speed CAN bus rates.

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SLOPE-CONTROL: Slope-control mode further reduces EMI by limiting the rise and fall times of CANH and CANL. The slope, or slew rate (SR), is controlled by connecting an external resistor (REXT) between RS and VOL (usually ground). The slope is proportional to the current output at the RS pin. Since the current is primarily determined by the slope-control resistance value REXT, a certain slew rate is achieved by applying a respective resistance. STANDBY MODE: The device may be placed in standby or “SLEEP” mode by applying a high-level to RS. In SLEEP mode, the transmitter is switched off and the receiver operates at a lower current. The receive pin on the controller side (RXD) is still functional but will operate at a slower rate. The attached microcontroller can monitor RXD for CAN bus activity and place the transceiver into normal operation via the RS pin (at higher bus rates, the first CAN message may be lost).

4.7 LIQUID CRYSTAL DISPLAY

4.7.1 INTRODUCTION: Liquid crystal display is a type of display used in digital watches and many portable computers.

Figure 17 : LCD

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LCD displays utilize two sheets of polarizing material with a liquid crystal solution between them. An electric current passed through the liquid causes the crystals to align so that light cannot pass through them. Each crystal, therefore, is like a shutter, either allowing light to pass through or blocking the light. The liquid crystals can be manipulated through an applied electric voltage so that light is allowed to pass or is blocked. By carefully controlling where and what wavelength (color) of light is allowed to pass, the LCD monitor is able to display images. A back light provides LCD monitor‟s brightness. Other advances have allowed LCD‟s to greatly reduce liquid crystal cell response times. Response time is basically the amount of time it takes for a pixel to “change colors”. In reality response time is the amount of time it takes a liquid crystal cell to go from being active to inactive. Here the LCD is used at both the Transmitter as well as the receiver side. The input which we give to the microcontroller is displayed on the LCD of the transmitter side and the message sent is received at the receiver side which displays at the receiver end of the LCD and the corresponding operation is performed They make complicated equipment easier to operate. LCDs come in many shapes and sizes but the most common is the 16 character x 4 line display with no backlight. It requires only 11 connections – eight bits for data (which can be reduced to four if necessary) and three control lines (we have only used two here). It runs off a 5V DC supply and only needs about 1mA of current. The display contrast can be varied by changing the voltage into pin 3 of the display.

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4.7.2 PIN DESCRIPTION of LCD:

From this description, the interface is a parallel bus, allowing simple and fast reading/writing of data to and from the LCD. This waveform will write an ASCII Byte out to the LCD's screen.

PIN DESCRIPTION: Vcc, Vss and Vee While Vcc and Vss provide +5V and ground respectively, Vee is used for controlling LCD contrast.

PIN 1 2 3

SYMBOL Vss Vcc Vee

I/O ----

DESCRIPTION Ground +5V power supply Power supply to control contrast RS=0 to select command register RS=1 to select data
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4

RS

I

register

5

R/W

I

R/W=0 for write R/W=1 for read

6 7 8 9 10 11 12 13 14

EN DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

I/O I/O I/O I/O I/O I/O I/O I/O I/O

Enable The 8-bit data bus The 8-bit data bus The 8-bit data bus The 8-bit data bus The 8-bit data bus The 8-bit data bus The 8-bit data bus The 8-bit data bus

Table 1 : Pin description of LCD

The ASCII code to be displayed is eight bits long and is sent to the LCD either four or eight bits at a time.If four bit mode is used, two "nibbles" of data (Sent high four bits and then low four bits with an "E" Clock pulse with each nibble) are sent to make up a full eight bit transfer. The "E" Clock is used to initiate the data transfer within the LCD. Deciding how to send the data to the LCD is most critical decision to be made for an LCD interface application. Eightbit mode is best used when speed is required in an application and at least ten I/O pins are available.The "R/S" bit is used to select whether data or an instruction is being transferred between the microcontroller and the LCD. If the Bit is set, then the byte at the current LCD "Cursor" Position can be reader written. When the Bit is reset, either an instruction is being sent to the LCD or the execution status of the last instruction is read back

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4.7.3 INTERFACING LCD WITH CONTROLLER:

P1.0 P1.1 P1.2 8052 µC P1.3 P1.4 P1.5 P1.6 P1.7

D0 D1 D2 D3 D4 D5 D6 D7 LCD

Figure 18 :Interfacing a LCD with a micro-controller 4.7.4 ADVANTAGES: LCD interfacing with 8051 is a real-world application. In recent years the LCD is finding widespread use replacing LEDs (seven segment LEDs or other multi-segment LEDs). This is due to following reasons: 1. The declining prices of LCDs.

2. The ability to display numbers, characters and graphics. This is in contrast to LEDs, which are limited to numbers and a few characters. An intelligent LCD display of two lines, 20 characters per line, which is interfaced to the 8051. 3. Incorporation of a refreshing controller into the LCD, thereby relieving the CPU to keep displaying the data. 4. Ease of programming for characters and graphics.

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4.7.5 BASIC COMMANDS of LCD: When LCD is powered up, the display should show a series of dark squares, possibly only on part of display. These characters are actually in their off state, so the contrast control should be adjusted anti-clockwise until the squares are just visible. The display module resets itself to an initial state when power is applied, which curiously the display has blanked off so that even if characters are entered, they cannot be seen. It is therefore necessary to issue a command at this point, to switch the display on. 4.7.6 PROTOTYPE CIRCUIT: For a LCD module to be used effectively in any piece of equipment, a microprocessor or a micro controller is usually required to drive it. However, before attempting to wire the two together, some initial experiments can be performed by connecting a series of switches to the pins of the module. This can be a quite beneficial step, if even you are thoroughly conversant with the workings of microprocessors. Circuit description of LCD experiment: The circuit can be wired up on a “plug-in-style” prototyping board, using dual-in-line switches for the data lines (S1-S8) A toggle switch for the RS input (S10) and a momentary action switch (or macro switch) for usage. Most of the LCD modules conform to a standard interface specification. A 14pin access is provided having eight data lines, three control lines and three power lines. The connections are laid out in one of the two common configurations, either two rows of seven pins, or a single row of 14 pins. One of the, pins are numbered on the LCD‟s print circuit board (PCB), but if not, it is quite easy to locate pin1.

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Since this pin is connected to ground, it often has a thicker PCB track, connected to it, and it is generally connected to metalwork at same point.

4.7.7 PIN DIAGRAM:

G +5V -5V

1
11

2 3

7 8

9 10 11 12 13

14 4 5

6

7 1

8

9 10 11 12 13 14 4
D2 D3 D4 D5 D6

5

6

D0 D1

D7 RS R\W EN

The LCD plays a major role in the entire operation as it has the ability to display the certain data that the user has entitled. LCD display varies from input to input as there is no specific outline for it to operate.

4.8. DC MOTOR
4.8.1 FEATURES:

Nominal voltage No load speed No load current Nominal speed Nominal torque Nominal current Stall torque Starting current Maximum efficiency

: : : : : : : : :

12v 4850rpm 26.2mA 3820rpm 29.1mNm 1.26A 137mNm 5.82A 87%
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CHARACTERISTICS: Terminal resistance Terminal inductance Torque constant Speed constant Speed/torque gradient Mechanical time constant Rotor inertia : : : : : : : 2.06Ω 0.238mH 23.5mNm/A 406rpm/V 35.6rpm/mNm 4mS 10.7gcm

4.8.2 DIAGRAM:

Figure 19 : DC Motor

4.8.3 L293D  L293D is a motor driver integrated circuit (IC).  Motor drivers act as current amplifiers since they take a low- current control signal and provide a higher-current signal. This higher current signal is used to drive the motors.  This chip is designed to control 2 DC motors  L293D has output current of 600mA  The output supply has a wide range from 4.5V to 36V
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CHAPTER 5 FIRMWARE IMPLEMENTATION OF THE PROJECT

5.1 INTRODUCTION TO KEIL MICRO VISION (IDE)
Keil an ARM Company makes C compilers, macro assemblers, real-time kernels, debuggers, simulators, integrated environments, evaluation boards, and emulators for ARM7/ARM9/Cortex-M3, XC16x/C16x/ST10, 251, and 8051 MCU families.

Keil development tools for the 8051 Microcontroller Architecture support every level of software developer from the professional applications engineer to the student just learning about embedded software development. When starting a new project, simply select the microcontroller you use from the Device Database and the µVision IDE sets all compiler, assembler, linker, and memory options for you.

Keil is a cross compiler. So first we have to understand the concept of compilers and cross compilers. After then we shall learn how to work with keil.

5.2 CONCEPT OF COMPILER
Compilers are programs used to convert a High Level Language to object code. Desktop compilers produce an output object code for the underlying microprocessor, but not for other microprocessors. I.E the programs written in one of the HLL like „C‟ will compile the code to run on the system for a particular processor like x86 (underlying microprocessor in the computer). For example compilers for Dos platform is different from the Compilers for Unix platform So if one wants to define a compiler then compiler is a program that translates source code into object code.

The compiler derives its name from the way it works, looking at the entire piece of source code and collecting and reorganizing the instruction. See there is a bit little difference between compiler and an interpreter. Interpreter just interprets whole program at a time while

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compiler analyses and execute each line of source code in succession, without looking at the entire program.

The advantage of interpreters is that they can execute a program immediately. Secondly programs produced by compilers run much faster than the same programs executed by an interpreter. However compilers require some time before an executable program emerges. Now as compilers translate source code into object code, which is unique for each type of computer, many compilers are available for the same language.

5.3 CONCEPT OF CROSS COMPILER
A cross compiler is similar to the compilers but we write a program for the target processor (like 8051 and its derivatives) on the host processors (like computer of x86). It means being in one environment you are writing a code for another environment is called cross development. And the compiler used for cross development is called cross compiler. So the definition of cross compiler is a compiler that runs on one computer but produces object code for a different type of computer.

5.4 KEIL C CROSS COMPILER
Keil is a German based Software development company. It provides several development tools like • • • • • IDE (Integrated Development environment) Project Manager Simulator Debugger C Cross Compiler, Cross Assembler, Locator/Linker

The Keil ARM tool kit includes three main tools, assembler, compiler and linker. An assembler is used to assemble the ARM assembly program. A compiler is used to compile the C source code into an object file. A linker is used to create an absolute object module suitable for our in-circuit emulator.

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5.5 Building an Application in µVision2
To build (compile, assemble, and link) an application in µVision2, you must: 1. Select Project -(forexample,166\EXAMPLES\HELLO\HELLO.UV2). 2. Select Project - Rebuild all target files or Build target.µVision2 compiles, assembles, and links the files in your project.

5.6 Creating Your Own Application in µVision2
To create a new project in µVision2, you must: 1. Select Project - New Project. 2. Select a directory and enter the name of the project file. 3. Select Project - Select Device and select an 8051, 251, or C16x/ST10 device from the Device Database™. 4. Create source files to add to the project. 5. Select Project - Targets, Groups, Files. Add/Files, select Source Group1, and add the source files to the project. 6. Select Project - Options and set the tool options. Note when you select the target device from the Device Database™ all special options are set automatically. You typically only need to configure the memory map of your target hardware. Default memory model settings are optimal for most applications. 7. Select Project - Rebuild all target files or Build target.

5.7 Debugging an Application in µVision2
To debug an application created using µVision2, you must: 1. Select Debug - Start/Stop Debug Session. 2. Use the Step toolbar buttons to single-step through your program. You may enter G, main in the Output Window to execute to the main C function. 3. Open the Serial Window using the Serial #1 button on the toolbar. Debug your program using standard options like Step, Go, Break, and so on.

5.8 Starting µVision2 and Creating a Project
µVision2 is a standard Windows application and started by clicking on the program icon. To create a new project file select from the µVision2 menu Project – New Project…. This opens a standard Windows dialog that asks you for the new project file name. We
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suggest that you use a separate folder for each project. You can simply use the icon Create New Folder in this dialog to get a new empty folder. Then select this folder and enter the file name for the new project, i.e. Project1. µVision2 creates a new project file with the name PROJECT1.UV2 which contains a default target and file group name. You can see these names in the Project.

5.9 Window – Files.
Now use from the menu Project – Select Device for Target and select a CPU for your project. The Select Device dialog box shows the µVision2 device data base. Just select the microcontroller you use. We are using for our examples the Philips 80C51RD+ CPU. This selection sets necessary tool Options for the 80C51RD+ device and simplifies in this way the tool Configuration.

5.10 Building Projects and Creating a HEX Files
Typical, the tool settings under Options – Target are all you need to start a new application. You may translate all source files and line the application with a click on the Build Target toolbar icon. When you build an application with syntax errors, µVision2 will display errors and warning messages in the Output Window – Build page. A double click on a message line opens the source file on the correct location in a µVision2 editor window. Once you have successfully generated your application you can start debugging.

After you have tested your application, it is required to create an Intel HEX file to download the software into an EPROM programmer or simulator. µVision2 creates HEX files with each build process when Create HEX files under Options for Target – Output is enabled. You may start your PROM programming utility after the make process when you specify the program under the option Run User Program #1.

5.11 CPU Simulation
µVision2 simulates up to 16 Mbytes of memory from which areas can be mapped for read, write, or code execution access. The µVision2 simulator traps and reports illegal memory accesses. In addition to memory mapping, the simulator also provides support for the integrated peripherals of the various 8051 derivatives. The on-chip peripherals of the CPU you have selected are configured from the Device.
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5.12 Database selection
You have made when you create your project target. Refer to page 58 for more Information about selecting a device. You may select and display the on-chip peripheral components using the Debug menu. You can also change the aspects of each peripheral using the controls in the dialog boxes.

5.13 Start Debugging
You start the debug mode of µVision2 with the Debug – Start/Stop Debug Session Command. Depending on the Options for Target – Debug Configuration, µVision2 will load the application program and run the startup code µVision2 saves the editor screen layout and restores the screen layout of the last debug session. If the program execution stops, µVision2 opens an editor window with the source text or shows CPU instructions in the disassembly window. The next executable statement is marked with a yellow arrow. During debugging, most editor features are still available. For example, you can use the find command or correct program errors. Program source text of your application is shown in the same windows. The µVision2 debug mode differs from the edit mode in the following aspects: _ The “Debug Menu and Debug Commands” described on page 28 are available. The additional debug windows are discussed in the following. _ The project structure or tool parameters cannot be modified. All build commands are disabled.

5.14 Disassembly Window
The Disassembly window shows your target program as mixed source and assembly program or just assembly code. A trace history of previously executed instructions may be displayed with Debug – View Trace Records. To enable the trace history, set Debug – Enable/Disable Trace Recording.

If you select the Disassembly Window as the active window all program step commands work on CPU instruction level rather than program source lines. You can select a
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text line and set or modify code breakpoints using toolbar buttons or the context menu commands. You may use the dialog Debug – Inline Assembly… to modify the CPU instructions. That allows you to correct mistakes or to make temporary changes to the target program you are debugging. Numerous example programs are included to help you get started with the most popular embedded 8051 devices. The Keil µVision Debugger accurately simulates on-chip peripherals (I²C, CAN, UART, SPI, Interrupts, I/O Ports, A/D Converter, D/A Converter, and PWM Modules) of your 8051 device. Simulation helps you understand hardware configurations and avoids time wasted on setup problems. Additionally, with simulation, you can write and test applications before target hardware is available.

5.15 EMBEDDED C
Use of embedded processors in passenger cars, mobile phones, medical equipment, aerospace systems and defense systems is widespread, and even everyday domestic appliances such as dish washers, televisions, washing machines and video recorders now include at least one such device.

Because most embedded projects have severe cost constraints, they tend to use lowcost processors like the 8051 family of devices considered in this book. These popular chips have very limited resources available most such devices have around 256 bytes (not megabytes!) of RAM, and the available processor power is around 1000 times less than that of a desktop processor. As a result, developing embedded software presents significant new challenges, even for experienced desktop programmers. If you have some programming experience - in C, C++ or Java - then this book and its accompanying CD will help make your move to the embedded world as quick and painless as possible.

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CHAPTER 6 HARDWARE TESTING
CONTINUITY TEST:

In electronics, a continuity test is the checking of an electric circuit to see if current flows (that it is in fact a complete circuit). A continuity test is performed by placing a small voltage (wired in series with an LED or noise-producing component such as a piezoelectric speaker) across the chosen path. If electron flow is inhibited by broken conductors, damaged components, or excessive resistance, the circuit is "open".

Devices that can be used to perform continuity tests include multi meters which measure current and specialized continuity testers which are cheaper, more basic devices, generally with a simple light bulb that lights up when current flows. An important application is the continuity test of a bundle of wires so as to find the two ends belonging to a particular one of these wires; there will be a negligible resistance between the "right" ends, and only between the "right" ends.

This test is the performed just after the hardware soldering and configuration has been completed. This test aims at finding any electrical open paths in the circuit after the soldering. Many a times, the electrical continuity in the circuit is lost due to improper soldering, wrong and rough handling of the PCB, improper usage of the soldering iron, component failures and presence of bugs in the circuit diagram. We use a multi meter to perform this test. We keep the multi meter in buzzer mode and connect the ground terminal of the multi meter to the ground. We connect both the terminals across the path that needs to be checked. If there is continuation then you will hear the beep sound.

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POWER ON TEST:

This test is performed to check whether the voltage at different terminals is according to the requirement or not. We take a multi meter and put it in voltage mode. Remember that this test is performed without microcontroller. Firstly, we check the output of the transformer, whether we get the required 12 v AC voltage.

Then we apply this voltage to the power supply circuit. Note that we do this test without microcontroller because if there is any excessive voltage, this may lead to damaging the controller. We check for the input to the voltage regulator i.e., are we getting an input of 12v and an output of 5v. This 5v output is given to the microcontrollers‟ 40th pin. Hence we check for the voltage level at 40th pin. Similarly, we check for the other terminals for the required voltage. In this way we can assure that the voltage at all the terminals is as per the requirement.

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CHAPTER 7 RESULT

Figure 20 : Project Kit

Figure 21 : LCD display without obstacle and with Obstacle

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 Here in this project there are two nodes each node contain ATMEGA 32 (AVR Controller), MCP2515 (CAN Controller), MCP2551 (CAN Transceiver).  The Transformers are connected to the kit by two pin connectors.  A CAN bus is used between transmitter and Receiver for transmission between them.  In first node we are interfacing GP2D12 to find the object, second node contains DC motor.  After providing the power supply LCD transmission occurs.  Hence when there is no obstacle --- LED in the GP2D12 is OFF , LCD displays NO OBSTACLE command and motor starts running.  When there is any obstacle --- LED glows in Distance sensor, LCD shows OBSTACLE SENSOR command and motor doesn‟t run.  When obstacle is removed Motor resumes to run.

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Chapter 8 CONCLUSION

This Project briefly reviewed the automobile collision avoidance problem in order to achieve safer transportation on highways. Once achieved, this will not only save lives, but result in a considerable amount of financial gains as well. In order to develop the so-called smart highways and smart cars, it is stated that the most important difference from the old practice is the fact that new design approach attempts to completely avoid collision instead of minimizing the damage by over-designing cars.

Future car collision-avoidance systems may be smart phone-based .You could stick your cell phone on the dashboard, and it would use onboard sensors] to provide the feedback needed by the system. [its

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REFERENCES
Text Books :
[1] Steven F Barrett, „„Embedded Systems Design With The Atmel AVR Microcontroller‟‟, Morgan & Claypool Publishers,2008 . [2] Jesse Russell, Ronald Cohn, „„Controller Area Network‟‟, Bookvika Publishing,2012 .

Websites :
[1] www.wikipedia.org [2] www.atmel.com [3] www.µvisionkeil.com [4] www.engineersgarage.com [5] www.authorstream.com [6] www.electronics.howstuffworks.com [7] www.allaboutcircuits.com

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APPENDIX

SOURCE CODE
#include <avr/io.h> #include <util/delay.h> #include <compat/ina90.h> #define RS 3 //portB #define RW 1 //portB #define EN 2 //portB #define setbit(Port,Bit) #define clrbit(Port,Bit) void lcd_data_out(char); void lcd_cmnd_out(char); void lcd_init(void); void lcd_busy_check(void); void lcd_string(char *ptr); void lcd_char(char byte); void lcd_clr(void); void lcd_Line1(void); void lcd_Line2(void); void lcd_Line3(void); void lcd_Line4(void); unsigned char a; /* int main(void) { //DDRC = 0xff; DDRA = 0xff; //PORTA = 0x00; DDRD = 0xff; 77 {Port |=(1<<Bit);} //Macro to set a port bit

{Port &= ~(1<<Bit);} //Macro to clear a port bit

DDRB = 0xff; lcd_init(); lcd_data_out('a'); PORTC=PORTA; while(1); }*/ void lcd_init(void) { lcd_cmnd_out(0x30); lcd_cmnd_out(0x38); lcd_cmnd_out(0x06); lcd_cmnd_out(0x0c); lcd_cmnd_out(0x01); lcd_cmnd_out(0x80); } void lcd_cmnd_out(char a) { //0_delay_ms(25); lcd_busy_check(); PORTC=a; clrbit(PORTB,RS); clrbit(PORTB,RW); setbit(PORTB,EN); _delay_ms(10); clrbit(PORTB,EN); } void lcd_data_out(char val) { lcd_busy_check(); //_delay_ms(25); PORTC=val; 78

setbit(PORTB,RS); clrbit(PORTB,RW); setbit(PORTB,EN); _delay_ms(10); clrbit(PORTB,EN); } void lcd_busy_check(void) { PORTC=0XFF; clrbit(PORTB,RS); setbit(PORTB,RW); while((PORTC&0X80)==1) { clrbit(PORTB,EN); _delay_ms(10); setbit(PORTB,EN); } } void lcd_string(char *ptr) { while(*ptr) { lcd_char(*ptr); ptr++; } } void lcd_char(char byte) { lcd_data_out(byte); } void lcd_clr(void) 79

{ lcd_cmnd_out(0x01); } void lcd_Line1(void) { lcd_cmnd_out(0x80); } void lcd_Line2(void) { lcd_cmnd_out(0xc0); } void lcd_Line3(void) { lcd_cmnd_out(0x94); } void lcd_Line4(void) { lcd_cmnd_out(0xD4); } #define MCP2515_DEFS_H #define MCP2515_DEFS_H #define SPI_RESET #define SPI_READ #define SPI_READ_RX #define SPI_WRITE #define SPI_WRITE_TX #define SPI_RTS 0xC0 0x03 0x90 0x02 0x40 0x80

#define SPI_READ_STATUS 0xA0 #define SPI_RX_STATUS #define SPI_BIT_MODIFY 0xB0 0x05

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#define RXF0SIDH #define RXF0SIDL #define RXF0EID8 #define RXF0EID0 #define RXF1SIDH #define RXF1SIDL #define RXF1EID8 #define RXF1EID0 #define RXF2SIDH #define RXF2SIDL #define RXF2EID8 #define RXF2EID0 #define BFPCTRL

0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C

#define TXRTSCTRL 0x0D #define CANSTAT #define CANCTRL #define RXF3SIDH #define RXF3SIDL #define RXF3EID8 #define RXF3EID0 #define RXF4SIDH #define RXF4SIDL #define RXF4EID8 #define RXF4EID0 #define RXF5SIDH #define RXF5SIDL #define RXF5EID8 #define RXF5EID0 #define TEC #define REC 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D

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#define RXM0SIDH #define RXM0SIDL #define RXM0EID8 #define RXM0EID0 #define RXM1SIDH #define RXM1SIDL #define RXM1EID8 #define RXM1EID0 #define CNF3 #define CNF2 #define CNF1 #define CANINTE #define CANINTF #define EFLG #define TXB0CTRL #define TXB0SIDH #define TXB0SIDL #define TXB0EID8 #define TXB0EID0 #define TXB0DLC #define TXB0D0 #define TXB0D1 #define TXB0D2 #define TXB0D3 #define TXB0D4 #define TXB0D5 #define TXB0D6 #define TXB0D7 #define TXB1CTRL #define TXB1SIDH #define TXB1SIDL

0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x40 0x41 0x42 82

#define TXB1EID8 #define TXB1EID0 #define TXB1DLC #define TXB1D0 #define TXB1D1 #define TXB1D2 #define TXB1D3 #define TXB1D4 #define TXB1D5 #define TXB1D6 #define TXB1D7 #define TXB2CTRL #define TXB2SIDH #define TXB2SIDL #define TXB2EID8 #define TXB2EID0 #define TXB2DLC #define TXB2D0 #define TXB2D1 #define TXB2D2 #define TXB2D3 #define TXB2D4 #define TXB2D5 #define TXB2D6 #define TXB2D7 #define RXB0CTRL #define RXB0SIDH #define RXB0SIDL #define RXB0EID8 #define RXB0EID0 #define RXB0DLC

0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x60 0x61 0x62 0x63 0x64 0x65 83

#define RXB0D0 #define RXB0D1 #define RXB0D2 #define RXB0D3 #define RXB0D4 #define RXB0D5 #define RXB0D6 #define RXB0D7 #define RXB1CTRL #define RXB1SIDH #define RXB1SIDL #define RXB1EID8 #define RXB1EID0 #define RXB1DLC #define RXB1D0 #define RXB1D1 #define RXB1D2 #define RXB1D3 #define RXB1D4 #define RXB1D5 #define RXB1D6 #define RXB1D7 #endif // MCP2515 #define DEFAULTS_H #define DEFAULTS_H #define P_MOSI #define P_MISO #define P_SCK B, #define MCP2515_CS #define MCP2515_INT

0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D

B,5 B,6 7 B,4 B,0

#endif // DEFAULTS_H 84

#ifndef GLOBAL_H #define GLOBAL_H // ---------------------------------------------------------------------------#define true #define false #define True #define False 1 0 1 0

// ---------------------------------------------------------------------------#define RESET(x) #define SET(x) #define SET_OUTPUT(x) _XRS(x) _XS(x) _XSO(x)

#define SET_INPUT(x) _XSI(x) #define IS_SET(x) #define PORT(x) #define DDR(x) #define PIN(x) #define _XRS(x,y) #define _XS(x,y) #define _XT(x,y) #define _XSO(x,y) #define _XSI(x,y) #define _XR(x,y) #define _port2(x) #define _ddr2(x) #define _pin2(x) #endif // GLOBAL_H _XR(x) _port2(x) _ddr2(x) _pin2(x) PORT(x) &= ~(1<<y) PORT(x) |= (1<<y) PORT(x) ^= (1<<y) DDR(x) |= (1<<y) DDR(x) &= ~(1<<y) ((PIN(x) & (1<<y)) != 0) PORT ## x DDR ## x PIN ## x

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