Chapter 6 Soc Encounter
Content
Cell-Based IC Physical Design and Verification
- SOC Encounter
張年翔
CIC 2006/02
Class Schedule
Day1
Day2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Design Flow Over View
Prepare Data
Getting Started
Importing Design
Specify Floorplan
Power Planning
Placement
Synthesize Clock Tree
Timing Analysis
Trial Route
Power Analysis
SRoute
NanoRoute
Fill Filler
Output Data
DRC
LVS
extraction/nanosim
2
Chapter1
Cell-Based Physical Design – SOC Encounter 4.2
3
Cell-Based Design Flow
Tape out
Verilog
VHDL
Post layout simulation
synthesis
DRC LVS
Gate level
netlist
Place & Route
GDSII
Routed
design
Add LVS/Nanosim text
Replace layout
4
SOC Encounter P&R flow
Netlist (verilog)
Timing constraints (sdc)
IO,P/G Placement
IO constraints
Specify floorplan
Amoeba Placement
Timing Analysis
Pre-CTS Optimization
Power Planning
Power Analysis
Clock Tree Synthesis
Timing Analysis
Post-CTS Optimization
Power Route
Output GDS, Netlist,Spef,DEF
SI Driven Route
Timing/SI Analysis
5
IO, P/G Placement
Corner1
I1
VDD
O1
Corner2
I2
O2
IOVDD
IOVSS
I3
O3
Corner3
I4
VSS
O4
Corner4
6
Specify Floorplan
Hight
Width
7
Floorplan
VDD
I1
O1
O2
I2
M2
IOVDD
IOVSS
M1
M3
O3
I3
I4
VSS
O4
8
Amoeba Placement
9
Power Planning
10
Clock Tree Synthesis
D
D
D
Q
D
Q
D
Q
D
D
D
D
Q
D
Q
D
D
Q
Q
D
Q
D
Q
D
Q
CLK
Q
Q
D
D
Q
D
Q
Q
Q
Q
Q
D
D
Q
D
D
CLK
D
Q
D
Q
D
Q
Q
Q
Q
D
Q
11
Power Analysis
12
Power Route
13
Add IO Filler
14
Routing
15
Prepare Data
Library
¾
¾
¾
¾
¾
Physical Library (LEF)
Timing Library (LIB)
Capacitance Table
Celtic Library
FireIce/Voltage Storm Library
User Data
¾ Gate-Level netlist (verilog)
¾ SDC constraints
¾ IO constraint
16
LEF Format
-- Process Technology
Layers
Design Rule
Net width
Net spacing
Contact Area
Enclosure
Metal1
Wide metal
Via1
slot
Metal2
Antenna
Current density
POLY
Parasitic
Resistance
Capacitance
17
LEF Format
-- Process Technology :
Layer define
Wide metal spacing
width
Layer Metal1
TYPE ROUTING ;
WIDTH 0.28 ;
MAXWIDTH 8 ;
AREA 0.202 ;
SPACING 0.28 ;
spacing
SPACING 0.6 RANGE 10.0 10000.0 ;
PITCH 0.66 ;
DIRECTION VERTICAL ;
THICKNESS 0.26 ;
ANTENNACUMDIFFAREARATIO 5496 ;
RESISTANCE RPERSQ 1.0e-01 ;
CAPACITANCE CPERSQDIST 1.11e-04 ;
EDGECAPACITANCE 9.1e-05 ;
END Metal1
Wide metal
18
LEF Format
-- APR technology
Unit
Site
Routing pitch
Default direction
Via rule
19
LEF Format
-- APR technology : SITE
¾ The Placement site give the placement grid of a family of
macros
a row
a site
20
Row Based PR
VDD
VSS
VDD
VSS
21
LEF Format
-- APR technology :
routing pitch , default direction
metal1 routing pitch
via
metal2 routing pitch
Horizontal Vertical
routing
routing
Metal1
Metal3
Metal5
Metal2
Metal4
Metal6
22
LEF Format
-- APR technology : via generate
To connect wide metal , create a via array to
reduce via resistance
Defines formulas for generating via arrays
Layer Metal1
Direction HORIZONTAL
OVERHANG 0.2
Layer Metal2
Direction VERTICAL
OVERHANG 0.2
Layer Via1
RECT –0.14 –0.14 0.14 0.14
SPACING 0.56 BY 0.56
Default via
Generated via
23
LEF Format
-- APR technology : via stack
Without via stack
With via stack
Higher density routing
Easier usage of upper layer
Must Follow minimum area rule
24
LEF Format
-- APR technology : Top of Stack Via
Metal3
Via23_TOS
Via12
Metal1
Meet minimum area rule
25
LEF Format
-- APR technology : Double Cut Via
Metal2
Double cut Via12
Metal1
26
LEF Format
-- APR technology : SameNet Spacing
SPACING
SAMENET Metal1 Metal1 0.23 ;
SAMENET Metal2 Metal2 0.28 STACK ;
SAMENET Metal3 Metal3 0.28 ;
SAMENET VIA12 VIA12 0.26 ;
SAMENET VIA23 VIA23 0.26 ;
SAMENET VIA12 VIA23 0.0 STACK ;
END SPACING
VIA12 and VIA23
Metal1
Metal3
VIA12 and VIA23 allow stack
Metal1
0.23
same net spacing rule
27
LEF Format
-- APR technology : Physical Macros
Define physical data for
¾
¾
¾
¾
Standard cells
I/O pads
Memories
other hard macros
describe abstract shape
¾
¾
¾
¾
Size
Class
Pins
Obstructions
28
LEF Format
-- APR technology : Physical Macros cont.
VDD
Y
B
VSS
A
MACRO ADD1
CLASS CORE ;
FOREIGN ADD1 0.0 0.0 ;
ORIGEN 0.0 0.0 ;
LEQ ADD ;
SIZE 19.8 BY 6.4 ;
SYMMETRY x y ;
SITE coresite ;
PIN A
DIRECTION INPUT ;
PORT
LAYER Metal1 ;
RECT 19.2 8.2 19.5 10.3 ;
……
END
END A
PIN B
…..
END B
OBS
……
END
END ADD1
29
LIB Format
Operating condition
¾ slow, fast, typical
Pin type
¾
¾
¾
¾
input/output/inout
function
data/clock
capacitance
Path delay
Timing constraint
¾ setup, hold, mpwh, mpwl, recovery
30
CeltIC Library
cdB model
The cdB noise library structure
SPICE Transistor Model
Noise Data for Cell 1
.subckt Transistor Description for Cell 1
Noise Data for Cell N
.subckt Transistor Description for Cell N
31
CeltIC Library
ECHO model
The UDN has pin caps, input noise threshold, output drive strength ,
and propagated noise to inject into the output driver
UDN
32
FireIce/Voltage Storm Library
Execute
¾ TimingÆFire&Ice Extract RC…
GenLib …
¾ PowerÆRun VoltageStorm…
Gen Lib …
Require
¾ All lef fie
¾ lefdef.layermap
9 lef &ICT layer mapping
9 gds &ICT layer mapping
¾ fireice technology file
9 process and layer information
33
FireIce/Voltage Storm Library
lefdef.layermap
#type
metal
metal
metal
metal
via
via
via
layer_ict
METAL_1
METAL_2
METAL_3
METAL_4
VIA_1
VIA_2
VIA_3
lefdef
lefdef
lefdef
lefdef
lefdef
lefdef
lefdef
lefdef
layer_lef
METAL1
METAL2
METAL3
METAL4
VIA12
VIA23
VIA34
34
gate-level netlist
If designing a chip , IO pads , power pads and Corner
pads should be added before the netlist is imported.
Make sure that there is no “assign” statement and no
“ *cell*” cell name in the netlist.
¾ Use the synthesis command below to remove assign statement.
set_boundary_optimization
¾ Use the synthesis commands below to remove “*cell*” cell name
define_name_rules name_rule –map {{\\*cell\\* cell”}}
change_names –hierarchy –output name_rule
35
SDC constraint
Clock constraints
Input delay / Input drive
Output delay/ Output drive
False path
Multicycle path
36
SDC constraint
-- Create Clock
create_clock [-name clock_name]
[-period period_value]
[-waveform edge_list]
[-add]
[sources]
20
I_CLK
10
CHIP
create_clock –name CLK1 –period 20 –waveform {0 10} [get_ports I_CLK]
37
SDC constraint
-- create_generated_clock
I_CLK
create_generated_clock [-add]
[-master_clock]
Top
[-name clock_name]
[-source source_pin]
[-multiply_by mult]
[-divide_by div]
[-duty_cycle percent]
D QN
[-neg]
div_clk
[-edges edge_list]
[-edge_shift edge_shift_list]
clock_root_list
create_generated_clock –name CLK2 –source [get_ports I_CLK] –divide_by 2 [get_pins DF/QN]
38
SDC constraint
-- set_clock_latency
set_clock_latency [-source]
[-early | -late]
[-min | -max]
latency
pin_or_clock_list
set_clock_latency 2 [get_clocks {CLK1}]
39
SDC constraint
-- set_clock_uncertainty
set_clock_uncertainty
[-setup | -hold]
[-from clksig_from_list]
[-to clksig_to_list]
[-rise | -fall]
float
pin_or_clock_list
set_clock_uncertainty 0.5 [get_clocks {CLK1}]
40
SDC constraint
--set_input_delay
CLK1
delay
In1 .. In7
In1
In2
: Design
:
I_CLK
set_input_delay delay_value
[-min] [-max]
[-rise] [-fall]
[-clock clock_name]
[-clock_fall]
[-add_delay]
[-network_latency_included]
[-source_latency_included]
port_pin_list
set_input_delay 1 –clock [get_clocks {CLK1}] [getports {In1}]
41
SDC constraint
--set_output_delay
CLK1
delay
Out1
Out1
:
Design
:
CLK1
CLK1
set_output_delay delay_value
[-min] [-max]
[-rise] [-fall]
[-clock clock_name]
[-add_delay]
[-network_latency_included]
[-source_latency_included]
port_pin_list
set_output_delay 1 –clock [get_clocks {CLK1}] [getports {Out1}]
42
SDC constraint
--set_drive
5KΩ
In1
3,2,4,3
In2
In1
In2
set_drive [-min] [-max]
[-rise] [-fall]
drive_strength
port_list
rise_min, rise_max, fall_min, fall_max
set_drive 1 [get_ports {In1}]
43
SDC constraint
--set_load
Out1
Out2
5pf
4~5pf
set_load [-min] [-max]
[-pin_load]
[-wire_load]
load_value
port_list
set_load 1 [get_ports {Out1}]
44
SDC constraint
--set_false_path
set_false_path [{-from | -rise_from | -fall_from} pin_list]
[{-through | -rise_through | -fall_through} pin_list]
[{-to | -rise_to | -fall_to} pin_list]
[-reset_path]
[-hold | -setup]
set_false_path –from {A}
45
SDC constraint
--set_multicycle_path
set_multicycle_path {-hold | -setup}
{-start | -end}
[-reset_path]
[{-from | -rise_from | -fall_from} pin_list]
[{-through | -rise_through | -fall_through} pin_list]
[{-to | -rise_to | -fall_to} pin_list]
set_multicycle_path 2 –from {A} –to {B}
46
Static Timing Analysis
Main steps of STA
¾ Break the design into sets of timing paths
¾ Calculate the delay of each path
¾ Check all path delays to see if the given timing constraints are met
Four types of paths
PI
Start Point
Combinational Logic
End Point
PO
47
Static Timing Analysis
AT=2
AT=5
AT=2
AT=5
3
1
9
2
1
3
2
3
1
AT=2
RAT=5
3
1
AT=5
RAT=4
AT=6
RAT=5
2
1
3
1
Path-based:
RAT=10
AT=7
RAT=7
9
10
10
11
(OK)
(OK)
(OK)
(OK)
(Fail)
(OK)
Block-based:
3
2
AT=9
RAT=8
2+2+3 = 7
2+3+1+3 =
2+3+3+2 =
5+1+1+3 =
5+1+3+2 =
5+1+2 = 8
RAT=10
AT=11
RAT=10
Critical path is determined
as collection of gates with
the same, negative slack:
In our case, we see one
critical path with slack = -1
48
Static Timing Analysis
Cell Delay
Cell Delay
Dcell(I2) = f(Dtransition(I1), Ceq)
Transition Delay
Dtransistion(I2) = g(Dtransition(I1), Ceq)
Output
Capacitance
Input Transition
0
0.5
1
0.1
0.123
0.234
0.456
0.2
0.222
0.432
0.801
Vin
I1
I2
Dtransition(I1)
index1: input transition
Index2: output capacitance
Dc Vout Dtransition(I2)
I3
Req
Dcell(I2)
Ceq
49
Static Timing Analysis
Setup time
To meet the setup time requirement:
Trequire >= Tarrival
Reg to Reg
¾ Tarrival = Tclk1+ TDFF1(clk->Q)+TPATH
¾ Trequire = Tclk2- TDFF2(setup)
Clk_source
¾ Tslack = Trequire- Tarrival
clk1
TDFF1+Tpath
Tarrival
clk2
Tsetup
Tslack
Trequire
50
Static Timing Analysis
Setup time
PI to Reg
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = Tclk1- TDFF1(setup)
¾ Tslack = Trequire- Tarrival
51
Static Timing Analysis
Setup time
Reg to PO
¾ Tarrival = Tclk1+ TDFF1(clk->Q)+TPATH
¾ Trequire = Tcycle- TPO(output delay)
¾ Tslack = Trequire- Tarrival
52
Static Timing Analysis
Setup time
PI to PO
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = Tcycle- TPO(output delay)
¾ Tslack = Trequire- Tarrival
Clk_source
TPI+Tpath
Tarrival
TPO(output delay)
Tslack
Trequire
Use set_max_delay or set_min_delay to overwrite STA constraint
53
Static Timing Analysis
hold time
To meet the hold time requirement:
Trequire <= Tarrival
Reg to Reg
¾ Tarrival = Tclk1+ TDFF1(clk->Q)+TPATH
¾ Trequire = Tclk2+ TDFF2(hold)
Clk_source
¾ Tslack = Tarrival-Trequire
clk1
TDFF1+Tpath
clk2
Thold
Tslack
Trequire
Tarrival
54
Static Timing Analysis
hold time
PI to Reg
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = Tclk+ TDFF(hold)
¾ Tslack = Tarrival-Trequire
Reg to PO
¾ Tarrival = Tclk+ TDFF(clk->Q)+TPATH
¾ Trequire = - TPO(output delay)
¾ Tslack = Tarrival-Trequire
PI to PO
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = - TPO(output delay)
¾ Tslack = Tarrival-Trequire
55
Timing exception: False path
Why are there false path constraints in a design?
¾ A path may exist in the circuit but never be used in its normal
functional operation
¾ A functional path may exist but the timing is very slow or irrelevant
¾ A block may be reused and certain signal functions are no longer
required
¾ A path may exist in the circuit but no combination of input vectors may
ever exercise it
¾ A combinational loop exists in the design that needs to be broken
56
Timing exception: multi-cycle path
Multicycle paths occur because the designer knows that the
particular logic function will not be used till a later cycle
57
IO constraint
Create an I/O assignment file manualy using the following template:
Version: 1
MicronPerUserUnit: value
Pin: pinName side |corner
Pad: padInstanceName side|corner [cellName]
Offset: length
Skip: length
Spacing: length
Keepclear: side offset1 offset2
58
IO constraint cont.
PAD_CLK
PAD_HALT
PAD_IOVDD1
PAD_IOVSS1
Version: 1
Pad: CORNER0 NW PCORNERDGZ
Pad: PAD_CLK N
Pad: PAD_HALT N
Pad: CORNER1 NE PCORNERDGZ
Pad: PAD_X1
W
Pad: PAD_X2
W
Pad: CORNER2 SW PCORNERDGZ
Pad: PAD_IOVDD1 S PVDD2DGZ
Pad: PAD_IOVSS1 S PVSS2DGZ
Pad: CORNER3 SE PCORNERDGZ
Pad: PAD_VDD1 E PVDD1DGZ
Pad: PAD_VSS1 E PVSS2DGZ
59
SSO Consideration
SSO
¾ Simultaneously Switch Outputs
SSN
¾ The noise produced by SSO buffers
DI
¾ maximum number of copies for one specific kind of I/O pad
switching from high to low simultaneously without making
ground voltage level higher than 0.8 volt for one ground pad
DF
¾ Drive Factor, DF = 1/DI
SDF
¾ Sum of Drive Factor
60
SSO Consideration cont.
Parameter of DF
¾
¾
¾
¾
operating condition
package inductance
slew-rate control IO
IO type with different drive strength
In SSO case
¾ Required number of ground pads = SDF
¾ Required number of power pads = SDF/1.1
Non SSO case (suggest)
¾ Required number of ground pads = SDF/1.5
¾ Required number of power pads = SDF/1.6
61
SDF Example
IO Type
2mA
4mA
8mA
12mA
16mA
24mA
DF Value
0.02
0.03
0.09
0.18
0.3
0.56
If a design has 20 PDB02DGZ(2mA), 10
PDD16DGZ(16mA). then
SDF = 20 x 0.02 + 10 x 0.3 = 3.4
In SSO case,
¾ number of VSS pad = 3.4 Î 4
¾ number of VDD pad = 3.4/1.1 = 3.09 Î 4
62
Tips to Reduce the Power/Ground Bounce
Don’t use stronger output buffers than what is necessary
Use slew-rate controlled outputs
Place power pad near the middle of the output buffer
Place noise sensitive I/O pads away from SSO I/Os
Place VDD and VSS pads next to clock input buffer
Consider using double bonding on the same power pad to
reduce inductance
63
Cadence On-Line document
unix% /usr/cadence/SOC/cur/tools/bin/cdsdoc &
unix% /usr/cadence/IC/cur/tools/bin/cdsdoc &
unix% /usr/cadence/LDV/cur/tools/bin/cdsdoc &
…..
html browser must be installed
do not set the proxy in html browser
64
Getting Started
Source the encounter environment:
unix% source /usr/cadence/cic_setup/soc.csh
Invoke soc encounter :
unix% encounter
Do not run in background mode. Because the terminal become the
interface of command input while running soc encounter.
The Encounter reads the following initialization files:
¾ $ENCOUNTER/etc/enc.tcl
¾ ./enc.tcl
¾ ./enc.pref.tcl
Log file:
¾ encounter.log*
¾ encounter.cmd*
65
GUI
menus
design views
tool widgets
switch bar
design display area
display control
name of
selected
object
design views
auto query
cursor coordinates
66
Tool Wedgits
Design Import
Zoom
In/Out
Fit
Hierarchy
Zoom
Previous Down/Up
Zoom
Select
Redraw
Calculate
Attribute Xwindow
Fence
Editor dump/undump
Density
Undo/Redo Design
Browser Summary Report
67
Design Views
FloorplanView
¾ displays the hierarchical module and block
guides,connection flight lines and floorplan objects
Amoeba View
¾ display the outline of modules after placement
Placement View
¾ display the detailed placements of cells, blocks.
68
Display Control
Select Bar
69
Common Used Bindkeys
Key
Action
Key
Action
q
Edit attribute
space
Select Next
f
Fits display
e
popup Edit
z
Zoom in
T
editTrim
Z
Zoom out
0-9
toggle layer[0-9] visibility
Arrows
pans design area in the
direction of the arrow
h/H
hierarchy up/down
x
clear Drc
Escape
K
Cancel
Removes all rulers
Looking for more bindkey:
Design->Preference, Binding Key
70
Import Design
9
9
DesignÆDesign Import…
Max Timing Libraries
¾ containing worst-case conditions for
setup-time analysis
Min Timing Libraries
9
¾ containing best-case conditions for
hold-time analysis
Common Timing Libraries
¾ used in both setup and hold analysis
IO Assignment File:
9
9
¾ get a IO assignment template:
DesignÆSaveÆI/O File…
9
71
Import Design -- Timing
Default Delay Pin Limit:
¾ Nets with terminal counts greater than
the specified value are assigned the
default net delay and net load entries.
9
Default Net Delay:
¾ Set the delay values for a net that
meets the pin limit default.
Default Net Load:
¾ Set the load for a net that meets the
pin limit default.
9
Input Transition Delay:
¾ Set the Primary inputs and clock nets.
72
Import Design -- Power
Specify the names of Power Nets and Ground Nets
9
9
73
Import Design – IPO/CTS
9
9
9
9
74
Import Design –IPO/CTS
Buffer Name/Footprint:
¾ specifies the buffer cell family to be inserted or swapped.
¾ required to run IPO and TD placement.
Footprint Example:
Delay Name/Footprint:
¾ required to run a fix hold time violation
Inverter Name/Footprint:
¾ required to run IPO and TD placement.
Get footprint of library cells by:
¾ TimingÆReportÆCell Footprint
For Cells:
BUFXL
BUFX1
BUFX2
BUFX3
BUFX4
BUFX8
BUFX12
BUFX16
BUFX20
Footprint : buf
75
Import Design -- Power
9
9
9
9
9
76
Global Net Connection
FloorplanÆ Gloval Net Connections…
9
9
77
Specify Floorplan
9
9
FloorplanÆSpecify Floorplan …
9
9
9
9
9
9
78
Specify Floorplan – Doube back rows
Double-back rows:
Row Spacing > 0
Row Spacing = 0
79
Core Limit, I/O Limnt
80
Place Blocks
FloorplanÆPlace Blocks/ModulesÆPlace …
automatic place blocks ( blackboxes
and partitions) and hard macros at the
top-level design.
Block halo
¾ Specifies the minimum amount of
space around blocks that is preserved
for routing.
81
Manually Place Block
Move/Resize/Reshape floorplan object.
Use functions in : FloorplanÆEdit Floorplan to
edit floorplan.
82
Add Halo To Block
FloorplanÆEdit Block Halo…
Prevent the placement of blocks and standard cells in order to reduce
congestion around a block.
Top
Left
9
9
9
9
Right
Bottom
83
Block Placement
Flow step
¾ I/O pre-placed
¾ Run quick block placement
¾ Throw away standard cell
placement
¾ Manually fit blocks
Block place issue
¾ power issue
¾ noise issue
¾ route issue
84
Block Placement
Preserve enough power pad
Create power rings around block
Follow default routing direction rule
Reserve a rounded core row area for placer
block
Default direction
85
Power Planning: Add Rings
FloorplanÆCustom Power PlanningÆAddRings
86
Power Planning: Add Rings
Use wire group to avoid
slot DRC error
9
9
9
87
Power Planning: Wire Group
9Use wire group
no interleaving
9number of bits = 2
9Use wire group
9interleaving
9number of bits = 2
88
Power Planning: Block Ring
89
Power Planning: Block Ring cont.
90
Power Planning: Block Ring cont.
Block A
Block B
Block C
Without shared ring edges
Block A
Block B
Block C
With shared ring edges
91
Power Planning: Add Stripes
9
9
92
Power Planning: Add Stripes
9
9
9
9
9
9
93
Power Planning:
Add Stripes
9
9
9
crossover
via array
94
Edit Route
Duplicate wire
Change layer
Fix wire wider than max width
Split wire Trim wire
Change width
Merge wire
Clear DRC markers
Delete wire
95
Edit Route cont.
Trim wire
Fix wire wider
than max width
96
Edit Route cont.
Move Wire
Add Wire
Cut Wire
Stretch Wire
97
Specify Scan Chain
encounter > specifyScanChain scanChainName
–start {ftname | instPinName}
– stop {ftname | instPinName}
Specifies a scan chain in a design. The actual tracing of the scan chain
is performed by the scanTrace or scanReorder command
ftname
¾ The design input/output pin name
instPinName
¾ The design instance input/output pin name
98
Scan Chain Reorder
SCAN IN
D
D
D
Q
D
Q
D
Q
D
D
Q
Q
D
D
Q
D
Q
Q
D
Q
D
Q
Q
Q
D
D
Q
D
Q
SCAN OUT
Q
Q
D
D
D
D
Q
Q
Q
D
SCAN IN
D
D
D
SCAN OUT
Q
D
Q
D
Q
Q
Q
Q
D
Q
99
Placement
PlaceÆPlace…
Prototyping : Runs quickly, but components may not be placed at legal
location.
Timing Driven:
¾ Build timing graph before place.
¾ meeting setup timing constraints
with routability.
¾ Limited IPO by
upsizeing/downsizing instances.
Reorder Scan Connection
9
9
¾ nets connected to either the
scan-in or scan-out are ignored.
Check placement after placed
¾ placeÆCheck Placement
100
Floorplan Purposes
Develop early physical layout to ensure design objective can be
archived
¾
¾
¾
¾
Minimum area for low cost
Minimum congestion for design routable
Estimate parasitic for delay calculation
Analysis power for reliability
gain early visibility into implementation issues
101
Difference Floorplan
Difference Performance
102
Wire Load After Placement
Logical
wire load after placement
103
Module Constraint
Soft Guide
Guide
Region
Fence
Soft Guide
Guide
Region
Fence
104
Guide , Region, Fence
Placement constraint
Create guide for timing issue
A critical path should not through
two different modules
The more region, the more
complicated floorplanning
105
Add Tiehi/Tielo cell
Tiehi/Tielo cell connect tiehi/tielo net to supply voltage or
ground with resister
Tiehi/Tielo cell is added for ESD protection.
Set add tiehi/tielo cell mode:
encounter> setTieHiLoMode –maxFanOut #num –maxDistance #num
PlaceÆTieHiLoÆAdd TieHiLo
106
Clock Problem
Clock problem
¾
¾
¾
¾
¾
¾
¾
Heavy clock net loading
Long clock insertion delay
Clock skew
Skew across clocks
Clock to signal coupling effect
Clock is power hungry
Electromigration on clock net
Clock is one of the most important treasure in a chip, do
not take it as other use.
107
Clock Tree Topology
108
Synthesize Clock Tree
Create Clock Tree Spec
clock spec
Specify Clock Tree
Synthesis Clock Tree
Modify
netlist
synthesis report
clock nets
routing guide
Display Clock Tree
109
Create Clock Tree Spec.
ClockÆCreate Clock Tree Spec
9
9
9
110
CTS
CTS traces the clock starting from a root pin, and stops at:
¾
¾
¾
¾
A clock pin
A D-input pin
An instance without a timing arc
A user-specified leaf pin or excluded pin
Write a CTS spec. template:
¾ specifyClockTree -template
111
CTS spec.
A CTS spec. contain the following information.
¾
¾
¾
¾
¾
¾
Timing constraint file (optional)
Naming attributes (optional)
Macro model data (optional)
Clock grouping data (optional)
Attributes used by NanoRoute routing solution (optional)
Requirement for manual CTS or automatic CTS
112
CTS spec.
--Naming Attributes Section
TimingConstraintFile filename
¾ define a timing constraint file for use during CTS
NameDelimiter delimiter
¾ name delimiter used when inserting buffers and updating clock
root and net names.
¾ NameDelimiter # Î create names clk##L3#I2
¾ default Î clk__L3_I2
UseSingleDelim YES|NO
¾ YES Î clk_L3_I2
¾ NO Î clk__L3_I2 (default)
113
CTS Spec.
-- NanoRoute Attribute Section
RouteTypeName name
RouteTypeName CK1
……
END
NonDefaultRule ruleName
¾ Specify LEF NONDEFAULTRULE to be used
PreferredExtraSpace [0-3]
¾ add space around clock wires
Shielding PGNetName
¾ Defines the power and ground net names
114
CTS Spec.
-- Macro Model Data Section
-- Clock Grouping Section
MacroModel
¾ MacroModel port R64x16/clk 90ps 80ps 90ps 80ps 17pf
¾ MacroModel pin ram1/clk 90ps 80ps 90ps 80ps 17pf
¾ delay_and_capacitance_value:
maxRise minRise maxFall minFall inputCap
ClkGroup
¾ Specifies tow or more clock domains for which you want CTS
to balance the skew.
¾ ClkGroup
+clockRootPinName1
+clockRootPinName2
…..
115
CTS Spec.
--Manually Define Clock Tree Topology
ClockNetName netName
LevelNumber number
¾ Specify the clock tree level number
LevelSpec levelNumber numberOfBuffers bufferType
¾ levelNumber
9 Specify the level number in the clock tree
¾ numberOfBuffer
9 the total number of buffers CTS should allow on the specified level
¾ Example:
LevelSpec 1 2 CLKBUFX2
LevelSpec 2 2 CLKBUFX2
End
116
CTS Spec.
-- Automatic Gated CTS Section
AutoCTSRootPin clockRootPinName
MaxDelay number{ns|ps}
MinDelay number{ns|ps}
SinkMaxTran number{ns|ps}
¾ maximum input transition time for sinks(clock pins)
BufMaxTran number{ns|ps}
¾ maximum input transition time for buffers (defalut 400)
MaxSkew number{ns|ps}
117
CTS Spec.
-- Automatic Gated CTS Section cont.
NoGating {rising|falling|NO}
¾ rising : stops tracing through a gate(include buffers and inverters) and
treats the gate as a rising-edge-triggered flip-flop clock pin.
¾ falling: stops tracing through a gate(include buffers and inverters) and
treats the gate as a falling-edge-triggered flip-flop clock pin.
¾ No: Allows CTS to trace through clock gating logic. (default)
AddDriverCell driver_cell_name
¾ Place a driver cell at the cloest possible
location to the clock port location .
118
CTS Spec.
-- Automatic Gated CTS Section cont.
MaxDepth number
RouteType routeTypeName
RouteClkNet YES|NO
¾ Specifies whether CTS routes clock nets.
PostOpt YES|NO
¾ whether CTS resizes buffers of inverters , refines placement,and
corrects routing for signal and clock wires.
¾ default YES
Buffer cell1 cell2 cell3 …
¾ Specifies the names of buffer cells to use during CTS.
119
CTS Spec.
-- Automatic Gated CTS Section cont.
LeafPin
+ pinName rising|falling
+ ……
¾ Mark the pin as a “leaf” pin for non-clock-type instances.
¾ LeafPin
+ instance1/A rising
+ instance2/A rising
A
……
LeafPort
+ portName rising|falling
+ ……
A
¾ Mark the port as a “leaf” port for non-clock-type instances
120
CTS Spec.
-- Automatic Gated CTS Section cont.
ExcludedPin
+ pinName
+ …..
ExcludedPort
+ portName
+ ……
8
¾ Treats the port as a non-leaf port, and prevents tracing and skew
analysis of the pin.
121
CTS Spec.
-- Automatic Gated CTS Section cont.
ThroughPin
+ pinName
+ …..
D
¾ Traces through the pin, even if the pin is a clock pin
PreservePin
+ inputPinName
+ …….
Preserve
¾ Preserve the netlist for the pin and pins below the pin in the
clock tree.
122
CTS Spec.
-- Automatic Gated CTS Section cont.
DefaultMaxCap capvalue
¾ CTS adheres to the following priority when using maximum
capacitance value:
9 MaxCap statements in the clock tree specification file
9 DefaultMaxCap statement in the clock tree specification file
9 Maximum capacitance values in the SDC file
9 maximum capacitance values in the .lib file
MaxCap
+ bufferName1 capValue1{pf|ff}
+ bufferName2 capValue2{pf|ff}
+ …..
¾ Buffer should be inserted if the given capacitance value is exceeded
123
Mapping from sdc to clock tree spec
Timing Constraints
Clock Tree Specs
creat_clock
AutoCTSRootPin / ClkGroup
create_generated_clock
ThroughPin
set_clock_latency
Maxdelay
set_clock_uncertainty
Maxskew
set_clock_transition
BufMaxTran / SinkMaxTran
124
Synthesize Clock Tree
ClockÆSynthesize Clock Tree
Reconvergence clock
Crossover clock
125
Clock Synthesis report
Summary report and detail report
¾
¾
¾
¾
¾
¾
number of sub trees
rise/fall insertion delay
trigger edge skew
rise/fall skew
buffer and clock pin transition time
detailed delay ranges for all buffers add to clocks
Clock nets
¾ Saves the generated clock nets
¾ used to guide clock net routing
Clock routing guide
¾ Saves the clock tree routing data
¾ used as preroute guide while running Trial Route
126
Display Clock Tree
ClockÆDisplayÆDisplay Clock Tree…
127
Display Clock Tree
--by phase delay
128
Clock Tree Browser
ClockÆClock Tree Brower
Display trig edge, rise/fall delay, rise/fall skew, input delay,
input tran of each cell.
Resize/Delete leaf cell or clock buffer
Reconnect clock tree
129
Optimization
TimingÆOptimization…
IPO
¾
¾
¾
¾
setup time
hold time
SI
DRV (Design
Rule Violation)
130
Optimization Advanced Option
131
Useful Skew
balanced clock
132
Trial Route
perform quick routing for congestion and parasitics
estimation
Prototyping:
¾ Quickly to gauge the
feasibility of netlist.
¾ components in design might
no be routed at legal location
133
Trial Route Congestion Marker
visually check the congestion
statistics.
dump congestion area:
BLOCK
¾ dumpCongesArea -all file_name
V=25/20 H=16/18
The vertical (V) overflow is 25/20 (25 tracks are required , but only 20 tracks are available) .
The Horizontal (H) overflow is 16/18 (16 tracks are required , and18 tracks are available) .
134
Trial Route Congestion Marker cont.
Level
Color
Overflow Value
1
Blue
One more track required
2
Green
Two more track required
3
Yellow
Three more track required
4
Red
Four more track required
5
Magenta
Five more track required
Grey to White
Six or more track required
6 and higher
135
Timing Analysis
TimingÆSpecify Analysis ConditionÆSpecify RC Extraction Mode …
TimingÆExtract RC…
TimingÆTiming Analysis…
No Async/Async:
¾ recovery, removal check
No Skew/Skew:
¾ check with/without clock
skew constraint
136
Slack Browser
TimingÆDebug Timing
137
Power Analysis
TimingÆExtract RC…
PowerÆEdit Pad Location…
PowerÆEdit Net Toggle Probability…
9
9
9
9
138
Statistical Power Analysis
PowerÆPower AnalysisÆStatistical …
analysis report:
9
9
¾ A power graph
¾ report contains
9 average power usage
9 worst IR drop
9 worst EM violation
9
¾ instance power file
¾ instance voltage file
¾ boundary voltage file
139
9
9
9
9
9
Simlation-Based
Power Analysis
PowerÆPower AnalysisÆ
Simulation-Based
save netlist for simulation
¾ DesignÆSaveÆNetlist…
save sdf for simulation
¾ TimingÆCalculate Delay…
simulation and dump vcd file.
¾ $dumpvars;
¾ $dumpfile(“wave.vcd”);
9
Input vcd file for power
analysis
140
VoltageStorm Anaylsis
PowerÆRun VoltageStorm…
9
9
9
9
141
Display Rail Analysis
PowerÆDisplayÆDisplay Rail Analysis Results…
142
Display IR Drop
143
Display Electron Migration
144
Display Resistor Current
145
Display Resistor Current Density
146
SRoute
Route Special Net (power/ground net)
¾
¾
¾
¾
¾
Block pins
Pad pins
Pad rings
Standard cell pins
Stripes (unconnected)
147
Add IO filler
addIoFiller
addIoFiller
addIoFiller
addIoFiller
–cell
–cell
–cell
–cell
PFILL –prefix IOFILLER
PFILL_9 –prefix IOFILLER
PFILL_1 –prefix IOFILLER
PFILL_01 –prefix IOFILLER -fillAnyGap
Connect io pad power bus by inserting IO filler.
Add from wider filler to narrower filler.
ADD IO FILLER
148
Add IO filler cont.
In order to avoid DRC error
¾ The sequence of placing fillers must be from wider fillers to
narrower ones.
¾ Only the smallest filler can use -fillAnyGap option.
149
NanoRoute
RouteÆNanoRoute
150
NanoRoute Attributes
RouteÆNanoRoute/Attributes
151
Crosstalk
Crosstalk problem are getting more serious in 0.25um and
below for:
¾ Smaller pitches
¾ Greater height/width ratio
¾ Higher design frequency
152
Crosstalk Problem
Delay problem
Aggressor
original signal
impacted signal
Noise problem
Aggressor
original signal
impacted signal
153
Crosstalk Prevention
Placement solution
¾ Insert buffer in lines
¾ Upsize driver
¾ Congestion optimization
Add buffer
Upsize
Routing solution
¾ Limit length of parallel nets
¾ Wider routing grid
¾ Shield special nets
154
CeltIC Crosstalk Analysis
SIÆRun CeltIC Crosstalk Analysis …
155
Display Noise Net
156
Antenna Effect
In a chip manufacturing process, Metal is initially deposited
so it covers the entire chip.
Then, the unneeded portions of the metal are removed by
etching, typically in plasma(charged particles).
The exposed metal collect charge from plasma and form
voltage potential.
If the voltage potential across the gate oxide becomes large
enough, the current can damage the gate oxide.
157
Antenna Ratio
Plasma
metal2
via2
+ + + + + ++ + + +
metal2
metal1
Plasma
+ + +
via1
poly gate oxide
Antenna Ratio =
Area of process antennas on a node
Area of gates to the node
158
Antenna Problem Repair
Add jumper
Add antenna cell (diode)
Add buffer
via1
poly
metal2
metal1
gate oxide
159
Add Core Filler
PlaceÆFillerÆAdd Filler…
Connect the NWELL/PWELL layer in core rows.
Insert Well contact.
Add from wider filler to narrower filler.
160
Add bonding pads (stagger IO pads only)
Linear IO pad
Stagger IO pad
Abutted Stagger IO
PIN
Logic and driver
PR boundary
Bonding matel
Inner Bonding
Outer Bonding
161
Add bonding pads (stagger IO pads only)
For the limitation of bonding wire technique , the stagger IO
pads are used in order to reduce IO pad width.
We have to add the bonding pads after APR is finished if
stagger IO pads is used. But SE does not provide a built-in
function for add bonding pads, CIC reaches this purpose by
the way of importing DEF.
CIC provides a perl script to calculate the bonding pad
location. The full flow is described in next page
162
Add bonding pads flow (stagger IO pads only)
A placed and routed
design in encounter
Export DEF
(In encounter)
routed.def
routed.def
bondPads.cmd
bondPads.cmd
addbonding.pl
addbonding.pl
addbonding.pl routed.def
(In unix terminal)
bondPads.eco
bondPads.eco
ioPad.list
ioPad.list
source bondPads.cmd
(In encounter terminal)
finish
163
Output Data
DesignÆSaveÆGDS…
DesignÆSave->Netlist…
DesignÆSave->DEF
Export GDS for DRC,LVS,LPE,and tape out.
Export Netlist for LVS and simulation.
Export DEF for reordered scan chain.
164
Stream Out map
Layer/object name layer/object type layer number data type
METAL1
NAME
NAME
NAME
NAME
VIA12
METAL2
…
…
ALL
METAL1/NET
METAL1/SPNET
METAL1/PIN
METAL1/LEFPIN
ALL
ALL
16
16
40
40
16
17
18
0
0
0
0
0
0
0
165
Chapter2
Post-Layout Verification –
DRC/ERC/LVS/LPE
Post-Layout Verification Overview
Post-Layout Verification do the following things :
¾
¾
¾
¾
DRC ( Design Rule Check )
ERC (Electrical Rule Check )
LVS (Layout versus Schematic )
LPE/PRE (Layout Parasitic Extraction / Parasitic Resistance
Extraction) and Post-Layout Simulation.
167
Post-Layout Verification Overview cont.
DRC
LVS
vdd!
i
0
1
2
zn
compare with
i
zn
gnd!
3
ERC
LPE/PRE
vdd!
clk
vdd!
short
extract
i
zn
i
zn
168
gnd!
Post-Layout Verification Overview
Layout Database
DRC
Schematic Netlist
optional
Extract Devices
ERC
LVS
Text and Graphical Error Reports
LPE/PRE
Extracted Netlist with
Parasitic Elements
Post-Layout Simulation
169
DRC flow
Prepare Layout
¾ stream in gds2
¾ add power pad text
¾ stream out gds2
Prepare command file
run DRC
View DRC error (DRC summary/RVE)
170
Prepare Layout
Stream In design
Stream In core gds2
DFII
Library
Stream In IO gds2
LEF in RAM lef
Add power Text
Stream Out
GDSII
GDSII
171
Prepare Layout: Stream In GDSII
Require:
¾ technology file
¾ display.drf
File->import->stream
9
9
9
172
Prepare Layout: Add Power Text
Add power text for LVS and Nanosim
Example: For TSMC18/artisan library
¾
¾
¾
¾
Add text DVDD for IO power pad
Add text DVSS for IO ground pad
Add text VDD for core power pad
Add text VSS for core ground pad
173
Prepare Layout: Stream Out GDSII
File->Export->stream..
9
9
9
174
Prepare command file
Prepare DRC Command file:
¾ 0.18 (CBDK018_UMC_Artisan) Calibre
9 180nm_layers.cal
9 G-DF-IXEMODE_RCMOS18-1.8V-3.3V-1P6M-MMC-Calibre-drc2.2-p1
¾ 0.18 (CBDK018_TSMC_Artisan) Calibre
9 T18drc_13a25a.drc
175
Prepare Calibre Command file
Edit runset file
LAYOUT PATH “CHIP.gds2”
LAYOUT PRIMARY “CHIP”
LAYOUT SYSTEM GDSII
…
…
…
DRC SELECT CHECK
NW.W.1
NW.W.2
…
DRC UNSELECT CHECK
NW.S.1Y
NW.S.2Y
…
DRC ICSTATION YES
INCLUDE “Calibre-drc-cur”
176
Submit Calibre Job
Submit Calibre Job
¾ calibre –drc 18nm_layers.cal
Result log
¾ CHIP.drc.summary (ASCII result)
¾ CHIP.drc.results (Graphic result)
177
Using Calibre RVE
Add in .cdsinit
setSkillPath(“. ~/ /usr/memtor/Calibre_ss/cur/shared/pkgs/icb/tools/queryskl”)
load(“calibre.skl”)
178
Using Calibre RVE
179
Using Calibre RVE
180
LVS Overview
Layout Data
Schematic Netlist
VDDclk rst cin sel GNDVDD
a<0>
b<0>
a<1>
b<1>
a<5:0>
a<2>
b<2>
b<5:0>
a<3>
b<3>
clk
a<4>
b<4>
rst
a<5>
b<5>
cin
VDD
gnd!
sel
GND s<0> s<1>. . . . .
s<5:0>
carry
GND
181
Initial Correspondence Points
Initial correspondence points establish a starting place for
layout and schematic comparison.
Create initial correspondence node pairs by
¾ adding text strings on layout database.
¾ all pins in the top of schematic netlist will be treated as an initial
corresponding node if calibre finds a text string in layout which
matches the node name in schematic.
VDD
global pin : VDD and GND
...
a<0>
...
b<0>
a<0>
b<0>
...
initial corresponding
node pairs
182
Black-Box LVS
Calibre black-box LVS
¾ One type of hierarchical LVS.
¾ Black-box LVS treats every library cell as a black box.
¾ Black-box LVS checks only the interconnections between library
cells in your design, but not cell inside.
¾ You need not know the detail layout of every library cells.
¾ Reduce CPU time.
183
Black-Box LVS vs. Transistor-Level LVS
Transistor Level LVS
VDD
i1
z
i1
z
vs.
i2
i2
GND
Black-Box LVS
inv0d1
VDD
inv0d1
i1
nd02d1
i1
z
GND
vs.
nd02d1
z
i2
184
i2
LVS flow
Prepare Layout
¾ The same as DRC Prepare Layout
Prepare Netlist
¾ v2lvs
Prepare calibre command file
run calibre LVS
View LVS error (LVS summary/RVE)
185
Prepare Netlist for Calibre LVS
Prepare Netlist
umc18lvs.v
umc18lvs.v
Verilog
Verilog
CHIP.v
CHIP.v
v2lvs
umc18lvs.spi
umc18lvs.spi
CHIP.spi
CHIP.spi
v2lvs –v CHIP.v –l umc18lvs.v –o source.spi –s umc18lvs.spi –s1 VDD –s0
GND
If a macro DRAM64x16 is used
v2lvs –v CHIP.v –l umc18lvs.v –l DRAM64x16.v –o source.spi –s
umc18lvs.spi –s DRAM64x16.spi –s1 VDD –s0 GND
186
CIC Supported Files (umc0.18)
CIC supports the following files in our cell library design
kit.
¾ Calibre LVS runset file
umc18LVS.cal
¾ Calibre LVS rule file
G-DF-MIXEDMODE_RFCMOS18-1.8V_3.3V-1P6M-MMCCALIBRE-LVS-1.2-P3.txt
¾ Black-box LVS relative files
9 pseudo spice file
umc18LVS.spi
9 pseudo verilog file
umc18LVS.v
187
CIC Supported Files (tsmc0.18)
CIC supports the following files in our cell library design
kit.
¾ Calibre LVS rule file
Calibre-lvs-cur_soce
Calibre-lvs-cur_astro
¾ Black-box LVS relative files
9 pseudo spice file
tsmc18_lvs.spi
9 pseudo verilog file
tsmc18_lvs.v
188
Black Box related file
Pseudo spice file
.GLOBAL VDD VSS
.SUBCKT AN2D1 Z A1 A2 VDD GND
.ENDS
…
Pseudo verilog file
module AN2D1 (Z, A1, A2);
output Z;
input A1;
input A2;
endmodule
…
189
Prepare command file for Calibre LVS
Edit Calibre LVS runset
LAYOUT PATH “CHIP.calibre.gds”
LAYOUT PIMARY “CHIP”
LAYOUT SYSTEM GDSII
SOURCE PATH “CHIP.spi”
SOURCE PRIMARY “CHIP”
…
…
INCLUDE “/calibre/LVS/Calibre-lvs-cur”
Edit …Calibre LVS rule file
…
LVS BOX PVSSC
LVS BOX PVSSR
LVS BOX DRAM64x4s
190
Submit Calibre LVS
calibre –lvs –spice layout.spi –hier –auto
umc18LVS.cal > lvs.log
layout
verilog
extract
v2lvs
layout.spi
source.spi
191
Check Calibre LVS Summary
OVERALL COMPAISON RESULTS
CELL SUMMARY
INFORMATION AND WARNINGS
Initial Correspondence Points
192
Check Calibre LVS Summary
OVERALL COMPAISON RESULTS
OVERALL COMPARISON RESULTS
#
#
#
#
# #
#
###################
#
#
#
CORRECT
#
#
#
###################
_
*
_
*
|
\___/
193
Check Calibre LVS Summary
CELL SUMMARY
*************************************************
CELL SUMMARY
*************************************************
Result
----------CORRECT
Layout
----------CHIP
Source
-------------CHIP
194
Check Calibre LVS Summary
INFORMATION AND WARNINGS
******************************************************************
INFORMATION AND WARNINGS
******************************************************************
Matched
Layout
----------11525
Matched
Source
----------11525
Unmatched Unmatched
Layout
Source
-------------- --------------0
0
Component
Type
--------------
1
54
79
542
……
8
----------Total Inst: 10682
1
54
79
542
……
8
----------10682
0
0
0
0
0
0
0
0
..
..
0
0
-------------- --------------0
0
ADDFHX1
ADDFHX4
ADDFX2
AND2X1
………….
XOR3X2
--------------
Nets:
Instances:
195
Check Calibre LVS Summary
Initial Correspondence Points
o Initial Correspondence Points:
Nets: DVDD VDD DGND GND I_X[2] I_X[3] I_X[4]
I_X[5] I_X[6] I_X[7] I_X[8] I_X[9] I_X[10] I_X[11]
O_SCAN_OUT O_Z[0] O_Z[1] O_Z[2] O_Z[3] I_HALT
I_RESET_ I_DoDCT I_RamBistE I_CLK I_SCAN_IN
I_SCAN_EN I_X[0] O_Z[4] I_X[1] O_Z[5] O_Z[6]
O_Z[7] O_Z[8] O_Z[9] O_Z[10] O_Z[11]
196
Check Calibre LVS Log
TEXT OBJECT FOR CONNECTIVITY EXTRACTION
PORTS
Extraction Errors and Warnings for cell “CHIP”
197
Check Calibre LVS Log
TEXT OBJECT FOR CONNECTIVITY EXTRACTION
-------------------------------------------------------------------------------TEXT OBJECTS FOR CONNECTIVITY EXTRACTION
-------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP
O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP
O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP
O_Z[5] (1164.455,372.964) 105 CHIP
O_Z[6] (1164.455,446.966) 105 CHIP O_Z[7] (1164.455,520.968) 105 CHIP
O_Z[8] (1164.455,594.97) 105 CHIP
O_Z[9] (1164.455,668.972) 105 CHIP
O_Z[10] (1164.455,742.974) 105 CHIP O_Z[11] (1164.455,816.976) 105 CHIP
……
……
198
Check Calibre LVS Log
PORTS
-------------------------------------------------------------------------------PORTS
-------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP
O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP
O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP
O_Z[5] (1164.455,372.964) 105 CHIP
……
……
199
Check Calibre LVS Log
Extraction Errors and Warnings for cell “CHIP”
Extraction Errors and Warnings for cell "CHIP"
---------------------------------------------WARNING: Short circuit - Different names on one net:
Net Id: 18
(1) name "GND" at location (330.301,216.95) on layer 102 "M2_TEXT"
(2) name "GND" at location (673.2,29.1) on layer 101 "M1_TEXT"
(3) name "VDD" at location (748.1,31.5) on layer 101 "M1_TEXT"
(4) name "VDD" at location (208.93,274.56) on layer 101 "M1_TEXT"
The name "VDD" was assigned to the net.
200
Chapter3
Post-Layout Timing Analysis
-- Nanosim
What Introduce After Place&Route?
Interconnection wire’s parasitic capacitance.
M1 to substrate
capacitance
M2
M1
M1 to M1
capacitance
M1 to M2
capacitance
vdd!
vdd!
gnd!
gnd!
202
What Introduce After Place&Route?
Interconnection wires’ parasitic resistance.
M2
M1 parasitic resistance
VIA
VIA parasitic resistance
M1
vdd!
vdd!
gnd!
gnd!
M2 parasitic resistance
203
Pre-Layout And Post-Layout Design
A pre-layout design (before P&R) and a post-layout design
(after P&R)
pre-layout
post-layout
204
Why Post-Layout Simulation?
clock skew
....
critical path delay
...
critical path delay
clk
data
. . .data
205
Post-layout Timing Analysis Flow
Gate-level
Netlist
Gate-level
Analysis
Tr.-level post-layout
timing analysis
Layout
Delay
Calculation
Extraction
Tr. Netlist
RC Network
Tr-level
Analysis
RC Network
Gate-level post-layout
timing analysis
206
Transistor-level Post-layout Simulation
layout
netlist/parasitic
extraction
Calibre LPE/PRE
SPICE netlist
simulation
pattern
Post-layout
simulation
simulation
result
Nanosim
207
What is Nanosim
Nanosim is a transistor- level timing simulation tool
for digital and mixed signal CMOS and BiCMOS
designs.
Nanosim handles voltage simulation and timing
check.
Simulation is event driven, targeting between SPICE
( circuit simulator ) and Verilog ( logic simulator ).
208
Prepare for Post-Layout Simulation
Apply for a CIC account
¾ http://www.cic.org.tw ⇒ 工作站帳號申請.
¾ fill in your personal data and your request.
Install identd program
¾ this program is used to identify yourself when you log into CIC’s
account from remote machine.
Put your DB file to CIC’s account
209
Replace Layout / LPE
Qentry
–M {LPE}
–tech {UMC18 | TSMC18 | TSMC25 | TSMC35}
–f GDSII
–T Top_cell_name
–s Ram_spce_filename
–t {ra1sd | ra1sh | ra2sd | ra2sh | rf2sh |
t18ra1sh | t18ra2sh | t18rf1sh | t18rf2sh | t18rodsh|
18ra1sh_1 | 18ra1sh_2 | 18ra2sh}
–c {UMC18 | TSMC18 | TSMC25 | TSMC35}
–i {UMC18 | TSMC18 | TSMC25 | TSMC35}
–o Netlist_file_name
Example:
¾Qentry –M LPE –tech UMC18 –f CHIP.gds –T CHIP
–s RAM1.spec –t 18ra2sh –s RAM2.spec –t 18ra1sh_1
–s RAM3.spec –t 18ra1sh_2 –c UMC18 –i UMC18 –o CHIP.netlist
Use Qstat to check the status of your job.
The result is stored in “result_#” directory.
210
Replace/LPE
INPUT
¾ gds2
¾ ram spec
OUTPUT
¾
¾
¾
¾
¾
¾
output netlist
TOP_CELL.NAME
nodename
spice.header
nanosim.run
log files for strem in, stream out, lpe
211
Running Nanosim
Qentry
–M {NANOSIM}
–n {CHIP.io}
–nspice CHIP.netlist spice.header
–nvec CHIP.vec
–m Top_cell_name
–c {CHIP.cfg}
–z {CHIP.tech.z}
–o Output_file_name
–out fsdb
–t Total_simulation_time
Example:
¾Qentry –M NANOSIM –nspice CHIP.netlist spice.header –nvec
CHIP.vec –m CHIP –c CHIP.cfg –z CHIP.tech.z –o UMC18 –t 100
Use Qstat to check the status of your job.
The result is stored in “result_#” directory.
212
Spice Header File
Spice Header File Æ Modify PVT
¾
¾
¾
¾
¾
.lib 'l18u18v.012' L18U_BJD
.lib 'l18u18v.012' L18U18V_TT
.lib 'l18u33v_g2.011' l18u33v_tt
*epic tech="voltage 3.3“
*epic tech="temperature 100"
213
Generate Nanosim Simulation Pattern
Input simulation pattern --- vec format
type vec
signal CLOCK,START,IN[7:0]
;
time
clock
start
radix
1
1
io
i
i
high 3.3
low 0.0
25
0
0
50
1
0
75
0
0
. . . . .
in<7:0>
44
ii
xx
xx
xx
214
Generate Nanosim Simulation Pattern
Input simulation pattern --- nsvt format
type nsvt
signal CLOCK,START,IN[7:0]
;
clock
start
radix
1
1
io
i
i
period 25
high 3.3
low 0.0
0
0
1
0
0
0
. . . . .
in[7:0]
44
ii
xx
xx
xx
215
Generate Nanosim Simulation Pattern
You can generate Nanosim simulation pattern from
Verilog-XL stimulus.
Verilog test bench file
integer outf;
initial begin
outf = $fopen("input.dat");
. . . . .
$fclose(outf);
$finish;
end
always @(sys_clock or start or in)
$fdisplay(outf,"%t %b %b %h",$time,sys_clock,start,in);
. . . . .
216
Nanosim Configuration File
Example Nanosim_configuration file
bus_notation [ : ]
print_node_logic ADRS[0]
print_node_logic CLK
print_node_logic DATA[0]
. . . . . .
report_node_power VDD
set_node_gnd DGND
set_node_gnd GND
set_node_v DVDD 3.3
set_node_v VDD 1.8
nodename file
ADRS[0]
ADRS[1]
. . . . . .
CLK
DATA[0]
. . . . . .
217
View Simulation Result --- nWave
NOVAS nWave
¾ a waveform viewer which support Timemill output waveform
format.
Environment setup
unix% source /usr/debussy/CIC/debussy.csh
Starting nWave
unix% nWave &
218
Load Simulation Result --- nWave
219
Select Signals --- nWave
Signals ⇒ Get Signals ...
220
Check Simulation Result --- nWave
221
Power Analysis Result
The power analysis result is stored in Nanosim simulation
log (xxx.log) file
. . . . . .
Current information calculated over the intervals:
0.00000e+00 Node: VDD
Average current
RMS current
Current
Current
Current
Current
Current
. . . . . .
peak
peak
peak
peak
peak
#1
#2
#3
#4
#5
1.00010e+03 ns
: -3.53355e+05 uA
: 3.53388e+05 uA
:
:
:
:
:
-4.54061e+05
-4.34973e+05
-3.88048e+05
-3.87280e+05
-3.84302e+05
uA
uA
uA
uA
uA
at
at
at
at
at
6.78400e+02
4.00000e-01
2.59000e+01
1.27500e+02
5.77800e+02
222
ns
ns
ns
ns
ns
- SOC Encounter
張年翔
CIC 2006/02
Class Schedule
Day1
Day2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Design Flow Over View
Prepare Data
Getting Started
Importing Design
Specify Floorplan
Power Planning
Placement
Synthesize Clock Tree
Timing Analysis
Trial Route
Power Analysis
SRoute
NanoRoute
Fill Filler
Output Data
DRC
LVS
extraction/nanosim
2
Chapter1
Cell-Based Physical Design – SOC Encounter 4.2
3
Cell-Based Design Flow
Tape out
Verilog
VHDL
Post layout simulation
synthesis
DRC LVS
Gate level
netlist
Place & Route
GDSII
Routed
design
Add LVS/Nanosim text
Replace layout
4
SOC Encounter P&R flow
Netlist (verilog)
Timing constraints (sdc)
IO,P/G Placement
IO constraints
Specify floorplan
Amoeba Placement
Timing Analysis
Pre-CTS Optimization
Power Planning
Power Analysis
Clock Tree Synthesis
Timing Analysis
Post-CTS Optimization
Power Route
Output GDS, Netlist,Spef,DEF
SI Driven Route
Timing/SI Analysis
5
IO, P/G Placement
Corner1
I1
VDD
O1
Corner2
I2
O2
IOVDD
IOVSS
I3
O3
Corner3
I4
VSS
O4
Corner4
6
Specify Floorplan
Hight
Width
7
Floorplan
VDD
I1
O1
O2
I2
M2
IOVDD
IOVSS
M1
M3
O3
I3
I4
VSS
O4
8
Amoeba Placement
9
Power Planning
10
Clock Tree Synthesis
D
D
D
Q
D
Q
D
Q
D
D
D
D
Q
D
Q
D
D
Q
Q
D
Q
D
Q
D
Q
CLK
Q
Q
D
D
Q
D
Q
Q
Q
Q
Q
D
D
Q
D
D
CLK
D
Q
D
Q
D
Q
Q
Q
Q
D
Q
11
Power Analysis
12
Power Route
13
Add IO Filler
14
Routing
15
Prepare Data
Library
¾
¾
¾
¾
¾
Physical Library (LEF)
Timing Library (LIB)
Capacitance Table
Celtic Library
FireIce/Voltage Storm Library
User Data
¾ Gate-Level netlist (verilog)
¾ SDC constraints
¾ IO constraint
16
LEF Format
-- Process Technology
Layers
Design Rule
Net width
Net spacing
Contact Area
Enclosure
Metal1
Wide metal
Via1
slot
Metal2
Antenna
Current density
POLY
Parasitic
Resistance
Capacitance
17
LEF Format
-- Process Technology :
Layer define
Wide metal spacing
width
Layer Metal1
TYPE ROUTING ;
WIDTH 0.28 ;
MAXWIDTH 8 ;
AREA 0.202 ;
SPACING 0.28 ;
spacing
SPACING 0.6 RANGE 10.0 10000.0 ;
PITCH 0.66 ;
DIRECTION VERTICAL ;
THICKNESS 0.26 ;
ANTENNACUMDIFFAREARATIO 5496 ;
RESISTANCE RPERSQ 1.0e-01 ;
CAPACITANCE CPERSQDIST 1.11e-04 ;
EDGECAPACITANCE 9.1e-05 ;
END Metal1
Wide metal
18
LEF Format
-- APR technology
Unit
Site
Routing pitch
Default direction
Via rule
19
LEF Format
-- APR technology : SITE
¾ The Placement site give the placement grid of a family of
macros
a row
a site
20
Row Based PR
VDD
VSS
VDD
VSS
21
LEF Format
-- APR technology :
routing pitch , default direction
metal1 routing pitch
via
metal2 routing pitch
Horizontal Vertical
routing
routing
Metal1
Metal3
Metal5
Metal2
Metal4
Metal6
22
LEF Format
-- APR technology : via generate
To connect wide metal , create a via array to
reduce via resistance
Defines formulas for generating via arrays
Layer Metal1
Direction HORIZONTAL
OVERHANG 0.2
Layer Metal2
Direction VERTICAL
OVERHANG 0.2
Layer Via1
RECT –0.14 –0.14 0.14 0.14
SPACING 0.56 BY 0.56
Default via
Generated via
23
LEF Format
-- APR technology : via stack
Without via stack
With via stack
Higher density routing
Easier usage of upper layer
Must Follow minimum area rule
24
LEF Format
-- APR technology : Top of Stack Via
Metal3
Via23_TOS
Via12
Metal1
Meet minimum area rule
25
LEF Format
-- APR technology : Double Cut Via
Metal2
Double cut Via12
Metal1
26
LEF Format
-- APR technology : SameNet Spacing
SPACING
SAMENET Metal1 Metal1 0.23 ;
SAMENET Metal2 Metal2 0.28 STACK ;
SAMENET Metal3 Metal3 0.28 ;
SAMENET VIA12 VIA12 0.26 ;
SAMENET VIA23 VIA23 0.26 ;
SAMENET VIA12 VIA23 0.0 STACK ;
END SPACING
VIA12 and VIA23
Metal1
Metal3
VIA12 and VIA23 allow stack
Metal1
0.23
same net spacing rule
27
LEF Format
-- APR technology : Physical Macros
Define physical data for
¾
¾
¾
¾
Standard cells
I/O pads
Memories
other hard macros
describe abstract shape
¾
¾
¾
¾
Size
Class
Pins
Obstructions
28
LEF Format
-- APR technology : Physical Macros cont.
VDD
Y
B
VSS
A
MACRO ADD1
CLASS CORE ;
FOREIGN ADD1 0.0 0.0 ;
ORIGEN 0.0 0.0 ;
LEQ ADD ;
SIZE 19.8 BY 6.4 ;
SYMMETRY x y ;
SITE coresite ;
PIN A
DIRECTION INPUT ;
PORT
LAYER Metal1 ;
RECT 19.2 8.2 19.5 10.3 ;
……
END
END A
PIN B
…..
END B
OBS
……
END
END ADD1
29
LIB Format
Operating condition
¾ slow, fast, typical
Pin type
¾
¾
¾
¾
input/output/inout
function
data/clock
capacitance
Path delay
Timing constraint
¾ setup, hold, mpwh, mpwl, recovery
30
CeltIC Library
cdB model
The cdB noise library structure
SPICE Transistor Model
Noise Data for Cell 1
.subckt Transistor Description for Cell 1
Noise Data for Cell N
.subckt Transistor Description for Cell N
31
CeltIC Library
ECHO model
The UDN has pin caps, input noise threshold, output drive strength ,
and propagated noise to inject into the output driver
UDN
32
FireIce/Voltage Storm Library
Execute
¾ TimingÆFire&Ice Extract RC…
GenLib …
¾ PowerÆRun VoltageStorm…
Gen Lib …
Require
¾ All lef fie
¾ lefdef.layermap
9 lef &ICT layer mapping
9 gds &ICT layer mapping
¾ fireice technology file
9 process and layer information
33
FireIce/Voltage Storm Library
lefdef.layermap
#type
metal
metal
metal
metal
via
via
via
layer_ict
METAL_1
METAL_2
METAL_3
METAL_4
VIA_1
VIA_2
VIA_3
lefdef
lefdef
lefdef
lefdef
lefdef
lefdef
lefdef
lefdef
layer_lef
METAL1
METAL2
METAL3
METAL4
VIA12
VIA23
VIA34
34
gate-level netlist
If designing a chip , IO pads , power pads and Corner
pads should be added before the netlist is imported.
Make sure that there is no “assign” statement and no
“ *cell*” cell name in the netlist.
¾ Use the synthesis command below to remove assign statement.
set_boundary_optimization
¾ Use the synthesis commands below to remove “*cell*” cell name
define_name_rules name_rule –map {{\\*cell\\* cell”}}
change_names –hierarchy –output name_rule
35
SDC constraint
Clock constraints
Input delay / Input drive
Output delay/ Output drive
False path
Multicycle path
36
SDC constraint
-- Create Clock
create_clock [-name clock_name]
[-period period_value]
[-waveform edge_list]
[-add]
[sources]
20
I_CLK
10
CHIP
create_clock –name CLK1 –period 20 –waveform {0 10} [get_ports I_CLK]
37
SDC constraint
-- create_generated_clock
I_CLK
create_generated_clock [-add]
[-master_clock]
Top
[-name clock_name]
[-source source_pin]
[-multiply_by mult]
[-divide_by div]
[-duty_cycle percent]
D QN
[-neg]
div_clk
[-edges edge_list]
[-edge_shift edge_shift_list]
clock_root_list
create_generated_clock –name CLK2 –source [get_ports I_CLK] –divide_by 2 [get_pins DF/QN]
38
SDC constraint
-- set_clock_latency
set_clock_latency [-source]
[-early | -late]
[-min | -max]
latency
pin_or_clock_list
set_clock_latency 2 [get_clocks {CLK1}]
39
SDC constraint
-- set_clock_uncertainty
set_clock_uncertainty
[-setup | -hold]
[-from clksig_from_list]
[-to clksig_to_list]
[-rise | -fall]
float
pin_or_clock_list
set_clock_uncertainty 0.5 [get_clocks {CLK1}]
40
SDC constraint
--set_input_delay
CLK1
delay
In1 .. In7
In1
In2
: Design
:
I_CLK
set_input_delay delay_value
[-min] [-max]
[-rise] [-fall]
[-clock clock_name]
[-clock_fall]
[-add_delay]
[-network_latency_included]
[-source_latency_included]
port_pin_list
set_input_delay 1 –clock [get_clocks {CLK1}] [getports {In1}]
41
SDC constraint
--set_output_delay
CLK1
delay
Out1
Out1
:
Design
:
CLK1
CLK1
set_output_delay delay_value
[-min] [-max]
[-rise] [-fall]
[-clock clock_name]
[-add_delay]
[-network_latency_included]
[-source_latency_included]
port_pin_list
set_output_delay 1 –clock [get_clocks {CLK1}] [getports {Out1}]
42
SDC constraint
--set_drive
5KΩ
In1
3,2,4,3
In2
In1
In2
set_drive [-min] [-max]
[-rise] [-fall]
drive_strength
port_list
rise_min, rise_max, fall_min, fall_max
set_drive 1 [get_ports {In1}]
43
SDC constraint
--set_load
Out1
Out2
5pf
4~5pf
set_load [-min] [-max]
[-pin_load]
[-wire_load]
load_value
port_list
set_load 1 [get_ports {Out1}]
44
SDC constraint
--set_false_path
set_false_path [{-from | -rise_from | -fall_from} pin_list]
[{-through | -rise_through | -fall_through} pin_list]
[{-to | -rise_to | -fall_to} pin_list]
[-reset_path]
[-hold | -setup]
set_false_path –from {A}
45
SDC constraint
--set_multicycle_path
set_multicycle_path {-hold | -setup}
{-start | -end}
[-reset_path]
[{-from | -rise_from | -fall_from} pin_list]
[{-through | -rise_through | -fall_through} pin_list]
[{-to | -rise_to | -fall_to} pin_list]
set_multicycle_path 2 –from {A} –to {B}
46
Static Timing Analysis
Main steps of STA
¾ Break the design into sets of timing paths
¾ Calculate the delay of each path
¾ Check all path delays to see if the given timing constraints are met
Four types of paths
PI
Start Point
Combinational Logic
End Point
PO
47
Static Timing Analysis
AT=2
AT=5
AT=2
AT=5
3
1
9
2
1
3
2
3
1
AT=2
RAT=5
3
1
AT=5
RAT=4
AT=6
RAT=5
2
1
3
1
Path-based:
RAT=10
AT=7
RAT=7
9
10
10
11
(OK)
(OK)
(OK)
(OK)
(Fail)
(OK)
Block-based:
3
2
AT=9
RAT=8
2+2+3 = 7
2+3+1+3 =
2+3+3+2 =
5+1+1+3 =
5+1+3+2 =
5+1+2 = 8
RAT=10
AT=11
RAT=10
Critical path is determined
as collection of gates with
the same, negative slack:
In our case, we see one
critical path with slack = -1
48
Static Timing Analysis
Cell Delay
Cell Delay
Dcell(I2) = f(Dtransition(I1), Ceq)
Transition Delay
Dtransistion(I2) = g(Dtransition(I1), Ceq)
Output
Capacitance
Input Transition
0
0.5
1
0.1
0.123
0.234
0.456
0.2
0.222
0.432
0.801
Vin
I1
I2
Dtransition(I1)
index1: input transition
Index2: output capacitance
Dc Vout Dtransition(I2)
I3
Req
Dcell(I2)
Ceq
49
Static Timing Analysis
Setup time
To meet the setup time requirement:
Trequire >= Tarrival
Reg to Reg
¾ Tarrival = Tclk1+ TDFF1(clk->Q)+TPATH
¾ Trequire = Tclk2- TDFF2(setup)
Clk_source
¾ Tslack = Trequire- Tarrival
clk1
TDFF1+Tpath
Tarrival
clk2
Tsetup
Tslack
Trequire
50
Static Timing Analysis
Setup time
PI to Reg
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = Tclk1- TDFF1(setup)
¾ Tslack = Trequire- Tarrival
51
Static Timing Analysis
Setup time
Reg to PO
¾ Tarrival = Tclk1+ TDFF1(clk->Q)+TPATH
¾ Trequire = Tcycle- TPO(output delay)
¾ Tslack = Trequire- Tarrival
52
Static Timing Analysis
Setup time
PI to PO
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = Tcycle- TPO(output delay)
¾ Tslack = Trequire- Tarrival
Clk_source
TPI+Tpath
Tarrival
TPO(output delay)
Tslack
Trequire
Use set_max_delay or set_min_delay to overwrite STA constraint
53
Static Timing Analysis
hold time
To meet the hold time requirement:
Trequire <= Tarrival
Reg to Reg
¾ Tarrival = Tclk1+ TDFF1(clk->Q)+TPATH
¾ Trequire = Tclk2+ TDFF2(hold)
Clk_source
¾ Tslack = Tarrival-Trequire
clk1
TDFF1+Tpath
clk2
Thold
Tslack
Trequire
Tarrival
54
Static Timing Analysis
hold time
PI to Reg
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = Tclk+ TDFF(hold)
¾ Tslack = Tarrival-Trequire
Reg to PO
¾ Tarrival = Tclk+ TDFF(clk->Q)+TPATH
¾ Trequire = - TPO(output delay)
¾ Tslack = Tarrival-Trequire
PI to PO
¾ Tarrival = TPI(delay)+ TPATH
¾ Trequire = - TPO(output delay)
¾ Tslack = Tarrival-Trequire
55
Timing exception: False path
Why are there false path constraints in a design?
¾ A path may exist in the circuit but never be used in its normal
functional operation
¾ A functional path may exist but the timing is very slow or irrelevant
¾ A block may be reused and certain signal functions are no longer
required
¾ A path may exist in the circuit but no combination of input vectors may
ever exercise it
¾ A combinational loop exists in the design that needs to be broken
56
Timing exception: multi-cycle path
Multicycle paths occur because the designer knows that the
particular logic function will not be used till a later cycle
57
IO constraint
Create an I/O assignment file manualy using the following template:
Version: 1
MicronPerUserUnit: value
Pin: pinName side |corner
Pad: padInstanceName side|corner [cellName]
Offset: length
Skip: length
Spacing: length
Keepclear: side offset1 offset2
58
IO constraint cont.
PAD_CLK
PAD_HALT
PAD_IOVDD1
PAD_IOVSS1
Version: 1
Pad: CORNER0 NW PCORNERDGZ
Pad: PAD_CLK N
Pad: PAD_HALT N
Pad: CORNER1 NE PCORNERDGZ
Pad: PAD_X1
W
Pad: PAD_X2
W
Pad: CORNER2 SW PCORNERDGZ
Pad: PAD_IOVDD1 S PVDD2DGZ
Pad: PAD_IOVSS1 S PVSS2DGZ
Pad: CORNER3 SE PCORNERDGZ
Pad: PAD_VDD1 E PVDD1DGZ
Pad: PAD_VSS1 E PVSS2DGZ
59
SSO Consideration
SSO
¾ Simultaneously Switch Outputs
SSN
¾ The noise produced by SSO buffers
DI
¾ maximum number of copies for one specific kind of I/O pad
switching from high to low simultaneously without making
ground voltage level higher than 0.8 volt for one ground pad
DF
¾ Drive Factor, DF = 1/DI
SDF
¾ Sum of Drive Factor
60
SSO Consideration cont.
Parameter of DF
¾
¾
¾
¾
operating condition
package inductance
slew-rate control IO
IO type with different drive strength
In SSO case
¾ Required number of ground pads = SDF
¾ Required number of power pads = SDF/1.1
Non SSO case (suggest)
¾ Required number of ground pads = SDF/1.5
¾ Required number of power pads = SDF/1.6
61
SDF Example
IO Type
2mA
4mA
8mA
12mA
16mA
24mA
DF Value
0.02
0.03
0.09
0.18
0.3
0.56
If a design has 20 PDB02DGZ(2mA), 10
PDD16DGZ(16mA). then
SDF = 20 x 0.02 + 10 x 0.3 = 3.4
In SSO case,
¾ number of VSS pad = 3.4 Î 4
¾ number of VDD pad = 3.4/1.1 = 3.09 Î 4
62
Tips to Reduce the Power/Ground Bounce
Don’t use stronger output buffers than what is necessary
Use slew-rate controlled outputs
Place power pad near the middle of the output buffer
Place noise sensitive I/O pads away from SSO I/Os
Place VDD and VSS pads next to clock input buffer
Consider using double bonding on the same power pad to
reduce inductance
63
Cadence On-Line document
unix% /usr/cadence/SOC/cur/tools/bin/cdsdoc &
unix% /usr/cadence/IC/cur/tools/bin/cdsdoc &
unix% /usr/cadence/LDV/cur/tools/bin/cdsdoc &
…..
html browser must be installed
do not set the proxy in html browser
64
Getting Started
Source the encounter environment:
unix% source /usr/cadence/cic_setup/soc.csh
Invoke soc encounter :
unix% encounter
Do not run in background mode. Because the terminal become the
interface of command input while running soc encounter.
The Encounter reads the following initialization files:
¾ $ENCOUNTER/etc/enc.tcl
¾ ./enc.tcl
¾ ./enc.pref.tcl
Log file:
¾ encounter.log*
¾ encounter.cmd*
65
GUI
menus
design views
tool widgets
switch bar
design display area
display control
name of
selected
object
design views
auto query
cursor coordinates
66
Tool Wedgits
Design Import
Zoom
In/Out
Fit
Hierarchy
Zoom
Previous Down/Up
Zoom
Select
Redraw
Calculate
Attribute Xwindow
Fence
Editor dump/undump
Density
Undo/Redo Design
Browser Summary Report
67
Design Views
FloorplanView
¾ displays the hierarchical module and block
guides,connection flight lines and floorplan objects
Amoeba View
¾ display the outline of modules after placement
Placement View
¾ display the detailed placements of cells, blocks.
68
Display Control
Select Bar
69
Common Used Bindkeys
Key
Action
Key
Action
q
Edit attribute
space
Select Next
f
Fits display
e
popup Edit
z
Zoom in
T
editTrim
Z
Zoom out
0-9
toggle layer[0-9] visibility
Arrows
pans design area in the
direction of the arrow
h/H
hierarchy up/down
x
clear Drc
Escape
K
Cancel
Removes all rulers
Looking for more bindkey:
Design->Preference, Binding Key
70
Import Design
9
9
DesignÆDesign Import…
Max Timing Libraries
¾ containing worst-case conditions for
setup-time analysis
Min Timing Libraries
9
¾ containing best-case conditions for
hold-time analysis
Common Timing Libraries
¾ used in both setup and hold analysis
IO Assignment File:
9
9
¾ get a IO assignment template:
DesignÆSaveÆI/O File…
9
71
Import Design -- Timing
Default Delay Pin Limit:
¾ Nets with terminal counts greater than
the specified value are assigned the
default net delay and net load entries.
9
Default Net Delay:
¾ Set the delay values for a net that
meets the pin limit default.
Default Net Load:
¾ Set the load for a net that meets the
pin limit default.
9
Input Transition Delay:
¾ Set the Primary inputs and clock nets.
72
Import Design -- Power
Specify the names of Power Nets and Ground Nets
9
9
73
Import Design – IPO/CTS
9
9
9
9
74
Import Design –IPO/CTS
Buffer Name/Footprint:
¾ specifies the buffer cell family to be inserted or swapped.
¾ required to run IPO and TD placement.
Footprint Example:
Delay Name/Footprint:
¾ required to run a fix hold time violation
Inverter Name/Footprint:
¾ required to run IPO and TD placement.
Get footprint of library cells by:
¾ TimingÆReportÆCell Footprint
For Cells:
BUFXL
BUFX1
BUFX2
BUFX3
BUFX4
BUFX8
BUFX12
BUFX16
BUFX20
Footprint : buf
75
Import Design -- Power
9
9
9
9
9
76
Global Net Connection
FloorplanÆ Gloval Net Connections…
9
9
77
Specify Floorplan
9
9
FloorplanÆSpecify Floorplan …
9
9
9
9
9
9
78
Specify Floorplan – Doube back rows
Double-back rows:
Row Spacing > 0
Row Spacing = 0
79
Core Limit, I/O Limnt
80
Place Blocks
FloorplanÆPlace Blocks/ModulesÆPlace …
automatic place blocks ( blackboxes
and partitions) and hard macros at the
top-level design.
Block halo
¾ Specifies the minimum amount of
space around blocks that is preserved
for routing.
81
Manually Place Block
Move/Resize/Reshape floorplan object.
Use functions in : FloorplanÆEdit Floorplan to
edit floorplan.
82
Add Halo To Block
FloorplanÆEdit Block Halo…
Prevent the placement of blocks and standard cells in order to reduce
congestion around a block.
Top
Left
9
9
9
9
Right
Bottom
83
Block Placement
Flow step
¾ I/O pre-placed
¾ Run quick block placement
¾ Throw away standard cell
placement
¾ Manually fit blocks
Block place issue
¾ power issue
¾ noise issue
¾ route issue
84
Block Placement
Preserve enough power pad
Create power rings around block
Follow default routing direction rule
Reserve a rounded core row area for placer
block
Default direction
85
Power Planning: Add Rings
FloorplanÆCustom Power PlanningÆAddRings
86
Power Planning: Add Rings
Use wire group to avoid
slot DRC error
9
9
9
87
Power Planning: Wire Group
9Use wire group
no interleaving
9number of bits = 2
9Use wire group
9interleaving
9number of bits = 2
88
Power Planning: Block Ring
89
Power Planning: Block Ring cont.
90
Power Planning: Block Ring cont.
Block A
Block B
Block C
Without shared ring edges
Block A
Block B
Block C
With shared ring edges
91
Power Planning: Add Stripes
9
9
92
Power Planning: Add Stripes
9
9
9
9
9
9
93
Power Planning:
Add Stripes
9
9
9
crossover
via array
94
Edit Route
Duplicate wire
Change layer
Fix wire wider than max width
Split wire Trim wire
Change width
Merge wire
Clear DRC markers
Delete wire
95
Edit Route cont.
Trim wire
Fix wire wider
than max width
96
Edit Route cont.
Move Wire
Add Wire
Cut Wire
Stretch Wire
97
Specify Scan Chain
encounter > specifyScanChain scanChainName
–start {ftname | instPinName}
– stop {ftname | instPinName}
Specifies a scan chain in a design. The actual tracing of the scan chain
is performed by the scanTrace or scanReorder command
ftname
¾ The design input/output pin name
instPinName
¾ The design instance input/output pin name
98
Scan Chain Reorder
SCAN IN
D
D
D
Q
D
Q
D
Q
D
D
Q
Q
D
D
Q
D
Q
Q
D
Q
D
Q
Q
Q
D
D
Q
D
Q
SCAN OUT
Q
Q
D
D
D
D
Q
Q
Q
D
SCAN IN
D
D
D
SCAN OUT
Q
D
Q
D
Q
Q
Q
Q
D
Q
99
Placement
PlaceÆPlace…
Prototyping : Runs quickly, but components may not be placed at legal
location.
Timing Driven:
¾ Build timing graph before place.
¾ meeting setup timing constraints
with routability.
¾ Limited IPO by
upsizeing/downsizing instances.
Reorder Scan Connection
9
9
¾ nets connected to either the
scan-in or scan-out are ignored.
Check placement after placed
¾ placeÆCheck Placement
100
Floorplan Purposes
Develop early physical layout to ensure design objective can be
archived
¾
¾
¾
¾
Minimum area for low cost
Minimum congestion for design routable
Estimate parasitic for delay calculation
Analysis power for reliability
gain early visibility into implementation issues
101
Difference Floorplan
Difference Performance
102
Wire Load After Placement
Logical
wire load after placement
103
Module Constraint
Soft Guide
Guide
Region
Fence
Soft Guide
Guide
Region
Fence
104
Guide , Region, Fence
Placement constraint
Create guide for timing issue
A critical path should not through
two different modules
The more region, the more
complicated floorplanning
105
Add Tiehi/Tielo cell
Tiehi/Tielo cell connect tiehi/tielo net to supply voltage or
ground with resister
Tiehi/Tielo cell is added for ESD protection.
Set add tiehi/tielo cell mode:
encounter> setTieHiLoMode –maxFanOut #num –maxDistance #num
PlaceÆTieHiLoÆAdd TieHiLo
106
Clock Problem
Clock problem
¾
¾
¾
¾
¾
¾
¾
Heavy clock net loading
Long clock insertion delay
Clock skew
Skew across clocks
Clock to signal coupling effect
Clock is power hungry
Electromigration on clock net
Clock is one of the most important treasure in a chip, do
not take it as other use.
107
Clock Tree Topology
108
Synthesize Clock Tree
Create Clock Tree Spec
clock spec
Specify Clock Tree
Synthesis Clock Tree
Modify
netlist
synthesis report
clock nets
routing guide
Display Clock Tree
109
Create Clock Tree Spec.
ClockÆCreate Clock Tree Spec
9
9
9
110
CTS
CTS traces the clock starting from a root pin, and stops at:
¾
¾
¾
¾
A clock pin
A D-input pin
An instance without a timing arc
A user-specified leaf pin or excluded pin
Write a CTS spec. template:
¾ specifyClockTree -template
111
CTS spec.
A CTS spec. contain the following information.
¾
¾
¾
¾
¾
¾
Timing constraint file (optional)
Naming attributes (optional)
Macro model data (optional)
Clock grouping data (optional)
Attributes used by NanoRoute routing solution (optional)
Requirement for manual CTS or automatic CTS
112
CTS spec.
--Naming Attributes Section
TimingConstraintFile filename
¾ define a timing constraint file for use during CTS
NameDelimiter delimiter
¾ name delimiter used when inserting buffers and updating clock
root and net names.
¾ NameDelimiter # Î create names clk##L3#I2
¾ default Î clk__L3_I2
UseSingleDelim YES|NO
¾ YES Î clk_L3_I2
¾ NO Î clk__L3_I2 (default)
113
CTS Spec.
-- NanoRoute Attribute Section
RouteTypeName name
RouteTypeName CK1
……
END
NonDefaultRule ruleName
¾ Specify LEF NONDEFAULTRULE to be used
PreferredExtraSpace [0-3]
¾ add space around clock wires
Shielding PGNetName
¾ Defines the power and ground net names
114
CTS Spec.
-- Macro Model Data Section
-- Clock Grouping Section
MacroModel
¾ MacroModel port R64x16/clk 90ps 80ps 90ps 80ps 17pf
¾ MacroModel pin ram1/clk 90ps 80ps 90ps 80ps 17pf
¾ delay_and_capacitance_value:
maxRise minRise maxFall minFall inputCap
ClkGroup
¾ Specifies tow or more clock domains for which you want CTS
to balance the skew.
¾ ClkGroup
+clockRootPinName1
+clockRootPinName2
…..
115
CTS Spec.
--Manually Define Clock Tree Topology
ClockNetName netName
LevelNumber number
¾ Specify the clock tree level number
LevelSpec levelNumber numberOfBuffers bufferType
¾ levelNumber
9 Specify the level number in the clock tree
¾ numberOfBuffer
9 the total number of buffers CTS should allow on the specified level
¾ Example:
LevelSpec 1 2 CLKBUFX2
LevelSpec 2 2 CLKBUFX2
End
116
CTS Spec.
-- Automatic Gated CTS Section
AutoCTSRootPin clockRootPinName
MaxDelay number{ns|ps}
MinDelay number{ns|ps}
SinkMaxTran number{ns|ps}
¾ maximum input transition time for sinks(clock pins)
BufMaxTran number{ns|ps}
¾ maximum input transition time for buffers (defalut 400)
MaxSkew number{ns|ps}
117
CTS Spec.
-- Automatic Gated CTS Section cont.
NoGating {rising|falling|NO}
¾ rising : stops tracing through a gate(include buffers and inverters) and
treats the gate as a rising-edge-triggered flip-flop clock pin.
¾ falling: stops tracing through a gate(include buffers and inverters) and
treats the gate as a falling-edge-triggered flip-flop clock pin.
¾ No: Allows CTS to trace through clock gating logic. (default)
AddDriverCell driver_cell_name
¾ Place a driver cell at the cloest possible
location to the clock port location .
118
CTS Spec.
-- Automatic Gated CTS Section cont.
MaxDepth number
RouteType routeTypeName
RouteClkNet YES|NO
¾ Specifies whether CTS routes clock nets.
PostOpt YES|NO
¾ whether CTS resizes buffers of inverters , refines placement,and
corrects routing for signal and clock wires.
¾ default YES
Buffer cell1 cell2 cell3 …
¾ Specifies the names of buffer cells to use during CTS.
119
CTS Spec.
-- Automatic Gated CTS Section cont.
LeafPin
+ pinName rising|falling
+ ……
¾ Mark the pin as a “leaf” pin for non-clock-type instances.
¾ LeafPin
+ instance1/A rising
+ instance2/A rising
A
……
LeafPort
+ portName rising|falling
+ ……
A
¾ Mark the port as a “leaf” port for non-clock-type instances
120
CTS Spec.
-- Automatic Gated CTS Section cont.
ExcludedPin
+ pinName
+ …..
ExcludedPort
+ portName
+ ……
8
¾ Treats the port as a non-leaf port, and prevents tracing and skew
analysis of the pin.
121
CTS Spec.
-- Automatic Gated CTS Section cont.
ThroughPin
+ pinName
+ …..
D
¾ Traces through the pin, even if the pin is a clock pin
PreservePin
+ inputPinName
+ …….
Preserve
¾ Preserve the netlist for the pin and pins below the pin in the
clock tree.
122
CTS Spec.
-- Automatic Gated CTS Section cont.
DefaultMaxCap capvalue
¾ CTS adheres to the following priority when using maximum
capacitance value:
9 MaxCap statements in the clock tree specification file
9 DefaultMaxCap statement in the clock tree specification file
9 Maximum capacitance values in the SDC file
9 maximum capacitance values in the .lib file
MaxCap
+ bufferName1 capValue1{pf|ff}
+ bufferName2 capValue2{pf|ff}
+ …..
¾ Buffer should be inserted if the given capacitance value is exceeded
123
Mapping from sdc to clock tree spec
Timing Constraints
Clock Tree Specs
creat_clock
AutoCTSRootPin / ClkGroup
create_generated_clock
ThroughPin
set_clock_latency
Maxdelay
set_clock_uncertainty
Maxskew
set_clock_transition
BufMaxTran / SinkMaxTran
124
Synthesize Clock Tree
ClockÆSynthesize Clock Tree
Reconvergence clock
Crossover clock
125
Clock Synthesis report
Summary report and detail report
¾
¾
¾
¾
¾
¾
number of sub trees
rise/fall insertion delay
trigger edge skew
rise/fall skew
buffer and clock pin transition time
detailed delay ranges for all buffers add to clocks
Clock nets
¾ Saves the generated clock nets
¾ used to guide clock net routing
Clock routing guide
¾ Saves the clock tree routing data
¾ used as preroute guide while running Trial Route
126
Display Clock Tree
ClockÆDisplayÆDisplay Clock Tree…
127
Display Clock Tree
--by phase delay
128
Clock Tree Browser
ClockÆClock Tree Brower
Display trig edge, rise/fall delay, rise/fall skew, input delay,
input tran of each cell.
Resize/Delete leaf cell or clock buffer
Reconnect clock tree
129
Optimization
TimingÆOptimization…
IPO
¾
¾
¾
¾
setup time
hold time
SI
DRV (Design
Rule Violation)
130
Optimization Advanced Option
131
Useful Skew
balanced clock
132
Trial Route
perform quick routing for congestion and parasitics
estimation
Prototyping:
¾ Quickly to gauge the
feasibility of netlist.
¾ components in design might
no be routed at legal location
133
Trial Route Congestion Marker
visually check the congestion
statistics.
dump congestion area:
BLOCK
¾ dumpCongesArea -all file_name
V=25/20 H=16/18
The vertical (V) overflow is 25/20 (25 tracks are required , but only 20 tracks are available) .
The Horizontal (H) overflow is 16/18 (16 tracks are required , and18 tracks are available) .
134
Trial Route Congestion Marker cont.
Level
Color
Overflow Value
1
Blue
One more track required
2
Green
Two more track required
3
Yellow
Three more track required
4
Red
Four more track required
5
Magenta
Five more track required
Grey to White
Six or more track required
6 and higher
135
Timing Analysis
TimingÆSpecify Analysis ConditionÆSpecify RC Extraction Mode …
TimingÆExtract RC…
TimingÆTiming Analysis…
No Async/Async:
¾ recovery, removal check
No Skew/Skew:
¾ check with/without clock
skew constraint
136
Slack Browser
TimingÆDebug Timing
137
Power Analysis
TimingÆExtract RC…
PowerÆEdit Pad Location…
PowerÆEdit Net Toggle Probability…
9
9
9
9
138
Statistical Power Analysis
PowerÆPower AnalysisÆStatistical …
analysis report:
9
9
¾ A power graph
¾ report contains
9 average power usage
9 worst IR drop
9 worst EM violation
9
¾ instance power file
¾ instance voltage file
¾ boundary voltage file
139
9
9
9
9
9
Simlation-Based
Power Analysis
PowerÆPower AnalysisÆ
Simulation-Based
save netlist for simulation
¾ DesignÆSaveÆNetlist…
save sdf for simulation
¾ TimingÆCalculate Delay…
simulation and dump vcd file.
¾ $dumpvars;
¾ $dumpfile(“wave.vcd”);
9
Input vcd file for power
analysis
140
VoltageStorm Anaylsis
PowerÆRun VoltageStorm…
9
9
9
9
141
Display Rail Analysis
PowerÆDisplayÆDisplay Rail Analysis Results…
142
Display IR Drop
143
Display Electron Migration
144
Display Resistor Current
145
Display Resistor Current Density
146
SRoute
Route Special Net (power/ground net)
¾
¾
¾
¾
¾
Block pins
Pad pins
Pad rings
Standard cell pins
Stripes (unconnected)
147
Add IO filler
addIoFiller
addIoFiller
addIoFiller
addIoFiller
–cell
–cell
–cell
–cell
PFILL –prefix IOFILLER
PFILL_9 –prefix IOFILLER
PFILL_1 –prefix IOFILLER
PFILL_01 –prefix IOFILLER -fillAnyGap
Connect io pad power bus by inserting IO filler.
Add from wider filler to narrower filler.
ADD IO FILLER
148
Add IO filler cont.
In order to avoid DRC error
¾ The sequence of placing fillers must be from wider fillers to
narrower ones.
¾ Only the smallest filler can use -fillAnyGap option.
149
NanoRoute
RouteÆNanoRoute
150
NanoRoute Attributes
RouteÆNanoRoute/Attributes
151
Crosstalk
Crosstalk problem are getting more serious in 0.25um and
below for:
¾ Smaller pitches
¾ Greater height/width ratio
¾ Higher design frequency
152
Crosstalk Problem
Delay problem
Aggressor
original signal
impacted signal
Noise problem
Aggressor
original signal
impacted signal
153
Crosstalk Prevention
Placement solution
¾ Insert buffer in lines
¾ Upsize driver
¾ Congestion optimization
Add buffer
Upsize
Routing solution
¾ Limit length of parallel nets
¾ Wider routing grid
¾ Shield special nets
154
CeltIC Crosstalk Analysis
SIÆRun CeltIC Crosstalk Analysis …
155
Display Noise Net
156
Antenna Effect
In a chip manufacturing process, Metal is initially deposited
so it covers the entire chip.
Then, the unneeded portions of the metal are removed by
etching, typically in plasma(charged particles).
The exposed metal collect charge from plasma and form
voltage potential.
If the voltage potential across the gate oxide becomes large
enough, the current can damage the gate oxide.
157
Antenna Ratio
Plasma
metal2
via2
+ + + + + ++ + + +
metal2
metal1
Plasma
+ + +
via1
poly gate oxide
Antenna Ratio =
Area of process antennas on a node
Area of gates to the node
158
Antenna Problem Repair
Add jumper
Add antenna cell (diode)
Add buffer
via1
poly
metal2
metal1
gate oxide
159
Add Core Filler
PlaceÆFillerÆAdd Filler…
Connect the NWELL/PWELL layer in core rows.
Insert Well contact.
Add from wider filler to narrower filler.
160
Add bonding pads (stagger IO pads only)
Linear IO pad
Stagger IO pad
Abutted Stagger IO
PIN
Logic and driver
PR boundary
Bonding matel
Inner Bonding
Outer Bonding
161
Add bonding pads (stagger IO pads only)
For the limitation of bonding wire technique , the stagger IO
pads are used in order to reduce IO pad width.
We have to add the bonding pads after APR is finished if
stagger IO pads is used. But SE does not provide a built-in
function for add bonding pads, CIC reaches this purpose by
the way of importing DEF.
CIC provides a perl script to calculate the bonding pad
location. The full flow is described in next page
162
Add bonding pads flow (stagger IO pads only)
A placed and routed
design in encounter
Export DEF
(In encounter)
routed.def
routed.def
bondPads.cmd
bondPads.cmd
addbonding.pl
addbonding.pl
addbonding.pl routed.def
(In unix terminal)
bondPads.eco
bondPads.eco
ioPad.list
ioPad.list
source bondPads.cmd
(In encounter terminal)
finish
163
Output Data
DesignÆSaveÆGDS…
DesignÆSave->Netlist…
DesignÆSave->DEF
Export GDS for DRC,LVS,LPE,and tape out.
Export Netlist for LVS and simulation.
Export DEF for reordered scan chain.
164
Stream Out map
Layer/object name layer/object type layer number data type
METAL1
NAME
NAME
NAME
NAME
VIA12
METAL2
…
…
ALL
METAL1/NET
METAL1/SPNET
METAL1/PIN
METAL1/LEFPIN
ALL
ALL
16
16
40
40
16
17
18
0
0
0
0
0
0
0
165
Chapter2
Post-Layout Verification –
DRC/ERC/LVS/LPE
Post-Layout Verification Overview
Post-Layout Verification do the following things :
¾
¾
¾
¾
DRC ( Design Rule Check )
ERC (Electrical Rule Check )
LVS (Layout versus Schematic )
LPE/PRE (Layout Parasitic Extraction / Parasitic Resistance
Extraction) and Post-Layout Simulation.
167
Post-Layout Verification Overview cont.
DRC
LVS
vdd!
i
0
1
2
zn
compare with
i
zn
gnd!
3
ERC
LPE/PRE
vdd!
clk
vdd!
short
extract
i
zn
i
zn
168
gnd!
Post-Layout Verification Overview
Layout Database
DRC
Schematic Netlist
optional
Extract Devices
ERC
LVS
Text and Graphical Error Reports
LPE/PRE
Extracted Netlist with
Parasitic Elements
Post-Layout Simulation
169
DRC flow
Prepare Layout
¾ stream in gds2
¾ add power pad text
¾ stream out gds2
Prepare command file
run DRC
View DRC error (DRC summary/RVE)
170
Prepare Layout
Stream In design
Stream In core gds2
DFII
Library
Stream In IO gds2
LEF in RAM lef
Add power Text
Stream Out
GDSII
GDSII
171
Prepare Layout: Stream In GDSII
Require:
¾ technology file
¾ display.drf
File->import->stream
9
9
9
172
Prepare Layout: Add Power Text
Add power text for LVS and Nanosim
Example: For TSMC18/artisan library
¾
¾
¾
¾
Add text DVDD for IO power pad
Add text DVSS for IO ground pad
Add text VDD for core power pad
Add text VSS for core ground pad
173
Prepare Layout: Stream Out GDSII
File->Export->stream..
9
9
9
174
Prepare command file
Prepare DRC Command file:
¾ 0.18 (CBDK018_UMC_Artisan) Calibre
9 180nm_layers.cal
9 G-DF-IXEMODE_RCMOS18-1.8V-3.3V-1P6M-MMC-Calibre-drc2.2-p1
¾ 0.18 (CBDK018_TSMC_Artisan) Calibre
9 T18drc_13a25a.drc
175
Prepare Calibre Command file
Edit runset file
LAYOUT PATH “CHIP.gds2”
LAYOUT PRIMARY “CHIP”
LAYOUT SYSTEM GDSII
…
…
…
DRC SELECT CHECK
NW.W.1
NW.W.2
…
DRC UNSELECT CHECK
NW.S.1Y
NW.S.2Y
…
DRC ICSTATION YES
INCLUDE “Calibre-drc-cur”
176
Submit Calibre Job
Submit Calibre Job
¾ calibre –drc 18nm_layers.cal
Result log
¾ CHIP.drc.summary (ASCII result)
¾ CHIP.drc.results (Graphic result)
177
Using Calibre RVE
Add in .cdsinit
setSkillPath(“. ~/ /usr/memtor/Calibre_ss/cur/shared/pkgs/icb/tools/queryskl”)
load(“calibre.skl”)
178
Using Calibre RVE
179
Using Calibre RVE
180
LVS Overview
Layout Data
Schematic Netlist
VDDclk rst cin sel GNDVDD
a<0>
b<0>
a<1>
b<1>
a<5:0>
a<2>
b<2>
b<5:0>
a<3>
b<3>
clk
a<4>
b<4>
rst
a<5>
b<5>
cin
VDD
gnd!
sel
GND s<0> s<1>. . . . .
s<5:0>
carry
GND
181
Initial Correspondence Points
Initial correspondence points establish a starting place for
layout and schematic comparison.
Create initial correspondence node pairs by
¾ adding text strings on layout database.
¾ all pins in the top of schematic netlist will be treated as an initial
corresponding node if calibre finds a text string in layout which
matches the node name in schematic.
VDD
global pin : VDD and GND
...
a<0>
...
b<0>
a<0>
b<0>
...
initial corresponding
node pairs
182
Black-Box LVS
Calibre black-box LVS
¾ One type of hierarchical LVS.
¾ Black-box LVS treats every library cell as a black box.
¾ Black-box LVS checks only the interconnections between library
cells in your design, but not cell inside.
¾ You need not know the detail layout of every library cells.
¾ Reduce CPU time.
183
Black-Box LVS vs. Transistor-Level LVS
Transistor Level LVS
VDD
i1
z
i1
z
vs.
i2
i2
GND
Black-Box LVS
inv0d1
VDD
inv0d1
i1
nd02d1
i1
z
GND
vs.
nd02d1
z
i2
184
i2
LVS flow
Prepare Layout
¾ The same as DRC Prepare Layout
Prepare Netlist
¾ v2lvs
Prepare calibre command file
run calibre LVS
View LVS error (LVS summary/RVE)
185
Prepare Netlist for Calibre LVS
Prepare Netlist
umc18lvs.v
umc18lvs.v
Verilog
Verilog
CHIP.v
CHIP.v
v2lvs
umc18lvs.spi
umc18lvs.spi
CHIP.spi
CHIP.spi
v2lvs –v CHIP.v –l umc18lvs.v –o source.spi –s umc18lvs.spi –s1 VDD –s0
GND
If a macro DRAM64x16 is used
v2lvs –v CHIP.v –l umc18lvs.v –l DRAM64x16.v –o source.spi –s
umc18lvs.spi –s DRAM64x16.spi –s1 VDD –s0 GND
186
CIC Supported Files (umc0.18)
CIC supports the following files in our cell library design
kit.
¾ Calibre LVS runset file
umc18LVS.cal
¾ Calibre LVS rule file
G-DF-MIXEDMODE_RFCMOS18-1.8V_3.3V-1P6M-MMCCALIBRE-LVS-1.2-P3.txt
¾ Black-box LVS relative files
9 pseudo spice file
umc18LVS.spi
9 pseudo verilog file
umc18LVS.v
187
CIC Supported Files (tsmc0.18)
CIC supports the following files in our cell library design
kit.
¾ Calibre LVS rule file
Calibre-lvs-cur_soce
Calibre-lvs-cur_astro
¾ Black-box LVS relative files
9 pseudo spice file
tsmc18_lvs.spi
9 pseudo verilog file
tsmc18_lvs.v
188
Black Box related file
Pseudo spice file
.GLOBAL VDD VSS
.SUBCKT AN2D1 Z A1 A2 VDD GND
.ENDS
…
Pseudo verilog file
module AN2D1 (Z, A1, A2);
output Z;
input A1;
input A2;
endmodule
…
189
Prepare command file for Calibre LVS
Edit Calibre LVS runset
LAYOUT PATH “CHIP.calibre.gds”
LAYOUT PIMARY “CHIP”
LAYOUT SYSTEM GDSII
SOURCE PATH “CHIP.spi”
SOURCE PRIMARY “CHIP”
…
…
INCLUDE “/calibre/LVS/Calibre-lvs-cur”
Edit …Calibre LVS rule file
…
LVS BOX PVSSC
LVS BOX PVSSR
LVS BOX DRAM64x4s
190
Submit Calibre LVS
calibre –lvs –spice layout.spi –hier –auto
umc18LVS.cal > lvs.log
layout
verilog
extract
v2lvs
layout.spi
source.spi
191
Check Calibre LVS Summary
OVERALL COMPAISON RESULTS
CELL SUMMARY
INFORMATION AND WARNINGS
Initial Correspondence Points
192
Check Calibre LVS Summary
OVERALL COMPAISON RESULTS
OVERALL COMPARISON RESULTS
#
#
#
#
# #
#
###################
#
#
#
CORRECT
#
#
#
###################
_
*
_
*
|
\___/
193
Check Calibre LVS Summary
CELL SUMMARY
*************************************************
CELL SUMMARY
*************************************************
Result
----------CORRECT
Layout
----------CHIP
Source
-------------CHIP
194
Check Calibre LVS Summary
INFORMATION AND WARNINGS
******************************************************************
INFORMATION AND WARNINGS
******************************************************************
Matched
Layout
----------11525
Matched
Source
----------11525
Unmatched Unmatched
Layout
Source
-------------- --------------0
0
Component
Type
--------------
1
54
79
542
……
8
----------Total Inst: 10682
1
54
79
542
……
8
----------10682
0
0
0
0
0
0
0
0
..
..
0
0
-------------- --------------0
0
ADDFHX1
ADDFHX4
ADDFX2
AND2X1
………….
XOR3X2
--------------
Nets:
Instances:
195
Check Calibre LVS Summary
Initial Correspondence Points
o Initial Correspondence Points:
Nets: DVDD VDD DGND GND I_X[2] I_X[3] I_X[4]
I_X[5] I_X[6] I_X[7] I_X[8] I_X[9] I_X[10] I_X[11]
O_SCAN_OUT O_Z[0] O_Z[1] O_Z[2] O_Z[3] I_HALT
I_RESET_ I_DoDCT I_RamBistE I_CLK I_SCAN_IN
I_SCAN_EN I_X[0] O_Z[4] I_X[1] O_Z[5] O_Z[6]
O_Z[7] O_Z[8] O_Z[9] O_Z[10] O_Z[11]
196
Check Calibre LVS Log
TEXT OBJECT FOR CONNECTIVITY EXTRACTION
PORTS
Extraction Errors and Warnings for cell “CHIP”
197
Check Calibre LVS Log
TEXT OBJECT FOR CONNECTIVITY EXTRACTION
-------------------------------------------------------------------------------TEXT OBJECTS FOR CONNECTIVITY EXTRACTION
-------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP
O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP
O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP
O_Z[5] (1164.455,372.964) 105 CHIP
O_Z[6] (1164.455,446.966) 105 CHIP O_Z[7] (1164.455,520.968) 105 CHIP
O_Z[8] (1164.455,594.97) 105 CHIP
O_Z[9] (1164.455,668.972) 105 CHIP
O_Z[10] (1164.455,742.974) 105 CHIP O_Z[11] (1164.455,816.976) 105 CHIP
……
……
198
Check Calibre LVS Log
PORTS
-------------------------------------------------------------------------------PORTS
-------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP
O_Z[1] (598.068,31.68) 105 CHIP
O_Z[2] (821.931,31.68) 105 CHIP
O_Z[3] (896.553,31.68) 105 CHIP
O_Z[4] (971.175,31.68) 105 CHIP
O_Z[5] (1164.455,372.964) 105 CHIP
……
……
199
Check Calibre LVS Log
Extraction Errors and Warnings for cell “CHIP”
Extraction Errors and Warnings for cell "CHIP"
---------------------------------------------WARNING: Short circuit - Different names on one net:
Net Id: 18
(1) name "GND" at location (330.301,216.95) on layer 102 "M2_TEXT"
(2) name "GND" at location (673.2,29.1) on layer 101 "M1_TEXT"
(3) name "VDD" at location (748.1,31.5) on layer 101 "M1_TEXT"
(4) name "VDD" at location (208.93,274.56) on layer 101 "M1_TEXT"
The name "VDD" was assigned to the net.
200
Chapter3
Post-Layout Timing Analysis
-- Nanosim
What Introduce After Place&Route?
Interconnection wire’s parasitic capacitance.
M1 to substrate
capacitance
M2
M1
M1 to M1
capacitance
M1 to M2
capacitance
vdd!
vdd!
gnd!
gnd!
202
What Introduce After Place&Route?
Interconnection wires’ parasitic resistance.
M2
M1 parasitic resistance
VIA
VIA parasitic resistance
M1
vdd!
vdd!
gnd!
gnd!
M2 parasitic resistance
203
Pre-Layout And Post-Layout Design
A pre-layout design (before P&R) and a post-layout design
(after P&R)
pre-layout
post-layout
204
Why Post-Layout Simulation?
clock skew
....
critical path delay
...
critical path delay
clk
data
. . .data
205
Post-layout Timing Analysis Flow
Gate-level
Netlist
Gate-level
Analysis
Tr.-level post-layout
timing analysis
Layout
Delay
Calculation
Extraction
Tr. Netlist
RC Network
Tr-level
Analysis
RC Network
Gate-level post-layout
timing analysis
206
Transistor-level Post-layout Simulation
layout
netlist/parasitic
extraction
Calibre LPE/PRE
SPICE netlist
simulation
pattern
Post-layout
simulation
simulation
result
Nanosim
207
What is Nanosim
Nanosim is a transistor- level timing simulation tool
for digital and mixed signal CMOS and BiCMOS
designs.
Nanosim handles voltage simulation and timing
check.
Simulation is event driven, targeting between SPICE
( circuit simulator ) and Verilog ( logic simulator ).
208
Prepare for Post-Layout Simulation
Apply for a CIC account
¾ http://www.cic.org.tw ⇒ 工作站帳號申請.
¾ fill in your personal data and your request.
Install identd program
¾ this program is used to identify yourself when you log into CIC’s
account from remote machine.
Put your DB file to CIC’s account
209
Replace Layout / LPE
Qentry
–M {LPE}
–tech {UMC18 | TSMC18 | TSMC25 | TSMC35}
–f GDSII
–T Top_cell_name
–s Ram_spce_filename
–t {ra1sd | ra1sh | ra2sd | ra2sh | rf2sh |
t18ra1sh | t18ra2sh | t18rf1sh | t18rf2sh | t18rodsh|
18ra1sh_1 | 18ra1sh_2 | 18ra2sh}
–c {UMC18 | TSMC18 | TSMC25 | TSMC35}
–i {UMC18 | TSMC18 | TSMC25 | TSMC35}
–o Netlist_file_name
Example:
¾Qentry –M LPE –tech UMC18 –f CHIP.gds –T CHIP
–s RAM1.spec –t 18ra2sh –s RAM2.spec –t 18ra1sh_1
–s RAM3.spec –t 18ra1sh_2 –c UMC18 –i UMC18 –o CHIP.netlist
Use Qstat to check the status of your job.
The result is stored in “result_#” directory.
210
Replace/LPE
INPUT
¾ gds2
¾ ram spec
OUTPUT
¾
¾
¾
¾
¾
¾
output netlist
TOP_CELL.NAME
nodename
spice.header
nanosim.run
log files for strem in, stream out, lpe
211
Running Nanosim
Qentry
–M {NANOSIM}
–n {CHIP.io}
–nspice CHIP.netlist spice.header
–nvec CHIP.vec
–m Top_cell_name
–c {CHIP.cfg}
–z {CHIP.tech.z}
–o Output_file_name
–out fsdb
–t Total_simulation_time
Example:
¾Qentry –M NANOSIM –nspice CHIP.netlist spice.header –nvec
CHIP.vec –m CHIP –c CHIP.cfg –z CHIP.tech.z –o UMC18 –t 100
Use Qstat to check the status of your job.
The result is stored in “result_#” directory.
212
Spice Header File
Spice Header File Æ Modify PVT
¾
¾
¾
¾
¾
.lib 'l18u18v.012' L18U_BJD
.lib 'l18u18v.012' L18U18V_TT
.lib 'l18u33v_g2.011' l18u33v_tt
*epic tech="voltage 3.3“
*epic tech="temperature 100"
213
Generate Nanosim Simulation Pattern
Input simulation pattern --- vec format
type vec
signal CLOCK,START,IN[7:0]
;
time
clock
start
radix
1
1
io
i
i
high 3.3
low 0.0
25
0
0
50
1
0
75
0
0
. . . . .
in<7:0>
44
ii
xx
xx
xx
214
Generate Nanosim Simulation Pattern
Input simulation pattern --- nsvt format
type nsvt
signal CLOCK,START,IN[7:0]
;
clock
start
radix
1
1
io
i
i
period 25
high 3.3
low 0.0
0
0
1
0
0
0
. . . . .
in[7:0]
44
ii
xx
xx
xx
215
Generate Nanosim Simulation Pattern
You can generate Nanosim simulation pattern from
Verilog-XL stimulus.
Verilog test bench file
integer outf;
initial begin
outf = $fopen("input.dat");
. . . . .
$fclose(outf);
$finish;
end
always @(sys_clock or start or in)
$fdisplay(outf,"%t %b %b %h",$time,sys_clock,start,in);
. . . . .
216
Nanosim Configuration File
Example Nanosim_configuration file
bus_notation [ : ]
print_node_logic ADRS[0]
print_node_logic CLK
print_node_logic DATA[0]
. . . . . .
report_node_power VDD
set_node_gnd DGND
set_node_gnd GND
set_node_v DVDD 3.3
set_node_v VDD 1.8
nodename file
ADRS[0]
ADRS[1]
. . . . . .
CLK
DATA[0]
. . . . . .
217
View Simulation Result --- nWave
NOVAS nWave
¾ a waveform viewer which support Timemill output waveform
format.
Environment setup
unix% source /usr/debussy/CIC/debussy.csh
Starting nWave
unix% nWave &
218
Load Simulation Result --- nWave
219
Select Signals --- nWave
Signals ⇒ Get Signals ...
220
Check Simulation Result --- nWave
221
Power Analysis Result
The power analysis result is stored in Nanosim simulation
log (xxx.log) file
. . . . . .
Current information calculated over the intervals:
0.00000e+00 Node: VDD
Average current
RMS current
Current
Current
Current
Current
Current
. . . . . .
peak
peak
peak
peak
peak
#1
#2
#3
#4
#5
1.00010e+03 ns
: -3.53355e+05 uA
: 3.53388e+05 uA
:
:
:
:
:
-4.54061e+05
-4.34973e+05
-3.88048e+05
-3.87280e+05
-3.84302e+05
uA
uA
uA
uA
uA
at
at
at
at
at
6.78400e+02
4.00000e-01
2.59000e+01
1.27500e+02
5.77800e+02
222
ns
ns
ns
ns
ns
