ECET 340 Week 2 Homework

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Pages 402-403, problem 1,3,6,7,10,12,13,14,27,36,55 1. Which technique, interrupt or polling, avoids tying down the microcontroller? 3. In the HCS12, what memory location in the interrupt vector table is assigned to Reset? 6. What memory address in the interrupt vector table is assigned to IRQ? 7. What memory address in the interrupt vector table is assigned to XIRQ 10. How many bytes of address space in the interrupt vector table are assigned to each interrupt? 12. With a single instruction, show how to disable all the peripheral interrupts. 13. With a single instruction, show how to enable the XIRQ interrupt. 14. True or falseP. Upon reset, all interrupts are enabled by the HCS12. 27. Assume that the I bit for external hardware interrupt IRQ is enabled and is low-level 402403triggered. Explain how this interrupt works when it is activated. How can we make sure that a single interrupt is not interpreted as multiple interrupts? 36. Explain the difference between the low-level and edge-triggered interrupts. 55. Explain what happens if both IRQ and XIRQ are activated at the same time.

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Pages 402-403, problem 1,3,6,7,10,12,13,14,27,36,55 1. Which technique, interrupt or polling, avoids tying down the microcontroller? 3. In the HCS12, what memory location in the interrupt vector table is assigned to Reset? 6. What memory address in the interrupt vector table is assigned to IRQ? 7. What memory address in the interrupt vector table is assigned to XIRQ 10. How many bytes of address space in the interrupt vector table are assigned to each interrupt? 12. With a single instruction, show how to disable all the peripheral interrupts. 13. With a single instruction, show how to enable the XIRQ interrupt. 14. True or falseP. Upon reset, all interrupts are enabled by the HCS12. 27. Assume that the I bit for external hardware interrupt IRQ is enabled and is low-level 402403triggered. Explain how this interrupt works when it is activated. How can we make sure that a single interrupt is not interpreted as multiple interrupts? 36. Explain the difference between the low-level and edge-triggered interrupts. 55. Explain what happens if both IRQ and XIRQ are activated at the same time.

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