Embedded Systems

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Embedded based industrial security system

Chapter-1

Embedded Systems
1.1 Introduction
An embedded system is a special-purpose system in which the
computer is completely encapsulated by the device it controls. Unlike a
general-purpose computer, such as a personal computer, an embedded
system performs pre-defined tasks, usually with very specific requirements.
Since the system is dedicated to a specific task, design engineers can
optimize it, reducing the size and cost of the product. Embedded systems are
often mass-produced, so the cost savings may be multiplied by millions of
items.
Physically, embedded systems range from portable devices such
as digital watches and MP3 players, to large stationary installations

like

traffic lights, factory controllers. Complexity varies from low, with a
single microcontroller chip, to very high with multiple units, peripherals and
networks mounted inside a large chassis or enclosure.
Embedded

systems

contain

either microcontrollers or digital

signal

processing

cores

that

processors (DSP). The

are
key

characteristic, however, is being dedicated to handle a particular task. Since
the embedded system is dedicated to specific tasks, design engineers can
optimize it to reduce the size and cost of the product and increase the
reliability and performance. Some embedded systems are mass-produced,
benefiting from economies of scale.
Robotics and automation are a part of embedded systems itself. Robot
development and automation needs study of embedded systems.
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Examples of Embedded System are
I.
II.

automatic teller machines (ATMs)
avionics, such as inertial guidance

systems,

flight

control

hardware/software and other integrated systems in aircraft and
III.
IV.
V.
VI.

missiles
cellular telephones and telephone switches
computer equipment such as routers and printers
engine controllers and antilock brake controllers for automobiles
home automation products, like thermostats, air conditioners,
sprinklers, and security monitoring systems
handheld calculators
household appliances, including microwave

VII.
VIII.
IX.
X.
XI.

ovens,

washing

machines, television sets
medical equipment
handheld computers
videogame consoles

1.2 Characteristics of Embedded System
1. Embedded systems are designed to do some specific task, rather than
be a general-purpose computer for multiple tasks.
2. The program instructions written for embedded systems are referred to
as firmware,

and

are

stored

in

read-only

memory

or Flash

memory chips.
3. The embedded systems are special purpose computer systems
designed to perform only the specific purposes. For Example- a system
designed to display numbers cannot be used to operate motors.
4. Embedded systems range from no user interface at all — dedicated
only to one task — to complex graphical user interfaces that resemble
modern computer desktop operating systems.

CHAPTER-2
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Microcontroller Families
2.1 8051
These microcontrollers are old but still trendy and most of the
companies fabricate these microcontrollers. The Intel MCS-51 is a Harvard
architecture, CISC instruction

set,

single

chip microcontroller (µC)

series

which was developed by Intel in 1980 for use in embedded systems.

2.2 PIC
Programmable Interface Controller is usually referred as PIC. They are
slightly older than 8051 microcontrollers but excel cause of their small low
pin count devices. They perform well and are affordable. The Microchip
technology fabricated the single chip microcontroller PIC with Harvard
architecture.

2.3 AVR
Advanced Version RISC.In 1996, Atmel fabricated this single chip
microcontroller with a modified Harvard Architecture. This chip is loaded with
C- compiler, Free IDE and many more features. This microcontroller is a bit
difficult for the starters to handle.

2.4 ARM
The ARM

architectures are reduced

instruction

set

computer (RISC) instruction set architectures (ISA), such as 64-bit ARMv8
and 32-bit ARMv7 and ARMv6 developed by British company ARM Holdings,
who have designed and licensed a family of computer processors that use
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these instruction set architectures; some other companies have also
designed processors that use the ARM architectures.

CHAPTER-3

8051 Microcontroller
3.1 Introduction
Circumstances that we find ourselves in today in the field of microcontr
ollers had their
beginnings in the development of technology of integrated circuits. This
development

has

made

it

possible

to store hundreds

of thousands

of transistors into one chip. That was a prerequisite for production of
microprocessors,

and

the

first

computers

were

made

by

adding

external peripherals such as memory, input-output lines, timers and other.
Further increasing of the volume of the package resulted in creation of
integration circuits.

3.2 Definition of a Microcontroller
M i c r o c o n t ro l l e r , a re s m a l l c o n t ro l l e r s . T h e y a re l i ke s i n g l e c
h i p computes that are often embedded into other systems to function as
processing/controlling unit. For example, the remote control we are
using probably has microcontrollers inside that do decoding and other
controlling functions. They are also used in automobiles, washing machines,
microwave ovens, toys etc, where automation is needed. The key features of
microcontrollers include:


High Integration of Functionality
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Microcontrollers sometimes are called single-chip computers because
they have on-chip memory and I/O circuitry and other circuitries
that



enable

them

to

function

as

small

computers without other supporting circuitry.
Microcontrollers
often
use EEPROM or

standalone
EPROM as

their storage device to allow fi eld programmability so they are
fl exible to use. Once the program is tested to be correct the
large quantities of microcontrollers can be programmed to be


used in embedded systems.
Easy to Use Assembly language is often used in microcontrollers and
since they usually follow RISC architecture, the instruction set is small.
The

development

package

of

microcontrollerso f t e n i n c l u d e s a n a s s e m b l e r , a s i m u l a t o r , a
p ro g r a m m e r t o " b u rn " t h e

chip and a

demonstration

board.

Some packages include a high level language compiler such as a C


compiler and more sophisticated libraries.
A Timer module to allow the microcontroller to perform tasks for
certain time periods.

3.3

AT89C51

AT89C51 is an 8-bit, 40 pin microcontroller that belongs to Atmel's 8051
family. ATMEL 89C51 has 4KB of Flash programmable and erasable read
only memory (PEROM) and 128 bytes of RAM. It can be erased and program
to a maximum of 1000 times.

In 40 pin AT89C51, there are four ports designated as P 1, P2, P3 and P0. All
these ports are 8-bit bi-directional ports, i.e., they can be used as both input
and output ports. Except P0 which needs external pull-ups, rest of the ports
have internal pull-ups. When 1s are written to these port pins, they are
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pulled high by the internal pull-ups and can be used as inputs. These ports
are also bit addressable and so their bits can also be accessed individually.
The main features of 8051 are:-



8-bit ALU and Accumulator,
special move

instructions),

8-bit Registers (one 16-bit register
8-bit data

bus and

with

2x16-bit address

bus/program counter/data pointer and related 8/11/16-bit operations;
hence it is mainly an 8-bit microcontroller.


Boolean processor with 17 instructions, 1-bit accumulator, 32 registers
(4 bit addressable 8-bit) and up to 144 special 1-bit addressable RAM



variables (18 bit addressable 8-bit).
4 fast switchable register banks with 8 registers each (memory





mapped).
Fast interrupt with optional register bank switching.
Interrupts with selectable priority.
128 bytes of on-chip RAM






Four 8-bit bi-directional input/output port
UART (serial port), two 16-bit Counter/timers
Power saving mode
Fully Static Operation: 0 Hz to 24 MHz

3.4

PIN DESCRIPTION OF AT89C51

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Figure 3.1: Pin Diagram

We have 4 ports in 8051 micro controller. They are port0, port1, port2, port3
which can be accessed as i/o ports. The pins of the micro controller are
explained below.
Port 0:-The P0 port is characterized by two functions. If external memory is
used then the lower address byte (addresses A0-A7) is applied on it.
Otherwise, all bits of this port are configured as inputs/outputs.
The other function is expressed when it is configured as an output.
Unlike other ports consisting of pins with built-in pull-up resistor connected
by its end to 5 V power supply, pins of this port have this resistor left out.
This apparently small difference has its consequences. When the pin is
configured as an output, it acts as an “open drain”. By applying logic 0 to a
port bit, the appropriate pin will be connected to ground (0V). By applying

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logic 1, the external output will keep on “floating”. In order to apply logic 1
(5V) on this output pin, it is necessary to built in an external pull-up resistor.

Figure 3.2:Pull up at Port 0

Pins 1-8 (Port 1) - Each of these pins can be configured as an input or an
output.
Pin 9 (Reset) - A logic one on this pin disables the microcontroller and
clears the contents of most registers. In other words, the positive voltage on
this pin resets the microcontroller. By applying logic zero to this pin, the
program starts execution from the beginning.
Pins 10- 17 (Port 3) -Similar to port 1, each of these pins can serve as
general input or output. Besides, all of them have alternative functions:
Pin 10 (RXD) - Serial asynchronous communication input or Serial
synchronous communication output.
Pin

11(TXD)

- Serial

asynchronous

communication

output

or

Serial

synchronous communication clock output.
Pin 12 (INT 0) - Interrupt 0 input
.
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Pin 13(INT 1) - Interrupt 1 input.
Pin 14(T0) - Counter 0 clock input.
Pin 15(T1) - Counter 1 clock input.
Pin 16(WR) -Write to external (additional) RAM
.
Pin 17 (RD) -Read from external RAM.
Pin 18 and 19(X1, X2) - Internal oscillator input and output. A quartz
crystal which specifies operating frequency is usually connected to these
pins. Instead of it, miniature ceramics resonators can also be used for
frequency stability. Later versions of microcontrollers operate at a frequency
of 0 Hz up to over 50 Hz.
Pin 20 (GND) - Ground.
Pin 21-28 (Port 2) - If there is no intention to use external memory then
these port pins are configured as general inputs/outputs. In case external
memory is used, the higher address byte, i.e. addresses A8-A15 will appear
on this port. Even though memory with capacity of 64Kb is not used, which
means that not all eight port bits are used for its addressing, the rest of them
are not available as inputs/outputs.
Pin 29 (PSEN) - If external ROM is used for storing program then a logic
zero (0) appears on it every time the microcontroller reads a byte from
memory.

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Pin 30 (ALE) - Prior to reading from external memory, the microcontroller
puts the lower address byte (A0-A7) on P0 and activates the ALE output.
After receiving signal from the ALE pin, the external register memorizes the
state of P0 and uses it as a memory chip address. Immediately after that, the
ALU pin is returned its previous logic state and P0 is now used as a Data Bus.
As seen, port data multiplexing is performed by means of only one additional
(and cheap) integrated circuit. In other words, this port is used for both data
and address transmission
.
Pin 31 (EA) - By applying logic zero to this pin, P2 and P3 are used for data
and address transmission with no regard to whether there is internal memory
or not. It means that even there is a program written to the microcontroller,
it will not be executed. Instead, the program written to external ROM will be
executed. By applying logic one to the EA pin, the microcontroller will use
both memories, first internal then external (if exists).
Pin 40 (Vcc) - +5V power supply.
Reset: It resets total 8051 micro controller.
RXD: It receives data in serial communication.
TXD: It transmits data in serial communication.
INT0: External interrupt for timer 0.
INT1: External interrupt for timer1
T0: Timer0.T1: Timer1.RD: To read into external memory.

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WR: To write into external memory.
XTAL1 & XTAL2: To connect the crystal oscillator.
ALE: Address latch enable which is used to access the address locationsfrom
external memory.
PSEN: Program store enable which is used for storing programmingcode into
the external memory.
EA: External Access: 64 KB of ROM is the limit for external memory
3.4.1 Crystal Circuit

Figure 3.3: Crystal circuit

XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator. Either a
quartz crystal or ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while XTAL1 is
driven as .There are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is through a divide-bytwo flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
3.4.2 Reset circuit
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RESET pin is an input and is active high (normally low).Upon applying a
high pulse to this pin, the microcontroller will reset and terminate all
activities. This is often referred to as a power-on reset. Activating a power-on
reset will cause all values in the registers to be lost.
In order for the RESET input to be effective, it must have a minimum
duration of 2 machine cycles. In other words, the high pulse must be high for
a minimum of 2 machine cycles
before it is allowed to go low.

Figure 3.4: Reset Circuit

3.5Architecture of AT89C51
3.5.1Block Diagram.
Address bus-For a device (memory or I/O) to be recognized by the CPU, it
must be assigned an address. The address assigned to a given device must
be unique. The CPU puts the address on the address bus, and the decoding
circuitry finds the device.
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Data bus-The CPU either gets data from the deviceor sends data to it.
Control bus-Provides read or write signals to the device to indicate if the
CPU is asking for information or sending it information

Figure 3.5: Block diagram of 8051

3.6 RAM ARCHITECTURE
Ram Architecture: The 8051 has a bank of 128 bytes of Internal
RAM .This Internal RAM is found on-chip o n t h e 8 0 5 1 s o i t i s t h e
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f a s t e s t RA M a v a i l a b l e , a n d i t i s a l s o t h e m o s t fl e x i b l e i n t e rm s
o f reading, writing, and modifying its contents. Internal RAM is volatile, so
when the 8051 is reset this memory is cleared. The 128 bytes of
internal ram is subdivided as shown on the memory map. The fi rst 8
bytes (00h - 07h) are "register bank 0". These alternative register
banks are located in internal RAM in addresses 08h through 1Fh.Bit memory
actually resides in internal RA M , f ro m a d d re s s e s 2 0 h t h r o u g h 2 F h .
T h e 8 0 b y t e s re m a i n i n g o f I n t e r n a l RA M , f r o m addresses 30h
through

7Fh, may

be

used

by user

variables

that need

to

be

accessed frequently o r a t h i g h - s p e e d . T h i s a re a i s a l s o u t i l i z e d b y
t h e m i c ro c o n t r o l l e r a s a s t o r a g e a re a f o r t h e operating stack

3.6.1 Memory and Registers
The 8051 microcontroller has a total of 256 bytes of RAM in which 128
is visible or user accessible and extra 128 is for special function registers.
The user accessible RAM is used for temporary data storage. The user
accessible RAM is from the address range 00 to 7Fh.
From the user accessible RAM, 32 bytes of RAM is used for registers
and rest for Stack operations. The 32 Bytes of RAM is divided into four
register Banks i.e. Bank0, Bank 1, Bank 2, Bank3. Each of these banks have 8
Registers i.e. R0 to R7 each.
RAM locations from 0 to 7 are set aside for bank 0 of R0 – R7 where R0
is RAM location 0, Rl is RAM location 1, and R2 is location 2, and so on, until
memory location 7, which belongs to R7 of bank 0. The second bank of
registers R0 – R7 starts at RAM location 08 and goes to location 0FH. The
third bank of R0 – R7 starts at memory location 10H and goes to location
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17H. Finally, RAM locations 18H to 1FH are set aside for the fourth bank of R0
– R7.

Figure 3.6: Register Banks

Generally for normal operations, Register bank Bank0 is set by default. But
we can switch to other banks by using PSW Commands.

Figure 3.7: Bank Selection

3.6.2 SFRs (Special Function Register) - These Registers are in extra 128
bytes of the memory. This part of memory is not user accessible and these
registers are used for special purposes. These registers range from 80h to
FFh. There are a total of only 21 SFRs in this range and all other addresses
from 80h to FFh are invalid and there use can cause errors and not valuable
results.
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Some of the SFRs are TCON, SBUF, ACC, B, SCON, TMOD SP, P0, PSW,
TL0, and TL1. These all the registers have some specific function that has to
be performed after they are programmed.
(i) Byte Addressable SFR with byte address
SP – Stack printer – 81H
DPTR – Data pointer 2 bytes
DPL – Low byte – 82H
DPH – High byte – 83H
TMOD – Timer mode control – 89H
TH0 – Timer 0 Higher order bytes – 8CH
TL0 – Timer 0 Low order bytes – 8AH
TH1 – Timer 1 High bytes = 80H
TL1 – Timer 1 Low order byte = 86H
SBUF – Serial data buffer = 99H
PCON – Power control – 87H.
3.6.3 Registers
The Accumulator
The Accumulator, as its name suggests.
The "R" registers
T h e " R " re g i s t e r s a re a s e t o f e i g h t re g i s t e r s t h a t a re
n a m e d R 0 , R 1 , e t c . u p t o a n d including R7. These registers are used
as auxiliary registers in many 8-bit(1-operations.
The "B" Register
The "B" register is very similar to the Accumulator in the sense that it
may hold an byte) value. The "B" register is only used by two 8051
instructions: MUL AB and DIV AB.
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The Data Pointer (DPTR)
The Data Pointer (DPTR) is the 8051’s only user-accessible 16-bit (2byte) register. The Accumulator, "R" registers, and "B" register are all 1-byte
values. DPTR, as the name suggests, is used to point to data. It is used
by

a

number

of

commands

which

allow

the

8051

to

access

external memory.
Program Counter
T h e P ro g r a m C o u n t e r ( P C ) i s a 2 - b y t e a d d re s s w h i c h t e l l s
the

8051

w h e re

the

next

i nstruction to execute is found in

memory. When the 8051 is initialized PC always starts at 0000h and is
incremented each time an instruction is executed..
The Stack Pointer (SP)
The Stack Pointer, like all registers except DPTR and PC, may
hold an 8-bit (1-byte)value. The Stack Pointer is used to indicate where
the next value to be removed from the stack should be

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Figure 3.8: RAM allocation

3.7 8051 Assembly Language Programming
3.7.1 How to Program an 8051 microcontroller
[Label:] mnemonic [operands] [; comment]
Mnemonics -Assembly level instructions are called mnemonic like MOV R5
Operands -On which the operation is performed.
Example:
Loop: MOVR1, #25H; transfer 25H into R1
↑↑↑↑
Label mnemonics operand comments
Two instructions which are used to start and terminate program are
ORG -This instruction indicate the origin of program,
Example- ORG 3000H
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→ means program starts from 3000H location.
→ This instruction hasn’t take any memory space. It is used to show the
starting address of program.
END - This instruction show the END of program or it is used to terminate the
program.
Example:
ORG 0H; start compiler from 0h address
Again: MOV R5, # 25H; transfer 25H to R5
ADD A, R5; Add the R5 with Accumulator
SJMP Again; - jump to the location again
END; end the program.

3.7.2 Addressing Modes
Register Addressing Mode-The register addressing instruction involves
information transfer between registers
Example:
MOV R0, A
The instruction transfers the accumulator content into the R0register.
The register bank (Bank 0, 1, 2 or 3) must be specified prior to this
instruction.
In the Register Addressing mode, the instruction involves transfer of
information between registers. The accumulator is referred to as the A
register.

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Direct Addressing Mode- This mode allows you to specify the operand by
giving its actual memory address (typically specified in hexadecimal format)
or by giving its abbreviated name (e.g. P3).Used for SFR accesses
Example:
MOV A, P3; Transfer the contents of Port 3 to the accumulator
MOV A, 020H; Transfer the contents of RAM location 20H to the accumulator.
Indirect Addressing Mode-In the Indirect Addressing mode, a register is
used to hold the effective address of the operand. This register, which holds
the address, is called the pointer register and is said to point to the operand.
Only registers R0, R1 and DPTR can be used as pointer registers.R0
and R1 registers can hold an 8-bit address whereas DPTR can hold a 16-bit
address.DPTR is useful in accessing operands which are in the external
memory.
Examples:
MOV @R0, A; Store the content of accumulator into the memory location
pointed to by the contents of register R0. R0 could have an 8-bit address,
such as 60H.
MOVX A, @DPTR; Transfer the contents from the memory location pointed to
by DPTR into the accumulator. DPTR could have a 16-bit address, such as
1234H.
Immediate Addressing Mode-In the Immediate Constant Addressing
mode, the source operand is an 8- or 16-bit constant value. This constant is
specified in the instruction itself (rather than in a register or a memory
location).
The destination register should hold the same data size which is specified by
the source operand.
Examples:
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ADD A, #030H; Add 8-bit value of 30H to the accumulator register (which is
an 8-bit register).
MOV DPTR, #0FE00H; Move 16-bit data constant FE00H into the 16-bit Data
Pointer Register.
3.7.3 Instruction Types
The 8051 instructions are divided into four functional groups:





Arithmetic operations
Logical operations
Data transfer operations
Program branching operations

Arithmetic

Instructions-This

group of operators perform arithmetic

operations. Arithmetic operations affect the flags, such as Carry Flag (CY),
Overflow Flag (OV) etc., in the PSW register. The appropriate status bits in
the PSW are set when specific conditions are met, which allows the user
software to manage the different data formats.
Logical

Instructions-Logical

instructions

perform

standard

Boolean

operations such as AND, OR, XOR, NOT (compliment). Other logical
operations are clear accumulator, rotate accumulator left and right, and
swap nibbles in accumulator.
Examples:
ANL A, #02H;

Mask bit 1

ORL TCON, A;

TCON=TCON OR A

Data Transfer Instructions- Data transfer instructions can be used to
transfer data between an internal RAM location and an SFR location without
going through the accumulator.It is also possible to transfer data between
the internal and external RAM by using indirect addressing. The upper 128

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bytes of data RAM are accessed only by indirect addressing and the SFRs
areaccessed only by direct addressing.
Program Branching Instructions- Program branching instructions are
used to control the flow of program execution.

Some instructions provide

decision making capabilities before transferring control to other parts of the
program e.g. conditional and unconditional branches
3.7.4 Flags and PSW (Program Status Word) Register in 8051


The program status word (PSW) register, also referred to as the flag



register, is an 8 bit register.
Only 6 bits are used These four are CY (carry), AC (auxiliary carry),
P(parity), and OV (overflow) They are called conditional flags, meaning
that they indicate some conditions thatresulted after an instruction was



execute.
The PSW3 and PSW4 are designed as RS0 and RS1, and are used to



change the bank.
The two unused bits are user-definable.

PSW 7

PSW 6

PSW 5

PSW 4

PSW 3

PSW 2

PSW 1

PSW 0
Figure 3.9: PSW Register

C

A

F0

RS1

RS0

OV

---------

P

CY- PSW.7- Carry flag.
AC- PSW.6- Auxiliary Carry flag.
F0 (-----) - PSW.5- Available to the user for general purpose
RS1 -PSW.4 - Register Bank selector bit 1.
RS0- PSW.3 -Register Bank selector bit 0.
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OV -PSW.2 -Overflow flag.
F0 (-----) - PSW.1- User definable bit.
P- PSW.0 -Parity flag. Set/cleared by hardware each.

3.8 TIMERS AND COUNTERS
3.8.1Timers
The 8051 comes equipped with two timers, both of which may be
controlled, set, read, and configured individually. The 8051 timers have three
general functions:
1) Keeping time and/or calculating the amount of time between events,
2) Counting the events themselves,
3) Generating baud rates for the serial port.
Both Timer 0 and Timer 1 are 16 bits wide.Since 8051 has an 8-bit
architecture, each 16-bits timer is accessed as two separate registers of low
byte and high byte.
One timer is TIMER0 and the other is TIMER1. The two timers share two
SFRs (TMOD and TCON) which control the timers, and each timer also has
two SFRs dedicated to itself (TH0/TL0 and TH1/TL1).The upper higher bits are
TH0 and TH1 and the lower bits are TL0 AND TL1.The TMOD and TCON are
two control registers for the two timers.

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Figure 3.10 :Timer Registers

(i) TMOD Register
It is used to set the various timer operation mode.
– TMOD is an 8-bit register where the lower 4 bits are set aside for timer 0
and the upper 4 bits are set aside for timer 1.
MSB
Gate

LSB
C/T

M0

M1

GATE

C/T

Timer 1

M0

MI

Timer 0
Figure 3.11:TMOD Register

GATE: To start and stop the timer


GATE=1 _Hardware control: is enabled only while INTx pin is ‘1’and TRx



control pin (in TCON) is set.
GATE=0 _Software control (used frequently)

C/T: Timer or counter selection


C/T = 0 _Timer (input from internal system clock) the crystal (1/12) is



used to trigger the timer.
C/T = 1 _Counter (input from Tx input pin)

M1 and M0: Mode selection for timer and counter
Mode M1 M0
0

0

101

0

13-bit timer/counter mode
16-bit timer/counter mode
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210
31

8-bit auto reload timer/counter mode
1

split timer/counter mode

(ii) TCON Register
MSB

LSB

TF1

TF0

TR1

TIMER 1

TR0

IE1

TIMER 0

IE0

IT1

IT0

TIMER1

TIMER0
Figure 3.12: TCON Register

TF1: Timer 1 overflows flag



TF1=1: Timer/counter 1 overflows.
TF1=0: processor vectors to the interrupt services.

TR1: Timer 1 run control bit



TR1=1: turn Timer 1 ON
TR1=0: turn Timer 1 OFF

IE1: External interrupt 1 edge flag



IE1=1: external interrupt is detected.
IE1=0: when interrupt is processed.

IT1: Interrupt 1 type control bit



IT1=1: falling edge.
IT1=0: low level triggered external interrupt.

Gate=0, SETB TR1 _Run Timer 1
SETB TR0 _Run Timer 0
Gate=0, CLR TR1 _OFF Timer 1
CLR TR0 _OFF Timer 0

Timer Mode 0


Mode 0: 13-bit Timer/counter mode
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0000 ~ 1FFFH

Timer Mode 2
Mode 2: 8-bit auto reload Timer/counter mode (00 ~ FFH).
In auto reload, TH is loaded with the initial count and a copy of it is given to
TL.
This reloading leaves TH unchanged still holding a copy of original values.
This mode has many applications, including setting the baud rate in serial
communication.
3.8.2 Counters
Counter is used to count input pulses.
C/T=0: As Time, using 8051’s crystal as the source of the frequency.
C/T=1: As counter, a pulse outside of the 8051 that increments the TH and
TL register.
When the C/T=1, the counter counts up as pulses are fed from Pins P3.4 (for
counter 0) or P3.5 (for counter 1).

3.9 INTERUPTS
An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service.


The advantage of interrupts is that the microcontroller can serve many



devices.
Each device can get the attention of the microcontroller based on the



assigned priority.
The microcontroller can also ignore (mask) a device request for
service.

3.9.1 Hardware and Software interrupt
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The interrupts in a controller can be either hardware or software. If the
interrupts are generated by the controller’s inbuilt devices, like timer
interrupts; or by the interfaced devices, they are called the hardware
interrupts. If the interrupts are generated by a piece of code, they are
termed as software interrupts.
The 8051 controller has six hardware interrupts of which five are available to
the programmer.
1. RESET Interrupt - This is also known as Power on Reset (POR). When the
RESET interrupt is received, the controller restarts executing code from
0000H location. This is an interrupt which is not available to or, better to say,
need not be available to the programmer.
2. Timer interrupts - Each Timer is associated with a Timer interrupt. A
timer interrupt notifies the microcontroller that the corresponding Timer has
finished counting. Therefore these are two interrupts for the timers.
3. External interrupts - There are two external interrupts EX0 and EX1 to
serve external devices. Both these interrupts are active low. In AT89C51, P3.2
(INT0) and P3.3 (INT1) pins are available for external interrupts 0 and 1
respectively. An external interrupt notifies the microcontroller that an
external device needs its service.
4. Serial interrupt - This interrupt is used for serial communication. When
enabled, it notifies the controller whether a byte has been received or
transmitted.

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Figure3.13: Various Interrupts

CHAPTER-4

Interfacings with 8051 microcontroller
4.1 LED Interfacing
Interfacing an LED with 8051 is easy. The I/O pins are used as output
pins. When any of the bit is set to 1, the LED glows if LED n side is connected
to ground and p side with bit. And if p side is connected to power and n side
to bit, then on bit low, the LED glows.
4.1.1 Assembly Code for led interfacing
org 00h
back: mov a,#00h
mov P0,a
acall secdelay
mov a,#0ffh
mov P0,a
acall secdelay
Sjmp back
secdelay: mov r5,#25
H3: mov r4,#55
H2: mov r3,#ffh
H1: djnz r3,H1
djnz r4,H2

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djnz r5,H3
ret

Figure

4.1:

LED Interfacing

4.2 Seven Segment Display Interfacing
A seven segment consists of eight LEDs which are aligned in a manner
so as to display digits from 0 to 9 when proper combination of LED is
switched on. Seven segment uses seven LED’s to display digits from 0 to 9
and the eighth LED is used for the dot.

Figure 4.2: Seven Segment Display

Assembly Code
org 00h
mov P1,#3fh
call delay
mov P0,#06h
call delay
mov P0,#5bh

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call delay
mov P0,#4fh
call delay
mov P0,#66h
call delay
mov P0,#6dh
call delay
mov P0,#7dh
call delay
mov P0,#07h
call delay
mov P0,#7fh
call delay
mov P0,#67h
call delay
jmp main
delay: mov 40h,#0FFh
L1: mov 41h,#99h
L2: djnz 41h,L2
djnz 40h,L1
ret

Figure 4.3: 7 Segment Display Interfacing

4.3 LCD INTERFACING
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A 16x2 LCD means it can display 16 characters per line and there are 2
such lines. In this LCD each character is displayed in 5x7 pixel matrix.
This LCD has two registers.
1. Command/Instruction Register - stores the command instructions
given to the LCD. A command is an instruction given to LCD to do a
predefined task like initializing, clearing the screen, setting the cursor
position, controlling display etc.
2.Data Register - stores the data to be displayed on the LCD. The data is
the ASCII value of the character to be displayed on the LCD.

Figure 4.4: LCD Interfacing
Table 4.1: LCD Commands

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Assembly Code
ORG 0H
MOV A,#38H
ACALL COMNWRT
ACALL DELAY
MOV A,#0EH
ACALL COMNWRT
ACALL DELAY
MOV A,#01
ACALL COMNWRT
ACALL DELAY
MOV A,#84H
ACALL COMNWRT
ACALL DELAY
MOV A,#’c’
ACALL DATAWRT
ACALL DELAY
MOV A,#’d’
ACALL DATAWRT
AGAIN: SJMP AGAIN
MOV A,#’a’
ACALL DATAWRT
ACALL DELAY
MOV A,#’c’
ACALL DATAWRT

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AGAIN: SJMP AGAIN
COMNWRT: ; MOV P1,A
CLR P2.0
CLR P2.1
SETB P2.2
ACALL DELAY
CLR P2.2
RET
DATAWRT:MOV P1,A
SETB P2.0
CLR P2.1
SETB P2.2
ACALL DELAY
CLR P2.2
RET
DELAY: MOV R3,#50
HERE2: MOV R4,#255
HERE: DJNZ R4,HERE
DJNZ R3,HERE2
RET

4.4 Keypad Interfacing
Keyboards are organized in a matrix of rows and columns. The CPU
accesses both rows and columns through ports. Therefore, with two 8-bit
ports, an 8 x 8 matrix of keys can be connected to a microcontroller. When a
key is pressed, a row and a column make a contact. Otherwise, there is no
connection between rows and columns. A 4x4 matrix connected to two ports
The rows are connected to an output port and the columns are connected to
an input port It is the function of the microcontroller to scan the keyboard
continuously to detect and identify the key pressed.To detect a pressed key,
the microcontroller grounds all rows by providing 0 to the output latch, then
it reads the columns.If the data read from columns is D3 – D0 =1111, no key

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has been pressed and the process continues till key press is detected. If one
of the column bits has a zero, this means that a key press has occurred.
Assembly Code
org 00h
here:mov p1,#0ffh
clr p1.0
h1:jb p1.4,h2
mov p2,#3fh
h2:jb p1.5,h3
mov p2,#06h
h3:jb p1.6,h4
mov p2,#5bh
h4:jb p1.7,h5
mov p2,#4fh
h5:setb p1.0
clr p1.1
jb p1.4,h6
mov p2,#66h
h6:jb p1.5,h7
mov p2,#6dh
h7:jb p1.6,h8
mov p2,#7dh
h8:jb p1.7,h9
mov p2,#07h
h9:setb p1.1
clr p1.2
jb p1.4,h10
mov p2,#7fh
h10:jb p1.5,h11
mov p2,#67h
h11:jb p1.6,h12
mov p2,#77h
h12:jb p1.7,h13
mov p2,#7fh
h13:setb p1.2
clr p1.3

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jb p1.4,h14
mov p2,#39h
h14:jb p1.5,h15
mov p2,#3fh
h15:jb p1.6,h16
mov p2,#79h
h16:jb p1.7,h17
mov p2,#71h
h17:ljmp here
end

Figure 4.5: Keypad Interfacing

4.5 Relay interfacing
A relays is an electrical switch that opens and closes under control of
another electrical circuit. It is therefore connected to ouput pins of the
microcontroller and used to turn on/off high-power devices such as motors,
transformers, heaters, bulbs, antenna systems etc.
Assembly Code
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org 00h
back: mov a,#00h
mov P1,a
acall secdelay
mov a,#01h
mov P1,a
acall secdelay
Sjmp back
Secdelay: mov r5,#25
H3: mov r4,#55
H2: mov r3,#ff
H1:djnz r3,H1
djnz r4,H2
djnz r5,H3
ret

Figure 4.6:Relay Interacing

4.6 Stepper Motor Interfacing
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A stepper motor (or step motor) is a brushless synchronous electric
motor that can divide a full rotation into a large number of steps. The motor's
position can be controlled precisely without any feedback mechanism, as
long as the motor is carefully sized to the application. Stepper motors are
similar to switched reluctance motor (which are very large stepping motors
with a reduced pole count, and generally are closed-loop The stepper motor
can

be

interfaced

with

the

8051

using

l293d

connected

to

p1.0,p1.2,p1.3,p1.4Stepper motor two types of step sequence 1) full step
and 2) half step sequence. In the full step sequence, two coils are energized
at the same time and motor shaft rotates.
Assembly Code
org 00h
mov a,#66h
back:mov p2,a
rr a
acall delay
sjmp back
delay:mov r2,#100
h1: mov r3,#255
h2: djnz r3,h2
djnz r2,h1
ret

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Figure 4.7: Stepper Motor

4.7 Serial Communication
We need a line driver (voltage converter) to convert the R232’s signals
to TTL voltage levels that will be acceptable to 8051’s TxD and RxD pins.

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Figure 4.8: MAX232 pin out

Assembly Code
ORG 00H
AGAIN:MOV TMOD,#20H
MOV TH1,#-3
MOV SCON,#50H
SETB TR1
AGAIN: MOV SBUF,#”A”
HERE: JNB TI,HERE
CLR TI
SJMP AGAIN

CHAPTER-5

AVR MICROCONTROLLER
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5.1 Introduction
The acronym AVR has been reported to stand for “Advanced Virtual
RISC”, but it has also been rumored to stand for the initials of the chip's
designers. The AVR architecture was conceived by two students at
the Norwegian institute of technology, Alf-Egil Bogen and Vegard Wollan
Microcontroller

was developed by Atmel in 1996The AVR is a modified

Harvard architecture 8-bit RISC single chip microcontroller . The AVR was one
of the first microcontroller families to use on-chip flash memory for program
storage,

as

opposed

to one-time

programmable

ROM, EPROM,

or EEPROM used by other microcontrollers at the time. Among the first of the
AVR line was the AT90S8515, which in a 40-pin DIP package has the same
pinout as an 8051 microcontroller, including the external multiplexed address
and data bus. The polarity of the RESET line was opposite (8051's having an
active-high RESET, while the AVR has an active-low RESET), but other than
that, the pin out was identical.

5.2 Features
• High-performance, Low-power AVR 8-bit Microcontroller
• RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
– 8K Bytes of In-System Self-programmable Flash
– 512 Bytes EEPROM
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– 512 Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
– Three PWM Channels
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power-down and Standby
• I/O and Packages
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V for ATmega8515L
– 4.5 - 5.5V for ATmega8515
• Speed Grades
– 0 - 8 MHz for ATmega8515L
– 0 - 16 MHz for ATmega8515

5.3 Basic Families
AVR generally Classified into basically five Groups

-

Tiny AVR- the ATtiny Series
0.5-8kB program memory

- 6-32 pin Package
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- Limited Peripheral


Mega AVR- the ATmega Series

- 4-256kB program memory
28-100 pin package
- Extended instruction set
- Extensive peripheral set


XMEGA – ATxmega series

-

16-384 kB program memory

-

44-64-100 pin package.

-

Extended Performa features such as DMA, “Event system ”and
cryptography system.

-

Extensive Peripheral Set



Application Specific AVR

-

Mega AVR with special features such as LCD controller , Advanced AVR



FPSLIC (AVR with FPGA)

-

Field

Programmable

Specific

Language

Integrated

combination of AVR with Field Programmable Gate Array of

Circuit

is

5K to 40K

gates
-

SRAM for the AVR program code

-

AVR core can be run at up to 50 MHz

5.4 Pin Diagram

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Figure 5.1: Pin Configuration of AVR

VCC Digital supply voltage.
GND Ground.
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port A output buffers have
symmetrical drive characteristics with both high sink and source capability.
When pins PA0 to PA7 are used as inputs and are externally pulled low, they
will source current if the internal pull-up resistors are activated. The PortA
pins are tri-stated when a reset condition becomes active, even if the clock is
not running. Port A also serves the functions of various special features of
the ATmega8515.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port B output buffers have
symmetrical drive characteristics with both high sink and source capability.
As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated
when a reset condition becomes active, even if the clock is not running.
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Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port C output buffers have
symmetrical drive characteristics with both high sink and source capability.
As inputs, Port C pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port D output buffers have
symmetrical drive characteristics with both high sink and source capability.
As inputs, Port D pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port E output buffers have
symmetrical drive characteristics with both high sink and source capability.
As inputs, Port E pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
RESET Reset input. A low level on this pin for longer than the minimum pulse
length will generate a reset, even if the clock is not running.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal
clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.

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5.5 Architecture

Figure 5.2: Architecture of AVR

The AVR core combines a rich instruction set with 32 general purpose
working registers. All the 32 registers are directly connected to the
Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clockcycle. The resulting
architecture is more code efficient while achieving throughputs up to ten
times faster than conventional CISC microcontrollers.
The ATmega8515 provides the following features: 8K bytes of InSystem Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes
SRAM, an External memory interface, 35 general purpose I/O lines, 32
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general purpose working registers, two flexible Timer/Counters with compare
modes, Internal and External interrupts, a Serial Programmable USART, a
programmable Watchdog Timer with internal Oscillator, a SPI serial port, and
three software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and Interrupt system to
continue functioning. The Power-down mode saves the Register contents but
freezes the Oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator
is running while the rest of the device is sleeping. This allows very fast startup combined with low-power consumption.
Six of the 32 registers can be used as three 16-bit indirect address
register pointers for Data Space addressing – enabling efficient address
calculations. One of the these address pointers can also be used as an
address pointer for look up tables in Flash Program memory. These added
function registers are the 16-bit X-, Y-, and Z-register,
.
The ALU supports arithmetic and logic operations between registers or
between a constant and a register. Single register operations can also be
executed in the ALU. After an arithmetic operation, the Status Register is
updated to reflect information about the result of the operation. Program flow
is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have
a single 16-bit word format. Every Program memory address contains a 16or 32-bit instruction.
During interrupts and subroutine calls, the return address Program
Counter (PC) is stored on the Stack. The Stack is effectively allocated in the
general data SRAM, and consequently the Stack size is only limited by the
total SRAM size and the usage of the SRAM. All user programs must initialize
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the SP in the reset routine (before subroutines or interrupts are executed).
The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM
can easily be accessed through the five different addressing modes
supported in the AVR architecture. The memory spaces in the AVR
architecture are all linear and regular memory maps. A flexible interrupt
module has its Control Registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate
interrupt vector in the Interrupt Vector table. The interrupts have priority in
accordance with their Interrupt Vector position. The lower the Interrupt
Vector address, the higher the priority. The I/O memory space contains 64
addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or asthe Data Space
locations following those of the Register File, $20 - $5F.
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all
the 32 general
Purpose working registers. Within a single clock cycle, arithmetic operations
between general purpose registers or between a register and an immediate
are executed. The ALU operations are divided into three main categories –
arithmetic,

logical,

architecture

also

and

bit-functions.

provide

a

Some

powerful

implementations

multiplier

of

supporting

the
both

signed/unsigned multiplication and fractional format.
Status Register
The Status Register contains information about the result of the most
recently executed

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arithmetic instruction. This information can be used for altering program flow
in order to perform conditional operations. The Status Register is updated
after all ALU operations, as specified in the Instruction Set Reference. This
will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be
enabled. The individual interrupt enable control is then performed in
separate Control Registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by
hardware after an interrupt has occurred, and is set by the RETI instruction to
enable subsequent interrupts. The I bit can also be set and cleared by the
application with the SEI and CLI instructions
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit Load) and BST (Bit Store) use the Tbit as source or destination for the operated bit. A bit from a register in the
Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic
operations. Half Carry is
useful in BCD arithmetic.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and
the Two’s Complement Overflow Flag V.
• Bit 3 – V: Two’s Complement Overflow Flag

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The Two’s Complement Overflow Flag V supports two’s complement
arithmetic.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or
logic operation.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic
operation.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation.

Figure 5.3: Status Register

5.6General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction
set. In order toachieve the required performance and flexibility, the following
input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
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Most of the instructions operating on the Register File have direct
access to all registers,
and most of them are single cycle instructions. each register is also assigned
a Data memory address, mapping them directly into the first 32 locations of
the user Data Space. Although not being physically implemented as SRAM
locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y-, and Z-pointer Registers can be set to index any
register in the file.
Byte
5.6.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general
purpose usage. These registers are 16-bit address pointers for indirect
addressing of the Data Space. The three indirect address registers X, Y, and
Z In the different addressing modes these address registers have functions
as fixed displacement, automatic increment, and automatic decrement.
5.6.2 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local
variables and for storing return addresses after interrupts and subroutine
calls. The Stack Pointer Register always points to the top of the Stack. the
Stack is implemented as growing from higher memory locations to lower
memory locations. This implies that a Stack PUSH command decreases the
Stack Pointer.The Stack Pointer points to the data SRAM Stack area where the
Subroutine and Interrupt Stacks are located. This Stack space in the data
SRAM must be defined by the program before any subroutine calls are
executed or interrupts are enabled. The. The Stack Pointer is decremented by
one whendata is pushed onto the Stack with the PUSH instruction, and it is
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decremented by two when the return address is pushed onto the Stack with
subroutine call or interrupt. The stack Pointer is incremented by one when
data is popped from the Stack with the POP instruction, and it is incremented
by two when address is popped from the Stack with return from subroutine
RET or return from interrupt RETI.The AVR Stack Pointer is implemented as
two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent.

5.7 I/O Port Registers
Each of the AVR Digital I/O ports is associated with three (3) I/O
register. A Data Direction Register (DDRx), A Pin Register (PINx) and a Port
Register
DDRx

(PORTx).
-

Port

Where x is
X

the

Data

port A,

B,C,etc. .

Direction

Register

Figure 5.4: DDR Register

DDRx is an 8-bit register which stores configuration information for the pins
of Portx. Writing a 1 in the pin location in the DDRx makes the physical pin of
that port an output pin and writing a 0 makes that pin an input pin.
PINx

-

Port

X

Input

Pins

Register

Figure 5.5:Input Pin Register

PINx is an 8-bit register that stores the logic value, the current state, of the
physical pins on Portx. So to read the values on the pins of Portx, you read
the

values

that

are

in

its

PIN

register.

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PORTx

-

Port

X

Data

Register

Figure 5.6: Port Data Register

PORTx is an 8-bit register which stores the logic values that currently being
outputted on the physical pins of Portx if the pins are configured as output
pins. So to write values to a port, you write the values to the PORT register of
that port.

5.8 Memories
5.8.1 Program memory
It is a continuous chunk of flash memory. The exact size varies from
controller to controller. Program memory is accessed every clock cycle and
an instruction is loaded in the Instruction Register. The Instruction Register
feeds the Register File, selecting which of the registers will be used for the
program execution. The program memory besides storing the instructions
also stores the Interrupt Vectors. The ATmega8515 contains 8K bytes On-chip
In-System Reprogrammable Flash memory for program storage. Since all AVR
instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For
software security, the Flash Program memory space is divided into two
sections, Boot Program section and Application Program section.

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Figure 5.7 :Program Memory

5.8.2 Data Memory
A Register File with 32 registers of 8-bit width.8-bit wide I/O registers.
Number of I/O registers depends on the on-chip peripherals. Internal SRAM.
Used for stack as well as for storing variables. The lower 608 Data Memory
locations address the Register File, the I/O Memory, and the internal data
SRAM. The first 96 locations address the Register File and I/O Memory, and
the next 512 locations address the internal data SRAM.

Figure 5.8: Data Memory

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5.9 Addressing Modes
The ATmega8515 AVR RISC microcontroller supports powerful and
efficient Addressing Modes for access to the program memory (Flash) and
data memory (SRAM, Register

file and I/O memory). The five different

addressing modes for the data memory cover:
Register Direct, with 1 and 2 registers
I/O Direct
Data Direct
Data Indirect
– with pre-decrement
– with post-increment
 Code Memory Addressing





1.Register Direct
Register Direct (single operand) .Instructions can operate on any of the
32 registers. The group of 32 registers are referred to as the Register File
– The microcontroller:
• Reads the data in the register
• Operates on the data in the register
• Stores the results back in the register
Register Direct (two operands):Instructions can operate on any of the 32
registers One of these registers is the source register (Rs) and one is the
destinationregister (Rd) Relative to the data.

Figure 5.9: Register Direct Addressing

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Figure 5.10: Register Direct addressing(two operands)

2. I/O Direct
Used to access I/O space (I/O registers and ports).I/O registers may
only be accessed with two instructions:
IN: for reading data from an input port: PINx
OUT: for sending data out the output port: PORTx

Figure 5.11: I/O Direct Addressing

3.Data Direct
Instructions are two word (16-bit).One of the operands is the address of
the data (address of where the data is stored).The other operand is a
register.

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Figure 5.12: Data Direct Addressing

5. Data Indirect
In Data Direct, one of the operands is an explicitly specified address (to
store or retrieve data).In Data Indirect, the address is specified as the
contents of the X, Y, or Z .registerX is the combination of r26 & r27.Y is the
combination of r28 & r29.Z is the combination of r30 &r31.
X, Y, or Z are referred to as the “pointer register”.

Figure 5.13: Data Indirect Addressing

6.Code Memory Addressing
The Z register is used as a pointer to Program Memory Up to 64k (16
bit register) and used for Indirect Jumps or subroutine calls.

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1

1

Figure 5.14: Program Memory Addressing

5.10 Timers and Counters
The ATmega8515 provides two general-purpose Timer/Counters – one 8bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling
selection from the same 10-bit prescaling timer. Both Timer/Counters can
either be used as a timer with an internal clock time base or as a counter
with an external pin connection that triggers the counting.
5.10.1 8 bit Timer/Counter 0
Timer/Counter0

is

a

general

purpose,

single

channel,

8-bit

Timer/Counter module. The
main features are:
• Single Channel Counter
• Clear Timer on Compare Match (Auto Reload)
• Frequency Generator
• External Event Counter
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• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)
Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are
8-bit registers. Interrupt request signals are all visible in the Timer Interrupt
Flag Register (TIFR). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK). The Timer/Counter can be clocked
internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the
Timer/Counter uses to increment (or decrement) its value. The Timer/Counter
is inactive when no clock source is selected. The output from the clock select
logic is referred to as the timer clock (clkT0).The double buffered Output
Compare Register (OCR0) is compared with the Timer/Counter value at all
times. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare Pin
(OC0).
5.10.2

8-bit Timer/Counter Register Description

Figure 5.15: TCCR0 Register

• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM00 bit specifies a non-PWM
mode. However, for ensuring compatibility with future devices, this bit must
be set to zero when TCCR0 is written when operating in PWM mode. When
writing a logical one to the FOC0 bit, an immediate Compare Match is forced
on the waveform generation unit. The OC0 output is changed according to its
COM01:0 bits setting.
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• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for
the maximum
(TOP) counter value, and what type of waveform generation to be used.
Modes of operation
supported by the Timer/Counter unit are: Normal mode, Clear Timer on
Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM)
modes.

• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0) behavior. If one or
both of the COM01:0 bits are set, the OC0 output overrides the normal port
functionality of the I/O pin it is connected to.
Table 5.1: COM01:0 bits settings

• Bit 2:0 – CS02:0: Clock Select
Table 5.2: Clock select bits

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Register TCNT0

Figure 5.16: TCNT0 Register

The Timer/Counter Register gives direct access, both for read and write
operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks
(removes) the Compare Match on the following timer clock.
Output Compare Register – OCR0

Figure 5.17: OCR0 Register

The Output Compare Register contains an 8-bit value that is continuously
compared with the counter value (TCNT0). A match can be used to generate
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an output compare interrupt, or to generate a waveform output on the OC0
pin.
Timer/Counter Interrupt Mask Register – TIMSK

Figure 5.18 :TIMSK Register

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status
Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The
corresponding interrupt is executed if an overflow in Timer/Counter0 occurs,
i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register –
TIFR.
• Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt
Enable
When the OCIE0 bit is written to one, and the I-bit in the Status
Register is set (one), the Timer/Counter0 Compare Match interrupt is
enabled. The corresponding interrupt is executed if a Compare Match in
Timer/Counter0 occurs.
Timer/Counter Interrupt Flag Register – TIFR

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Figure 5.19:TIFR Register

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0.
• Bit 0 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a Compare Match occurs between the
Timer/Counter0
and the data in OCR0 – Output Compare Register0.
5.10.3 16-bit Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution
timing

(event

management),wave

generation,

and

signal

timing

measurement. The main features are:
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceller
• Clear Timer on Compare Match (Auto Reload)
• Frequency Generator
• External Event Counter
• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Registers

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The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and
Input Capture
Register (ICR1) are all 16-bit registers.
5.10.4 16-bit Timer/Counter Register Description
Timer/Counter1 Control Register A – TCCR1A

Figure 5.20:TCCR1A Register

• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
Timer/Counter1 Control Register B – TCCR1B

Figure 5.21: TCCR1B Register
Table 5.3:Prescalar Setting

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Timer/Counter1 – TCNT1H and TCNT1L

Figure 5.22: TCNT1H and TCNT1L Registers

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1)
give direct access, both for read and for write operations, to the
Timer/Counter unit 16-bit counter.
Output Compare Register 1 A – OCR1AH and OCR1AL

Figure 5.23: OCR1AH and OCR1AL Registers

Output Compare Register 1 B– OCR1BH and OCR1BL

Figure 5.24: OCR1BH and OCR1BL Registers

The Output Compare Registers contain a 16-bit value that is
continuously compared with the counter value (TCNT1). A match can be used
to generate an output compare interrupt, or to generate a waveform output
on the OC1x pin.
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5.11 USART
AVR has a dedicated hardware for serial communication this part is
called

the

USART

-

Universal

Synchronous

Asynchronous

Receiver

Transmitter. We supply the data we need to transmit and it will do the rest.
serial communication occurs at standard speeds of 9600,19200 bps etc and
this speeds are slow compared to the AVR CPUs speed.
Also the USART automatically senses the start of transmission of RX line
and then inputs the whole byte and when it has the byte it informs The PC
CPU to read that data from one of its registers. The USART of AVR is very
versatile and can be setup for various different mode as required by our
application.
5.11.1

USART Registers

The USART of the AVR is connected to the CPU by the following six
registers.UDR - USART Data Register : Actually this is not one but two register
but when we read it we will get the data stored in receive buffer and when
we write data to it goes into the transmitters buffer.
UCSRA - USART Control and status Register A : As the name suggests it
is used to configure the USART and it also stores some status about the
USART. There are two more of this kind the UCSRB and UCSRC.
UBRRH and UBRRL : This is the USART Baud rate register, it is 16BIT wide
so UBRRH is the High Byte and UBRRL is Low byte.

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Figure 5.25: USART Registers

UCSRA: USART Control and Status Register A

Figure 5.26: UCSRA Register

RXC- this bit is set when the USART has completed receiving a byte from the
host (may be your PC) and the program should read it from UDR .
TXC -This bit is set (1) when the USART has completed transmitting a byte to
the host and your program can write new data to USART via UDR.
UCSRB: USART Control and Status Register B

Figure 5.27 UCSRB Register

RXCIE: Receive Complete Interrupt Enable - When this bit is written one
the associated interrupt is enabled.

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TXCIE: Transmit Complete Interrupt Enable - When this bit is written one
the the associated interrupt is enabled.
RXEN: Receiver Enable - When you write this bit to 1 the USART receiver is
enabled. The normal port functionality of RX pin will be overridden. So you
see that the associated I/O pin now switch to its secondary function,i.e. RX
for USART.
TXEN: Transmitter Enable
UCSZ2: USART Character Size
UCSRC: USART Control And Status Register C

Figure 5.28 : UCSRC Register

URSEL: USART register select
UMSEL: USART Mode Select - This bit selects between asynchronous and
synchronous mode. As asynchronous mode is more popular with USART .
USBS: USART Stop Bit Select - This bit selects the number of stop bits in
the data transfer.
UCSZ: USART Character size - These three bits (one in the UCSRB) selects
the number of bits of data that is transmitted in each frame.
Table 5.4: Character Size Setting

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UBRR: USART Baud Rate Register:
This is the USART Baud rate register, it is 16BIT wide so UBRRH is the
High Byte andUBRRL is Low byte. This register is used by the USART to
generate the data transmission at specified speed (say 9600Bps).UBRR value
is calculated according to following formula

CHAPTER-6

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Interfacings with AVR
6.1 LED Interfacing

U1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
19
18
9

PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK

39
38
37
36
35
34
33
32

PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7

PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD

D2

LED-red

LED-BLUE
LED-BLUELED-red
LED-BLUE

D3

D4

D5

D6

D7

D8

LED-red

LED-BLUE

LED-red

21
22
23
24
25
26
27
28

PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI

XTAL1
XTAL2
RESET

D1

31
30
29

PE0/ICP/INT2
PE1/ALE
PE2/OC1B

ATMEGA8515

Figure 6.1: LED Interfacing

Assembly Code
.include "m8515def.inc"
.org 0x00
ldi r16,0xff
out sph,r16
ldi r16,0x00
out spl,r16
ldi r17,0xff
out ddra,r17
ldi r18,0xaa
next:out porta,r18
delay:ldi r19,0x1
l2:

ldi r20,0x1

l1: dec r20
breq l1
dec r19
breq l2

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com r18
rjmp next

6.2 Switch Interfacing

U1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
19
18
9

PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD
XTAL1
XTAL2
RESET

PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
PE0/ICP/INT2
PE1/ALE
PE2/OC1B

39
38
37
36
35
34
33
32

D1

D2

D3

LED-RED

LED-RED

LED-RED

ATMEGA8515

D5

D6

D7

D8

LED-RED

LED-RED

LED-RED

LED-RED

LED-RED

21
22
23
24
25
26
27
28
31
30
29

D4

R1

R2

R3

6.98K

6.98K

6.98K

Figure 6.2: Switch Interfacing

Assembly Code
.include "m32def.inc"
.org 0x00
ldi r16,high(ramend)
out sph,r16
ldi r16,low(ramend)
out spl,r16
ldi r17,0x00
out ddrc,r17
ldi r18,0xff
out ddra,r18
here:in r19,pinc
bst r19,0
brts next1
bst r19,1

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brts next2
bst r19,2
brts next3
rjmp here
next1:ldi r20,0x80
out porta,r20
ret
next2:ldi r20,0x40
out porta,r20
ret
next3:ldi r20,0x20
out porta,r20
ret

6.3 Relay Interfacing

Figure 6.3: Relay Interfacing

Assembly Code
.include "8515def.inc"
.org 0x00
ldi r16,high(ramend)
out sph,r16
ldi r16,low(ramend)

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out spl,r16
ldi r17,0xff
out ddrc,r17
here: ldi r18,0xff
out portc,r18
rcall delay
ldi r18,0x00
out portc,r18
rcall delay
rjmp here
delay: ldi r19,0xff
l2: ldi r20,0xff
l1:dec r20
brne l1
dec r19
brne l2
ret

6.4 LCD Interfacing
Assembly Code
.include "m8515def.inc"
.org 0x00
ldi r16,high(ramend)
out sph,r16
ldi r16,low(ramend)
out spl,r16
ldi r17,0xf0
out ddra,r17
ldi r17,0xff
out ddrd,r17
ldi r17,0xff
out ddrc,r17
ldi r18,0x38
rcall command
rcall delay
ldi r18,0x0e
rcall command

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rcall delay
ldi r18,0x01
rcall command
rcall delay
ldi r18,0x06
rcall command
rcall delay
ldi r18,0x84
rcall command
rcall delay
ldi r18,’c’
rcall data
rcall delay
ldi r18,’d’
rcall data
rcall delay
ldi r18,’a’
rcall data
rcall delay
ldi r18,’c’
rcall data
rcall delay
here:rjmp here
command: out portd,r18
cbi portc,4
sbi portc,5
rcall delay
cbi portc,5
ret
data: out portd,r18
sbi portc,4
sbi portc,5
rcall delay
cbi portc,5
ret
delay: ldi r19,0xff

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l1: ldi r20,0x0f
l2: dec r20
brne l2
dec r19
brne l1
ret

LCD1

19
18
9

XTAL1
XTAL2
RESET

PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
PE0/ICP/INT2
PE1/ALE
PE2/OC1B

21
22
23
24
25
26
27
28

D0
D1
D2
D3
D4
D5
D6
D7

VSS
VDD
VEE

39
38
37
36
35
34
33
32

7
8
9
10
11
12
13
14

PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD

PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7

4
5
6

10
11
12
13
14
15
16
17

PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK

1
2
3

1
2
3
4
5
6
7
8

RS
RW
E

LM016L

U1

31
30
29

ATMEGA8515

Figure 6.4: LCD Interfacing

6.5 Seven Segment Interfacing

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U1
1
2
3
4
5
6
7
8

PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK

10
11
12
13
14
15
16
17

PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/W R
PD7/RD

19
18
9

XTAL1
XTAL2
RESET

PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7
PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI
PE0/ICP/INT2
PE1/ALE
PE2/OC1B

39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
31
30
29

ATMEGA8515

Figure 6.5: Seven Segment Interfacing

Assembly Code
.include "8515def.inc"
.org 0
LDI

R16, low(RAMEND)

OUT

SPL, R16

LDI

R16, high(RAMEND)

OUT

SPH, R16

ldi r17,0xff
out portd,r17
here:
ldi r18,0x3f
out portd,r18
rcall delay
rcall delay
ldi r18,0x06
out portd,r18
rcall delay
rcall delay
ldi r18,0x5b
out portd,r18
rcall delay
rcall delay
ldi r18,0x4f
out portd,r18
rcall delay

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rcall delay
ldi r18,0x66
out portd,r18
rcall delay
rcall delay
ldi r18,0x6d
out portd,r18
rcall delay
rcall delay
ldi r18,0x7c
out portd,r18
rcall delay
rcall delay
ldi r18,0x07
out portd,r18
rcall delay
rcall delay
ldi r18,0x7f
out portd,r18
rcall delay
rcall delay
ldi r18,0x67
out portd,r18
rcall delay
rcall delay
rjmp here
delay: ldi r20,0xff
l2:ldi r21,0xff
1:dec r21
brne l1
dec r20
brne l2
ret

6.6 Keypad Interfacing
Assembly Code
.include "m8515def.inc"

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.org 0x00
ldi r16,high(ramend)
out sph,r16
ldi r16,low(ramend)
out spl,r16
ldi r17,0xf0
out ddra,r17
ldi r17,0xff
out ddrd,r17
ldi r17,0xff
out ddrc,r17
chek_key:
ldi r17,0b11101111
out porta,r17
rcall delay
sbis pina,pa0
rjmp next1
sbis pina,pa1
rjmp next2
sbis pina,pa2
rjmp next3
sbis pina,pa3
rjmp next4
ldi r17,0b11011111
out porta,r17
rcall delay
sbis pina,pa0
rjmp next5
sbis pina,pa1
rjmp next6
sbis pina,pa2
rjmp next7
sbis pina,pa3
rjmp next8
ldi r17,0b10111111
out porta,r17
rcall delay

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sbis pina,pa0
rjmp next9
sbis pina,pa1
rjmp next10
sbis pina,pa2
rjmp next11
sbis pina,pa3
rjmp next12
ldi r17,0b01111111
out porta,r17
rcall delay
sbis pina,pa0
rjmp next13
sbis pina,pa1
rjmp next14
sbis pina,pa2
rjmp next15
sbis pina,pa3
rjmp next16
rjmp chek_key
commandcode:
ldi r18,0x38
rcall command
rcall delay
ldi r18,0x0e
rcall command
rcall delay
ldi r18,0x01
rcall command
rcall delay
ldi r18,0x06
rcall command
rcall delay
ldi r18,0x84
rcall command
rcall delay
ret

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next1: rcall commandcode
rcall delay
ldi r18,'0'
rcall data
rcall delay
rjmp chek_key
next2: rcall commandcode
rcall delay
ldi r18,'1'
rcall data
rcall delay
rjmp chek_key
next3: rcall commandcode
rcall delay
ldi r18,'2'
rcall data
rcall delay
rjmp chek_key
next4: rcall commandcode
rcall delay
ldi r18,'3'
rcall data
rcall delay
rjmp chek_key
next5: rcall commandcode
rcall delay
ldi r18,'4'
rcall data
rcall delay
rjmp chek_key
next6: rcall commandcode
rcall delay
ldi r18,'5'
rcall data
rcall delay
rjmp chek_key
next7: rcall commandcode

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rcall delay
ldi r18,'6'
rcall data
rcall delay
rjmp chek_key
next8: rcall commandcode
rcall delay
ldi r18,'7'
rcall data
rcall delay
rjmp chek_key
next9: rcall commandcode
rcall delay
ldi r18,'8'
rcall data
rcall delay
rjmp chek_key
next10: rcall commandcode
rcall delay
ldi r18,'9'
rcall data
rcall delay
rjmp chek_key
next11: rcall commandcode
rcall delay
ldi r18,'a'
rcall data
rcall delay
rjmp chek_key
next12: rcall commandcode
rcall delay
ldi r18,'b'
rcall data
rcall delay
rjmp chek_key
next13: rcall commandcode
rcall delay

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ldi r18,'c'
rcall data
rcall delay
rjmp chek_key
next14: rcall commandcode
rcall delay
ldi r18,'d'
rcall data
rcall delay
rjmp chek_key
next15: rcall commandcode
rcall delay
ldi r18,'e'
rcall data
rcall delay
rjmp chek_key
next16: rcall commandcode
rcall delay
ldi r18,'f'
rcall data
rcall delay
rjmp chek_key
command: out portd,r18
cbi portc,4
sbi portc,5
rcall delay
cbi portc,5
ret
data: out portd,r18
sbi portc,4
sbi portc,5
rcall delay
cbi portc,5
ret
delay: ldi r19,0xff
l1: ldi r20,0x0f
l2: dec r20

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brne l2
dec r19
brne l1

1

2

3

ON

0

=

+
4

C

D

C

LCD1

D0
D1
D2
D3
D4
D5
D6
D7

LM016L

1
2
3

ATMEGA8515

6

7
8
9
10
11
12
13
14

31
30
29

5

RS
RW
E

PE0/ICP/INT2
PE1/ALE
PE2/OC1B

21
22
23
24
25
26
27
28

4

4
5
6

XTAL1
XTAL2
RESET

PC0/A8
PC1/A9
PC2/A10
PC3/A11
PC4/A12
PC5/A13
PC6/A14
PC7/A15/TDI

39
38
37
36
35
34
33
32

9

VSS
VDD
VEE

19
18
9

PD0/RXD
PD1/TXD
PD2/INT0
PD3/INT1
PD4/XCK
PD5/OC1A
PD6/WR
PD7/RD

PA0/AD0
PA1/AD1
PA2/AD2
PA3/AD3
PA4/AD4
PA5/AD5
PA6/AD6
PA7/AD7

8

3

10
11
12
13
14
15
16
17

PB0/T0/OC0
PB1/T1
PB2/AIN0
PB3/AIN1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK

7

B

1

U1
1
2
3
4
5
6
7
8

A

2

ret

Figure 6.6: Keypad Interfacing

6.7 USART Interfacing
AssemblyCode
.include "m8515def.inc"
.cseg
.org 0x00
ldi r16,high(ramend)
out sph,r16
ldi r16,low(ramend)
out spl,r16
rcall usart_init
main: rcall usart_transmit

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rcall delay
rjmp main
usart_init:
ldi r16,0x00
out ubrrh,r16
ldi r16,51
out ubrrl,r16
ldi r16,(1<<rxen)|(1<<txen)
out ucsrb,r16
ldi r16,(1<<ursel)|(1<<usbs)|(3<<ucsz0)
out ucsrc,r16
ret
usart_transmit:
sbis ucsra,udre
rjmp usart_transmit
ldi r16,'f'
out udr,r16
nop
nop
nop
nop
ret
delay:
ldi r16,0xff
l1: ldi r17,0xff
l2: dec r17
brne l2
dec r16
brne l1
ret

CHAPTER-7
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Softwares Used
7.1 Keil µ Vision
Keil MicroVision is a free software which solves many of the pain points for an
embedded program developer. This software is an integrated development
environment (IDE), which integrated a text editor to write programs, a
compiler and it will convert your source code to hex files too.
7.1.1 Steps to use Keil

Step 1: After opening Keil uV4, Go to Project tab and Create new uVision
project .Now Select new folder and give name to Project

Figure 7.1: Opening new project

Step 2: Select device model.

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Figure 7.2: Selecting device model
Step 3: Now go to File and create new file and save it with .C extension if you
will write program in C language or save with .asm for assembly language.
Now write program and save it again.Right click on target and click
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on options for target. Click output tab here & check create Hex file Right click
on group and click on Add files to source group.

Figure 7.3: Options for target

Figure 7.4:Adding Files to Source group

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Step-4: Click on Build target.

Figure 7.5:Building Target

Figure 7.6: Built Output

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7.2 AVR Studio
Run :Start\Programs\Atmel AVR Tools\AVR Studio.

Figure 7.7: Creating new Project

To create a new project, we click on New Project (new Projects can also be
created later by selecting Project\New from the Menu system). On the next
dialog Box, we select Atmel AVR assembler, enter the project name

and

navigate to our desired location by clicking the button labeled “…”

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Figure 7.8: Selecting Device

Figure 7.9:Editor Window

Then we save your file and build it.

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Figure 7.10:Error Window

7.3 Pony Prog Serial Programmer
PonyProg is a serial device programmer based on some simple and
cheap interfaces for the PC and a user friendly GUI available for
Windows9x/NT/2K/XP and Intel Linux. Its purpose is programming every
serial device like eeproms and microcontrollers.

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Figure 7.11: Pony Prog Window

7.4 ORCAD 9.1
7.4.1 Starting Capture
The Orcad Family installation process offers a default location for Capture
and adds Orcad Family Release to the Programs menu (available from the
Start button).To start Capture
1 From the Start menu, point to Programs and choose Orcad Family Release.
2 From the Orcad Family Release menu item, choose Capture. Once you start
Capture, you see the Capture session frame . You do all your schematic design and processing within this
window.

Figure7.12: Capture Window

The minimized Session Log icon in the lower left portion of the Capture
session frame is the session log. The session log provides information about
everything you have donein the current Capture session.

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Figure 7.13:New project window

These resources include schematic folders, schematic pages, part
libraries, parts, VHDL files, and output reports such as bills of materials and
net lists
In the schematic page editor, we can display and edit schematic pages.
We can place parts, wires, buses, and draw graphics. The schematic page
editor has a tool palette that we can use to draw and place everything we
need to create a schematic page. We can print from within the schematic
page editor, or from the project manager window.

Figure 7.14: Schematic page editor

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Figure 7.15: Part Editor

Figure 7.16:Session log Window

7.4.2 Creating Netlist
1.In the project manager, select your design.
2. From the Tools menu, choose Create Netlist. The Create Netlist dialog box
displays.

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Figure 7.17: Creating Netlist

7.4.3 Creating Bill of materials
From the project manager’s Tools menu, choose Bill of Materials. The
Bill of Materials dialog box displays.Fill in this dialog box as desired.

Figure 7.18:Creating bill of materials

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7.4.4 Orcad Layout Plus
Layout Plus is a circuit board layout tool that accepts a layoutcompatible circuit
netlist (ex. from Capture CIS) and generates an output layout files that
suitable for PCB
fabrication.
To open Layout Plus, from Windows Start Menu, select Program then
Layout Plus. Go to File and New to create a new design. You will see the
dialog . Enter the default technology template located on C:\Program
files\Orcad\tools\layout_plus\data\_default.tch in “Input Layout TCH” textbox.
Enter the netlist (generated from Capture CIS) of your design in “Input MNL”
textbox. And then enter the location and file name that you want the design
file to be
saved in “Output Layout” textbox. Layout Plus will give the output layout file
name as same as the input netlist file by default. If you change the output
file, do not change the output file extension (.max). Then click Apply ECO.

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Figure 7.19: Layout Plus Window after importing netlist

Figure 7.20: Preplace components

Figure 7.21: Board after routing

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CHAPTER-8

PCB Designing
8.1 Introduction
A PCB is a printed circuit board, also known as a printed wiring
board. It is used in electronics to build electronic devices. A PCB serves
two purposes in the construction of an electronic device; it is a place to
mount the components and it provides the means of electrical connection
between the components.
The inventor of the printed circuit was the Austrian engineer Paul
Eisler (1907–1995) who, while working in England,made one circa 1936 as
part
of
a
radio
set.

8.2 Material
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Conducting layers are typically made of thin copper foil. Insulating
layers dielectric are typically laminated together with epoxy resin
prepreg. The board is typically coated with a solder mask that is green in
color. Other colors that are normally available are blue and red. There are
quite a few different dielectrics that can be chosen to provide
different insulating values depending on the requirements of the circuit.
Some of these dielectrics are polytetrafluoroethylene (Teflon), FR-4, FR-1,
CEM-1 or CEM-3. Well known prepreg materials used in the PCB industry
are FR-2 (Phenolic cotton paper), FR-3 (Cotton paper and epoxy), FR-4
(Woven glass and epoxy), FR-5 (Woven glass and epoxy), FR-6(Matte glass
and polyester), G-10(Woven glass and epoxy), CEM-1 (Cotton paper and
epoxy), CEM-2 (Cotton paper and epoxy), CEM-3 (Woven glass and
epoxy),CEM-4 (Woven glass and epoxy), CEM-5 (Woven glass and
polyester). Thermal expansion is an important consideration especially
with BGA and naked die technologies, and glass fiber offers the
best dimensional stability.

8.3 Patterning
The vast majority of printed circuit boards are made by bonding a
layer of copper over the entire substrate, sometimes on both sides,
(creating
a
"blank
PCB")
then
removing unwanted
copper
after applying a temporary mask (e.g. by etching), leaving only the
desired copper traces. A few PCBs are made by adding traces to the
bare substrate (or asubstrate with a very thin layer of copper) usually
by a complex process of multiple electroplating steps. The
PCBmanufacturing method primarily depends on whether it is
for production volume or sample/prototype quantities. PCB milling uses
a two or three- axis mechanical milling system to mill away the copper
foil from the substrate. A PCB milling machine (referred to as a 'PCB
Prototyper') operates in a similar way to a plotter, receiving
commands from the host software that control the position of the
milling head in the x, y, and (if relevant) z axis. Data to drive
the Prototyper is extracted from files generated in PCB design software
and stored in HPGL or Gerber file format.

8.4 Etching
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Chemical etching is done with ferric chloride, ammonium persulfate,
or sometimes hydrochloric acid.For PTH (plated-through holes),
additional steps of electroless deposition are done after the holes
are drilled, then copper is electroplated to build up the thickness, the
boards are screened, and plated with tin/lead. The tin/lead becomes the
resist leaving the bare copper to be etched away.

8.5Laminating
Some PCBs have trace layers inside the PCB and are called multi-layer
PCBs. These are formed by bonding together separately etched thin
boards.

8.6Drilling
Holes through a PCB are typically drilled with tiny drill bits made of solid
tungsten carbide. The drilling is performed by automated drilling machines
with placement controlled by a drill tape or drill file. These computergenerated files are also called numerically controlled drill (NCD) files or
"Excellon files". The drill file describes the location and size of each drilled
hole. These holes are often filled with annular rings (hollow rivets) to
create vias. Vias allow the electricaland thermal connection of conductors
on opposite sides of the PCB.Most common laminate is epoxy filled
fiberglass.Drill bit wear is partly due to embedded glass, which is harder
than steel. High drill speed necessary for cost effectivedrilling of hundreds
of holes per board causes very high temperatures at the drill bit tip, and
high temperatures (400-700 degrees) soften steel and decompose
(oxidize)
laminate
filler. Copper
is
softer
than
epoxy
and interior conductors may suffer.When very small vias are required,
drilling with mechanical bits is costly because of high rates of wear and
breakage. In this case, the vias may be evaporated by lasers. Laser-drilled
vias typically have an inferior surface finish inside thehole. These holes
are called micro vias.It is also possible with controlled-depth drilling, laser
drilling, or by pre-drillingthe individual sheets of the PCB
before lamination, to produce holes that connect only some of the copper
layers, rather than passing through the entire board. These holes
are called blind vias when they connect an internal copper layer to an
outer layer, or buried vias when they connect two or more internal copper
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layers and no outer layers.The walls of the holes, for boards with 2 or
more layers, are made conductive then plated with copper to form platedthrough holes that electrically connect the conducting layers of the PCB.
For multilayer boards, those with 4 layers or more, drilling typically
produces a smear of the high temperature decomposition products of
bonding agent in the laminate system. Before the holes can be
plated through, this smear must be removed by a chemical de-smear
process, or by plasma-etch. Removing(etching back) the smear also
reveals the
interior
conductors
as
well.

8.7 Exposed conductor plating and coating
PCBs are plated with solder, tin, or gold over nickel as a resist for
etching away the unneeded underlying copper.After PCBs are etched and
then rinsed with water, the soldermask is applied, and then any exposed
copper is coated with solder, nickel/gold, or some other anti-corrosion
coating.Matte solder is usually fused to provide a better bonding surface
or stripped to bare copper. Treatments, such as benzimidazolethiol,
prevent surface oxidation of bare copper. The places to which components
will be mounted are typically plated, because untreated bare
copper oxidizes quickly, and therefore is not readily solderable.
Traditionally, any exposed copper was coated with solder by Hot air solder
levelling (HASL). This solder was a tin-lead alloy, however new solder
compounds are now used to achieve compliance with the RoHS directive
in the EU and US, which restricts the use of lead. One of these leadfree compounds is SN100CL, made up of 99.3% tin, 0.7% copper, 0.05%
nickel, and a nominal of 60ppm germanium.It is important to use solder
compatible with both the PCB and the parts used. An example is Ball Grid
Array (BGA) using tin-lead solder balls for connections losing their balls on
bare copper traces or using lead-free solder paste.Other platings used are
OSP (organic surface protectant), immersion silver (IAg), immersion tin,
electroless nickel with immersion gold coating (ENIG), and direct gold
plating (over nickel). Edge connectors, placed along one edge of some
boards, are often nickel plated then gold plated. Another coating
consideration is rapid diffusion of coating metal into Tin solder. Tin forms
intermetallics such as Cu5Sn6 and Ag3Cu that dissolve into the Tin
liquidus or solidus(@50C), stripping surface coating and/or leaving
voids.Electrochemical migration (ECM) is the growth of conductive
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metal filaments on or in a printed circuit board (PCB) under the influence
of a DC voltage bias. Silver, zinc, and aluminum are known to grow
whiskers under the influence of an electric field. Silver also grows
conducting surface paths in the presence of halide and other ions, making
it a poor choice for electronics use. Tin will grow "whiskers" due to
tension in the plated surface. Tin-Lead or Solder plating also grows
whiskers, only reduced by the percentage Tin replaced. Reflow to melt
solder or tin plate to relieve surface stress lowers whisker incidence.

8.8Solder resist
Areas that should not be soldered may be covered with a polymer
solder resist (solder mask) coating. The solder resist prevents solder from
bridging between conductors and creating short circuits. Solder resist also
provides some protection from the environment. Solder resist is typically
20-30 micrometres thick

8.9 Printed circuit assembly
After the printed circuit board (PCB) is completed, electronic
components must be attached to form a functional printed circuit
assembly,or PCA (sometimes called a "printed circuit board assembly"
PCBA). In through-hole construction, component leads are inserted in
holes. In surface-mount construction, the components are placed on
pads or lands on the outer surfaces of the PCB. In both kinds of
construction, component leads are electrically and mechanically fixed to
the board with a molten metal solder.There are a variety of soldering
techniques used to attach components to a PCB.High volume production is
usually done with machine placement and bulk wave soldering or reflow
ovens, but skilledtechnicians are able to solder very tiny parts (for
instance 0201 packages which are 0.02 in. by 0.01 in.) by hand under
a microscope, using tweezers and a fine tip soldering iron for small volume
prototypes. Some parts are impossible to solder by hand, such as ball grid
array (BGA) packages.Often, through-hole and surface-mount construction
must be combined in a single assembly because some required
components are available only in surface-mount packages, while
others are available only in through-hole packages. Another reason to use
both methods is that through-hole mounting can provide needed strength
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for components likely to endure physical stress, while components that are
expected to go untouched will take up less space using surface-mount
techniques.After the board has been populated it may be tested in a
variety of ways:While the power is off, visual inspection, automated
optical inspection. JEDECguidelines for PCB component placement,
soldering, and inspection are commonly used to maintain quality control in
this stage of PCB manufacturing. While the power is off, analog signature
analysis, power-off testing.While the power is on, in-circuit test, where
physical measurements (i.e. voltage, frequency) can be done.While the
power is on, functional test, just checking if the PCB does what it had been
designed for.To facilitate these tests, PCBs may be designed with extra
pads to make temporary connections.Sometimes these pads must be
isolated with resistors. The in-circuit test may also exercise boundary
scan test features of some components. In-circuit test systems may also
be used to program nonvolatile memory components on the board.In
boundary scan testing, test circuits integrated into various ICs on the
board form temporary connections between the PCB traces to test that the
ICs are mounted correctly. Boundary scan testing requires that all the ICs
to be tested use a standard test configuration procedure, the most
common one being the Joint Test Action Group (JTAG) standard.When
boards fail the test, technicians may desolder and replace failed
components, a task known as rework.

8.10Surface Mount Technology

Figure:8.1SMT Technology

Surface-mount technology emerged in the 1960s, gained momentum
in the early 1980s and became widely used by the mid
1990s.Components were mechanically redesigned to have small metal
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tabs or end caps that could be soldered directly on to the PCB
surface.Components became much smaller and component placement on
both sides of the board became more common than with through-hole
mounting, allowing much higher circuit densities. Surface mounting lends
itself well to a high degree of automation,reducing labour costs
and greatly increasing production and quality rates. Carrier Tapes provide
a stable and protective environment for Surface mount devices (SMDs)
which can be one-quarter to one-tenth of the size and weight, and
passive components can be one-half to one-quarter of the cost of
corresponding through-hole parts. However, integrated circuits are often
priced the same regardless of the package type, because the chip itself is
the most expensive part. As of 2006, some wire-ended components, such
as small-signal switch diodes are actually significantly cheaper than
corresponding SMD versions.

8.11 Different types of PCB:
1)Breadboard
This is a way of making a temporary circuit, for testing purposes or to
try out an idea. No soldering is required and all the components can be
re-used afterwards. It is easy to change connections and replace
components.

Figure8.2: Breadboard

2)Stripboard
Stripboard has parallel strips of copper track on one side. The strips
are 0.1" (2.54mm) apart and there are holes every 0.1" (2.54mm). It can
be cut with a junior hacksaw, or simply snap it along the lines of holes by
putting it over the edge of a bench or table and pushing hard.
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Figure8.3: Stripboard

3)Printed Circuit Board
Chemical etching is done with ferric chloride, ammonium persulfate, or
sometimes hydrochloric acid.For PTH (plated-through holes), additional
steps of electroless deposition are done after the holes are drilled, then
copper is electroplated to build up the thickness, the boards are screened,
and plated with tin/lead. The tin/lead becomes the resist leaving the bare
copper to be etched away.

CHAPTER-9

ARM PROCESSOR
9.1 Introduction
The idea behind the Reduced Instruction Set computer (RISC )
originated in processor research programmers at Stanford and Brekeley
universities around 1980 through some of the central ideas can be traced
back to earlier machines.ARM1 prototype was designed in 1985.
ARM stands for Advanced RISC Machine.It was invented as a joint
venture between Apple, Acorn and VLSI in November 1990.ARM is the
industry’s leading provider of 16/32bit RISC processor.The company licences
the high performance,low cost and high efficiency RISC processor.ARM
provides a comprehensive support required in building a whole system.
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9.2 Features of ARM



ARM core is a single core, whole family of designs sharing similar
design principles and a common instruction set.



ARM7TDMI is one of ARM’s most successful core.



It provides 120 Dhrystone MIPS.



It is known for high code density.



ARM processor has been specifically designed to be small.



Consumes low power making it ideal for mobile embedded devices.



ARM is a RISC processor.



ARM peripherals are memory mapped( Programming interface is a set
of memory addressed registers.)Address of these registers is an offset
from a specific peripheral base address.



ARM has incorporated hardware debug technology within the processor
so that software engineers can view what is happening while the
processor is executing code.(JTAG port).

9.3 RISC Processor
RISC processors are aimed to deliver simple powerful instructions that
execute within a single cycle at a high clock speed.RISC processors reduce
complexity of instructions performed by the hardware because it provides
greater flexibility and intelligence in software.RISC have a reduced no. of
instruction classes. These classes provide simple operations which get
executed in a single cycle. There are fixed length instructions in RISC.RISC
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processors support pipelining.RISC machines have large general purpose
register set. With these features make RISC processor simple, thus core can
operate at higher clock frequencies.

9.4The ARM programmer's model
A

processor's

instruction

set

defines

the

operations

that

the

programmer can use to change the state of the system incorporating the
processor. This state usually comprises the values of the data items in the
processor's visible registers and the system's memory. Each instruction can
be viewed as performing a defined transformation from the state before the
instruction is executed to the state after it has completedWhen writing userlevel programs, only the 15 general-purpose 32-bit registers (r0 to r!4), the
program counter (r15) and the current program status register (CPSR) need
be considered. The remaining registers are used only for system-level
programming and for handling exceptions (for example, interrupts).

Figure 9.1 ARM's visible registers

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Figure 9.2 ARM CPSR format.

The Current Program Status Register (CPSR)
The CPSR is used in user-level programs to store the condition code
bits. These bits are used, for example, to record the result of a comparison
operation and to control whether or not a conditional branch is taken. The
bits at the bottom of the register control the processor mode, instruction set
and interrupt enables and are protected from change by the user-level
program. The condition code flags are in the top four bits of the register and
have the following meanings:
• N: Negative; the last ALU operation which changed the flags produced a
negative result (the top bit of the 32-bit result was a one).
• Z: Zero; the last ALU operation which changed the flags produced a zero
result (every bit of the 32-bit result was zero).
• C: Carry; the last ALU operation which changed the flags generated a carryout,either as a result of an arithmetic operation in the ALU or from the shifter.
• V: oVerflow; the last arithmetic ALU operation which changed the flags
generated an overflow into the sign bit.
The memory System
In addition to the processor register state, an ARM system has memory
state. Memory may be viewed as a linear array of bytes numbered from zero
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up to 232.Data items may be 8-bit bytes, 16-bit half-words or 32-bit words.
Words are always aligned on 4-byte boundaries (that is, the two least
significant address bits are zero) and half-words are aligned on even byte
boundaries. A small area of memory where each byte location has a unique
number. A byte may occupy any of these locations. A word-sized data item
must occupy a group of four byte locations starting at a byte address which
is a multiple of four. Half-words occupy two byte locations starting at an even
byte address.
Load-store architecture
In common with most RISC processors, ARM employs a load-store
architecture.This means that the instruction set will only process (add,
subtract, and so on)values which are in registers (or specified directly within
the instruction itself), and will always place the results of such processing
into a register. The only operations which apply to memory state are ones
which copy memory values into registers (load instructions) or copy register
values into memory (store instructions). CISC processors typically allow a
value from memory to be added to a value in a register, and sometimes
allow a value in a register to be added to a value in memory.ARM does not
support such 'memory-to-memory' operations. Therefore all ARM instructions
fall into one of the following three categories:
1. Data processing instructions. These use and change only register values.
For example, an instruction can add two registers and place the result in a
register.
2. Data transfer instructions. These copy memory values into registers (load
instructions) or copy register values into memory (store instructions). An
additional form, useful only in systems code, exchanges a memory value
with a register value.
3. Control flow instructions. Normal instruction execution uses instructions
stored at consecutive memory addresses. Control flow instructions cause
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execution to switch to a different address, either permanently (branch
instructions) or saving a return address to resume the original sequence
(branch and link instructions) or trapping into system code (supervisor calls).
9.4

.1Processor modes

The ARM has six operating modes:




User (unprivileged mode under which most tasks run) (10000)
FIQ (p) (entered when a high priority (fast) interrupt is raised) (10001)
IRQ (p) (entered when a low priority (normal) interrupt is raised)



(10010)
Supervisor (p) (entered after reset and and is generally the mode that




an os kernel operates in) (10011)
Abort ( p) (used to handle memory access violations) (10111)
Undef ( p) (used to handle undefined instructions) (11011)

ARM Architecture Version 4 adds a seventh mode:


System (p) (privileged mode using the same registers as user mode)
(11111)
Every Processor mode except user mode can change mode by writing

directly to the mode bits in cpsr.All processors modes except system
mode have a set of associated banked registers that are a subset of the
main 16 registers. Processor mode can be changed by a program that
writes directly to the cpsr( the processor core has to be in privileged
mode) or by hardware when the core responds to an exception or
interrupt.

Figure 9.3:ARM operating modes and register usage

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User32 / System
FIQ32Supervisor32
Abort32 IRQ32Undefined32
r0
r0
r0
r0
r0
r0
r1
r1
r1
r1
r1
r1
r2
r2
r2
r2
r2
r2
r3
r3
r3
r3
r3
r3
r4
r4
r4
r4
r4
r4
r5
r5
r5
r5
r5
r5
r6
r6
r6
r6
r6
r6
r7
r7
r7
r7
r7
r7
r8
r8_fiq
r8
r8
r8
r8
r9
r9_fiq
r9
r9
r9
r9
r10
r10
r10
r10
r10_fiq r10
r11
r11
r11
r11
r11_fiq r11
r12
r12_fiq r12
r12
r12
r12
r13 (sp) r13_fiq r13_svc r13_abt r13_irq r13_undef
r14 (lr) r14_fiq r14_svc r14_abt r14_irq r14_undef
r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc)
Program Status Registers
cpsr
cpsr
cpsr
cpsr
cpsr
cpsr
sprsr_fiq
spsr_fiq spsr_svc spsr_abt sprsr_fiq
spsr_irq sprsr_fiq
spsr_u
ndef
Figure 9.4 :Register usage of different modes

9.5 Exceptions
Exceptions are usually used to handle unexpected events which arise
during the execution of a program, such as interrupts or memory faults. In
the ARM architecture the term is also used to cover software interrupts and
undefined instruction traps (which do not really qualify as 'unexpected') and
the system reset function which logically arises before rather than during the
execution of a program (although the processor may be reset again while
running). These events are all grouped under the 'exception' heading
because they all use the same basic mechanism within the processor. ARM
exceptions may be considered in three groups:

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1. Exceptions generated as the direct effect of executing an instruction.
Software

interrupts,

undefined

instructions

(including

coprocessor

instructions where the requested coprocessor is absent) and prefetch aborts
(instructions that are invalid due to a memory fault occurring during fetch)
come under this heading.
2. Exceptions generated as a side-effect of an instruction. Data aborts (a
memory fault during a load or store data access) are in this class.
3. Exceptions generated externally, unrelated to the instruction flow. Reset,
IRQ and FIQ fall into this category.
When an exception arises, ARM completes the current instruction as
best it can (except that reset exceptions terminate the current instruction
immediately) and then departs from the current instruction sequence to
handle the exception. Exception entry caused by a side-effect or an external
event usurps the next instruction in the current sequence; direct-effect
exceptions are handled in sequence as they arise. The processor performs
the following sequence of actions:
• It changes to the operating mode corresponding to the particular
exception.
• It saves the address of the instruction following the exception entry
instruction in r14 of the new mode.
• It saves the old value of the CPSR in the SPSR of the new mode.
• It disables IRQs by setting bit 7 of the CPSR and, if the exception is a fast
inter rupt, disables further fast interrupts by setting bit 6 of the CPSR.
• It forces the PC to begin executing at the relevant vector address.
Table 9.1: Exceptions vector addresses

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Once the exception has been handled the user task is normally
resumed. This requires the handler code to restore the user state exactly as
it was when the exception first arose:

• Any modified user registers must be restored from the handler's stack.
• The CPSR must be restored from the appropriate SPSR.
• The PC must be changed back to the relevant instruction address in the
user instruction stream.
Since multiple exceptions can arise at the same time it is necessary to
define a priority order to determine the order in which the exceptions are
handled. On ARM this is:
1. reset (highest priority)
2. data abort
3. FIQ
4. IRQ
5. prefetch abort
6. SWI, undefined instruction (including absent coprocessor). These are
mutually exclusive instruction encodings and therefore cannot occur
simultaneously.
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Reset starts the processor from a known state and renders all other
pending exceptions
irrelevant.

9.6 State and Instruction set
Two instruction sets are :i)

ARM

ii)

Thumb (T bit in cpsr is 1).

9.6.1 ARM & Thumb instruction set features
Table 9.2: ARM and Thumb mode features

ARM (cpsr T-0)

Tumb (cpsr T=1)

Instruction size

32-bit

16-bit

Core instruction

58

30

Conditional execution

most

Only branch instructions

Data Processing instruction

Access to barrel shifter and ALU

Separate barrel shifter and
ALU instructions

Program status register

Read-write in privileged mode

No direct access

Register usage

15 general purpose register +pc

8 general purpose registers
+7 high registers +pc

9.6

.2Coprocessors
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Coprocessors extends the processing features of a core by extending the
instruction set or by providing configuration registers.More than one
coprocessor can be added to the ARM core via the coprocessor interface.The
coprocessor can be accessed through a group of dedicated ARM instructions
that provide a load –store type interface.E.g coprocessor 15 which controls
the cache, TCM, and memory management.
Coprocessor can also extend the instruction set by providing a specialized
group of new instructions.E.g Set on instruction to perform vector floating –
point (VFP) operations.The new instructions are processed in the decode
stage of ARM pipeline. If the decode stage sees a coprocessor instruction,
then it offers it to the relevant coprocessor. If coprocessor is not present then
ARM takes an undefined instruction exception which allows us to emulate the
behavior of the coprocessor in software.

9.7 Data Processing Instructions
The ARM data processing instructions are used to modify data values in
registers. The operations that are supported include arithmetic and bit-wise
logical combinations of 32-bit data types. One operand may be shifted or
rotated to the ALU, allowing, for example, shift and add in a single
instruction. These are the only Instruction that modify the data values in
ARM. Typically require two operands & produce single results. The ARM data
processing instructions employ a 3-address format, which means that the
two

source

operands

and

the

destination

register

are

specified

independently. One source operand is always a register; the second may be a
register, a shifted register or an immediate value. The shift applied to the
second operand, if it is a register, may be a logical or arithmetic shift or a
rotate and it may be by an amount specified either as an immediate quantity
or by a fourth register
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9.7.1 Bitwise logical operations
Table 9.3 Bitwise logical operations

AND r0, r1, r2

r0 := r1 and r2

ORR r0, r1, r2

r0 := r1 or r2

or

r0 = r1 |

r2
EOR r0, r1, r2

r0 := r1 xor r2 or

r0 = r1^r2

BIC r0, r1, r2

r0 := r1 and (not) r2 or r0=r1
&^ r2
Pre

post

r1 =0b1111

BIC r0,r1,r2

r0=0b1010
r2 =0b0101

9.7.2 Comparison operation
Table 9.4: Comparison operation

CMP r1, r2 compare

set cc flag on r1 - r2

CMN r1, r2 compare negated

Set cc flag on r1 + r2

TST r1, r2 test for quality of two

set flag cc on r1 and r2

32 bit value
TEQ r1, r2 test for equality of 32-

set flag cc on r1 xor r2

bit values

or r1^r2

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9.7.3 Arithmetic operations
Table 9.5: Arithmetic operations

ADD r0, r1, r2

r0 := r1 + r2

ADC r0, r1, r2

r0 := r1 + r2 + C

SUB r0, r1, r2

r0 := r1 – r2

SBC r0, r1, r2

r0 := r1 - r2 + C – 1

or

r0 = r1-r2-!

(carry flag)
RSB r0, r1, r2

r0 := r2 – r1
Pre
r0=0x00000000
r1=0x00000077
RSB r0,r1, #0 ;

Rd= 0x0 –r1

Post r0 = -r1=0xffffff89

RSC r0, r1, r2

r0 := r2 – r1 + C – 1

or

r0= r2-r1-!

(carry flag)
9.7.4 Multiply Instructions
ARM multiply instructions produce the product of two 32-bit binary
numbers held in registers. The result of multiplying two 32-bit binary
numbers is a 64-bit product. Some forms of the instruction, available only on
certain versions of the processor, store the full result into two independently
specified registers; other forms store only the least significant 32 bits into a
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single register.In all cases there is a multiply-accumulate variant that adds
the product to a running total and both signed and unsigned operands may
be used. The least significant 32 bits of the result are the same for signed
and unsigned operands, so there is no need for separate signed and
unsigned versions of the 32-bit result instructions.

Figure 9.5:Multiply instruction binary encoding
Table 9.6: Multiply operations

MLA

Multiply &accumulate

Rd=(Rm* Rs)+Rn

MUL

Multiply

Rd =Rm *Rs

9.8 Load Store Instructions
Table 9.7 :Load Store instructions

LDR

Load word into a reg.

Rd<-mem32[address]

STR

Save byte or word from a

Rd->mem32[address]

reg.
LDRB

Load byte into a reg.

Rd<-mem8[address]

STRB

Save byte from a reg.

Rd->mem8[address]

LDRH

Load halfword into a reg.

Rd<-mem16[address]

STRH

Save halfword from a reg.

Rd->mem16[address]

LDRSB

Load signed byte into a

Rd<-SignExtend

reg.

(mem8[address])

9.9 ARM architecture
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Architecture version
- Version 1 (obsolete)
• Basic data processing
• Byte, word and multi-word load/store
• Software interrupt
• 26 bit address bus
• No Multiply & Coprocessor Support
- Version 2 (obsolete)
• Multiply
• Coprocessor support
• 26 bit address bus
• First ARM with on-chip Cache (Coprocessor CP15)
• SWAP Instruction Introduced
- Version 3
• 32 bit address bus
• Separate CPSR, SPSR
• Add MRS, MSR. Modify exception handler
• Add ‘Abort Mode’ and ‘Undef Mode’
• Was Backward Compatible with 26-bit
• MUL & MLA
- Version 4
• Half word transfer
• Introduce THUMB processor state
• Add ‘Privileged mode’ for operating system
• First fully formalized architecture
- Version 5
• Improve ARM/THUMB inter-working
• Add CLZ instruction for efficient integer divide
• Add software breakpoint
• Add more coprocessor support
• More tight definition of arithmetic flags

9.10 ARM Based Products

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Figure 9.5:Applications of ARM

BIBILOGRAPHY
I.
II.
III.
IV.
V.
VI.
VII.
VIII.

The MAZIDI BOOKS
ENGINEERSGARAGE.COM
WIKIPEDIA.ORG
ATMEL.COM
DATASHEETS.COM
CIRCUITSTODAY.COM
PDFs FROM VARIOUS SITES
GOOGLE.COM

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