Interface

interface mem_interface (input bit slow_clock);
logic [07:00] mem_rdata;
logic [07:00] mem_wdata;
logic [01:00] mem_addr;
logic mem_rstn;
logic mem_en;
logic mem_rd_wr;
clocking cb@(posedge slow_clock);
default input #1 output #1;
input mem_rdata;
output mem_wdata;
output mem_addr;
output mem_en;
output mem_rd_wr;
output mem_rstn;
endclocking
modport MEM (clocking cb, input slow_clock);
endinterface
interface input_interface (input bit fast_clock);
logic data_stall;
logic data_valid;
logic [07:00] data;
logic reset;
clocking cb@(posedge fast_clock);
default input #1 output #1;
input data_stall;
output data_valid;
output data;
endclocking
modport IP(clocking cb,output reset,input fast_clock);
endinterface
interface output_interface(input bit slow_clock);
logic read;
logic ready;
logic [7:0] port;
clocking cb@(posedge slow_clock);
default input #1 output #1;
output read;
input ready;
input port;
endclocking
modport OP(clocking cb, input slow_clock);
endinterface