L1
Content
L1: INTRODUCTION
2010/2011-2
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES
CAD for Electronic Design
1
L1: INTRODUCTION
2010/2011-2
INTEGRATED CIRCUITS (IC)
●
●
●
● ●
An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et al. of Bell Laboratories invented transistor in 1948. Most current integrated circuits are built with MOSFET (metal oxidesemiconductor fieldeffect transistor) transistors. ICs commercially available since early 1960s. Phenomenal advancement in IC design and fabrication technologies.
CAD for Electronic Design
2
L1: INTRODUCTION
2010/2011-2
●
●
More and more transistors are packed in a chip SSI, MSI, LSI, and VLSI. Currently millions of transistors in a single chip. E.g., Intel Pentium IV processor has 40 million transistors using 0.13 µm technology. Integration Scale SSI MSI LSI VLSI Number of Transistors < 10 10 – 1,000 1,000 – 10,000 > 10,000 Examples Logic gates Adders, counters Multipliers Microprocessors
CAD for Electronic Design
3
L1: INTRODUCTION
2010/2011-2
●
●
Moore's Law Maximum number of transistors on a chip approximately doubles every eighteen months. This prediction has been accurate for the last four decades.
On-Chip Transistor Count
1 09 1 08 1 07 1 06 1 05 1 04 1 03 1 02 1970 1980 1990 Ye a r 2000
CAD for Electronic Design
4
L1: INTRODUCTION
2010/2011-2
DIGITAL IC IMPLEMENTATION ALTERNATIVES
● ●
●
●
●
Various implementation of digital logic designs Traditional offtheshelf IC chips, e.g., SSI and MSI TTL, perform a fixed operation defined by the device manufacturer. Applicationspecific Integrated Circuits (ASICs) are customized ICs whose internal functional operation is userdefined. CPLD or FPGA requires user hardware programming to perform the desired operation. The circuitlevel design of a VLSI or ASIC chip involves circuit components design, placement, and interconnect routing.
CAD for Electronic Design
5
L1: INTRODUCTION
2010/2011-2
Digital Implementation Alternatives
Standard Components
VLSI Integrated Circuits
SoC
(System-on-Chip)
Applications fixed
Applications by Programming
Reconfigurable ASIC
Semicustom VLSI
Structured ASIC
Full-custom VLSI
Prefabricated Logic Gates Software Hardware Reconfigurable Masked Gate & Logic Programming Programming Array (MGA) Microchip Modules CMOS TTL ECL Microprocessor & EPROM PLA PLD ROM Channeled GA Sea-of-gates GA master slice
Standard Cell-based Design
FPGA CPLD
CAD for Electronic Design
6
L1: INTRODUCTION
2010/2011-2
●
●
●
●
●
Fullcustom VLSI uses circuit elements, e.g., transistors and connections as the primitive components. Offers a designer flexibility to optimize circuit characteristics, placement, and their interconnects, as long as certain design rules are satisfied. Very time consuming for complex ICs and requires a full knowledge of the operation of the components at the circuit level. Semicustom design uses a library of circuitlevel cells (standard cells) specified by their functions and characteristics. The use of standard cells at the logic level simplifies the design process, but reduces design flexibility.
CAD for Electronic Design
7
L1: INTRODUCTION
2010/2011-2
● ●
Another semicustom style is the gatearray design. Basic components (usually basic gates) are placed on a regular structure within a chip, and the design consists of determining the connections between the gates.
Horizontal routing channel a a' abd (y = abc + a'c + c'd) y
b b' a'c
c c' c'd
d Vertical routing channel (z = a + b) z
CAD for Electronic Design
8
L1: INTRODUCTION
2010/2011-2
●
A combination of fullcustom and semicustom design is best, where the critical portions of the system are designed using fullcustom. IC TYPE Mask layers customized All All Some None Logic cells customized Some None None None Fabrication lead time > 2 months ~2 months ~1 to 2 weeks
Fullcustom VLSI Standard Cellbased ASIC Masked Gate Arrays FPGA / CPLD
CAD for Electronic Design
9
L1: INTRODUCTION
2010/2011-2
DIGITAL DESIGN ABSTRACTION
● ● ●
●
●
Today’s circuits are more complex. Timetomarket is one of the crucial factors. New techniques must be used when we move from a smallscale to largescale designs Digital designers use two techniques Design abstraction Hierarchical modular design Need electronic design automation (EDA) or computeraided design (CAD) tools.
CAD for Electronic Design
10
L1: INTRODUCTION
2010/2011-2
Design abstraction
●
●
●
● ●
At each design level, the internal details of a complex module may be abstracted away and replaced by a black box view or model. This model contains virtually all the information needed to deal with the block at the next (lower) level of the design hierarchy. For all purposes, the model can be considered a black box with known characteristics. As there is no need for the system designer to look inside this box, design complexity is substantially reduced. Design abstraction is crucial in hardware system design. Hardware designers use these multiple levels of design abstraction to meet performance goals for very large designs and reduce design lead times.
CAD for Electronic Design
11
L1: INTRODUCTION
2010/2011-2
CAD for Electronic Design
12
L1: INTRODUCTION
2010/2011-2
Hierarchical modular design technique
●
●
●
The solution to working in any complex environment is modularization (divide and conquer) The complexity of design is broken down (divided) into a hierarchy of modules – general (top) to specific (bottom). Benefits to ● Focus on a single module at a time ● Create customized lowlevel modules for design reuse.
CAD for Electronic Design
13
L1: INTRODUCTION
2010/2011-2
●
●
●
The topdown approach decomposes the system into smaller subsystems up to a level which the subsystems can be realized. The bottomup approach connects available modules to form bigger, more complex subsystems. Usually combined topdown decomposition and bottomup composition (reuse of primitive modules).
CAD for Electronic Design
14
L1: INTRODUCTION
2010/2011-2
Top Level
A B
C
D
Bottom Level
A B
C
D
(a) Topdown approach (b) Bottomup approach.
CAD for Electronic Design
15
L1: INTRODUCTION
2010/2011-2
ELECTRONIC DESIGN PROCESS
System Specification
Circuit Design
Architectural Design
Physical Design
Functional Design
Fabrication
Logic Design
Packaging
CAD for Electronic Design
16
L1: INTRODUCTION
2010/2011-2
System Specification
Architectural Modelling HW/SW Partition
Hardware Spec
Software Spec
Hardware Modelling Hardware Implementation Integrated Circuits ASIC FPGA PLD
Standard Parts
Software Modelling Software Implementation
Boards and Systems
Software
CAD for Electronic Design
17
L1: INTRODUCTION
2010/2011-2
COMPUTERAIDED DESIGN (CAD)
● ● ●
●
A.k.a Electronic Design Automation (EDA) systems. Makes design process efficient, timely, and economical. CAD tools are intended to support all phases of a digital design: ● Description (specification), ● Design (synthesis), including various optimizations to reduce cost and improve performance, ● Verification (by simulation or formal approach) with respect to its specification. These three phases typically require several passes to obtain a suitable implementation.
CAD for Electronic Design
18
L1: INTRODUCTION
2010/2011-2
HDL (Hardware Description Language)
● ● ●
It is replacing schematic capture Today, VHDL and Verilog are the two widely used languages These two description approaches can coexist.
CAD for Electronic Design
19
L1: INTRODUCTION
2010/2011-2
Schematic Design vs. HDL Design
●
●
●
The traditional way is by (schematic capture) logic diagram of the system (modules and their interconnects). An alternative is using hardwaredescription language (HDL), e.g., VHDL and Verilog are the two languages widely used to model and design digital hardware. HDLs offer/allow ● Reduction in development time and allows more exploration of design alternatives. ● Description in higher levels of abstraction. ● A mean to standardize or method of specifying a design. ● Representation of sequential logic and manipulation of data type.
20
CAD for Electronic Design
L1: INTRODUCTION
D e s ig n C o n ce p t
2010/2011-2
P a rtitio n
D e s ig n o n e m o d u le
...
D e sig n o n e m o d u le
D e fin e in te rc o n n e ctio n b e tw e e n m o d u le s
Fu n c tio n a l s im u la tio n o f co m p le te syste m No
C o rre ct? Ye s Te ch n o lo g y m a p p in g
Tim in g sim u la tio n No
C o rre ct? Ye s Im p le m e n ta tio n
CAD for Electronic Design
21
L1: INTRODUCTION
2010/2011-2
CAD Methodology with HDL
●
● ●
Design entry in HDL format (e.g. UTM VHDLmg, Altera Quartus II™). HDL behavioural simulation (e.g. Aldec ActiveVHDL). Synthesis (e.g., Altera Quartus II, Synopsys FPGA Express), converting the code to a logic netlist file. Functional simulation to verify for design correctness (e.g. Altera Quartus II). Implementation – converting netlist file to a physical design to the target implementation technology. Timing Simulation – the physical layout is verified with timing information.
22
●
●
●
CAD for Electronic Design
L1: INTRODUCTION
Design Entry VHDL DESIGN .vhd or .v (hdl source code )
2010/2011-2
Compilation
VHDL ANALYZER (translation)
Synthesis
LOGIC SYNTHESIS
Design Constraints Technology Library Functional Simulation
Design Verification
.edif file DEVICE FITTING • partitioning • fitting • place & route .pof file .sof file Implementation DEVICE PROGRAMMING
WAVEFORM SIMULATOR EDITOR .scf file Timing Simulation Timing diagram
Physical Design
.snf file
FPGA
●
CAD for Electronic Design
23
L1: INTRODUCTION
2010/2011-2
Logic Synthesis
RTL Description
Translation
Unoptimized Intermediate Representation
Logic Optimization
Design Constraints
(Timing, Area, Power)
Technology Mapping and Optimization
Technology Library
(library of available gates, and leaf-level cells)
Gate-level Netlist
(Optimized Gate-Level Representation)
CAD for Electronic Design
24
L1: INTRODUCTION
2010/2011-2
Altera Quartus II™ CAD Tool
• •
•
A sophisticated CAD system. Comprehensively an integrated design environment (IDE) for the design of digital systems. Includes solutions for all phases of FPGAbased designs.
Modelsim
• • •
Costeffective HDL simulation solution Intuitive GUI for efficient interactive debug Integrated project management simplifies managing project data
CAD for Electronic Design
25
L1: INTRODUCTION
2010/2011-2
EVOLVING TRENDS
Increasing Design Density and Complexity Gate Count
Electronic System Level - ESL (systemC/ systemverilog) Behavioural or Algorithmic Synthesis Register-Transfer Level - RTL (VHDL/ Verilog)
1M
500K
100K
Simple HDL, PLA-based (eg ABEL)
Schematicbased
10K 1K
1970's
1980's
1990's
2000
CAD for Electronic Design
26
L1: INTRODUCTION
2010/2011-2
Further Reading
1.
2.
Jan M.Rabaey, A.Chandrakasan & B.Nikolic, Digital Integrated Circuits A Design Perspective, 2nd edition, Prentice Hall, 2003, Chapter 1.1 – 1.2. Neil W.E. Weste & David Harris, CMOS VLSI Design A Circuits and Systems Perspective, 3rd edition, Pearson Addison Wesley, 2005, Chapter 1.
CAD for Electronic Design
27
2010/2011-2
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES
CAD for Electronic Design
1
L1: INTRODUCTION
2010/2011-2
INTEGRATED CIRCUITS (IC)
●
●
●
● ●
An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et al. of Bell Laboratories invented transistor in 1948. Most current integrated circuits are built with MOSFET (metal oxidesemiconductor fieldeffect transistor) transistors. ICs commercially available since early 1960s. Phenomenal advancement in IC design and fabrication technologies.
CAD for Electronic Design
2
L1: INTRODUCTION
2010/2011-2
●
●
More and more transistors are packed in a chip SSI, MSI, LSI, and VLSI. Currently millions of transistors in a single chip. E.g., Intel Pentium IV processor has 40 million transistors using 0.13 µm technology. Integration Scale SSI MSI LSI VLSI Number of Transistors < 10 10 – 1,000 1,000 – 10,000 > 10,000 Examples Logic gates Adders, counters Multipliers Microprocessors
CAD for Electronic Design
3
L1: INTRODUCTION
2010/2011-2
●
●
Moore's Law Maximum number of transistors on a chip approximately doubles every eighteen months. This prediction has been accurate for the last four decades.
On-Chip Transistor Count
1 09 1 08 1 07 1 06 1 05 1 04 1 03 1 02 1970 1980 1990 Ye a r 2000
CAD for Electronic Design
4
L1: INTRODUCTION
2010/2011-2
DIGITAL IC IMPLEMENTATION ALTERNATIVES
● ●
●
●
●
Various implementation of digital logic designs Traditional offtheshelf IC chips, e.g., SSI and MSI TTL, perform a fixed operation defined by the device manufacturer. Applicationspecific Integrated Circuits (ASICs) are customized ICs whose internal functional operation is userdefined. CPLD or FPGA requires user hardware programming to perform the desired operation. The circuitlevel design of a VLSI or ASIC chip involves circuit components design, placement, and interconnect routing.
CAD for Electronic Design
5
L1: INTRODUCTION
2010/2011-2
Digital Implementation Alternatives
Standard Components
VLSI Integrated Circuits
SoC
(System-on-Chip)
Applications fixed
Applications by Programming
Reconfigurable ASIC
Semicustom VLSI
Structured ASIC
Full-custom VLSI
Prefabricated Logic Gates Software Hardware Reconfigurable Masked Gate & Logic Programming Programming Array (MGA) Microchip Modules CMOS TTL ECL Microprocessor & EPROM PLA PLD ROM Channeled GA Sea-of-gates GA master slice
Standard Cell-based Design
FPGA CPLD
CAD for Electronic Design
6
L1: INTRODUCTION
2010/2011-2
●
●
●
●
●
Fullcustom VLSI uses circuit elements, e.g., transistors and connections as the primitive components. Offers a designer flexibility to optimize circuit characteristics, placement, and their interconnects, as long as certain design rules are satisfied. Very time consuming for complex ICs and requires a full knowledge of the operation of the components at the circuit level. Semicustom design uses a library of circuitlevel cells (standard cells) specified by their functions and characteristics. The use of standard cells at the logic level simplifies the design process, but reduces design flexibility.
CAD for Electronic Design
7
L1: INTRODUCTION
2010/2011-2
● ●
Another semicustom style is the gatearray design. Basic components (usually basic gates) are placed on a regular structure within a chip, and the design consists of determining the connections between the gates.
Horizontal routing channel a a' abd (y = abc + a'c + c'd) y
b b' a'c
c c' c'd
d Vertical routing channel (z = a + b) z
CAD for Electronic Design
8
L1: INTRODUCTION
2010/2011-2
●
A combination of fullcustom and semicustom design is best, where the critical portions of the system are designed using fullcustom. IC TYPE Mask layers customized All All Some None Logic cells customized Some None None None Fabrication lead time > 2 months ~2 months ~1 to 2 weeks
Fullcustom VLSI Standard Cellbased ASIC Masked Gate Arrays FPGA / CPLD
CAD for Electronic Design
9
L1: INTRODUCTION
2010/2011-2
DIGITAL DESIGN ABSTRACTION
● ● ●
●
●
Today’s circuits are more complex. Timetomarket is one of the crucial factors. New techniques must be used when we move from a smallscale to largescale designs Digital designers use two techniques Design abstraction Hierarchical modular design Need electronic design automation (EDA) or computeraided design (CAD) tools.
CAD for Electronic Design
10
L1: INTRODUCTION
2010/2011-2
Design abstraction
●
●
●
● ●
At each design level, the internal details of a complex module may be abstracted away and replaced by a black box view or model. This model contains virtually all the information needed to deal with the block at the next (lower) level of the design hierarchy. For all purposes, the model can be considered a black box with known characteristics. As there is no need for the system designer to look inside this box, design complexity is substantially reduced. Design abstraction is crucial in hardware system design. Hardware designers use these multiple levels of design abstraction to meet performance goals for very large designs and reduce design lead times.
CAD for Electronic Design
11
L1: INTRODUCTION
2010/2011-2
CAD for Electronic Design
12
L1: INTRODUCTION
2010/2011-2
Hierarchical modular design technique
●
●
●
The solution to working in any complex environment is modularization (divide and conquer) The complexity of design is broken down (divided) into a hierarchy of modules – general (top) to specific (bottom). Benefits to ● Focus on a single module at a time ● Create customized lowlevel modules for design reuse.
CAD for Electronic Design
13
L1: INTRODUCTION
2010/2011-2
●
●
●
The topdown approach decomposes the system into smaller subsystems up to a level which the subsystems can be realized. The bottomup approach connects available modules to form bigger, more complex subsystems. Usually combined topdown decomposition and bottomup composition (reuse of primitive modules).
CAD for Electronic Design
14
L1: INTRODUCTION
2010/2011-2
Top Level
A B
C
D
Bottom Level
A B
C
D
(a) Topdown approach (b) Bottomup approach.
CAD for Electronic Design
15
L1: INTRODUCTION
2010/2011-2
ELECTRONIC DESIGN PROCESS
System Specification
Circuit Design
Architectural Design
Physical Design
Functional Design
Fabrication
Logic Design
Packaging
CAD for Electronic Design
16
L1: INTRODUCTION
2010/2011-2
System Specification
Architectural Modelling HW/SW Partition
Hardware Spec
Software Spec
Hardware Modelling Hardware Implementation Integrated Circuits ASIC FPGA PLD
Standard Parts
Software Modelling Software Implementation
Boards and Systems
Software
CAD for Electronic Design
17
L1: INTRODUCTION
2010/2011-2
COMPUTERAIDED DESIGN (CAD)
● ● ●
●
A.k.a Electronic Design Automation (EDA) systems. Makes design process efficient, timely, and economical. CAD tools are intended to support all phases of a digital design: ● Description (specification), ● Design (synthesis), including various optimizations to reduce cost and improve performance, ● Verification (by simulation or formal approach) with respect to its specification. These three phases typically require several passes to obtain a suitable implementation.
CAD for Electronic Design
18
L1: INTRODUCTION
2010/2011-2
HDL (Hardware Description Language)
● ● ●
It is replacing schematic capture Today, VHDL and Verilog are the two widely used languages These two description approaches can coexist.
CAD for Electronic Design
19
L1: INTRODUCTION
2010/2011-2
Schematic Design vs. HDL Design
●
●
●
The traditional way is by (schematic capture) logic diagram of the system (modules and their interconnects). An alternative is using hardwaredescription language (HDL), e.g., VHDL and Verilog are the two languages widely used to model and design digital hardware. HDLs offer/allow ● Reduction in development time and allows more exploration of design alternatives. ● Description in higher levels of abstraction. ● A mean to standardize or method of specifying a design. ● Representation of sequential logic and manipulation of data type.
20
CAD for Electronic Design
L1: INTRODUCTION
D e s ig n C o n ce p t
2010/2011-2
P a rtitio n
D e s ig n o n e m o d u le
...
D e sig n o n e m o d u le
D e fin e in te rc o n n e ctio n b e tw e e n m o d u le s
Fu n c tio n a l s im u la tio n o f co m p le te syste m No
C o rre ct? Ye s Te ch n o lo g y m a p p in g
Tim in g sim u la tio n No
C o rre ct? Ye s Im p le m e n ta tio n
CAD for Electronic Design
21
L1: INTRODUCTION
2010/2011-2
CAD Methodology with HDL
●
● ●
Design entry in HDL format (e.g. UTM VHDLmg, Altera Quartus II™). HDL behavioural simulation (e.g. Aldec ActiveVHDL). Synthesis (e.g., Altera Quartus II, Synopsys FPGA Express), converting the code to a logic netlist file. Functional simulation to verify for design correctness (e.g. Altera Quartus II). Implementation – converting netlist file to a physical design to the target implementation technology. Timing Simulation – the physical layout is verified with timing information.
22
●
●
●
CAD for Electronic Design
L1: INTRODUCTION
Design Entry VHDL DESIGN .vhd or .v (hdl source code )
2010/2011-2
Compilation
VHDL ANALYZER (translation)
Synthesis
LOGIC SYNTHESIS
Design Constraints Technology Library Functional Simulation
Design Verification
.edif file DEVICE FITTING • partitioning • fitting • place & route .pof file .sof file Implementation DEVICE PROGRAMMING
WAVEFORM SIMULATOR EDITOR .scf file Timing Simulation Timing diagram
Physical Design
.snf file
FPGA
●
CAD for Electronic Design
23
L1: INTRODUCTION
2010/2011-2
Logic Synthesis
RTL Description
Translation
Unoptimized Intermediate Representation
Logic Optimization
Design Constraints
(Timing, Area, Power)
Technology Mapping and Optimization
Technology Library
(library of available gates, and leaf-level cells)
Gate-level Netlist
(Optimized Gate-Level Representation)
CAD for Electronic Design
24
L1: INTRODUCTION
2010/2011-2
Altera Quartus II™ CAD Tool
• •
•
A sophisticated CAD system. Comprehensively an integrated design environment (IDE) for the design of digital systems. Includes solutions for all phases of FPGAbased designs.
Modelsim
• • •
Costeffective HDL simulation solution Intuitive GUI for efficient interactive debug Integrated project management simplifies managing project data
CAD for Electronic Design
25
L1: INTRODUCTION
2010/2011-2
EVOLVING TRENDS
Increasing Design Density and Complexity Gate Count
Electronic System Level - ESL (systemC/ systemverilog) Behavioural or Algorithmic Synthesis Register-Transfer Level - RTL (VHDL/ Verilog)
1M
500K
100K
Simple HDL, PLA-based (eg ABEL)
Schematicbased
10K 1K
1970's
1980's
1990's
2000
CAD for Electronic Design
26
L1: INTRODUCTION
2010/2011-2
Further Reading
1.
2.
Jan M.Rabaey, A.Chandrakasan & B.Nikolic, Digital Integrated Circuits A Design Perspective, 2nd edition, Prentice Hall, 2003, Chapter 1.1 – 1.2. Neil W.E. Weste & David Harris, CMOS VLSI Design A Circuits and Systems Perspective, 3rd edition, Pearson Addison Wesley, 2005, Chapter 1.
CAD for Electronic Design
27
