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DESIGN OF LOW POWER ALU USING AREA EFFICIENT CARRY SELECT ADDER
Presented By
A. Ramakrishna Reddy
ES & VLSI Under the Guidance of
Mr.
K. Naresh.
Assistant Professor
1
OBJECTIVE To design Low Power ALU using Efficient Carry Select Adder (CSLA)
2
ALU
• Arithmetic operations – Addition, Subtraction. • Logical operations- AND, OR, XOR, XNOR, Increment and Decrement • Adder is the main block in ALU.
3
ONE BIT ALU
4
8-BIT ALU USING RIPPLE CARRY ADDERS
s2
s1 0 0 1 1 0 0 1
s0 0 1 0 1 0 1 0
operation AND XOR XNOR OR DECREMENT ADDTION SUBTRACTION
0 0 0 0 1 1 1
1
1
1
INCREMENT
5
REGULAR 16-BIT SQRT CSLA
A[15:11] B[15:11] A[10:7] B[10:7] A[6:4] B[6:4] 0 0 A[3:2] B[3:2] A[1:0] B[1:0] 0
15:11 RCA 15:11 RCA MUX 12:6
0 1
10 :7 RCA 10:7 RCA
1
6:4 RCA 6:4 RCA
1
3:2 RCA 3:2 RCA
1:0 RCA
Cin
1
CY
CY
MUX 10:5
C Y
MUX 8:4
CY MUX
6:3
C OUT
S[15:11]
S[10:7]
group4
S[6:4]
group3
S[3:2]
group2
S[1:0]
group1
group5
6
GROUP-2 IN REGULAR SQRT CSLA
• .
A[3:2] B[3:2]
2-bit RCA
0
1
2-bit RCA
Carry to the next group
MUX
Carry from previous group
S3 S2
7
EXISTING TECHNIQUE
• 2nd level RCA block is replaced by BEC Block
1
n-bit RCA
(n+1)-bit BEC
8
GROUP-2 IN EXISTING SQRT CSLA
A[3:2] B[3:2]
2-bit RCA
0
3-bit BEC
Carry to the next group
MUX
Carry from previous group
S3 S2
9
OVERHEADS IN 3-BIT BEC
• Number of NOT gates=1 • Number of XOR gates=2 • Number of AND gates=1
Total number of transistors required = 32
10
PROPOSED TECHNIQUE
n-bit BEC
n-bit SHM
SHM=SPECIAL HARDWARE WITH MULTIPLEXERS
11
16-BIT SQRT CSLA USING PROPOSED TECHNIQUE
A[15:11] B[15:11]
.
A[10:7]
B[10:7]
A[6:4] B[6:4]
A[3:2] B[3:2]
A[1:0] B[1:0]
0
0
0
15:11 RCA
10 :7 RCA
6:4 RCA
6-bit SHM
5-bit SHM
4-biT SHM
3:2 RCA 3-bit SHM
0
1:0 RCA
Cin
CY
MUX 12:6
CY
MUX 10:5
CY MUX
CY
8:4
MUX 6:3
C OUT
S[15:11]
S[10:7] group4
S[6:4] group3
S[3:2] group2
SUM[1:0] group1
group5
12
3-BIT SHM
X0= b0 X1= X0.b1+X0.b1 X2=(X1+b1).b2+X1.b1.b2
13
COMPARISION OF 3-BIT BEC AND SHM
Type of logic 3-bit BEC
Gates 2 -XOR 1-AND 1-NOT 3-MUX 3-NOT
Number of transistors 24 6 2 18 6
Total number of transistors 32
3-bit SHM
24
14
CRITICAL PATH DELAY FROM DSCH TOOL
Critical path delay
15
NUMBER OF TRANSISTORS AND POWER FROM MICROWIND TOOL
NUMBER OF TRANSISTORS
POWER DISSIPATION
16
COMPARISION OF SECOND LEVEL 2BIT RCA, 3-BIT BEC AND 3-BIT SHM
Logic for Second level RCA using CMOS BEC using CMOS SHM using CMOS
Number Critical path of delay(ns) transistors 56 32 24 1.900 1.200 2.350
Area ( um2) 1342 781 486
Power dissipation (uw) static dynam total ic 6.706 42.565 49.271 3.269 25.746 29.015 3.100 22.843 25.94 3
17
COMPARISION OF EXISTING AND PROPOSED TECHNIQUES FOR SECOND BLOCK
Design Type Number of transistor s 106 Critical path delay (ns) Area (µm2) Power dissipation (µw) static dynamic total 3.240 3465 21.005 106 127.0 05 118.7 62
RCA-BECMUX(CMOS ) RCA-SHMMUX(CMOS )
98
3.770
2996
20.138
98.624
18
GDI TECHNIQUE
19
FULL ADDER USING GDI TECHNIQUE
10 TRANSISTOR FA
8-TRANSISTOR FA
20
8-BIT ALU USING EFFICIENT CARRY SELECT ADDER
21
COMPARISION OF EXISTING AND PROPOSED ALU FOR 10-TRANSISTOR FA
MODEL(ALU) NUMBER OF TRANSISTO RS Critical path delay(ns) Area(µm) Power( mw)
8BIT ALU USING 10 TRANSISTOR RCA 8BIT ALU USING 10 TRANSISTOR CSLA
448
3.195
12384
0.204
508
1.865
24682
0.205
22
COMPARISION OF EXISTING AND PROPOSED ALU FOR 8-TRANSISTOR FA
MODEL(ALU) NUMBER OF TRANSISTO RS Critical path delay(ns) Area(µm) Power( mw)
8BIT ALU USING 8 TRANSISTOR RCA 8BIT ALU USING 8 TRANSISTOR CSLA
432
3.745
11832
0.221
494
2.070
20988
0.262
23
CONCLUSION
• Speed is increased 41.6% in case 10 transistor full adder. • 44.7% in case of 8-transistor full adder. • Satisfactory level of power consumption and propagation delay can be achieved using the proposed technology without the need to purchase new technology libraries, which may lead to design cost reduction. • The proposed work can be extended and carried further with an aim of increasing the number of bits and approach to new technology such as 0.08, 0.06 micron meter technology.
24
THANK YOU
25
Presented By
A. Ramakrishna Reddy
ES & VLSI Under the Guidance of
Mr.
K. Naresh.
Assistant Professor
1
OBJECTIVE To design Low Power ALU using Efficient Carry Select Adder (CSLA)
2
ALU
• Arithmetic operations – Addition, Subtraction. • Logical operations- AND, OR, XOR, XNOR, Increment and Decrement • Adder is the main block in ALU.
3
ONE BIT ALU
4
8-BIT ALU USING RIPPLE CARRY ADDERS
s2
s1 0 0 1 1 0 0 1
s0 0 1 0 1 0 1 0
operation AND XOR XNOR OR DECREMENT ADDTION SUBTRACTION
0 0 0 0 1 1 1
1
1
1
INCREMENT
5
REGULAR 16-BIT SQRT CSLA
A[15:11] B[15:11] A[10:7] B[10:7] A[6:4] B[6:4] 0 0 A[3:2] B[3:2] A[1:0] B[1:0] 0
15:11 RCA 15:11 RCA MUX 12:6
0 1
10 :7 RCA 10:7 RCA
1
6:4 RCA 6:4 RCA
1
3:2 RCA 3:2 RCA
1:0 RCA
Cin
1
CY
CY
MUX 10:5
C Y
MUX 8:4
CY MUX
6:3
C OUT
S[15:11]
S[10:7]
group4
S[6:4]
group3
S[3:2]
group2
S[1:0]
group1
group5
6
GROUP-2 IN REGULAR SQRT CSLA
• .
A[3:2] B[3:2]
2-bit RCA
0
1
2-bit RCA
Carry to the next group
MUX
Carry from previous group
S3 S2
7
EXISTING TECHNIQUE
• 2nd level RCA block is replaced by BEC Block
1
n-bit RCA
(n+1)-bit BEC
8
GROUP-2 IN EXISTING SQRT CSLA
A[3:2] B[3:2]
2-bit RCA
0
3-bit BEC
Carry to the next group
MUX
Carry from previous group
S3 S2
9
OVERHEADS IN 3-BIT BEC
• Number of NOT gates=1 • Number of XOR gates=2 • Number of AND gates=1
Total number of transistors required = 32
10
PROPOSED TECHNIQUE
n-bit BEC
n-bit SHM
SHM=SPECIAL HARDWARE WITH MULTIPLEXERS
11
16-BIT SQRT CSLA USING PROPOSED TECHNIQUE
A[15:11] B[15:11]
.
A[10:7]
B[10:7]
A[6:4] B[6:4]
A[3:2] B[3:2]
A[1:0] B[1:0]
0
0
0
15:11 RCA
10 :7 RCA
6:4 RCA
6-bit SHM
5-bit SHM
4-biT SHM
3:2 RCA 3-bit SHM
0
1:0 RCA
Cin
CY
MUX 12:6
CY
MUX 10:5
CY MUX
CY
8:4
MUX 6:3
C OUT
S[15:11]
S[10:7] group4
S[6:4] group3
S[3:2] group2
SUM[1:0] group1
group5
12
3-BIT SHM
X0= b0 X1= X0.b1+X0.b1 X2=(X1+b1).b2+X1.b1.b2
13
COMPARISION OF 3-BIT BEC AND SHM
Type of logic 3-bit BEC
Gates 2 -XOR 1-AND 1-NOT 3-MUX 3-NOT
Number of transistors 24 6 2 18 6
Total number of transistors 32
3-bit SHM
24
14
CRITICAL PATH DELAY FROM DSCH TOOL
Critical path delay
15
NUMBER OF TRANSISTORS AND POWER FROM MICROWIND TOOL
NUMBER OF TRANSISTORS
POWER DISSIPATION
16
COMPARISION OF SECOND LEVEL 2BIT RCA, 3-BIT BEC AND 3-BIT SHM
Logic for Second level RCA using CMOS BEC using CMOS SHM using CMOS
Number Critical path of delay(ns) transistors 56 32 24 1.900 1.200 2.350
Area ( um2) 1342 781 486
Power dissipation (uw) static dynam total ic 6.706 42.565 49.271 3.269 25.746 29.015 3.100 22.843 25.94 3
17
COMPARISION OF EXISTING AND PROPOSED TECHNIQUES FOR SECOND BLOCK
Design Type Number of transistor s 106 Critical path delay (ns) Area (µm2) Power dissipation (µw) static dynamic total 3.240 3465 21.005 106 127.0 05 118.7 62
RCA-BECMUX(CMOS ) RCA-SHMMUX(CMOS )
98
3.770
2996
20.138
98.624
18
GDI TECHNIQUE
19
FULL ADDER USING GDI TECHNIQUE
10 TRANSISTOR FA
8-TRANSISTOR FA
20
8-BIT ALU USING EFFICIENT CARRY SELECT ADDER
21
COMPARISION OF EXISTING AND PROPOSED ALU FOR 10-TRANSISTOR FA
MODEL(ALU) NUMBER OF TRANSISTO RS Critical path delay(ns) Area(µm) Power( mw)
8BIT ALU USING 10 TRANSISTOR RCA 8BIT ALU USING 10 TRANSISTOR CSLA
448
3.195
12384
0.204
508
1.865
24682
0.205
22
COMPARISION OF EXISTING AND PROPOSED ALU FOR 8-TRANSISTOR FA
MODEL(ALU) NUMBER OF TRANSISTO RS Critical path delay(ns) Area(µm) Power( mw)
8BIT ALU USING 8 TRANSISTOR RCA 8BIT ALU USING 8 TRANSISTOR CSLA
432
3.745
11832
0.221
494
2.070
20988
0.262
23
CONCLUSION
• Speed is increased 41.6% in case 10 transistor full adder. • 44.7% in case of 8-transistor full adder. • Satisfactory level of power consumption and propagation delay can be achieved using the proposed technology without the need to purchase new technology libraries, which may lead to design cost reduction. • The proposed work can be extended and carried further with an aim of increasing the number of bits and approach to new technology such as 0.08, 0.06 micron meter technology.
24
THANK YOU
25
