Scheme Apple Macbook Pro a1278 k24
Content
8
6
7
2
3
4
5
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
K24 MLB SCHEMATIC
A
K24 MLB PVT RELEASE
0000713283
5/6/09
DATE
?
PVT RELEASE
D
D
5/6/2009
(.csa)
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39
41
42
Date
Contents
Sync
Table of Contents
(.csa)
Page
08/22/2007
TABLE_TABLEOFCONTENTS_HEAD
12/12/2007
TABLE_TABLEOFCONTENTS_ITEM
T17_MLB
System Block Diagram
T18_MLB
03/13/2008
Power Block Diagram
TABLE_TABLEOFCONTENTS_ITEM
DRAGON
TABLE_TABLEOFCONTENTS_ITEM
BOM Configuration
M97_MLB
TABLE_TABLEOFCONTENTS_ITEM
Revision History
M97_MLB
TABLE_TABLEOFCONTENTS_ITEM
FUNC TEST
M97_MLB
04/21/2008
Power Aliases
TABLE_TABLEOFCONTENTS_ITEM
BEN
TABLE_TABLEOFCONTENTS_ITEM
SIGNAL ALIAS
M97_MLB
CPU FSB
T18_MLB
12/12/2007
CPU Power & Ground
T18_MLB
CPU Decoupling
RAYMOND
eXtended Debug Port(MiniXDP)
TABLE_TABLEOFCONTENTS_ITEM
12/12/2007
TABLE_TABLEOFCONTENTS_ITEM
03/31/2008
TABLE_TABLEOFCONTENTS_ITEM
11/07/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
K19_MLB
MCP CPU Interface
T18_MLB
MCP Memory Interface
T18_MLB
MCP Memory Misc
T18_MLB
MCP PCIe Interfaces
T18_MLB
MCP Ethernet & Graphics
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
06/26/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
12/12/2007
TABLE_TABLEOFCONTENTS_ITEM
T18_MLB
MCP PCI & LPC
T18_MLB
MCP SATA & USB
T18_MLB
MCP HDA & MISC
T18_MLB
MCP Power & Ground
T18_MLB
MCP Standard Decoupling
T18_MLB
MCP Graphics Support
T18_MLB
SB Misc
04/05/2008
TABLE_TABLEOFCONTENTS_ITEM
03/31/2008
TABLE_TABLEOFCONTENTS_ITEM
06/30/2008
TABLE_TABLEOFCONTENTS_ITEM
05/09/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/22/2008
TABLE_TABLEOFCONTENTS_ITEM
01/30/2009
TABLE_TABLEOFCONTENTS_ITEM
05/23/2008
TABLE_TABLEOFCONTENTS_ITEM
07/01/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
11/02/2008
TABLE_TABLEOFCONTENTS_ITEM
12/22/2008
TABLE_TABLEOFCONTENTS_ITEM
RAYMOND
FSB/DDR3 Vref Margining
BEN
DDR3 SO-DIMM Connector A
BEN
DDR3 SO-DIMM Connector B
BEN
DDR3 Support
T18_MLB
Right Clutch Connector
YITE
SECUREDIGITAL CARD READER
VEMURI
Ethernet PHY (RTL8211CL)
SUMA
Ethernet & AirPort Support
SUMA
ETHERNET CONNECTOR
SUMA
FireWire LLC/PHY (FW643)
K19_MLB
FireWire Port Power
YUN_K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
43
45
46
48
49
50
51
52
53
54
55
56
57
58
59
61
62
63
65
66
67
68
69
70
72
73
74
75
76
77
78
79
90
93
94
Date
Contents
(.csa)
Sync
FireWire Ports
Page
11/02/2008
TABLE_TABLEOFCONTENTS_HEAD
12/04/2008
TABLE_TABLEOFCONTENTS_ITEM
K19_MLB
SATA Connectors
K19_MLB
External USB Connectors
01/18/2008
TABLE_TABLEOFCONTENTS_ITEM
05/28/2008
TABLE_TABLEOFCONTENTS_ITEM
06/26/2008
TABLE_TABLEOFCONTENTS_ITEM
05/28/2008
TABLE_TABLEOFCONTENTS_ITEM
05/09/2008
TABLE_TABLEOFCONTENTS_ITEM
04/21/2008
TABLE_TABLEOFCONTENTS_ITEM
02/04/2008
TABLE_TABLEOFCONTENTS_ITEM
YUAN.MA
Front Flex Support
YUAN.MA
SMC
T18_MLB
SMC Support
YUAN.MA
LPC+SPI Debug Connector
CHANGZHANG
K24 SMBUS CONNECTIONS
BEN
VOLTAGE SENSING
YUNWU
Current Sensing
YUNWU
Thermal Sensors
YUNWU
Fan
CHANGZHANG
WELLSPRING 1
YUAN.MA
WELLSPRING 2
YUAN.MA
SMS
YUNWU
SPI ROM
CHANGZHANG
AUDIO: CODEC/REGULATOR
AUDIO
AUDIO: LINE INPUT FILTER
AUDIO
AUDIO: HEADPHONE FILTER
AUDIO
AUDI0: SPEAKER AMP
AUDIO
AUDIO: JACK
AUDIO
AUDIO: JACK TRANSLATORS
AUDIO
DC-In & Battery Connectors
YUNWU
PBUS Supply/Battery Charger
RAYMOND
5V/3.3V SUPPLY
RAYMOND
1.5V/0.75V DDR3 SUPPLY
RAYMOND
IMVP6 CPU VCore Regulator
RAYMOND
MCP CORE REGULATOR
K19_MLB
12/17/2008
TABLE_TABLEOFCONTENTS_ITEM
03/20/2008
TABLE_TABLEOFCONTENTS_ITEM
01/18/2008
TABLE_TABLEOFCONTENTS_ITEM
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72
73
74
75
76
77
78
79
80
81
97
98
100
101
102
103
104
105
106
107
109
Date
Contents
Sync
12/05/2008
LCD BACKLIGHT DRIVER
KIRAN
LCD Backlight Support
YITE
CPU/FSB Constraints
T18_MLB
Memory Constraints
T18_MLB
MCP Constraints 1
T18_MLB
MCP Constraints 2
T18_MLB
Ethernet Constraints
T18_MLB
FireWire Constraints
K19_MLB
SMC Constraints
T18_MLB
K24 SPECIAL CONSTRAINTS
M97_MLB
K24 RULE DEFINITIONS
M97_MLB
06/30/2008
01/04/2008
01/04/2008
01/04/2008
12/14/2007
03/19/2008
12/01/2008
01/04/2008
C
04/22/2008
05/09/2008
06/26/2008
05/02/2008
03/04/2009
01/31/2009
02/03/2009
12/18/2008
03/20/2009
03/20/2009
12/11/2008
01/31/2008
02/08/2008
01/31/2008
01/31/2008
B
12/10/2008
02/08/2008
CPU VTT(1.05V) SUPPLY
RAYMOND
MISC POWER SUPPLIES
RAYMOND
POWER SEQUENCING
YUAN.MA
POWER FETS
YUAN.MA
LVDS CONNECTOR
NMARTIN
DISPLAYPORT SUPPORT
AMASON
DisplayPort Connector
AMASON
01/23/2008
12/11/2008
12/11/2008
04/04/2008
04/18/2008
06/30/2008
TABLE_TABLEOFCONTENTS_ITEM
DIMENSIONS ARE IN MILLIMETERS
A
APPLE INC.
METRIC
XX
X.XX
DRAFTER
Schematic / PCB #’s
PART NUMBER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
QTY
DESCRIPTION
REFERENCE DES
051-7898
1
SCHEM,MLB,K24
SCH
CRITICAL
820-2530
1
PCBF,MLB,K24
PCB
CRITICAL
CRITICAL
7
TITLE
DO NOT SCALE DRAWING
BOM OPTION
SCHEM,MLB,K24
NONE
THIRD ANGLE PROJECTION
8
ENG APPD
6
A
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
5
4
3
MATERIAL/FINISH
NOTED AS
APPLICABLE
SIZE
D
2
DRAWING NUMBER
REV.
051-7898
SHT
1
1
A
OF
81
8
6
7
2
3
4
5
1
U1000
U1300
INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
PG 9
D
FSB
D
J6950
64-Bit
800/1067/1333 MHz
DC/BATT
PG 13
2 UDIMMs
MAIN
FSB INTERFACE
GPIOs
POWER SUPPLY
PG 60
J2900
DDR2-800MHZ
DDR3-1067/1333MHZ
MEMORY
DIMM
PG 14
U4900
PG 25,26
TEMP SENSOR
PG 41
Misc
CLK
PG 24
U6100
SYNTH
POWER SENSE
PG 45
SPI
J4510
Boot ROM
SPI
SATA
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
PG 52
Conn
1.05V/3GHZ.
PG 48,49
PG 20
PG 38
HD
NVIDIA
J4520
SATA
Conn
PG 38
C
J4900
B,0
ADC
BSB
MCP79
SATA
1.05V/3GHZ.
Ser
Fan
LPC
PG 19
ODD
J5100
Prt
SMC
LPC Conn
Port80,serial
PG 41
C
PG 43
PG 18
U1400
J9000
PWR
LVDS
CONN
CTRL
LVDS OUT
PG 71
RGB OUT
J3500
DP OUT
J4720
SD CARD READER
J4700
J9400
HDMI OUT
J4710
PG 40
PG 40
IR
J3900,4635,4655
CAMERA
PG 40
PG 40
EXTERNAL
USB
Connectors
PG 16
PG 34
7
6
5
4
0
PCI-E
B
PG 34
UP TO 20 LANES3
FIREWIRE PORT
FW643
CONN
1
2
J4310
3
USB
PG 17
PG 19
TMDS OUT
PG 71
11
PG 39
DVI OUT
(UP TO 12 DEVICES)
DISPLAY PORT
CONN
PG 30
J4710
TRACKPAD/
KEYBOARD
Bluetooth
B
SMB
SMB
PG 20
PG 34
CONN
RGMII
HDA
PCI
(UP TO FOUR PORTS)
PG 44
DIMM’s
PG 17
PG 18
PG 20
J3400
Mini PCI-E
AirPort
U6200
Audio
PG 28
Codec
PG 53
U6301
U3700
A
U6400
U6500
GB
Line In
Line Out
Speaker
E-NET
Amp
Amp
Amp
Amps
PG 54
PG 55
PG 56
PG 57
RTL8211CL
HEADPHONE
System Block Diagram
U6600,6605,6610,6620
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PG 31
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
U3900
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
J6800,6801,6802,6803
E-NET
Conn
Audio
SIZE
Conns
D
PG 33
APPLE INC.
PG 56
DRAWING NUMBER
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
2
1
81
A
8
6
7
D6905
PPVIN_G3H_P3V42G3H
D6905
01
02
ENABLE
PPBUS_G3H
V
Q5315
02
CPUVTTS0_EN
(S0)
VOUT
CPUVTT
U5403
VOUT
SMC_BATT_ISENSE
PP1V05_S0
(8A MAX CURRENT)
31
CPUVTTS0_PGOOD
V
CPU VCORE
IMVP_VR_ON
Q7050
29
26
06 P1V05ENET_EN
1.05V SO
PP1V05_ENET_FET
FETS
PPBUS_G3H
(Q3841)
4.5V AUDIO
TPS7174S
VIN
EN
PM_SLP_S4_L
ISL8009
06
P1V05_S5_EN
U7750
SLP_S3#
11-3
P60
P5VRTS0_EN_L
04
U4900
DDRREG_EN
RC
DELAY
U1400
SMC_PM_G2_EN
PP4V5_AUDIO_ANALOG
RESET*
VOUT
U1000
P3V3S5_EN_L
02
11-2
15-1
SMC_PM_G2_EN
P5VLTS3_EN
RC
DELAY
Q7940
PP5V_S3_REG
VIN
EN1
5V
(RT)
VOUT1
VOUT2
EN2
3.3V
PP5V_S3
PP5V_S3_REG
PP5V_S0_FET
PP3V3_S5_REG
PP3V3_S5
BKLT_EN
LP8543
U9701
ENA
Q7910
PP3V3_S3_FET
13
VREG3
P3V3S3_EN
P5V3V3_PGOOD
PPVOUT_S0_LCDBKLT
VOUT
PP3V3_S0_FET
18
09
MCPCORESO_PGOOD
CPUVTTS0_PGOOD
WOL_EN
04-1
02
=DDRREG_EN
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
P1V8S0_EN
16-3
=DDTVTT_EN
MCPDDR_EN
16-2
CPUVTTS0_EN
MCPCORES0_EN
8
16-3
16-4
P1V05S0_EN
(S0)
P3V3S0_EN
(S0)
16-2
16-2
PBUSVSENS_EN
(S0)
16-2
P5VRTS0_EN_L
(S0)
16-1
7
SLP_S5_L
VIN
S5
S3
1.5V
PP1V5_S0_FET
PP1V5_S0
21
TPS62202
U7760
PP1V5_S3_REG
(12A MAX CURRENT)
14
TPS51116
U7300
20
VOUT2
EN2
SLP_S3_L(P93)
U4900
PPVCORE_S0_MCP_REG_R
R7572
PP1V8_S0_REG
19-1
PP3V3_S0
V1
PP1V5_S0
V2
PP1V05_S0
V3
Power Block Diagram
SYNC_MASTER=DRAGON
LTC2909
U7870
SYNC_DATE=03/13/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PPVCORE_S0_MCP
(25A MAX CURRENT)
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5V (LT)
VIN
6
SMC_RESET_L
II NOT TO REPRODUCE OR COPY IT
EN1
02
PM_PWRBTN_L
RST*
PP0V75_S0_REG
(1A MAX CURRENT)
MCP_CORE
25
1.8V LDO
VOUT1
MCPCORES0_EN
B
SLP_S4_L(P94)
SLP_S3_L
S0PGOOD_PWROK
(Q7901 & Q7971)
0.75V
VOUT2
IMVP_VR_ON(P16)
RSMRST_IN(P13)
PLT_RST*
PWR_BUTTON(P90)
P17(BTN_OUT)
IMVP_VR_ON
10
SLP_S5_L(P95)
SLP_S4_L
P5V_LT_S3_PGOOD
S3 TO S0
FETS
PM_RSMRST_L
99ms DLY
RST*
P3V3ENET_EN_L
PM_SLP_S3_L
RSMRST_PWRGD
05
P5V3V3_PGOOD
Q3802
PWRGD(P12)
SMC_ONOFF_L
P3V3S0_EN
Q3810
P3V3_ENET_FET
16
RSMRST_OUT(P15)
ALL_SYS_PWRGD
Q3801
SMC_ADAPTER_EN
SMC
24
Q7930
PM_ENET_EN_L
P5VS0_EN
07
(4A MAX CURRENT)
TPS51125
U7200
PGOOD1,2
17
(4A MAX CURRENT)
VIN
B
A
32
VOUT
08
05
Q7800
(S5)
PCI_RESET0#
PM_SLP_S3_L
U6200
P16
15
15
C
PWRGOOD
PP1V05_S5_REG
02
SMC
CPU_RESET#
CPU
22
1.05V (S5)
RC
DELAY
30
U2850
28
VR_PWRGOOD_DELAY
PGOOD
U7400
P3V3S3_EN
CPU_PWRGD
CPUPWRGD(GPIO49)
U1400
VR_ON
25
PPVBAT_G3H_CHGR_OUT
RSMRST*
FSB_CPURST_L
ISL9504B
11-1
LPC_RESET_L
MCP_PS_PWRGD PS_PWRGD
SMC_CPU_VSENSE
PPVCORE_S0_CPU
(44A MAX CURRENT)
SMC_CPU_ISENSE
VOUT
VIN
11
06-1
PWRBTN*
PLTRST*
01
CHGR_BGATE
MCP79
PGOOD
A
J6950
MCP79
D
TPS51117
U7600
02
BATT_POS_F
U5000
(1.05V)
VIN
ISL6258A
U7000
(9 TO 12.6V)
EN_PSV
ENABLES
PBUS SUPPLY/
BATTERY CHARGER
C
04
PP5V_S0_CPUVTTS0
VIN
3S2P
SMC PWRGD
RN5VD30A-F
23 R5492 PPBUS_G3H_CPU_ISNS
PPBUS_G3H_CPU_ISNS_R
F7000
CHGR_EN
(S5)
PP3V42_G3H_REG 03
3.425V G3HOT
LT3470
VOUT
U6990
PBUS_VSENSE
7A FUSE
PPVBAT_G3H_CHGR_REG
D
AC
DCIN(16.5V)
ADAPTER
IN
1
K24 POWER SYSTEM ARCHITECTURE
PP18V5_DCIN_CONN
F6905
6A FUSE
2
3
4
5
VOUT1
SIZE
DRAWING NUMBER
D
APPLE INC.
ISL6236
U7500
SCALE
SHT
NONE
5
4
3
2
REV.
051-7898
4.7.0
OF
3
1
81
A
8
6
7
BOM Variants
2
3
4
5
1
Bar Code Labels / EEE #’s
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
630-9923
PCBA,MLB,BETTER,K24
K24_COMMON,CPU_2_26GHZ,EEE_6GC,KB_BL
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_BOMGROUP_ITEM
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:6G4]
CRITICAL
EEE_6G4
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:6GC]
CRITICAL
EEE_6GC
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:6GD]
CRITICAL
EEE_6GD
TABLE_BOMGROUP_ITEM
630-9924
PCBA,MLB,BEST,K24
K24_COMMON,CPU_2_53GHZ,EEE_6GD,KB_BL
085-0741
K24 MLB DEVELOPMENT BOM
K24_DEVEL_PVT
TABLE_BOMGROUP_ITEM
D
BOM Groups
D
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K24_COMMON
COMMON,ALTERNATE,K24_MCP,K24_MISC,K24_DEBUG_PVT,K24_PROGPARTS
K24_MCP
MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC
K24_MISC
ONEWIRE_PU,DP_ESD,MIKEY,BKLT_PROD,SUPERCAP_NO,LDO_NO
K24_PROGPARTS
BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG
K24_DEBUG_ENG
DEVEL_BOM,SMC_DEBUG_YES,XDP
K24_DEBUG_PVT
DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN
K24_DEBUG_PROD
BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
K24_DEVEL_ENG
BMON_ENG,XDP_CONN,LPCPLUS,VREFMRGN,FWPHY_WAKE_YES
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
K24 BOARD STACK-UP
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Top
2
3
4
5
6
7
8
9
10
11
BOTTOM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
K24_DEVEL_PVT
LPCPLUS
Module Parts
PART NUMBER
C
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
337S3646
1
PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA
U1000
CRITICAL
CPU_2_0GHZ
337S3704
1
PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA
U1000
CRITICAL
CPU_2_26GHZ
337S3639
1
PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA
U1000
CRITICAL
CPU_2_4GHZ
337S3756
1
PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA
U1000
CRITICAL
CPU_2_53GHZ
337S3761
1
PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA
U1000
CRITICAL
CPU_2_66GHZ
338S0710
1
IC,GMCP,MCP79,35X35MM,BGA1437,B03
U1400
CRITICAL
MCP_B03
Programmable Parts
338S0563
1
IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900
CRITICAL
SMC_BLANK
341S2445
1
IC,SMC,K24
U4900
CRITICAL
SMC_PROG
335S0610
1
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM_BLANK
341S2441
1
IC,PRGRM,EFI BOOTROM,UNLOCK,K24
U6100
CRITICAL
BOOTROM_PROG
338S0375
1
IC,CY7C63833,ENCORE II,USB CONTROLLER
U4800
CRITICAL
IR_BLANK
341S2093
1
IC,IR CONTROLLER,M97
U4800
CRITICAL
IR_PROG
337S2983
1
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
U5701
CRITICAL
WELLSPRING_BLANK
341S2503
1
IC,PRGRM,WELLSPRING CONTROLLER
U5701
CRITICAL
WELLSPRING_PROG
SIGNAL
GROUND
SIGNAL(High
SIGNAL(High
GROUND
POWER
POWER
GROUND
SIGNAL(High
SIGNAL(High
GROUND
SIGNAL
Speed)
Speed)
C
Speed)
Speed)
LOCKED BOOTROM APN IS 341S2443
Alternate Parts
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
152S0778
152S0693
ALL
CYNTEC AS ALTERNATE
152S0796
152S0685
ALL
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
B
B
TABLE_ALT_ITEM
TABLE_ALT_ITEM
157S0058
157S0055
ALL
DELTA AS ALTERNATE
104S0018
104S0023
ALL
DALE/VISHAY AS ALTERNATE
128S0093
128S0218
ALL
KEMET AS ALTERNATE
152S0874
152S0516
ALL
MAGLAYERS AS ALTERNATE
152S0847
152S0586
ALL
MAGLAYERS AS ALTERNATE
516-0213
516-0201
ALL
MOLEX AS ALTERNATE
516S0709
516S0706
ALL
MOLEX AS ALTERNATE
152S1025
152S1024
ALL
TOKO AS ALTERNATE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM Configuration
A
SYNC_MASTER=M97_MLB
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
DEVELOPMENT BOM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
085-0741
QTY
1
DESCRIPTION
REFERENCE DES
K24 MLB DEVELOPMENT BOM
DEVEL
CRITICAL
BOM OPTION
CRITICAL
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DEVEL_BOM
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
4
1
81
8
7
6
5
4
3
2
1
Revision History
D
D
C
C
B
B
Revision History
A
A
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
NOTE: All page numbers are .csa, not PDF.
8
7
6
SCALE
SHT
NONE
See page 1 for .csa -> PDF mapping.
5
4
3
2
REV.
051-7898
4.7.0
OF
5
1
81
8
6
7
2
3
4
5
1
Functional Test Points
Fan Connectors
D
I12
I15
I16
PP5V_S0
FAN_RT_PWM
FAN_RT_TACH
TRUE
TRUE
TRUE
(NEED 3 TP)
6D3 7D5
I303
47B4
I301
I302
47C4
(NEED TO ADD 3 GND TP)
I238
I237
I239
I227
I226
I228
I230
I229
I231
I232
I233
I259
I258
C
I260
I245
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249
I395
MIC FUNC_TEST
TRUE
BI_MIC_LO
TRUE
BI_MIC_HI
TRUE
BI_MIC_SHIELD
SPEAKER
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I300
I299
I298
I293
56C2 57B1
I297
56C2 57B1
I294
56C2 57B1
FUNC_TEST
SPKRAMP_L_N_OUT
SPKRAMP_L_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SUB_P_OUT
I288
I292
I296
55A2 56B2
I291
55B2 56B2
I295
55C2 56A2
I290
55C2 56B2
I271
55B2 56B2
I289
THERMAL FUNC_TEST
MCPTHMSNS_D2_P
TRUE
MCPTHMSNS_D2_N
TRUE
LVDS FUNC_TEST
PP3V3_LCDVDD_SW_F
TRUE
PP3V3_S0_LCD_F
TRUE
PPVOUT_S0_LCDBKLT
TRUE
LVDS_IG_DDC_CLK
TRUE
LVDS_IG_DDC_DATA
TRUE
LVDS_IG_A_DATA_N<0>
TRUE
LVDS_IG_A_DATA_P<0>
TRUE
LVDS_IG_A_DATA_N<1>
TRUE
LVDS_IG_A_DATA_P<1>
TRUE
LVDS_IG_A_DATA_N<2>
TRUE
LVDS_IG_A_DATA_P<2>
TRUE
LVDS_IG_A_CLK_F_N
TRUE
LVDS_IG_A_CLK_F_P
TRUE
LED_RETURN_1
TRUE
LED_RETURN_2
TRUE
LED_RETURN_3
TRUE
LED_RETURN_4
TRUE
LED_RETURN_5
TRUE
LED_RETURN_6
TRUE
TP_BKL_SYNC
TRUE
46B5 80D3
I375
46B5 80D3
I374
I372
I370
6C3 68C2
I371
68C3
I369
6C3 68B2 71C1
I368
17B3 68C5
I361
17A3 68C5
I366
17B3 68C2 75B3
I365
17B3 68C2 75B3
I363
17B3 68C2 75B3
I364
17B3 68C2 75B3
I362
17B3 68C2 75B3
I360
17B3 68C2 75B3
I359
68C2 75B3
I357
68C2 75B3
I358
68B3 71B1
I377
68B3 71B1
I378
I267
I265
I266
I315
I318
I317
I307
I309
I311
I354
I355
SATA ODD CONN
(NEED
PP5V_SW_ODD
TRUE
SMC_ODD_DETECT
TRUE
SATA_ODD_D2R_C_P
TRUE
SATA_ODD_D2R_C_N
TRUE
SATA_ODD_R2D_P
TRUE
SATA_ODD_R2D_N
TRUE
I347
I349
4 TP) 6C3
I348
37D3
I350
37C7 40B8
I352
37C6 75A3
I351
37C6 75A3
I353
37C6 75A3
I327
6A7 37C6 75A3
(NEED TO ADD 4 GND TP)
I328
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R
IR_RX_OUT
PP5V_S3_IR_R
(NEED TO ADD 4 GND TP)
I343
I342
(NEED 4 TP)
I341
6C3 37B6
I339
37A5 75A3
I340
37A5 75A3
I338
37B5 75A3
I336
37B5 75A3
I337
37A7
I333
37A7 39D4
I335
37A7
I334
I331
A
I320
I305
BATT POWER CONN
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SYS_DETECT_L
TRUE
BATT_POS_F
TRUE
6A7 43C5 79D3
43C5 79D3
I356
58A8
(NEED 3 TP)
58A7 58B8 59A3
I394
(NEED TO ADD 3 GND TP)
I326
I323
I324
I325
I308
I281
29C7 75D3
I282
29C7 75D3
I376
29B7 76C3
29B7 76C3
6C3
29C5
I283
2 TP)
I279
I278
16B6 29C7
I270
6C5 43D2 79D3
I379
6C5 43D2 79D3
I273
29B7 76C3
I274
29B7 76B3
I275
29C7
I276
29A7
(NEED TO ADD 6 GND TP)
I272
IPD_FLEX_CONN
PP3V3_S3_LDO
TRUE
PP18V5_S3
TRUE
Z2_CS_L
TRUE
Z2_DEBUG3
TRUE
Z2_MOSI
TRUE
Z2_MISO
TRUE
Z2_SCLK
TRUE
Z2_BOOST_EN
TRUE
Z2_HOST_INTN
TRUE
Z2_CLKIN
TRUE
Z2_KEY_ACT_L
TRUE
Z2_RESET
TRUE
PSOC_MISO
TRUE
PSOC_MOSI
TRUE
PSOC_SCLK
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
PSOC_F_CS_L
TRUE
PICKB_L
TRUE
I392
I391
I390
6C3 49B4 49C3
I389
6C3 49C1 49D3
I388
48C8 49C3
I387
48C8 49C3
I386
48C8 49C3
I385
48C8 49C3
I383
48C8 49C3
I382
49C3 49C5
I381
48D8 49C3
I380
48C6 49C3
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PPVCORE_S0_CPU
PPVCORE_S0_MCP
PP0V75_S0
PP1V05_S0
PP1V5_S0
PP1V8_S0
PP5V_S0
PP3V3_S0
PP1V5_S3
PP3V3_S3
PP5V_S3
PP1V1R1V05_S5
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET_PHY
PP1V2R1V05_ENET
PP3V3_G3_RTC
PP5V_WLAN
PP5V_SW_ODD
PP5V_S0_HDD_FLT
PP3V3_S5_AVREF_SMC
PP18V5_S3
PP3V3_S3_LDO
PP3V3_LCDVDD_SW_F
PPVOUT_S0_LCDBKLT
PP4V5_AUDIO_ANALOG
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L
D
7D7
7C7
7C7
7D7
7C6
7B6
6D7 7D5
7D5
7D3
6B5 7D3
7C3
7B3
7B3
6A7 6B5 7D1
7C1
7B5
7B5
20C8 21A5 24D4
6D5 29C5
6B7 37D3
6B7 37B6
40D4 41C6
6C5 49C1 49D3
6C5 49B4 49C3
6C7 68C2
6C7 68B2 71C1
52A5 52D2 52D7
C
40D5 60C5 66D8
20C3 40C5 41A2 66C8
20C3 32B7 35A5 40C5 66D5 70D8
(NEED TO ADD 4 GND TP)
48C8 49C1
48C8 49C1
48C8 49C1
48C8 49C1
48C8 49C1
6D5 43D2 79D3
6D5 43D2 79D3
48C8 49C1
48D8 49C1
DC POWER CONN
PP18V5_DCIN_FUSE
TRUE
ADAPTER_SENSE
TRUE
(NEED TO ADD 4 GND TP)
(NEED 3 TP) 58D6
58D7
68B3 71A1
68C2
I330
I321
I280
29C7 75D3
KEYBOARD CONN
68B3 71B1
I332
I322
29C7 75D3
I304
SATA HDD/IR/SIL
I314
I284
68B3 71B1
I329
I319
I285
I312
I346
I269
I287
68B3 71B1
I345
I268
29C7
16B6 29C7 75D3
I393
I344
B
DEBUG VOLTAGE
16B6 29C7 75D3
55C2 56B2
(NEED TO ADD 5 GND TP)
I264
RIGHT CLUTCH CONN
PP5V_S3_BTCAMERA_F
TRUE
PCIE_MINI_D2R_P
TRUE
PCIE_MINI_D2R_N
TRUE
PCIE_MINI_R2D_P
TRUE
PCIE_MINI_R2D_N
TRUE
PCIE_CLK100M_MINI_CONN_P
TRUE
PCIE_CLK100M_MINI_CONN_N
TRUE
USB_CAMERA_CONN_P
TRUE
USB_CAMERA_CONN_N
TRUE
(NEED
PP5V_WLAN
TRUE
PCIE_WAKE_L
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
CONN_USB2_BT_P
TRUE
CONN_USB2_BT_N
TRUE
MINI_CLKREQ_Q_L
TRUE
MINI_RESET_CONN_L
TRUE
BATT SIGNAL CONN
(NEED
PP3V42_G3H
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMC_BIL_BUTTON_L
TRUE
SMC_LID_R
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S3
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
6D3 7D3
6A7 6D3 7D1
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
B
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C2 48C6
48C2
48C2
48C2 48D6
48C2 48D7
48C2 48D7
48C2 48D7
48C2 48D7
48C2 48D7
48C2 48D7
48C2
48B3 48B5 48C2
48B3 48B5 48C2
48B3 48B5 48C2
(NEED TO ADD 1 GND TP)
KBD BACKLIGHT CONN
(NEED
KBDLED_ANODE
TRUE
TRUE SMC_KDBLED_PRESENT_L
FUNC TEST
2 TP) 49A4
SYNC_MASTER=M97_MLB
49A4 49A6
(NEED TO ADD 2 GND TP)
3 TP)
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
6B5 6D3 7D1
II NOT TO REPRODUCE OR COPY IT
6A7 43C5 79D3
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
6A7 43C5 79D3
SIZE
40C5 58C4
DRAWING NUMBER
D
58C2
(NEED TO ADD 5 GND TP)
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
4.7.0
OF
6
1
81
8
6
7
"S0,S0M" RAILS
62D1
=PPVCORE_S0_CPU_REG
(CPU VCORE PWR)
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_VSENSE
D
67B6
=PP5V_S0_FET
6D3
61C1
PP5V_S0
=PP5V_S0_HDD
=PP5V_S0_LPCPLUS
=PP5V_S0_FAN_RT
10B5 10D6 11D6
44D8
=PPCPUVTT_S0_REG
PP1V05_S0
=PP1V05_S0_CPU
=PP1V05_S0_MCP_FSB
=PP1V05_S0_SMC_LS
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_HDMI_VDD
=PP1V05_S0_VMON
=PP1V05_S0_MCP_PLL_UF_R
=PP1V05_FW_P1V05FWFET
=PP1V05_FWPWRCTL
63C7 63C1 63B8
=PPMCPCORE_S0_REG
(MCP VCORE AFTER SENSE RES)
9D5 10C6 11B6 12D6
13A2 13B7 21D3 22C8
47C5
62D8
67C6
=PP3V3_S0_FET
17A6 23D7
66A8
65B3
35C6
35B4
PPVCORE_S0_MCP
6D3
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
21D5 22D8
=PPVCORE_S0_MCP_VSENSE
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PPVTT_S0_VTTCLAMP
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
67D1
=PP1V5_S0_FET
PP3V3_S0
26A4
27A4
PP1V5_S0
6D3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V8_S0_REG
10B6 11B6
66A8
15C3 15C7 22C8
27B3
65B6
PP1V8_S0
12D6
20C2 21B3 22B8
=PP3V3R1V8_S0_MCP_IFP_VDD
=PP1V8_S0_AUDIO
B
=PP1V05_S0_MCP_PLL_UF
37B8
43D3
=PP3V3_ENET_FET
37C7 37D6
60B8
=PP5V_S3_REG
PP5V_S3
PP1V05_S0_MCP_PLL_UF
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
43C3
43D8
=PP5V_S3_EXTUSB
=PP5V_S3_IR
=PP5V_S3_BTCAMERA
=PP5V_S3_VTTCLAMP
=PP5V_S3_MCPDDRFET
=PP5V_S3_SYSLED
=PP5V_S3_TPAD
=PP5V_S3_WLAN
=PP5V_S3_1V5S30V75S0
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_P5VS0FET
=PP5V_S3_ODD
47C5
52A8 52D2 56D8 57B8 57D3
62D8
68C5
17C1 18D1 20A4
22B6
20D3 20D8 22A8
41A1 41D3
46B6
46D6
70B8 70C8
26A8
=PP3V3_ENET_PHY
58C2 58C4
40D4 41C1 41C3
41C7 41D8
42C7 42C8 42D5
24D8
45B8
=PP3V42_G3H_ONEWIRE
=PP3V42_G3H_AUDIO
43B5
25D8
58D2
56B6
29A6
20A3
58D1 58C8
48A6 48B5 48C5 48D2
=PP18V5_DCIN_CONN
PP18V5_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
50B7
30D7
=PP18V5_G3H_CHGR
59D8
59C1
=PPBUS_G3H
PPBUS_G3H
6C3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPBUS_S0_LCDBKLT
=PPVIN_S0_MCPCORE
=PPVIN_S5_1V5S30V75S0
=PPVIN_S5_3V3S5
=PPVIN_S3_5VS3
=PPBUS_G3HRS5
=PPBUS_S5_FWPWRSW
=PPCPUVCORE_VTT_ISNS_R
38C7
37A8 39D7
29C3
67A3
67D4
41B8
49B6 49D7
29C1
72D8
63D5
61C2
60C3
60C6 60C7
35B7
45B8
(BEFORE HIGH SIDE SENSING RES.)
61C5
52A8 52D2 54D5 56B6
55B7 55C7 55D7
67B8
37D5
66A5
66A8
61D8 25D3
=PPVTT_S3_DDR_BUF
45C7
49A6
PPVTT_S3_DDR_BUF
45B7
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PPCPUVCORE_VTT_ISNS
PPBUS_G3H_CPU_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
(AFTER HIGH SIDE CPU VCORE
& CPU VTT SENSING RES.)
43C8
=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP
65D8
64C6
62C3 62D4 62D8
71C7
45D8
65C6
35D6
35B1 35D2
"FIREWIRE" RAILS
=PP1V05_S5_REG
35D4
PP1V1R1V05_S5
PP3V3_FW
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
36D5
36B6
35D8
34B1
34D2
35C7
=PP3V3_FW_FWPHY
=PP3V3_S0_P1V05FWFET
6D3
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_ENET_P1V05ENETFET
17D3 17D7 22A5 22B6
=PP3V3_FW_FET
=PP1V05_ENET_FET
PP1V2R1V05_ENET
32C4
35B1
PPVP_FW
=PPBUS_S5_FW_FET
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE
31D7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
6C3
60B1
=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY
=PP3V3_S5_REG
22A8
17D3 22D6
31D2
=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_AVDD1
PP1V05_S0_MCP_PEX_AVDD
16B3
206 mA (A01)
16A3
MAKE_BASE=TRUE
206 mA (A01)
A
22D8 7D7
=PP1V05_S0_MCP_PEX_DVDD0
=PP1V05_S0_MCP_PEX_DVDD1
=PP1V05_S0_MCP_PEX_DVDD
16B6
57 mA (A01)
16A6
206 mA (A01)
22D2
PP1V05_S0_MCP_SATA_AVDD
=PP1V05_S0_MCP_SATA_AVDD0
=PP1V05_S0_MCP_SATA_AVDD1
MAKE_BASE=TRUE
127 mA (A01)
22D6 7D7
=PP1V05_S0_MCP_SATA_DVDD
19B6
35C5
=PP1V0_FW_FET
19B6
36C6
PP1V05_FW
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
17C7 19C1
42B5 42C7 51C6
=PP1V0_FW_FWPHY
34D8
35D3
68C8
21B3 22B8
24B8
66B3
32C5
67D8
67C8
65B8
28C4
Power Aliases
32D5
70D8
SYNC_MASTER=BEN
A
36A7
NOTICE OF PROPRIETARY PROPERTY
35A8
35C7
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
19B6
=PP1V05_S0_MCP_SATA_DVDD0
=PP1V05_S0_MCP_SATA_DVDD1
127 mA (A01)
127 mA (A01)
36C3
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP3V3_S5_MCP
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_PWRCTL
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P1V05S5
=PP3V3_S5_MEMRESET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR
=PP3V3_FW_LATEVG
=PP3V3_FW_LATEVG_ACTIVE
=PP3V3_S5_P1V05FWFET
PEX & SATA AVDD/DVDD aliases
22D1
PP3V3_S5
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
43 mA (A01)
II NOT TO REPRODUCE OR COPY IT
19B6
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
B
21A3 22D8
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
32B2
C
44B8
27A8
6C3
=PP3V3_ENET_MCP_RMGT
D
38B8
48B5 48C2 48C3
48C5
61B3
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
43D5
65A5
PP3V3_ENET_PHY
66B3 66C8 66D8
59A8 59C6 59D5
23C7
"ENET" RAILS
52D7
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_RTC_D
=PP3V42_G3H_BMON_ISNS
6B5 6D3
"S5" RAILS
17B6 23D7
32D2
65B1 22C4
28C6
41C8
43C5
23D4
6D3
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE
27D7
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PDCISENS
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_TPAD
=PP3V3_S3_SMS
=PP3V3_S3_CARDREADER
6A7 6B5 6D3
=PPVIN_S5_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_CHGR
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PP3V42_G3H_BATT
26D7
PP3V3_S3
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_DPCONN
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_PWRCTL
=PP3V3_S0_VMON
=PP3V3_S0_CPUVTTISNS
=PP3V3_S0_TPAD
=PP3V3_S0_SMBUS_MCP_1
=PP3V3_S0_P1V8S0
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_MCP_PLL_VLDO
=PP3V3_S0_P3V3FWFET
=PP3V3_S0_FWPWRCTL
67B3
PP3V42_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
67D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
63D4
=PP3V3_S0_LCD
=PP3V3_S0_MCP_GPIO
6D3
=PP1V5_S0_CPU
=PP1V5_S0_VMON
=PP1V8R1V5_S0_MCP_MEM
=PP1V5_S0_MEM_MCP
=PP1V5_S0_MCP_PLL_VLDO
65C5
=PP3V3_S3_FET
66B5
=PP3V3_S0_MCP_PLL_UF
PP0V75_S0
67D6
71D4
=PP3V3_S0_IMVP
44D8
=PP3V42_G3H_REG
69B6
64C8
=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PP3V3_S0_MCP_DAC_UF
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_ODD
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_FAN_RT
=PP3V3_S0_AUDIO
C
=PP0V75_S0_REG
=PP1V5_S3_HDD
58B4
49A5
22D4
7A8 22D6
6D3
=PP1V5_S3_P1V5S0FET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_MEMRESET
37B3
7A8 22D8
=PPVCORE_S0_MCP
61C8
PP1V5_S3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
42D5
=PP5V_S0_KBDLED
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_CPUVTTS0
=PP5V_S0_BKL
=PP5V_S0_MCPREG
=PP5V_S0_VMON
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V5_S3_REG
6D3 6D7
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
1
"G3H" RAILS
"S3" RAILS
=PP5V_S0_CPU_IMVP
64C2
2
3
4
5
4.7.0
OF
7
1
81
8
6
7
HEATSINK STANDOFFS
Z0902
Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
1
1
16D6 16C6
UNUSED GPU LANES
=PEG_D2R_N<15:0>
NC_PEG_D2R_N<15:0>
16D6 16C6
=PEG_D2R_P<15:0>
NC_PEG_D2R_P<15:0>
16D3 16C3
=PEG_R2D_C_N<15:0>
NC_PEG_R2D_C_N<15:0>
16D3 16C3
LEFT OF CPU
D
ABOVE CPU
16C6
16C3
Z0904
Z0903
STDOFF-4.5OD.98H-1.1-3.48-TH
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
PEG_PRSNT_L
TP_PEG_PRSNT_L
PEG_CLK100M_P
16C3
17C6
17C6
NO_TEST=TRUE
MCP_TV_DAC_VREF
MCP_CLK27M_XTALIN
NC_MCP_CLK27M_XTALOUT
CRT_IG_R_C_PR
NC_CRT_IG_R_C_PR
17C3
CRT_IG_G_Y_Y
NC_CRT_IG_G_Y_Y
PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
TP_PCIE_EXCARD_D2R_N
NC_CRT_IG_B_COMP_PB
NC_CRT_IG_HSYNC
NO_TEST=TRUE
NO_TEST=TRUE
16B3
PCIE_EXCARD_R2D_C_P
TP_PCIE_EXCARD_R2D_C_P
16B3
PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_N
16C6
PCIE_EXCARD_PRSNT_L
TP_PCIE_EXCARD_PRSNT_L
17B3
MAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_P
TP_PCIE_CLK100M_EXCARD_P
16C3
PCIE_CLK100M_EXCARD_N
TP_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
LVDS ALIASES
17B3
TP_EXCARD_CLKREQ_L
16C3
MAKE_BASE=TRUE
NC_CRT_IG_VSYNC
NO_TEST=TRUE
=P3V3ENET_EN
=P1V05ENET_EN
=PP3V3_ENET_PHY_VDDREG
=RTL8211_REGOUT
=RTL8211_ENSWREG
32C5
32B5
31C2
31C2
PM_SLP_RMGT_L
D
20C3
MAKE_BASE=TRUE
TP_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
31B6
NO_TEST=TRUE
R0931
22
LVDS_IG_A_DATA_N<3>
1
5%
1/16W
MF-LF
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATA_N3
NO_TEST=TRUE
2 402
MAKE_BASE=TRUE
LVDS_IG_B_CLK_P
NC_LVDS_IG_B_CLK_P
17B3
LVDS_IG_B_CLK_N
NC_LVDS_IG_B_CLK_N
17B3
LVDS_IG_B_DATA_P<3:0>
NC_LVDS_IG_B_DATA_P<3:0>
17B3
LVDS_IG_B_DATA_N<3:0>
NC_LVDS_IG_B_DATA_N<3:0>
MAKE_BASE=TRUE
TP_RTL8211_CLK125
UNUSED LVDS SIGNALS
LVDS_IG_A_DATA_P<3>
NC_LVDS_IG_A_DATA_P3
17B3
MAKE_BASE=TRUE
1
MAKE_BASE=TRUE
31C6
MAKE_BASE=TRUE
Z0905
MAKE_BASE=TRUE
CRT_IG_HSYNC
CRT_IG_VSYNC
MAKE_BASE=TRUE
ETHERNET ALIASES
MAKE_BASE=TRUE
CRT_IG_B_COMP_PB
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
NO_TEST=TRUE
17C3
17C3
TP_MEM_A_A15
TP_MEM_B_A15
MAKE_BASE=TRUE
MAKE_BASE=TRUE
17C3
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
27D5
MAKE_BASE=TRUE
MCP_CLK27M_XTALOUT
16B6
EXCARD_CLKREQ_L
NO_TEST=TRUE
17C6
TP_PEG_CLK100M_N
MEM_A_A<15>
MEM_B_A<15>
26D5
NC_MCP_CLK27M_XTALIN
17C3
16B6
16C6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FAN STANDOFF
UNUSED ADDRESS PINS
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
NO_TEST=TRUE
1
SO-DIMM ALIASES
UNUSED CRT & TV-OUT INTERFACE
MCP_TV_DAC_RSET
NC_MCP_TV_DAC_RSET
MAKE_BASE=TRUE
UNUSED EXPRESS CARD LANE
BELOW CPU
17C6
TP_PEG_CLK100M_P
PEG_CLK100M_N
1
BELOW MCP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
1
MAKE_BASE=TRUE
NC_PEG_R2D_C_P<15:0>
NO_TEST=TRUE
DACS ALIASES
MAKE_BASE=TRUE
=PEG_R2D_C_P<15:0>
2
3
4
5
PCI-E ALIASES
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
FW ALIASES
MAKE_BASE=TRUE
18B7
FW_PME_L
FW_PLUG_DET_L
=FW_PME_L
FW643_WAKE_L
35B1 35D7
MAKE_BASE=TRUE
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
OMIT
R0950
OMIT
Z0906
3R2P5
Z0907
3R2P5
1
MISC MCP79 ALIASES
FIREWIRE PRESENT SIGNALS
35D3 16C6
PCIE_FW_PRSNT_L
1
0
NOSTUFF
MAKE_BASE=TRUE
CPU_PECI_MCP
TP_CPU_PECI_MCP
16B6
GMUX_JTAG_TCK_L
GMUX_JTAG_TDO
TP_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE
TP_GMUX_JTAG_TDO
18D4
GMUX_JTAG_TDI
TP_GMUX_JTAG_TDI
18D4
GMUX_JTAG_TMS
TP_GMUX_JTAG_TMS
13B6
MAKE_BASE=TRUE
2
5%
1/16W
MF-LF
402
1
35C8 34B2
16B6
C
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB ALIASES
UNUSED USB PORTS
MLB MOUNTING (TO TOPCASE) SCREW HOLES
OMIT
Z0908
3R2P5
OMIT
Z0909
3R2P5
1
19C3
19C3
OMIT
Z0910
3R2P5
1
19D3
19D3
19C3
1
19C3
19D3
OMIT
Z0911
3R2P5
OMIT
Z0912
3R2P5
1
19D3
USB_EXTC_P
USB_EXTC_N
USB_EXTD_P
USB_EXTD_N
USB_EXCARD_P
USB_EXCARD_N
TP_USB_EXTC_P
TP_USB_EXTC_N
TP_USB_EXTD_P
TP_USB_EXTD_N
TP_USB_EXCARD_P
TP_USB_EXCARD_N
USB_MINI_P
TP_USB_MINI_P
LAN ALIASES
MAKE_BASE=TRUE
MAKE_BASE=TRUE
17D6
MAKE_BASE=TRUE
17D6
MAKE_BASE=TRUE
17D6
MCP_MII_PD
MAKE_BASE=TRUE
R0930
1
47K
CPU FSB FREQUENCY STRAPS
5%
1/16W
MF-LF
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BSEL<2..0>
2 402
MAKE_BASE=TRUE
USB_MINI_N
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
TP_USB_MINI_N
DP HOTPLUG PULL-DOWN
MAKE_BASE=TRUE
1
17B6
=DVI_HPD_GMUX_INT
73C3 9B4
IN
CPU_BSEL<0:2>
MAKE_BASE=TRUE
=MCP_BSEL<0:2>
OUT
13A7
HPLUG_DET2
MAKE_BASE=TRUE
R0940
20K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
FSB MHZ
0
1
0
1
0
1
0
1
266
133
200
(166)
333
100
(400)
(RSVD)
1
5%
1/16W
MF-LF
2 402
B
B
EMI IO POGO PINS
ZS0900
1.4DIA-SHORT-EMI-MLB-M97-M98
SM OMIT
ZS0901
SM OMIT
1.4DIA-SHORT-EMI-MLB-M97-M98
1
ZS0902
SM OMIT
1.4DIA-SHORT-EMI-MLB-M97-M98
1
PART NUMBER
870-1801
QTY
6
ZS0903
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1
DESCRIPTION
REFERENCE DES
POGO PIN,SHORT,EMI,MLB,K19/K24
CRITICAL
ZS0900,ZS0901,ZS0902,ZS0903,ZS0908,ZS0909
1
OMIT
ZS0908
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1
OMIT
ZS0909
SM OMIT
1.4DIA-SHORT-EMI-MLB-M97-M98
1
BOM OPTION
SIGNAL ALIAS
CRITICAL
A
SYNC_MASTER=M97_MLB
A
NOTICE OF PROPRIETARY PROPERTY
EMI POGO PINS
ZS0904
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
ZS0905
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ZS0906
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
ZS0907
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2.0DIA-TALL-EMI-MLB-M97-M98
II NOT TO REPRODUCE OR COPY IT
SM
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
8
1
81
8
6
7
2
3
4
5
1
OMIT
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13B6
BI
73D3 13B6
BI
73D3 13B6
BI
73D3 13B6
BI
73D3 13B6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
73C3 13C6
BI
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
C
BI
73D3 13B6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13B6
BI
73C3 13A3
73C3 13B7
73C3 13A3
K3
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
IN CPU_A20M_L
OUT CPU_FERR_L
IN CPU_IGNNE_L
73B3 13A3
IN
73C3 13A3
IN
73C3 13A3
IN
73B3 13A3
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
IN
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
H2
K2
J3
L1
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
F6
D2
D22
D3
FCBGA
1 OF 4
DEFER*
DRDY*
DBSY*
BR0*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
G5
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
H5
F21
E1
FSB_BREQ0_L
F1
BI
13B6 73C3
BI
13B6 73C3
BI
13B3 73C3
BI
13B3 73C3
BI
13B6 73C3
BI
13B6 73C3
BI
B3
CPU_IERR_L
CPU_INIT_L
IN
LOCK*
H4
FSB_LOCK_L
BI
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
IERR*
INIT*
D20
HIT*
HITM*
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
73B3
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
PROCHOT*
THERMDA
THERMDC
1%
1/16W
MF-LF
402
THERMTRIP*
13B6 73C3
12C2 13A3 73C3
13A6 73C3
IN
13A6 73C3
IN
13A6 73C3
IN
13B6 73C3
BI
13B6 73C3
BI
13B6 73C3
OMIT
12C6 73A3
BI
12C6 73A3
BI
12C6 73A3
BI
12C6 73A3
R1001 1
BI
73D3 13D3
73D3 13D3
BI
73D3 13D3
BI
73D3 13D3
BI
2
12C6 73A3
BI
73D3 13D3
BI
IN
9B6 12B3 73A3
73D3 13D3
BI
OUT
9B6 12B3 73A3
73D3 13D3
IN
9B6 12B3 73A3
73D3 13D3
BI
IN
9A6 12B3 73A3
73D3 13D3
BI
73D3 13D3
BI
12B3 24A3
R1002 1
46D5 80D3
C7
PM_THRMTRIP_L
OUT
13B7 41C4 73B3
73D3 13D3
5%
1/16W
MF-LF
402
73D3 13D3
BI
73D3 13D3
BI
73D3 13D6
BI
73D3 13D6
BI
73D3 13D6
BI
73D3 13D3
BI
73D3 13D3
BI
73D3 13D3
BI
2
OUT
IN
IN
13B6 41D4 62C8 73C3
13B3 73B3
13B3 73B3
BI
73D3 13D3
BI
73D3 13C3
BI
1K
CPU JTAG Support
R1090
1
73A3 12B3 9C6
73A3 12B3 9C6
XDP_TDI
1
2
1%
1/16W
MF-LF
402
XDP_TDO
BI
73D3 13C3
BI
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
54.9
BI
73D3 13C3
BI
73D3 13C3
BI
1%
1/16W
MF-LF
2 402
C1014
2
1
R1094
73A3 12B3 9C6
XDP_TRST_L
1
649
2
1%
1/16W
MF-LF
402
73D3 13D6
BI
73D3 13D6
BI
73D3 13D6
BI
10%
16V
X5R
402
R1010
2
0
5%
1/16W
MF-LF
402
R1011 1
1K
5%
1/16W
MF-LF
402 2
1
0.1uF
NO STUFF
NO STUFF
XDP_TCK
BI
NO STUFF
1
73A3 12B6 9C6
BI
73D3 13C3
R1006
1%
1/16W
MF-LF
402
54.9
BI
73D3 13C3
2.0K
R1093
BI
73D3 13C3
2
NO STUFF
1
2
73C3 8B2
73C3 8B2
73C3 8B2
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
E22
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7
OUT CPU_BSEL<0>
OUT CPU_BSEL<1>
OUT CPU_BSEL<2>
73B3 25B1
1
R1092
1
2
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
R1091
54.9
54.9
R1005
BI
73D3 13C3
73D3 13C3
1
BI
73D3 13D3
73D3 13C3
XDP_TMS
BI
68
73D3 13C3
73A3 12B3 9C6
BI
IN
OUT
B
BI
73D3 13D3
OUT
FSB_CLK_CPU_P
FSB_CLK_CPU_N
73D3 13D3
9A6 12B6 73A3
B25
A21
BI
1%
1/16W
MF-LF
402
12C6 73A3
46D5 80D3
A22
73D3 13D3
54.9
H CLK
BCLK0
BCLK1
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
2
D
OUT
A24
1
54.9
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
D21
7D7 10C6 11B6 12D6
13A3 73C3
IN
BI
R1000
13B6 73C3
IN
BI
=PP1V05_S0_CPU
THERMAL
A20M*
FERR*
IGNNE*
STPCLK*
LINT0
LINT1
SMI*
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
H1
E2
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2
U1000
PENRYN
FCBGA
2 OF 4
DATA GRP 2
BI
ADS*
BNR*
BPRI*
PENRYN
DATA GRP 3
BI
73D3 13C6
M3
U1000
DATA GRP 0
73D3 13D6
K5
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
DATA GRP 1
BI
L4
CONTROL
73D3 13D6
L5
XDP/ITP SIGNALS
BI
J4
ADDR GROUP0
BI
73D3 13D6
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ADDR GROUP1
BI
73D3 13D6
ICH
BI
73D3 13D6
RESERVED
D
73D3 13D6
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
Y22
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
AE24
COMP0
COMP1
COMP2
COMP3
MISC
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13B3 73D3
BI
13D6 73D3
BI
13D6 73D3
BI
13D6 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13D6 73D3
BI
13D6 73D3
BI
13D6 73D3
C
B
R26 73A3 CPU_COMP<0>
U26 73B3 CPU_COMP<1>
AA1 73B3 CPU_COMP<2>
Y1
E5
B5
D24
D6
D7
AE6
73B3
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
IN
13A3 62C7 73B3
IN
13A3 73B3
IN
13A3 73B3
IN
12C7 13A3 73C3
IN
13A3 73B3
OUT
R1023 1
R1021 1
54.9
1%
1/16W
MF-LF
402
54.9
1%
1/16W
MF-LF
402
2
62C7
1
5%
1/16W
MF-LF
2 402
1
R1022
R1020
27.4
R1012
1K
2
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
2
27.4
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
PLACEMENT_NOTE (all 4 resistors):
1%
1/16W
MF-LF
402
Place within 12.7mm of CPU
CPU FSB
A
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SYNC FROM T18
CHANGE CPU FROM SOCKET TO BGA SYMBOL
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
9
1
81
A
8
6
7
5
2
3
4
A4
(CPU CORE POWER)
D
A9
A10
OMIT
AB7
U1000
AC7
A
A
A
A
(SV
(SV
(SV
(LV
Design Target)
HFM)
LFM)
Design Target)
A14
U1000
A16
PENRYN
P24
R2
R5
FCBGA
A19
R25
AF2
T1
B6
T4
B8
T23
AC12
B11
T26
3 OF 4
AC13
B13
U3
A17
AC15
B16
U6
A18
AC17
B19
U21
A20
AC18
B21
U24
B7
AD7
B24
V2
B9
AD9
C5
V5
A15
B10
AD10
C8
V22
B12
AD12
C11
V25
B14
AD14
C14
W1
B15
AD15
C16
W4
B17
AD17
C19
W23
B18
AD18
C2
W26
B20
AE9
C22
Y3
Y6
VCC
C9
AE10
C25
C10
AE12
D1
Y21
C12
AE13
D4
Y24
C13
AE15
D8
AA2
C15
AE17
D11
AA5
C17
AE18
D13
AA8
C18
AE20
D16
AA11
AF9
D19
AA14
D10
AF10
D23
AA16
D12
AF12
D26
AA19
D14
AF14
E3
AA22
D15
AF15
D9
VCC
E6
AA25
D17
AF17
E8
AB1
D18
AF18
E11
AB4
E7
AF20
(CPU IO POWER 1.05V)
E14
=PP1V05_S0_CPU
E9
7D7 9D5 11B6 12D6
G21
E10
4500 mA (before VCC stable)
2500 mA (after VCC stable)
VSS
VSS
AB11
E19
AB13
E21
AB16
V6
E13
J6
E24
AB19
E15
K6
F5
AB23
E17
M6
F8
AB26
E18
J21
F11
AC3
E20
K21
F13
AC6
F7
M21
F16
AC8
N21
F19
AC11
VCCP
F10
N6
F2
AC14
F12
R21
F22
AC16
F14
R6
F25
AC19
F15
T21
G4
AC21
F17
T6
G1
AC24
F18
V21
F20
W21
AA7
AD2
G26
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16
62C7 73A3
J2
AD19
OUT
62C7 73A3
J5
AD22
OUT
62C7 73A3
J22
AD25
OUT
62C7 73A3
J25
AE1
OUT
62C7 73A3
K1
AE4
OUT
62C7 73A3
K4
AE8
OUT
62C7 73A3
=PP1V5_S0_CPU
(BR1#)
AA9
B26
VCCA
AA10
G23
(CPU INTERNAL PLL POWER 1.5V)
7B6 11B6
130 mA
C26
AA12
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
=PPVCORE_S0_CPU
1
2
AB14
VCCSENSE
AF7
R1100
100
AB10
AB12
7D7 10D6 11D6
CPU_VCCSENSE_P
1%
1/16W
MF-LF
402
OUT
62A5 73A3
AB15
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
AB17
AB18
VSSSENSE
AE7
CPU_VCCSENSE_N
OUT
1
62A5 73A3
R1101
100
2
1%
1/16W
MF-LF
402
K23
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
M22
AF8
M25
AF11
N1
AF13
N4
AF16
N23
AF19
N26
AF21
P3
B1
C
AB8
E16
E12
F9
D
R22
4 OF 4
A23
AC9
PENRYN
A13
B
44
41
30.4
23
P21
OMIT
FCBGA
A12
C
7D7 10B5 11D6
AB20
A7
P6
A8
A11
=PPVCORE_S0_CPU
1
B
A25
(Socket-P KEY)
AF25
CPU Power & Ground
A
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SYNC FROM T18
CHANGE CPU FROM SOCKET TO BGA SYMBOL
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
SCALE
SHT
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
10
1
81
A
8
6
7
2
3
4
5
1
CPU VCore HF and Bulk Decoupling
4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219):
10D6 10B5 7D7
=PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D
CRITICAL
1
CRITICAL
C1200
1
20%
6.3V
CERM-X5R
805
2
22UF
2
20%
6.3V
CERM-X5R
805
2
1
2
1
20%
6.3V
CERM-X5R
805
2
1
1
20%
6.3V
CERM-X5R
805
2
C1213
1
2
20%
6.3V
CERM-X5R
805
2
1
20%
6.3V
CERM-X5R
805
2
1
20%
6.3V
CERM-X5R
805
2
1
C1215
2
20%
6.3V
CERM-X5R
805
1
20%
6.3V
CERM-X5R
805
2
C1216
20%
6.3V
CERM-X5R
805
1
20%
6.3V
CERM-X5R
805
2
C1217
2
20%
6.3V
CERM-X5R
805
1
20%
6.3V
CERM-X5R
805
2
20%
6.3V
CERM-X5R
805
CRITICAL
C1218
1
22UF
2
C1209
22UF
CRITICAL
1
22UF
D
CRITICAL
C1208
22UF
CRITICAL
1
22UF
2
CRITICAL
C1207
22UF
CRITICAL
1
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1206
22UF
CRITICAL
C1214
22UF
2
CRITICAL
C1205
22UF
CRITICAL
1
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1204
22UF
CRITICAL
C1212
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1203
22UF
CRITICAL
C1211
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1202
22UF
CRITICAL
C1210
22UF
2
1
22UF
CRITICAL
1
CRITICAL
C1201
C1219
22UF
20%
6.3V
CERM-X5R
805
2
20%
6.3V
CERM-X5R
805
C
C
PLACEMENT_NOTE (C1240-C1243):
Place on secondary side.
NOSTUFF
CRITICAL
1
1
C1240
470UF-4MOHM
3
2
Place on secondary side.
CRITICAL
20%
2.0V
POLY-TANT
D2T-SM
CRITICAL
1
C1241
470UF-4MOHM
3
2
20%
2.0V
POLY-TANT
D2T-SM
Place on secondary side.
CRITICAL
1
C1242
470UF-4MOHM
3
2
20%
2.0V
POLY-TANT
D2T-SM
C1243
470UF-4MOHM
3
20%
2.0V
POLY-TANT
D2T-SM
2
Place on secondary side.
VCCA (CPU AVdd) DECOUPLING
1x 10uF, 1x 0.01uF
10B6 7B6
=PP1V5_S0_CPU
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
C1250
1
1
2
2
10uF
20%
6.3V
X5R
603
C1251
0.01UF
10%
16V
CERM
402
B
B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
12D6 10C6 9D5 7D7
=PP1V05_S0_CPU
PLACEMENT_NOTE=Place C1260 between CPU & NB.
CRITICAL
C1260
1
1
20%
2.0V
POLY-TANT
D2T-SM2
C1261
1
0.1UF
330UF
2
3
2
20%
10V
CERM
402
C1262
1
0.1UF
2
20%
10V
CERM
402
C1263
1
0.1UF
2
20%
10V
CERM
402
C1264
1
0.1UF
2
20%
10V
CERM
402
C1265
1
0.1UF
2
20%
10V
CERM
402
C1266
0.1UF
2
20%
10V
CERM
402
CPU Decoupling
A
SYNC_MASTER=RAYMOND
SYNC_DATE=03/31/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SYNC FROM T18
REMOVE NO STUFF CAPS C1220 TO C1231
REMOVE C1244 & C1245
CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
11
1
81
A
8
6
7
2
3
4
5
1
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
D
Use with 920-0620 adapter board to support CPU, MCP debugging.
D
MCP79-specific pinout
7C5
11B6 10C6 9D5 7D7
=PP3V3_S0_XDP
=PP1V05_S0_CPU
XDP
XDP_CONN
CRITICAL
R1315 1
J1300
54.9
1%
1/16W
MF-LF
402 2
73A3 9C5
73A3 9C6
73A3 9C6
73A3 9C6
BI
BI
BI
IN
73A3 9C6
IN
73A3 9C6
IN
C
LTH-030-01-G-D-NOPEGS
F-ST-SM
XDP_BPM_L<5>
XDP_BPM_L<4>
OBSFN_A0
OBSFN_A1
XDP_BPM_L<3>
XDP_BPM_L<2>
OBSDATA_A0
OBSDATA_A1
XDP_BPM_L<1>
XDP_BPM_L<0>
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
OBSFN_B0
OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
OBSDATA_B0
OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
XDP
OBSDATA_B2
OBSDATA_B3
R1399
73C3 13A3 9B2
IN
CPU_PWRGD
1
1K
XDP_PWRGD
2
XDP_OBS20
5%
1/16W
MF-LF
402
18C4
20B7
IN
OUT
76B3 43D8 20C3
BI
76B3 43D8 20C3
BI
73A3 9C6 9A6
OUT
PM_LATRIGGER_L
JTAG_MCP_TCK
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
SDA
SCL
TCK1
TCK0
XDP_TCK
NC
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
1
1
2
2
0.1uF
10%
16V
X5R
402
JTAG_MCP_TRST_L
OBSDATA_C0
OBSDATA_C1
MCP_DEBUG<0>
MCP_DEBUG<1>
BI
18D7 76D3
BI
18D7 76D3
OBSDATA_C2
OBSDATA_C3
MCP_DEBUG<2>
MCP_DEBUG<3>
BI
18D7 76D3
OBSFN_D0
OBSFN_D1
JTAG_MCP_TDI
JTAG_MCP_TMS
OUT
20B7
OUT
20B7
OBSDATA_D0
OBSDATA_D1
MCP_DEBUG<4>
MCP_DEBUG<5>
BI
18D7 76D3
BI
18D7 76D3
OBSDATA_D2
OBSDATA_D3
MCP_DEBUG<6>
MCP_DEBUG<7>
BI
18D7 76D3
BI
18D7 76D3
FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
73A3 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
XDP_PRESENT#
XDP
XDP
C1300
JTAG_MCP_TDO
OBSFN_C0
OBSFN_C1
IN
20B7
OUT
20B7
BI
18D7 76D3
IN
13B3 73B3
IN
13B3 73B3
C
XDP
R1303
1
OUT
9C6 24A3
IN
9B6 9C6 73A3
OUT
9A6 9C6 73A3
OUT
9B6 9C6 73A3
OUT
9B6 9C6 73A3
1K
5%
1/16W
MF-LF
402
2
FSB_CPURST_L
IN
9D6 13A3 73C3
PLACEMENT_NOTE=Place close to CPU to minimize stub.
C1301
0.1uF
B
10%
16V
X5R
402
B
998-1571
Direction of XDP module
Please avoid any obstructions
on even-numbered side of J1300
eXtended Debug Port(MiniXDP)
A
SYNC_MASTER=K19_MLB
SYNC_DATE=11/07/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
12
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
BI
73D3 9C4
BI
73D3 9C4
73D3 9B4
D
C
73D3 9B4
BI
73D3 9C2
BI
73D3 9C2
BI
73D3 9C2
BI
73D3 9B2
BI
73D3 9B2
BI
73D3 9B2
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73C3 9D8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
73D3 9D8
R1410 1
B
73B3 41C4 9C6
73C3 9C8
IN
IN
R1415 1
54.9
62
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
2
2
73D3 9D8
BI
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
R1420
8B1
IN
8B1
IN
8B1
IN
1
NO STUFF
R1421
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
R1422
1K
2
BI
2
U40
V41
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
W39
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
N37
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
M39
W37
V35
L36
N35
M41
J41
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
AC34
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
AE36
AE38
AE34
AC37
AE37
AE35
AB35
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AJ34
AL38
AL35
AN34
AR39
AN35
AK35
AC38
AA33
AC39
AC33
AC35
FSB_ADS_L
FSB_BNR_L
BI
FSB_BREQ0_L
BI
73C3 FSB_BREQ1_L
FSB_DBSY_L
BI
FSB_DRDY_L
BI
FSB_HIT_L
BI
FSB_HITM_L
BI
FSB_LOCK_L
IN
FSB_TRDY_L
OUT
AD42
BI
NO STUFF
1
T40
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
BI
BI
73C3 9D6
NO STUFF
BI
BI
73C3 9D6
PM_THRMTRIP_L
CPU_FERR_L
BI
73D3 9D8
62
5%
1/16W
MF-LF
402
BI
73D3 9D8
73D3 9D8
R1416
BI
73C3 9C8
73D3 9D8
=PP1V05_S0_MCP_FSB
BI
BI
73C3 9C8
22C8 21D3 13A2 7D7
BI
73D3 9B4
73C3 9C8
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
8C4
OUT
73C3 62C8 41D4 9C5
OUT
AD43
AE40
AL32
AD39
AD41
AB42
AD40
AC43
AE41
CPU_PECI_MCP
CPU_PROCHOT_L
E41
AJ41
AG43
5%
1/16W
MF-LF
402
AH40
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)
F42
D42
F41
CPU_DSTBP0#
CPU_DSTBN0#
CPU_DBI0#
CPU_DSTBP1#
CPU_DSTBN1#
CPU_DBI1#
CPU_DSTBP2#
CPU_DSTBN2#
CPU_DBI2#
CPU_DSTBP3#
CPU_DSTBN3#
CPU_DBI3#
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#
FSB
73D3 9C4
CPU_ADSTB0#
CPU_ADSTB1#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_BPRI#
CPU_DEFER#
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43
AA41
AA40
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
G42
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
AL43
BCLK_OUT_NB_P
BCLK_OUT_NB_N
AL41
BCLK_IN_N
BCLK_IN_P
AK41
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
AF41
CPU_PWRGD
CPU_RESET#
AH43
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
AM33
G41
AL42
AK42
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
FSB_BPRI_L
FSB_DEFER_L
OUT
9D6 73C3
OUT
9D6 73C3
FSB_CLK_CPU_P
FSB_CLK_CPU_N
OUT
9B6 73B3
OUT
9B6 73B3
FSB_CLK_ITP_P
FSB_CLK_ITP_N
OUT
12C3 73B3
OUT
12C3 73B3
D
C
B
FSB_CLK_MCP_P
73B3 FSB_CLK_MCP_N
73B3
Loop-back clock for delay matching.
R1430
1
1
R1435
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
2
73C3 9D6
OUT
73C3 9D6
OUT
73C3 9D6
OUT
22C2
73B3
73B3
73B3
1
73B3
R1436
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
2
AC41
AB41
AC42
CPU_RS0#
CPU_RS1#
CPU_RS2#
PP1V05_S0_MCP_PLL_FSB
270 mA (A01)
A
R1431 1
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
206
20
29
15
mA
mA
mA
mA
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
AG27
AH27
AG28
AH28
AM39
AM40
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
AM43
AM42
+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU
BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND
AJ40
AH39
AH42
AF42
AG41
AH41
H38
AN33
AM32
AG42
AN32
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
9C8 73C3
OUT
9C8 73C3
OUT
9D6 73C3
OUT
9C8 73C3
OUT
9B8 73C3
OUT
9B8 73B3
=PP1V05_S0_MCP_FSB
R1440
150
2
9D6 12C2 73C3
OUT
9B2 73B3
OUT
9B2 73B3
OUT
9B2 73B3
OUT
9C8 73B3
OUT
9B2 62C7 73B3
MCP CPU Interface
5%
1/16W
MF-LF
402
OUT
OUT
7D7 13B7 21D3 22C8
NO STUFF
1
SYNC_MASTER=T18_MLB
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
7
DRAWING NUMBER
D
APPLE INC.
8
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
9B2 12C7 73C3
4.7.0
OF
13
1
81
A
6
7
5
2
3
4
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
BGA
(2 OF 11)
BI
74D3 26A5
BI
74D3 26B7
D
BI
74D3 26A7
BI
74D3 26A7
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B7
BI
BI
74D3 26B7
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26C5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26C7
BI
74D3 26C2
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26C4
74D3 26C4
74D3 26C4
BI
BI
BI
74D3 26B4
BI
74D3 26B2
BI
74D3 26C4
BI
74D3 26C4
BI
74D3 26B2
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26B4
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C2
B
BI
74D3 26B5
74D3 26B5
C
BI
74D3 26A7
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C4
BI
74D3 26C4
BI
74D3 26C4
BI
74D3 26D2
BI
74D3 26D2
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26D4
BI
74D3 26D4
BI
74C3 26A7
OUT
74C3 26B5
OUT
74C3 26B7
OUT
74C3 26B5
OUT
74C3 26C2
OUT
74C3 26B4
OUT
74C3 26C2
OUT
74D3 26C4
OUT
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
(3 OF 11)
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MEMORY PARTITION 0
74D3 26A5
1
OMIT
U1400
MRAS0#
MCAS0#
MWE0#
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
AV17
AP17
AR17
BI
26A5 74C3
74B3 27B5
BI
BI
26A5 74C3
74B3 27A5
BI
BI
26B7 74C3
74B3 27A7
BI
26B7 74C3
74B3 27A7
BI
BI
26B5 74C3
74B3 27B5
BI
BI
26B5 74C3
74B3 27A7
BI
BI
26B7 74C3
74B3 27A5
BI
BI
26B7 74C3
74B3 27B7
BI
BI
26C4 74C3
74B3 27B7
BI
BI
26C4 74C3
74B3 27B7
BI
26B2 74C3
74B3 27B7
BI
BI
26C2 74C3
74B3 27B5
BI
BI
26C4 74C3
74B3 27B5
BI
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
AP23
AP19
AW17
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19
26C4 74C3
74B3 27B5
BI
26C2 74C3
74B3 27B7
BI
BI
26D2 74C3
74B3 27B5
BI
74B3 27B7
BI
74B3 27B7
BI
74B3 27B7
BI
74B3 27B5
BI
74B3 27B5
BI
OUT
74B3 27B5
BI
OUT
26C7 74D3
74B3 27B7
BI
OUT
26C7 74D3
74B3 27B5
BI
AV33
MCLK0A_1_P
MCLK0A_1_N
BA24
MCLK0A_0_P
MCLK0A_0_N
BB20
MCS0A_1#
MCS0A_0#
AY24
BC20
AR18
BI
74B3 27C7
BI
74B3 27C5
BI
74B3 27B7
BI
26C7 74D3
74B3 27B5
BI
OUT
26C5 74D3
74B3 27B5
BI
OUT
74B3 27B7
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C7 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C5 74D3
BI
74B3 27B2
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27B2
BI
74B3 27B4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C4
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C2
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27D2
BI
OUT
26C5 74D3
74B3 27D2
BI
OUT
26C5 74D3
74B3 27C4
BI
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
74B3 27C2
OUT
26C7 74D3
BI
OUT
26C7 74D3
OUT
26C7 74D3
74B3 27A7
OUT
OUT
26C5 74D3
74B3 27B5
OUT
74B3 27D4
BI
74B3 27D4
BI
74B3 27B7
MODT0A_1
MODT0A_0
MEM_A_ODT<1>
MEM_A_ODT<0>
AP15
AV15
MEM_A_CKE<1>
MEM_A_CKE<0>
AU23
AT23
OUT
OUT
26C5 74D3
74B3 27B5
OUT
OUT
26C5 74D3
74B3 27B4
OUT
74B3 27C2
MCKE0A_1
MCKE0A_0
BI
74B3 27B4
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
AT15
BI
74B3 27B5
OUT
TP_MEM_A_CLK2P
TP_MEM_A_CLK2N
AW33
BI
26C5 74D3
MEMORY
CONTROL
0A
MCLK0A_2_P
MCLK0A_2_N
BI
BI
74B3 27B7
MBA0_2
MBA0_1
MBA0_0
BI
OUT
OUT
26D5 74D3
74B3 27C2
OUT
OUT
26D7 74D3
74B3 27C4
OUT
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEMORY PARTITION 1
8
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43
MRAS1#
MCAS1#
MWE1#
AW16
MBA1_2
MBA1_1
MBA1_0
BB29
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
BA29
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
BA15
BA16
BB17
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18
27A5 74A3
BI
27B7 74A3
BI
27B7 74A3
BI
27B5 74A3
BI
27B5 74A3
BI
27B7 74A3
BI
27B7 74A3
BI
27B2 74A3
BI
27C2 74A3
BI
27C4 74A3
BI
27C4 74A3
BI
27C4 74A3
BI
27C4 74A3
BI
27C2 74A3
BI
27D2 74A3
27C5 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
27C5 74C3
OUT
27C5 74C3
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
27C7 74C3
OUT
27C7 74C3
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
27C7 74B3
OUT
27C5 74B3
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
27C5 74B3
OUT
27C5 74B3
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
27D5 74B3
OUT
27D7 74B3
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
BA14
27A5 74A3
BI
OUT
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
BB18
BI
D
C
MEMORY
CONTROL
1A
MCLK1A_2_P
MCLK1A_2_N
BA42
MCLK1A_1_P
MCLK1A_1_N
BB22
MCLK1A_0_P
MCLK1A_0_N
BA19
MCS1A_1#
MCS1A_0#
BB14
MODT1A_1
MODT1A_0
BB13
MCKE1A_1
MCKE1A_0
AY31
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
BB42
BA22
AY19
BB16
AY15
BB30
B
MCP Memory Interface
A
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
14
1
81
A
8
6
7
3
4
5
2
1
OMIT
U1400
MCP79-TOPO-B
BGA
22C8 15C3 7B6
22B2
=PP1V8R1V5_S0_MCP_MEM
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
BB24
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
BA21
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
AU17
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
AN17
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
AV23
BC24
BB21
AR15
AN15
AN25
MCLK0B_1_P
MCLK0B_1_N
MCLK0B_0_P
MCLK0B_0_N
MCS0B_0#
MCS0B_1#
MODT0B_0
MODT0B_1
MCKE0B_0
MCKE0B_1
R1610 1
40.2
74A3
17
12
19
39
mA
mA
mA
mA
T27
U28
U27
T28
+V_PLL_XREF_XS
+V_PLL_DP
+V_PLL_CORE
+V_VPLL
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
AN41
AM41
MCLK1B_1_P
MCLK1B_1_N
AY23
MCLK1B_0_P
MCLK1B_0_N
BA20
MCS1B_0#
MCS1B_1#
BC16
MODT1B_0
MODT1B_1
AY16
MCKE1B_0
MCKE1B_1
BA30
MRESET0#
AY32
BB41
BA23
AY20
BA13
BC13
BA31
TP_MEM_B_CLK5P
TP_MEM_B_CLK5N
D
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
MCP_MEM_RESET_L
OUT
28C6
TP or NC for DDR2.
MEM_COMP_VDD
MEM_COMP_GND
R1611 1
40.2
1%
1/16W
MF-LF
402
BA41
2
74A3
C
MCLK1B_2_P
MCLK1B_2_N
PP1V05_S0_MCP_PLL_CORE
87 mA (A01)
1%
1/16W
MF-LF
402
AU34
MCLK0B_2_P
MCLK0B_2_N
MEMORY CONTROL 1B
D
AU33
MEMORY CONTROL 0B
(4 OF 11)
TP_MEM_A_CLK5P
TP_MEM_A_CLK5N
AA22
AP12
2
G30
P10
T10
T6
V10
V34
W5
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
AR36
AU10
F28
BC21
AY9
B
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
A
T24
T26
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
=PP1V8R1V5_S0_MCP_MEM
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
AM17
7B6 15C7 22C8
4771 mA (A01, DDR3)
AM19
C
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
B
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31
T33
T34
T35
T37
T38
T7
MCP Memory Misc
T9
U18
SYNC_MASTER=T18_MLB
U20
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
U22
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
15
1
81
A
8
6
7
3
4
5
2
1
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
D
IN
8D6
IN
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
8D6
C
IN
8D6
8D6
8D6
=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>
IN
IN
IN
29D7
IN
35D3
IN
35D3 8C6
IN
8D6
IN
8D6
IN
57A4
B
8C4
OUT
30B7
OUT
E7
D7
C7
E6
F6
E5
F5
E4
E3
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4
PEG_PRSNT_L
IN
29D7
F7
C9
Int PU
D5
PEB_CLKREQ#/GPIO_49
D9
PEB_PRSNT# Int PU
FW_CLKREQ_L
PCIE_FW_PRSNT_L
E8
PEC_CLKREQ#/GPIO_50
Int PU
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>
C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
PEG_CLK100M_P
PEG_CLK100M_N
OUT
8D6
OUT
8D6
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
OUT
29C5 75D3
OUT
29C5 75D3
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
OUT
34C2
OUT
34C2
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
OUT
8D6
OUT
8C6
PE0_REFCLK_P
PE0_REFCLK_N
E11
PE1_REFCLK_P
PE1_REFCLK_N
G11
PE2_REFCLK_P
PE2_REFCLK_N
J11
PE3_REFCLK_P
PE3_REFCLK_N
G13
PE4_REFCLK_P
PE4_REFCLK_N
J13
PE5_REFCLK_P
PE5_REFCLK_N
L14
PE6_REFCLK_P
PE6_REFCLK_N
N14
M14
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N
D11
F11
C
B10
PED_PRSNT# Int PU
TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L
L16
PEE_CLKREQ#/GPIO_16
PEE_PRSNT#/GPIO_46
AUD_IP_PERIPHERAL_DET
GMUX_JTAG_TCK_L
M16
M17
M19
PEG_CLKREQ#/GPIO_18
PEG_PRSNT#/GPIO_48
F17
Int PU
PE_WAKE# Int PU (S5)
PEX_RST0#
K11
PCIE_RESET_L
OUT
24C4
PE1_RX0_P
PE1_RX0_N
PE1_TX0_P
PE1_TX0_N
D8
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
OUT
29C5 75D3
OUT
29C5 75D3
PE1_RX1_P
PE1_RX1_N
PE1_TX1_P
PE1_TX1_N
B8
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
OUT
34C1 75D3
OUT
34C1 75D3
PE1_RX2_P
PE1_RX2_N
PE1_TX2_P
PE1_TX2_N
A7
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
OUT
8D6
OUT
8D6
PE1_RX3_P
PE1_RX3_N
PE1_TX3_P
PE1_TX3_N
B6
L18
M18
75D3 29C7 6D5
IN
K9
75D3 29C7 6D5
IN
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
75D3 34C1
IN
H9
75D3 34C1
IN
PCIE_FW_D2R_P
PCIE_FW_D2R_N
8D6
IN
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
F9
TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN
H7
J9
G9
E9
G7
Int PU
Int PU
Int PU
F13
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
H13
Int PU
PEF_CLKREQ#/GPIO_17
PEF_PRSNT#/GPIO_47
Int PU
J10
D
PED_CLKREQ#/GPIO_51
PCIE_WAKE_L
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N
K14
Int PU
C8
A8
B7
C6
=PP1V05_S0_MCP_PEX_AVDD0
57 mA (A01, DVDD0 & 1)
T17
W19
U17
V19
W16
W17
W18
U16
+DVDD0_PEX1
+DVDD0_PEX2
+DVDD0_PEX3
+DVDD0_PEX4
+DVDD0_PEX5
+DVDD0_PEX6
+DVDD0_PEX7
+DVDD0_PEX8
=PP1V05_S0_MCP_PEX_DVDD1
U19
+DVDD1_PEX1
+DVDD1_PEX2
T16
+V_PLL_PEX
T19
PP1V05_S0_MCP_PLL_PEX
84 mA (A01)
MCP_PEX_CLK_COMP
A11
PEX_CLK_COMP
+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13
7A6
206 mA (A01, AVDD0 & 1)
Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12
=PP1V05_S0_MCP_PEX_AVDD1
+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3
B
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
=PP1V05_S0_MCP_PEX_DVDD0
75C3
8D6
OUT
M15
IN
22C2
8D6
OUT
EXCARD_CLKREQ_L
PCIE_EXCARD_PRSNT_L
29C7 6D5
7A6
8D6
OUT
PEC_PRSNT# Int PU
IN
7A6
OUT
C10
CARDREADER_RESET
GMUX_JTAG_TDO
IN
Int PU
PE0_PRSNT_16#
MINI_CLKREQ_L
PCIE_MINI_PRSNT_L
8C4
8D6
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
PCI EXPRESS
8D6
7A6
M13
N13
MCP PCIe Interfaces
P13
NO STUFF
A
1
SYNC_MASTER=T18_MLB
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
2.37K
2
1%
1/16W
MF-LF
402
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PLACEMENT_NOTE=Place within 12.7mm of U1400
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
16
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
MCP79-TOPO-B
BGA
=PP3V3_ENET_MCP_RMGT
(6 OF 11)
22B6 22A5 17D3 7B5
=PP3V3_ENET_MCP_RMGT
77D3 31C1
IN
77D3 31C1
IN
77D3 31C1
IN
77D3 31C1
IN
77D3 31C1
IN
77D3 31B1
IN
8C4
IN
8C4
IN
8C4
IN
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
B23
E24
A24
49.9
A23
RGMII_RXC/MII_RXCLK
C22
RGMII_RXCTL/MII_RXDV
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
F23
MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK
B26
B22
J22
5 mA (A01)
K24
+V_DUAL_RMGT1
+V_DUAL_RMGT2
U23
MII_VREF
E28
MCP_MII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
B24
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
RGMII_TXC/MII_TXCLK
D24
RGMII_TXCTL/MII_TXEN
C26
RGMII_MDC
RGMII_MDIO
D21
RGMII_PWRDWN/GPIO_37
=PP1V05_ENET_MCP_RMGT
RGMII_INTR/GPIO_35
T23
+V_DUAL_MACPLL
C27
MII_COMP_VDD
MII_COMP_GND
2
MCP_MII_COMP_VDD
77D3 MCP_MII_COMP_GND
B27
8D4
OUT
8D4
OUT
1
47K
42C3
8D4
IN
8D4
OUT
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
31C6 77D3
ENET_CLK125M_TXCLK
ENET_TX_CTRL
OUT
31C8 77D3
OUT
31B6 77C3
OUT
31B6 77D3
C21
ENET_MDC
ENET_MDIO
G23
TP_ENET_PWRDWN_L
BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
MII_RESET#
J23
ENET_RESET_L
E36
A35
TV_DAC_RSET
TV_DAC_VREF
MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
C38
D38
XTALIN_TV
XTALOUT_TV
TV
C
Y
Comp
K32
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
B39
RGB_DAC_HSYNC
RGB_DAC_VSYNC
Component
Pr
TV_DAC_RED
Y
TV_DAC_GREEN
Pb
TV_DAC_BLUE
A40
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45
D36
IFPA_TXC_P
IFPA_TXC_N
B35
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
B32
IFPB_TXC_P
IFPB_TXC_N
L31
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
J29
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
C30
DDC_CLK3
DDC_DATA3
D31
IFPAB_RSET
IFPAB_VPROBE
E32
/
/
/
/
103 mA
103 mA
J32
BI
32A5 77D3
OUT
31B7 77C3
206 mA (A01)
1
MII
0
=PP3V3_S0_MCP_GPIO
R1860 1
23D2
ENET_TXD<0>
RGMII
NOTE: All Apple products set strap to
MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
31B6 77D3
OUT
Interface
1
100K
5%
1/16W
MF-LF
402
7C5 18D1 20A4
R1861
100K
2
2
5%
1/16W
MF-LF
402
MCP_DDC_CLK0
MCP_DDC_DATA0
A31
B40
C
RGB DAC Disable:
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
A39
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
A41
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
A36
B36
C36
C37
TV DAC Disable:
OUT
8D4
OUT
8D4
OUT
8D4
CRT_IG_HSYNC
CRT_IG_VSYNC
OUT
8D4
OUT
8D4
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
OUT
68B3 75B3
OUT
68B3 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
8D4
OUT
8D4
OUT
8D4
OUT
8D4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
6C7 68C5
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
OUT
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
OUT
23C6 75B3
OUT
23C6 75B3
Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
2
LPCPLUS_GPIO
DP_IG_CA_DET
BI
69A5
Interface Mode
31C6 77D3
OUT
D25
B31
IN
72B7 71A7
OUT
72C8 72B7
OUT
68C8
OUT
69D3
OUT
69D3
OUT
69D3
69D3
OUT
OUT
69D3
OUT
69D3
OUT
69D3
OUT
75B3 69C7
OUT
OUT
8B4
IN
69D3
IN
G39
F40
D35
E35
G35
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
D43
F35
F33
G33
J33
H33
C43
(See below)
C31
F31
LCD_BKL_CTL/GPIO_57
LCD_BKL_ON/GPIO_59
LCD_PANEL_PWR/GPIO_58
HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
HDMI_TXD1_P/ML0_LANE1_P
HDMI_TXD1_N/ML0_LANE1_N
HDMI_TXD2_P/ML0_LANE0_P
HDMI_TXD2_N/ML0_LANE0_N
DP_AUX_CH0_P
DP_AUX_CH0_N
HPLUG_DET2/GPIO_22
HPLUG_DET3
=PP3V3R1V8_S0_MCP_IFP_VDD
190 mA (A01, 1.8V)
M27
M26
PP3V3_S0_MCP_VPLL
23C5
16 mA (A01)
23D7 7D7
75B3 23C7
GPIO_7/NFERR*/IGPU_GPIO_7
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD
23D7 7B6
75B3 23C7
GPIO_6/FERR*/IGPU_GPIO_6
B15
E37
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
OUT
69D3
75B3 69C7
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
(See below)
E16
=PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
MCP_HDMI_RSET
OUT
MCP_HDMI_VPROBE
OUT
8 mA
8 mA
M28
M29
+VDD_IFPA
+VDD_IFPB
+V_PLL_IFPAB
+V_PLL_HDMI
T25
+VDD_HDMI
J31
HDMI_RSET
HDMI_VPROBE
J30
FLAT PANEL
5%
1/16W
MF-LF
402
B
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
=PP3V3_S5_MCP_GPIO
R1820
OUT
C25
DDC_CLK0
DDC_DATA0
RGB ONLY
B38
RGB_DAC_RSET
RGB_DAC_VREF
C
19C1 7A3
31C6 77D3
31C6 77D3
+V_RGB_DAC
+V_TV_DAC
DACS
2
C39
22A4
OUT
PP3V3_S0_MCP_DAC
TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF
IN
OUT
C24
1
49.9
1%
1/16W
MF-LF
402
D
7A5 22D6
131 mA (A01)
V23
Network Interface Select
PP1V05_ENET_MCP_PLL_MAC
22A6
77D3
R1811
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
ENET_CLK125M_RXCLK
ENET_RX_CTRL
TP_ENET_INTR_L
R1810 1
1%
1/16W
MF-LF
402
C23
J24
+3.3V_DUAL_RMGT2
LAN
D
7B5 17D7 22A5 22B6
83 mA (A01)
+3.3V_DUAL_RMGT1
C35
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
A32
D32
C32
D33
C33
B34
C34
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
K31
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
H29
L29
K29
L30
K30
N30
M30
B30
E31
G31
1
BI
6C7 68C5
69D3
69D3
R1850
10K
GPIOs 57-59 (if LCD panel is used):
In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
A
BI
B
2
5%
1/16W
MF-LF
402
MCP Ethernet & Graphics
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
17
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
20A4 17C1 7C5
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
(7 OF 11)
35D6 35C7 35C4 35A4 18D2
57D3
D
OUT
OUT
18D2
IN
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
C
42D5 40C5
8C2
42D3 40C8
IN
IN
BI
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>
T2
V9
T3
U9
T4
AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7
PCI_REQ0#
PCI_REQ1#/FANRPM2
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
P2
N1
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
TP_PCI_TRDY_L
Y3
PCI_TRDY#
PM_CLKRUN_L
N3
N2
AD11
FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ
AE2
AE1
AE6
PCI_CLKRUN#/GPIO_42
LPC_DRQ1#/GPIO_19 Int PU
LPC_DRQ0#
Int PU
LPC_SERIRQ Int PU
18D4
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
U10
R4
U11
P3
AA3
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#
AA9
PCI_PME#/GPIO_30
Int PU (S5)
PCI_RESET0#
PCI_RESET1#
PCI_CLK0
PCI_CLK1
PCI_CLK2
TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L
R3
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI
76D3 18D2
PCI_REQ0_L
PCI_REQ1_L
FW_PWR_EN
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
U39
U4
U8
V16
B
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
A
Y24
Y25
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
8C4
OUT
8C4
OUT
18D2
35D6 35C7 35C4 35A4 18D7
18D7
AA11
W10
Y2
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L
T1
PM_LATRIGGER_L
OUT
12C6
R10
MEM_VTT_EN_R
TP_PCI_RESET1_L
OUT
24C4
Y4
AA10
Y1
AB9
AA7
R11
R6
R7
R8
R1989
8.2K
1
2
PCI_REQ0_L
PCI_REQ1_L
FW_PWR_EN
MCP_RS232_SIN_L
R1990
R1991
R1992
R1994
8.2K
8.2K
8.2K
8.2K
1
2
1
2
1
2
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
76C3
2
PCI_CLKIN
R9
76C3
PCI_CLK33M_MCP
LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
AD4
AE12
LPC_FRAME_R_L
LPC_PWRDWN_L
LPC_RESET0#
AE5
LPC_RESET_L
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AD3
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_CLK0
AE9
AD2
AD1
AD5
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
R1910
C
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to pin R8
R1960
22
1
LPC_FRAME_L
2
5%
R1950
R1951
R1952
R1953
22
22
22
22
1
2
1
2
1
2
1
2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
OUT
40C8 42D5 76C3
OUT
40C5 42D3
OUT
24D4 76C3
BI
40C8 42D5 76C3
BI
40C8 42D5 76C3
BI
40C8 42D3 76C3
BI
402
LPC_CLK33M_SMC_R
Y26
OUT
40C8 42D3 76C3
24B4 76C3
R1961
10K
Y27
AB18
2
H34
5%
1/16W
MF-LF
402
Strap for Boot ROM Selection (See HDA_SDOUT)
AB20
AB21
B
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
MCP PCI & LPC
AD28
AD33
SYNC_MASTER=T18_MLB
AD34
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
D
TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R
22
GND
U26
76D3 18D7
OUT
MCP_RS232_SOUT_L
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
AA6
1
U24
76D3 18D7
1
LPC
76D3 18D2
4.7.0
OF
18
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
75A3 37A2
75A3 37A2
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
OUT
OUT
75A3 37B2
IN
75A3 37B2
IN
SATA_HDD_D2R_N
SATA_HDD_D2R_P
AJ7
AJ6
AJ5
AJ4
SATA_A0_TX_P
SATA_A0_TX_N
USB0_P
USB0_N
USB1_P
USB1_N
SATA_A0_RX_N
SATA_A0_RX_P
D
USB2_P
USB2_N
OUT
75A3 37C3
OUT
75A3 37C3
75A3 37C3
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
IN
IN
AJ10
AJ9
AK9
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
TP_SATA_C_D2RN
TP_SATA_C_D2RP
AK2
AJ3
AJ2
AJ1
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
TP_SATA_D_D2RP
C
AJ11
AM4
AL3
AL4
AK3
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_E_D2RN
TP_SATA_E_D2RP
AN1
AM1
AM2
AM3
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
AP3
TP_SATA_F_D2RN
TP_SATA_F_D2RP
AN3
AP2
AN2
SATA_A1_TX_P
SATA_A1_TX_N
SATA_A1_RX_N
SATA_A1_RX_P
SATA_B1_TX_P
SATA_B1_TX_N
SATA_B1_RX_N
SATA_B1_RX_P
SATA_C0_TX_P
SATA_C0_TX_N
PP1V05_S0_MCP_PLL_SATA
22B2
AE16
AF19
AG17
AG19
B
SATA_C1_TX_P
SATA_C1_TX_N
SATA_C1_RX_N
SATA_C1_RX_P
SATA_LED#
+V_PLL_SATA
+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4
=PP1V05_S0_MCP_SATA_DVDD1
AH17
AH19
+DVDD1_SATA1
+DVDD1_SATA2
=PP1V05_S0_MCP_SATA_AVDD0
7A6
127 mA (A01, AVDD0 & 1)
AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13
AN14
AL14
AM13
AM14
75A3
1
MCP_SATA_TERMP
38A8 76C3
BI
8C6
BI
8C6
External D
USB_EXTD_P
USB_EXTD_N
BI
8C6
BI
8C6
USB_CAMERA_P
USB_CAMERA_N
BI
29B5 76C3
BI
29B5 76C3
USB_IR_P
USB_IR_N
BI
39D7 76B3
BI
39D7 76B3
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
BI
48B8 76B3
BI
48B8 76B3
Bluetooth
USB_BT_P
USB_BT_N
BI
29B5 76C3
BI
29B5 76C3
External B
USB_EXTB_P
USB_EXTB_N
BI
38A4 76B3
BI
38B4 76B3
ExpressCard
USB_EXCARD_P
USB_EXCARD_N
BI
8C6
BI
8C6
External C
USB_EXTC_P
USB_EXTC_N
BI
8C6
BI
8C6
D
F29
USB4_P
USB4_N
K27
USB5_P
USB5_N
J26
USB6_P
USB6_N
F27
G29
USB7_P
USB7_N
USB8_P
USB8_N
L27
J27
G27
D27
E27
K25
L25
USB9_P
USB9_N
H25
USB10_P
USB10_N
F25
USB11_P
USB11_N
K23
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
L21
+V_PLL_USB
L28
J25
=PP3V3_S5_MCP_GPIO
1
8.2K
TP_USB_10P
TP_USB_10N
G25
2
USB_CARDREADER_P
USB_CARDREADER_N
L23
BI
30C7 76B3
BI
30C7 76B3
1
R2051
R2050
1
R2053
8.2K
5%
1/16W
MF-LF
402
2
R2052
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
C
1
2
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
K21
J21
H21
PP3V3_S0_MCP_PLL_USB
7A3 17C7
IN
38C7
IN
38C7
IN
IN
41C4
22B4
19 mA (A01)
A27
76B3
MCP_USB_RBIAS_GND
AE3
+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4
SATA_TERMP
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
AD35
AD37
AD38
806
1%
1/16W
MF-LF
402
2
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
B
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
R2010
2.49K
2
+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9
=PP1V05_S0_MCP_SATA_AVDD1
7A6
B28
38A8 76C3
BI
R2060 1
E12
AG16
7A6
A28
BI
AirPort (PCIe Mini-Card)
USB_MINI_P
USB_MINI_N
SATA_C0_RX_N
SATA_C0_RX_P
84 mA (A01)
7A6 =PP1V05_S0_MCP_SATA_DVDD0
43 mA (A01, DVDD0 & 1)
D28
USB3_P
USB3_N
USB_RBIAS_GND
TP_MCP_SATALED_L
C28
External A
USB_EXTA_P
USB_EXTA_N
IR
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
D29
Camera
SATA
USB
75A3 37C3
C29
1%
1/16W
MF-LF
402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
MCP SATA & USB
A
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
19
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
=PP3V3R1V5_S0_MCP_HDA
MCP79-TOPO-B
7C5 20D8 22A8
7 mA (A01)
BGA
(9 OF 11)
HDA
+V_DUAL_HDA1
+V_DUAL_HDA2
D
76A3 52C7
HDA_SDIN0
IN
G15
TP_MLB_RAM_SIZE
TP_MLB_RAM_VENDOR
=PP3V3R1V5_S0_MCP_HDA
22A8 20D3 7C5
J14
J15
(MXM_OK for MXM systems)
1
HDA_SDATA_IN0
Int PD
HDA_SDATA_OUT
HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
Int PD
HDA_BITCLK
OUT
IN
R2121
49.9K
2
2
MCP_HDA_PULLDN_COMP
A15
76B3 20A7
1%
1/16W
MF-LF
402
40C5
IN
40B8
IN
HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
Int PD
HDA_RESET*
20 mA
17 mA
=SPI_CS1_R_L_USE_MLB
SMC_ADAPTER_EN
TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
AE18
AE17
K15
L15
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA
K17
SLP_S3*
SLP_RMGT*
SLP_S5*
G17
THERM_DIODE_P
THERM_DIODE_N
B11
+V_PLL_NV_H
+V_PLL_SP_SPREF
L24
GPIO_1/PWRDN_OK/SPI_CS1
L26
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
C18
A20GATE
Int PU
KBRDRSTIN* Int PU
SIO_PME*
Int PU (S5)
EXT_SMI/GPIO_32* Int PU (S5)
B20
INTRUDER*
K13
L13
C19
40B8
IN
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR
40C8
IN
C16
24A1
IN
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
D16
PWRBTN* Int PU (S5)
RSTBTN* Int PU
RTC_RST_L
C20
RTC_RST*
76A3 20A7
76B3 20A7
H17
M21
SPKR
C13
MCP_SPKR
M25
M24
LID* Int PU (S5)
LLB* Int PU (S5)
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT*/GPIO_64
L19
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
(MGPIO2)
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62
B12
C12
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
(MGPIO3)
CPUVDD_EN
D17
MCP_CPUVDD_EN
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
K19
G21
F21
M23
A12
D12
E20
MCP_CPU_VLD
C17
CPU_VLD
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
E19
JTAG_TDI Int PU
JTAG_TDO
JTAG_TMS Int PU
JTAG_TRST*
JTAG_TCK
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
C14
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
A16
XTALIN
XTALOUT
SUS_CLK/GPIO_34
BUF_SIO_CLK
B18
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
A19
TEST_MODE_EN
PKG_TEST
K22
IN
OUT
12C3
IN
12C3
IN
12B6
IN
IN
OUT
IN
OUT
D20
F19
J19
J18
G19
B16
B19
1
10K
5%
1/16W
MF-LF
402
XTALIN_RTC
XTALOUT_RTC
D13
C15
B14
52C7 76B3
2
2
2
20D4 76A3
2
R2140
1
R2141
1
1
R2142
OUT
6C3 32B7 35A5 40C5 66D5 70D8
OUT
8D1
OUT
6C3 40C5 41A2 66C8
OUT
46B5 80D3
OUT
46B5 80D3
OUT
20A3 63D8
OUT
20A3 63C8
OUT
20A3 63C8
OUT
BI
OUT
BI
OUT
IN
OUT
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
20D4 76B3
MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L
20D4 76A3
20D4 76B3
ARB_DETECT
=PP3V3_S0_MCP
1
C2173
10PF
5%
50V
CERM
402
5%
50V
CERM
402
2
0
1
1
NOTE: MCP79 rev A01 does not support
SPI1 option. Rev B01 will.
7C5 21B3 22B8
1
R2180
5%
1/16W
MF-LF
402
IN
12B6 43D8 76B3
Frequency
41C5
R2181
10K
12B6 43D8 76B3
43B8 76B3
2
43B8 76B3
5%
1/16W
MF-LF
402
20A3 29D5 32C7
1
14.31818 MHz
0
SPI Frequency Select
Connects to SMC for
automatic recovery.
Frequency
37D6
20A4 41D4
24A8
42B7 76A3
OUT
42A5 42C8 76A3
IN
42A5 42B7 76A3
OUT
42A5 42C7 76A3
OUT
24B4 76A3
2
SPI_DO
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
NOTE: Straps not provided on this page.
B
1
R2163
R2190
1K
5%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
7C5 17C1 18D1
2
7D3
R2154
100K
1
5%
1/16W
MF-LF
402
AP_PWR_EN
20C3
20C3 29D5 32C7
20C3 57D3
MCP HDA & MISC
20B3 26A5 27A5 40B8
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
20B3 41D4
20B3
20C3 63D8
SYNC_MASTER=T18_MLB
1
R2147
R2155
1
R2156
100K
22K
22K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
1
NOTICE OF PROPRIETARY PROPERTY
20C3 63C8
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
R2157
22K
2
SYNC_DATE=06/26/2008
20C3 63C8
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
402
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
HDA_SYNC
24 MHz
USER mode: Normal
SAFE mode: For ROMSIP
recovery
20A4 26A5 27A5 40B8
OUT
C
BUF_SIO_CLK Frequency
10K
2
10PF
1
SPI1
20A4
1
1
SPI0
NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.
1
OUT
R2143
10K
2
1
R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
20A4 57D3
=PP3V3_S3_MCP_GPIO
1
0
MCP_TEST_MODE_EN
5%
1/16W
MF-LF
402
10PF
2
OUT
0
PCI
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
10K
For EMI Reduction on HDA interface
C2171
HDA_SYNC
LPC_FRAME#
0
L22
100K
HDA Output Caps
1
52C7 76A3
OUT
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
AE7
R2151
=PP3V3_S0_MCP_GPIO
2
OUT
HDA_SDOUT
LPC
BOOT_MODE_USER
IN
IN
R2150 1
5%
50V
CERM
402
HDA_RST_L
I/F
BOOT_MODE_SAFE
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
M20
1
C2172
2
5%
1/16W
MF-LF
402
IN
L20
IN
24C8
5%
50V
CERM
402
52C7 76B3
20A4
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
24A5
24C8
10PF
22
2
MCP_THMDIODE_P
MCP_THMDIODE_N
C11
24A5
24B8
C2170
22
OUT
R2172
1
1
52C7 76A3
BIOS Boot Select
HDA_BIT_CLK
HDA_RST_R_L
HDA_SYNC_R
OUT
5%
1/16W
MF-LF
402
2
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
J17
PWRGD_SB
PS_PWRGD
24C8
A
22
MCP_GPIO_4
AUD_I2C_INT_L
L17
PM_RSMRST_L
MCP_PS_PWRGD
12C3
1
1
HDA_SDOUT
2
73B3 62D8
12C3
B
HDA_PULLDN_COMP
TP_MCP_LID_L
PM_BATLOW_L
40D8
HDA_RST_R_L
HDA_SYNC_R
HDA_BIT_CLK_R
2
PP1V05_S0_MCP_PLL_NV
SM_INTRUDER_L
HDA_SDOUT_R
HDA_BIT_CLK_R
22
1
5%
1/16W
MF-LF
402
MISC
42B8
1%
1/16W
MF-LF
402
HDA_SDOUT_R
5%
1/16W
MF-LF
402
41B2 40D5 35B5 32B7
49.9K
E15
D
R2170
76A3 20A7
R2173
PP3V3_G3_RTC
C
5%
1/16W
MF-LF
402
R2171
HDA_SYNC
37 mA (A01)
1
8.2K
1%
1/16W
MF-LF
402
22A2
R2120 1
F15
R2160
R2110
76A3
24D4 21A5 6C3
1
K16
2
49.9
2
J16
4.7.0
OF
20
1
81
A
8
7
6
MCP79-TOPO-B
AH37
AH38
AJ39
D
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
C
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
B
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
A
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343
22D8 7C6
BGA
(10 OF 11)
=PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
AV40
BA1
AA25
AC23
BA4
U25
AW31
AH12
AY6
AG10
L35
AG5
BC33
Y21
BC37
Y23
BC41
AA16
AY14
AA26
BC5
AA27
C2
AA28
D10
AC16
D14
AC17
D15
AC18
D18
AC19
D19
AC20
D22
AC21
D23
AA17
D26
AC24
D30
AC25
D37
AC26
D6
AC27
E13
AC28
E17
AD21
E21
AD23
E25
W27
E29
V25
E33
AA18
F12
AE19
F16
AE21
F32
AE23
F8
AE25
G10
AE26
G12
AE27
G14
AE28
G16
AF10
BC12
AF11
G22
AA19
G24
AF2
AW20
AF21
G34
AF23
G4
AF25
G43
AF3
G6
AF4
G8
AF7
H11
AH23
H15
AF9
AW35
AA20
H23
AG11
AN8
AG12
G40
AG21
J12
AG23
J8
AG25
K10
AG3
K12
AG4
K18
AA21
K26
AG6
K37
AG7
K4
AG8
K40
AG9
K8
AH1
AU1
AH10
L40
AH11
L43
W26
L5
AH2
M10
AA23
M34
W28
M35
AH25
M37
AH21
Y28
AH3
Y33
AH4
Y34
AH5
Y35
AH6
Y37
AH7
Y38
AH9
AB17
AA24
AB16
W21
AN26
W23
AD7
W25
M11
AF12
+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81
POWER
AH34
GND
BGA
(11 OF 11)
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
1
U1400
MCP79-TOPO-B
AH33
2
OMIT
OMIT
U1400
AH26
3
4
5
=PP1V05_S0_MCP_FSB
+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
24D4 20C8 6C3
AY13
PP3V3_G3_RTC
10 uA (G3)
80 uA (S0)
P11
A20
+VBAT
7D7 13A2 13B7 22C8
1182 mA (A01)
AC32
E40
J36
N32
T32
D
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
C
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
+VTT_CPUCLK
AG32
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8
AD10
43 mA
=PP3V3_S0_MCP
7C5 20C2 22B8
450 mA (A01)
B
AE8
AB10
AD9
Y10
AB11
AA8
Y9
=PP3V3_S5_MCP
+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4
G18
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
G26
+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3
T21
16 mA
7A3 22B8
266 mA (A01)
H19
J20
K20
250 mA
H27
J28
K28
=PP1V05_S5_MCP_VDD_AUXC
AA4
AB19
1139 mA
R32
7B3 22D8
105 mA (A01)
MCP Power & Ground
U21
V21
SYNC_MASTER=T18_MLB
Y6
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
T11
V11
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
Y11
AH16
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
T22
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
21
1
81
A
8
MCP Core Power
21D5 7C6
6
7
2
3
4
5
1
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
(No IG vs. EG data)
C2500
20%
4V
X5R-1
402
D
C2501
1
4.7UF
C2502
1
4.7UF
20%
4V
X5R-1
402
2
C2503
1
4.7UF
20%
4V
X5R-1
402
2
1
1
4.7UF
20%
4V
X5R-1
402
2
C2504
1
1UF
2
2
2
MCP PCIE (DVDD) Power
7D7 7A8
C2505
1
1UF
10%
10V
X5R
402-1
C2506
1
1UF
10%
10V
X5R
402-1
2
C2507
1
1UF
10%
10V
X5R
402-1
2
C2508
1
0.1UF
10%
10V
X5R
402-1
2
C2509
1
0.1UF
20%
10V
CERM
402
2
20%
10V
CERM
402
C2510
1
0.1UF
2
C2511
1
0.1UF
20%
10V
CERM
402
2
C2512
1
20%
10V
CERM
402
2
0.1UF
20%
10V
CERM
402
2
C2513
0.1UF
20%
10V
CERM
402
MCP SATA (DVDD) Power
=PP1V05_S0_MCP_PEX_DVDD
57 mA (A01)
7D7
43 mA (A01)
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
C2515
1
20%
4V
X5R-1
402
2
2
4.7UF
C2516
1
1UF
C2517
1
10%
10V
X5R
402-1
2
1UF
10%
10V
X5R
402-1
2
C2518
1
333 mA (A01)
20%
10V
CERM
402
2
0.1uF
C2519
C2520
0.1uF
1
2
2
4.7UF
20%
10V
CERM
402
20%
4V
X5R-1
402
MCP 1.05V AUX Power
21A3 7B3
1
1
2
C2521
1
20%
10V
CERM
402
2
0.1uF
17D3 7A5
105 mA (A01)
C2570
1
20%
6.3V
CERM
402-LF
C2525
0.1uF
2
MCP FSB (VTT) Power
21D3 13B7 13A2 7D7
C2526
C2528
0.1uF
20%
10V
CERM
402
1
2
2
4.7UF
20%
10V
CERM
402
2
1
20%
4V
X5R-1
402
C2529
20%
10V
CERM
402
2
0.1uF
C2575
20%
6.3V
CERM
402-LF
1
1
2
C2531
1
2.2UF
20%
6.3V
CERM
402-LF
2
C2532
1
2.2UF
20%
6.3V
CERM
402-LF
2
20%
6.3V
CERM
402-LF
C2533
1
2.2UF
2
C2534
1
2.2UF
20%
6.3V
CERM
402-LF
2
C2535
1
2.2UF
20%
6.3V
CERM
402-LF
2
20%
6.3V
CERM
402-LF
C2536
2
1
20%
6.3V
X5R
603
2
C2540
1
1
4.7UF
20%
4V
X5R-1
402
C2541
1
0.1UF
2
2
C2542
1
0.1UF
20%
10V
CERM
402
2
C2543
1
0.1UF
20%
10V
CERM
402
2
C2544
1
0.1UF
20%
10V
CERM
402
2
C2545
1
0.1UF
20%
10V
CERM
402
2
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)
C2546
1
0.1UF
20%
10V
CERM
402
2
C2547
1
0.1UF
20%
10V
CERM
402
2
C2548
1
0.1UF
20%
10V
CERM
402
2
1
1
2.2UF
2
B
=PP3V3_S5_MCP
C2551
1
2.2UF
20%
6.3V
CERM
402-LF
1
2.2UF
20%
6.3V
CERM
402-LF
2
C2552
2
20%
6.3V
CERM
402-LF
C2553
1
2.2UF
2
2
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
MCP 3.3V Ethernet Power
22A5 17D7 17D3 7B5
2
1
1
2
2
13A6
270 mA (A01)
C
C2581
0.1UF
20%
10V
CERM
402
=PP3V3_ENET_MCP_RMGT
1
2
20%
10V
CERM
402
PP1V05_S0_MCP_PLL_SATA
C2584
1
1
20%
4V
X5R-1
402
2
2
4.7UF
20%
6.3V
CERM
402-LF
C2585
0.1UF
20%
10V
CERM
402
L2586
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_CORE
C2564
C2586
1
1
20%
4V
X5R-1
402
2
2
4.7UF
20%
6.3V
CERM
402-LF
15C6
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
87 mA (A01)
C2587
0.1UF
20%
10V
CERM
402
L2588
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_NV
C2562
C2588
2.2UF
22B6 17D7 17D3 7B5
1
1
4.7UF
MCP79 Ethernet VRef
20%
6.3V
CERM
402-LF
20%
4V
X5R-1
402
20C7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
2
19B6
84 mA (A01)
B
2.2UF
20%
6.3V
CERM
402-LF
C2583
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
C2560
16A6
84 mA (A01)
0.1UF
0402
C2555
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
1
C2589
1
20%
10V
CERM
402
2
0.1UF
2
2
37 mA (A01)
C2590
0.1UF
20%
10V
CERM
402
=PP3V3_ENET_MCP_RMGT
R2591 1
MCP Standard Decoupling
1.47K
A
1%
1/16W
MF-LF
402
L2595
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
20%
6.3V
CERM
402-LF
L2584
7 mA (A01)
7B5
2.2UF
127 mA (A01)
PP1V05_S0_MCP_PLL_PEX
30-OHM-1.7A
19 mA (A01)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
2.2UF
=PP3V3R1V5_S0_MCP_HDA
2
20%
4V
X5R-1
402
1
83 mA (A01)
1
20D8 20D3 7C5
2
4.7UF
2.2UF
20%
6.3V
CERM
402-LF
266 mA (A01)
MCP 3.3V/1.5V HDA Power
1
C2582
20%
10V
CERM
402
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
0402
C2550
C2549
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
19C3
L2555
30-OHM-1.7A
19 mA (A01)
1
21B3 7A3
1
20%
4V
X5R-1
402
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0.1UF
20%
10V
CERM
402
2
=PP3V3_S0_MCP_PLL_UF
7C5
450 mA (A01)
MCP 3.3V AUX/USB Power
C2574
L2582
1
0402
=PP3V3_S0_MCP
2
20%
6.3V
CERM
402-LF
C2580
30-OHM-1.7A
=PP1V8R1V5_S0_MCP_MEM
MCP 3.3V Power
20%
6.3V
CERM
402-LF
2.2UF
4.7UF
10UF
20%
6.3V
CERM
402-LF
4771 mA (A01, DDR3)
21B3 20C2 7C5
C2573
2.2UF
PP1V05_S0_MCP_PLL_FSB
C2592
2.2UF
MCP Memory Power
15C7 15C3 7B6
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
2.2UF
20%
6.3V
CERM
402-LF
1
PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
C2595
1
1
4.7UF
20%
4V
X5R-1
402
MCP_MII_VREF
2
OUT
17D3
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
5 mA (A01)
C2596
R2590 1
1
1%
1/16W
MF-LF
402 2
2
1.47K
20%
10V
CERM
402
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
2
17C6
0.1UF
2
SYNC_MASTER=T18_MLB
C2591
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0.1UF
II NOT TO REPRODUCE OR COPY IT
20%
10V
CERM
402
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
206 mA (A01)
C2576
2
30-OHM-1.7A
=PP1V05_S0_MCP_PLL_UF
562 mA (A01)
C2530
C2572
2.2UF
2
1
L2580
65B1 7B8
1
1
2.2UF
1182 mA (A01)
C
20%
6.3V
CERM
402-LF
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
1
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
2.2UF
2
0603
1
C2571
1
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
PP1V05_S0_MCP_SATA_AVDD
7A8
L2575
30-OHM-5A
=PP1V05_ENET_MCP_RMGT
131 mA (A01)
1
1
2.2UF
MCP 1.05V RMGT Power
=PP1V05_S5_MCP_VDD_AUXC
7A8
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
0603
1
D
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
PP1V05_S0_MCP_PEX_AVDD
L2570
=PP1V05_S0_MCP_SATA_DVDD
7D7 7A8
4.7.0
OF
22
1
81
A
8
6
7
5
2
3
4
1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
17B6 7B6
NO STUFF
7C5
190 mA (A01, 1.8V)
30-OHM-1.7A
=PP3V3_S0_MCP_DAC_UF
206 mA (A01)
1
1
C2610
2
D
17A6 7D7
NO STUFF
0402
2.2UF
2
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
PP3V3_S0_MCP_DAC
L2650
=PP3V3R1V8_S0_MCP_IFP_VDD
1
20%
6.3V
CERM
402-LF
C2650
2.2UF
2
20%
6.3V
CERM
402-LF
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
17C3
206 mA (A01)
1
R2651
0
5%
1/16W
MF-LF
D
2 402
=PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
C2615
1
1
2
2
4.7UF
20%
4V
X5R-1
402
75B3 17A6
75B3 17A6
0.1UF
20%
10V
CERM
402
MCP_HDMI_RSET
MCP_HDMI_VPROBE
C
75B3 17A3
75B3 17A3
NO STUFF
C2620
1
1
20%
10V
CERM
402
=PP3V3_S0_MCP_VPLL_UF
16 mA (A01)
2
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
2
NO STUFF
NO STUFF
R2620
C2630
1K
0.1UF
7C5
C2616
1%
1/16W
MF-LF
402
1
1
20%
10V
CERM
402
2
C
R2630
1K
0.1UF
2
1%
1/16W
MF-LF
402
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640
Apple: ???
30-OHM-1.7A
PP3V3_S0_MCP_VPLL
17B6
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
0402
C2640
1
1
20%
6.3V
CERM
603
2
2
4.7UF
16 mA (A01)
C2641
0.1uF
20%
10V
CERM
402
B
B
MCP Graphics Support
A
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
SYNC FROM T18
REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672
NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)
CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC
REMOVE HDCP ROMS
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
DRAWING NUMBER
D
4.7.0
OF
23
1
81
A
8
6
7
1
RTC Power Sources
U2801
MIC5232-2.8YD5
LPC Reset (Unbuffered)
TSOT-23-5
PP3V3_G3_RTC
NC
D
1
C2870
2
10%
10V
X5R
402
R2819
0.47UF
C2819
10%
100
10%
10V
X5R
402
2
GND
1UF
SUPERCAP_YES
C2871
1
4
2
SUPERCAP_YES
SUPERCAP_YES
402
PP3V3_G3_SUPERCAP
6C3 20C8 21A5
R2881
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
76C3 18C3
1
PLACEMENT_NOTE=Place close to U1400
LPC_RESET_L
IN
33
1
CERM
402
2
5%
1/16W
MF-LF
402
1UF
6.3V
1
MF-LF
=PP3V42_G3H_RTC_D
5
2
7D1
CRITICAL VOUT
EN
1
Platform Reset Connections
VIN
3
2
3
4
5
2
33
1
OUT
42D5
2
SMC_LRESET_L
OUT
40C8
BKLT_PLT_RST_L
OUT
72C8
MINI_RESET_L
OUT
29A6
PCA9557D_RESET_L
OUT
25A5
=FW_RESET_L
OUT
35D1
D
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to U1400
SUPERCAP_YES
1
DEBUG_RESET_L
R2883
C2800
0.08F
2%
2 3.3V
XHHG
SM
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79
PLACE C2819 CLOSE TO MCP79
PLACE C2800 AT COOLEST SPOT ON MLB
PCIE Reset (Unbuffered)
SUPERCAP_NO
R2820
0
1
R2892
2
16B3
PCIE_RESET_L
MAKE_BASE=TRUE
IN
5%
1/16W
MF-LF
402
0
RTC Crystal
2
5%
1/16W
MF-LF
402
C2810
R2871
RTC_CLK32K_XTALOUT
1
R28101
R2811 1
OUT
Y2810
32.768K
2
1
C2815
1
R2815
1
R2870
R2816
1M
5%
1/16W
MF-LF
402 2
OUT
33
1
MEM_VTT_EN
MAKE_BASE=TRUE
2
5%
1/16W
MF-LF
402
=DDRVTT_EN
IN
PLACEMENT_NOTE=Place close to U1400
LPC_CLK33M_SMC_R
1
3
4
33
2
5%
1/16W
MF-LF
402
NC
NC
C2816
OUT
61C8 67A3
LPC_CLK33M_SMC
OUT
40C8 76C3
LPC_CLK33M_LPCPLUS
OUT
42D3 76C3
1
PM_CLK32K_SUSCLK
OUT
40C5 76A3
R2826
1
PLACEMENT_NOTE=Place close to U1400
12pF
2
5%
50V
CERM
402
MCP S0 PWRGD & CPU_VLD
7A3
MEM_VTT_EN_R
R2825
1
Y2815
25.0000M
2
CRITICAL
IN
MCP_CLK25M_XTALOUT_R
MCP_CLK25M_XTALIN
B
18C4
76C3 18B3
SM-3.2X2.5MM
20B7
2
5%
50V
CERM
402
0
5%
1/16W
MF-LF
402 2
1
30A7
5%
50V
CERM
402
MCP_CLK25M_XTALOUT
NO STUFF
OUT
12pF
1
12pF
IN
CARDREADER_PLT_RST_L
2
C2811
7X1.5X1.4-SM
RTC_CLK32K_XTALIN
MCP 25MHz Crystal
20B7
0
5%
1/16W
MF-LF
402
4
10M
C
R2895
1
CRITICAL
5%
1/16W
MF-LF
402 2
2
5%
1/16W
MF-LF
402
RTC_CLK32K_XTALOUT_R
NO STUFF
20B7
2
5%
50V
CERM
402
0
5%
1/16W
MF-LF
402 2
C
0
1
12pF
IN
2
5%
1/16W
MF-LF
402
R2891
1
20B7
0
1
33
2
5%
1/16W
MF-LF
402
B
R2829
76A3 20B3
IN
PM_CLK32K_SUSCLK_R
1
PLACEMENT_NOTE=Place close to U1400
=PP3V3_S5_MCPPWRGD
22
2
5%
1/16W
MF-LF
402
MCPSEQ_SMC
1
C2850
0.1UF
2
20%
10V
CERM
402
Reset Button
40B8
IN
PM_SYSRST_L
MCPSEQ_SMC
66A4 40D8
IN
62C7
IN
ALL_SYS_PWRGD
VR_PWRGOOD_DELAY
2
1
5 TC7SZ08AFEAPE
U2850Y
4
XDP
R2853
SOT665
A
S0_AND_IMVP_PGOOD
1
0
R2898
MCP_PS_PWRGD
2
OUT
20B7
12B3 9C6
IN
XDP_DBRESET_L
1
5%
1/16W
MF-LF
402
B
3
5%
1/16W
MF-LF
402
R2852
1
A
0
5%
1/16W
MF-LF
402
20B3
IN
1
R28901
NO STUFF
0
33
5%
1/16W
MF-LF
402
SILK_PART=SYS RST
OUT
20C7
NO STUFF
1
C2899
1UF
2
10%
10V
X5R
402
MCP_CPU_VLD
OUT
20B7
MCPSEQ_SMC
MCP_CPUVDD_EN
SB Misc
R2850
1
0
SYNC_MASTER=RAYMOND
2
SYNC FROM T18
CHANGE RESET BUTTOM TO RESET PADS
REMOVE UNUSED PCIE RESET SIGNALS
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A
CHANGE RTC COIN CELL TO LDO & SUPERCAP
ALIAS MEM_VTT_EN TO =DDRVTT_EN
CHANGE Y2810 AND U2850 TO SMALLER PARTS
5%
1/16W
MF-LF
402
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.
MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
SYNC_DATE=04/05/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
7
PM_SYSRST_DEBOUNCE_L
2
2
PLACEMENT_NOTE=Place close to U1400
8
10K pull-up to 3.3V S0 inside MCP
2
5%
1/16W
MF-LF
402
R2851
1
0
R2899
2
5%
1/16W
MF-LF
402 2
MCPSEQ_MIX
MCPSEQ_MIX
0
4.7.0
OF
24
1
81
A
8
6
7
2
3
4
5
1
Page Notes
MEM A VREF DQ
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF
DAC channel
Min DAC code
Max DAC code
Max sink I
Max source I
Nominal Vref
Min Vref
Max Vref
Vref Stepping
(per DAC LSB)
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
D
BOM options provided by this page:
VREFMRGN
NO_VREFMRGN
MEM A VREF CA
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
MEM B VREF DQ
MEM B VREF CA
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
CPU FSB VREF
C
0x00
0x55
-0.91 mA
0.52 mA
0.70 V
0.091 V
1.044 V
11.2 mV
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
61D8 7C4
=PPVTT_S3_DDR_BUF
D
10mA max load
R2903
1
A2
C2903
V+
0.1UF
7D3
A3
VREFMRGN
R2901
C2901
0.1UF
20%
2 10V
CERM
402
C2
V+
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA
9 A0
ADDR=0x98(WR)/0x99(RD)
C
10 A1
VOUTB 2
VREFMRGN_CA_SODIMM
VOUTC 4
VREFMRGN_CPUFSB
VOUTD 5
NC
VREFMRGN_DQ_SODIMMB_BUF
1
R2902
100K
5%
1/16W
MF-LF
402
VREFMRGN
1
GND
3
A2
C2904
U2903
B1
V+
0.1UF
20%
10V
2 CERM
402
A3
1
VREFMRGN_CA_SODIMMA_BUF
R2907
VREFMRGN_CA_SODIMMB_BUF
R2908
100K
VREFMRGN
1
A2
C2905
0.1UF
A3
Place close to J3100.126
200
VREFMRGN
2
PP0V75_S3_MEM_VREFCA_B
100
27B3
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VREFMRGN
2
1%
1/16W
MF-LF
402
Place close to J3200.126
5%
1/16W
MF-LF
402
VREFMRGN
MAX4253
VREFMRGN
20%
2 10V
CERM
402
2
1
U2904
B1
V+
1
25A5 VREFMRGN_CA_SODIMMB_EN
B4
26B3
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VREFMRGN
1%
1/16W
MF-LF
402
C4
V-
100
C
PP0V75_S3_MEM_VREFCA_A
R2912
MAX4253
UCSP
C1
VREFMRGN
C3
5%
1/16W
MF-LF
402
VREFMRGN
2
2
V+
Place close to J3200.1
R2911
VREFMRGN
1
U2903
B1
200
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
2
1%
1/16W
MF-LF
402
1
100K
C2
1
25B5 VREFMRGN_CA_SODIMMA_EN
B4
27D5
R2910
A4
V-
100
VREFMRGN
1%
1/16W
MF-LF
402
MAX4253
UCSP
A1
VREFMRGN
PP0V75_S3_MEM_VREFDQ_B
R2909
VREFMRGN
VREFMRGN
2
1%
1/16W
MF-LF
402
25A5 VREFMRGN_DQ_SODIMMB_EN
B4
VREFMRGN_DQ_SODIMM
200
R2906
C4
V-
Place close to J3100.1
1%
1/16W
MF-LF
402
1
43B3
IN
DAC5574
43B3
C3
5%
1/16W
MF-LF
402
MAX4253
UCSP
C1
VREFMRGN
VREFMRGN
8 U2900
VDD
MSOP VOUTA 1
U2902
B1
1
20%
6.3V
CERM
402-LF
VREFMRGN
26D5
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VREFMRGN
2
R2905
1
100K
2
1
2.2UF
100
1%
1/16W
MF-LF
402
2
C2900
1
25A5 VREFMRGN_DQ_SODIMMA_EN
B4
VREFMRGN
VREFMRGN_DQ_SODIMMA_BUF
A4
V-
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
UCSP
A1
VREFMRGN
20%
10V
2 CERM
402
=PP3V3_S3_VREFMRGN
U2902
B1
2
1%
1/16W
MF-LF
402
2
VREFMRGN
1
200
VREFMRGN
UCSP
A1
NC
A4
VB4
B
B
16
C2902
0.1UF
U2901
A0
A1
5 A2
4
43A3
IN
BI
1
2
SCL
SDA
THRM
17
PAD
NC
7
VREFMRGN_DQ_SODIMMA_EN
10
VREFMRGN_CA_SODIMMB_EN
11
VREFMRGN_DQ_SODIMMB_EN
12
5%
1/16W
MF-LF
402
25C3
25D3
100
1%
1/16W
MF-LF
402
25B5 VREFMRGN_CPUFSB_EN
100K
25B3
1
C4
R2913
VREFMRGN_CPUFSB_EN
VREFMRGN_CA_SODIMMA_EN
9
R2914
VREFMRGN_CPUFSB_BUF
VREFMRGN
CPU_GTLREF
2
OUT
9B4 73B3
Place close to U1000.AD26
VREFMRGN
25B3
25C3
13
NC
NC
14
RESET* 15
PCA9557D_RESET_L
GND
IN
24C1
8
43A3
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
6
UCSP
C1
1
P0
P1
P2
P3
P4
P5
P6
P7
3
VB4
PCA9557
QFN
ADDR=0x30(WR)/0x31(RD)
C3
U2904
MAX4253
VREFMRGN
VCC
20%
2 10V
CERM
402
B1
V+
VREFMRGN
2
C2
VREFMRGN
1
FSB/DDR3 Vref Margining
A
SYNC_MASTER=BEN
SYNC_DATE=03/31/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
Required zero ohm resistors when no VREF margining circuit stuffed
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2903
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2905
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2909
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2911
CRITICAL
NO_VREFMRGN
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
25
1
81
A
8
6
7
Page Notes
7D3
2
3
4
5
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
=PP1V5_S3_MEM_A
Power aliases required by this page:
- =PP1V5_S0_MEM_A
1
- =PP1V5_S3_MEM_A
- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
2
C3100
1
C3101
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
2
1
C3110
1
0.1UF
2
2
CRITICAL
Signal aliases required by this page:
C3111
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
C3112
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
20%
6.3V
X6S-CERM
0204-1
1
0.1UF
2
CRITICAL
C3113
C3114
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
20%
6.3V
X6S-CERM
0204-1
1
0.1UF
2
CRITICAL
C3115
C3116
1
20%
6.3V
X6S-CERM
0204-1
2 6.3V
X6S-CERM
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
C3117
0.1UF
20%
0204-1
CRITICAL
CRITICAL
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
BOM options provided by this page:
25D1
D
PP0V75_S3_MEM_VREFDQ_A
(NONE)
C3130
1
C3131
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
2
20%
10V
CERM
402
1
C
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14B5
IN
73
MEM_A_CKE<0>
MEM_A_BA<2>
NC
B
7C5
BI
74D3 14C7
BI
74C3 14D5
BI
74C3 14D5
BI
74D3 14C7
BI
74D3 14C7
BI
79
81
83
MEM_A_A<12>
MEM_A_A<9>
85
87
89
MEM_A_A<8>
MEM_A_A<5>
91
93
95
MEM_A_A<3>
MEM_A_A<1>
97
99
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
101
MEM_A_A<10>
MEM_A_BA<0>
107
MEM_A_WE_L
MEM_A_CAS_L
113
MEM_A_A<13>
MEM_A_CS_L<1>
119
121
103
105
109
111
115
117
123
NC
74D3 14C7
75
77
125
127
MEM_A_DQ<32>
MEM_A_DQ<33>
129
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
135
MEM_A_DQ<34>
MEM_A_DQ<38>
141
143
131
133
137
139
145
147
149
74D3 14C7
BI
74D3 14C7
BI
MEM_A_DQ<44>
MEM_A_DQ<45>
74C3 14B7
IN
MEM_A_DM<5>
153
155
74D3 14D7
BI
157
74D3 14D7
BI
MEM_A_DQ<47>
MEM_A_DQ<46>
74D3 14D7
BI
74D3 14D7
BI
MEM_A_DQ<49>
MEM_A_DQ<52>
163
165
74C3 14D5
BI
74C3 14D5
BI
74D3 14D7
BI
74D3 14D7
BI
74D3 14D7
BI
74D3 14D7
BI
151
159
161
167
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
169
171
173
MEM_A_DQ<54>
MEM_A_DQ<51>
175
177
179
MEM_A_DQ<61>
MEM_A_DQ<60>
181
183
185
187
74C3 14B7
IN
MEM_A_DM<7>
74D3 14D7
BI
74D3 14D7
BI
MEM_A_DQ<58>
MEM_A_DQ<59>
189
191
193
195
MEM_A_SA<0>
197
199
MEM_A_SA<1>
201
=PPSPD_S0_MEM_A
203
1
A
C3140
1
2.2UF
2
20%
6.3V
CERM
402-LF
2
1
R3140
J3100
74
MEM_A_CKE<1>
76
78
IN
14A5 74D3
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
74D3 14B7
74D3 14B7
MEM_A_A<15>
MEM_A_A<14>
80
82
84
MEM_A_A<11>
MEM_A_A<7>
86
88
90
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
8D2
IN
14C5 74D3
74D3 14A7
74D3 14B7
BI
14C5 74D3
74D3 14B7
BI
IN
14B5 74D3
74D3 14B7
BI
IN
14B5 74D3
74D3 14B7
BI
MEM_A_A<2>
MEM_A_A<0>
IN
14B5 74D3
74C3 14D5
BI
IN
14B5 74D3
74C3 14D5
BI
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
IN
14B5 74D3
74D3 14B7
BI
IN
14B5 74D3
74D3 14B7
BI
MEM_A_BA<1>
MEM_A_RAS_L
IN
14C5 74D3
74D3 14C7
BI
IN
14C5 74D3
74D3 14C7
BI
MEM_A_CS_L<0>
MEM_A_ODT<0>
IN
14B5 74D3
74C3 14D5
BI
IN
14B5 74D3
74C3 14D5
BI
MEM_A_ODT<1>
IN
14B5 74D3
74D3 14C7
BI
74D3 14C7
BI
126
128
136
138
140
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DM<4>
BI
14C7 74D3
BI
14C7 74D3
IN
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQ<40>
MEM_A_DQ<41>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
BI
14D5 74C3
BI
14D5 74C3
MEM_A_DQ<43>
MEM_A_DQ<42>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQ<53>
MEM_A_DQ<48>
BI
14D7 74D3
BI
14D7 74D3
170
172
MEM_A_DM<6>
IN
174
MEM_A_DQ<55>
MEM_A_DQ<50>
BI
14D7 74D3
BI
14D7 74D3
MEM_A_DQ<57>
MEM_A_DQ<56>
BI
14D7 74D3
BI
14D7 74D3
146
148
150
152
154
156
158
160
162
164
166
168
176
178
180
182
184
186
188
192
194
198
200
BI
BI
14D5 74C3
MEM_A_DQ<62>
MEM_A_DQ<63>
BI
14D7 74D3
BI
14D7 74D3
202
204
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
OUT
BI
MEM_A_DQ<0>
MEM_A_DQ<1>
7
9
11
MEM_A_DM<0>
13
15
MEM_A_DQ<6>
MEM_A_DQ<7>
17
19
21
MEM_A_DQ<8>
MEM_A_DQ<12>
23
25
27
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
29
31
MEM_A_DQ<10>
MEM_A_DQ<15>
33
MEM_A_DQ<25>
MEM_A_DQ<24>
39
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
45
MEM_A_DQ<26>
MEM_A_DQ<30>
51
53
35
37
41
43
47
49
55
57
59
MEM_A_DQ<20>
MEM_A_DQ<21>
61
IN
MEM_A_DM<2>
63
65
74D3 14C7
BI
67
74D3 14B7
BI
MEM_A_DQ<23>
MEM_A_DQ<16>
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
VSS
DQ1
VSS
DQS0*
DM0
DQS0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
VSS
DQ22
DQ18
DQ23
DQ19
VSS
VSS
DQ28
DQ24
DQ29
VSS
DQ25
VSS
DQS3*
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
J3100
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
MEM_A_DQ<4>
MEM_A_DQ<5>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
BI
14D5 74C3
BI
14D5 74C3
MEM_A_DQ<3>
MEM_A_DQ<2>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQ<9>
MEM_A_DQ<13>
BI
14B7 74D3
MEM_A_DM<1>
MEM_RESET_L
IN
14A7 74C3
IN
27C2 28C5
MEM_A_DQ<11>
MEM_A_DQ<14>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQ<29>
MEM_A_DQ<28>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DM<3>
IN
MEM_A_DQ<27>
MEM_A_DQ<31>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQ<18>
MEM_A_DQ<17>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
BI
14D5 74C3
BI
14D5 74C3
MEM_A_DQ<19>
MEM_A_DQ<22>
BI
14B7 74D3
BI
14C7 74D3
BI
14B7 74D3
C
14B7 74C3
KEY
516-0201
B
PP0V75_S3_MEM_VREFCA_A
1
C3135
1
2.2UF
14D5 74C3
196
BI
74D3 14C7
3
5
14B7 74C3
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
190
74D3 14C7
74C3 14B7
14B7 74C3
MEM_A_DQ<35>
MEM_A_DQ<39>
142
144
IN
14C5 74D3
NC
132
134
BI
IN
124
130
BI
IN
MEM_A_A<6>
MEM_A_A<4>
92
IN
2
20%
6.3V
CERM
402-LF
25C1
C3136
0.1UF
2
20%
10V
CERM
402
20A4 20B3 27A5 40B8
BI
IN
"Factory" (top) slot
43D6
43D6
=PP0V75_S0_MEM_VTT_A
7C7
DDR3 SO-DIMM Connector A
R3141
10K
2
CKE0
CKE1
VDD
VDD
NC
A15
A14
BA2
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
(SYMBOL 2 OF 2)
74D3 14C5
IN
DDR3-SODIMM-DUAL-M97-3
74D3 14A5
KEY
(SYMBOL 1 OF 2)
1
DDR3-SODIMM-DUAL-M97-3
D
1
C3150
1
2.2UF
2
20%
6.3V
CERM
402-LF
C3151
SYNC_MASTER=BEN
2.2UF
2
SYNC_DATE=06/30/2008
NOTICE OF PROPRIETARY PROPERTY
20%
6.3V
CERM
402-LF
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
516-0201
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SPD ADDR=0xA0(WR)/0xA1(RD)
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
26
1
81
A
8
6
7
Page Notes
7D3
2
3
4
5
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
=PP1V5_S3_MEM_B
Power aliases required by this page:
- =PP1V5_S0_MEM_B
1
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
2
C3200
1
C3201
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
2
1
C3210
1
0.1UF
2
2
CRITICAL
Signal aliases required by this page:
C3211
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
C3212
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
20%
6.3V
X6S-CERM
0204-1
C3213
1
0.1UF
2
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
CRITICAL
CRITICAL
C3214
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
C3215
1
0.1UF
2
C3216
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
20%
2 6.3V
X6S-CERM
0204-1
CRITICAL
CRITICAL
C3217
0.1UF
20%
6.3V
X6S-CERM
0204-1
CRITICAL
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
BOM options provided by this page:
25C1
D
PP0V75_S3_MEM_VREFDQ_B
(NONE)
C3230
1
C3231
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
2
20%
10V
CERM
402
1
C
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14B1
IN
74B3 14B1
IN
74B3 14B1
IN
74C3 14B1
IN
74C3 14B1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14B1
75
77
MEM_B_BA<2>
IN
74B3 14C1
73
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
IN
79
81
83
85
87
89
91
93
95
97
99
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
101
MEM_B_A<10>
MEM_B_BA<0>
107
MEM_B_WE_L
MEM_B_CAS_L
113
MEM_B_A<13>
MEM_B_CS_L<1>
119
121
103
105
109
111
115
117
123
125
127
B
1
R3240
74B3 14C3
BI
74B3 14C3
BI
74A3 14D1
BI
74A3 14D1
BI
74B3 14C3
BI
74B3 14C3
BI
MEM_B_DQ<37>
MEM_B_DQ<32>
129
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
135
MEM_B_DQ<35>
MEM_B_DQ<39>
2
7C5
137
139
141
143
145
147
149
74B3 14C3
BI
74B3 14C3
BI
MEM_B_DQ<45>
MEM_B_DQ<41>
74B3 14B3
IN
MEM_B_DM<5>
153
155
74B3 14D3
BI
157
74B3 14D3
BI
MEM_B_DQ<46>
MEM_B_DQ<47>
74B3 14D3
BI
74B3 14D3
BI
74A3 14D1
BI
74A3 14D1
BI
74B3 14D3
BI
74B3 14D3
BI
74B3 14D3
BI
74B3 14D3
BI
151
MEM_B_DQ<53>
MEM_B_DQ<49>
159
161
163
165
167
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
169
171
173
MEM_B_DQ<55>
MEM_B_DQ<54>
175
177
179
MEM_B_DQ<56>
MEM_B_DQ<58>
181
183
185
187
74B3 14B3
IN
MEM_B_DM<7>
74B3 14D3
BI
74B3 14D3
BI
MEM_B_DQ<61>
MEM_B_DQ<60>
189
10K
5%
1/16W
MF-LF
402
131
133
191
193
195
MEM_B_SA<0>
197
199
MEM_B_SA<1>
201
=PPSPD_S0_MEM_B
203
1
A
1
C3240
2
R3241
10K
2.2UF
20%
6.3V
CERM
402-LF
2
5%
1/16W
MF-LF
402
205
207
209
211
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
VDD F-RT-BGA3 VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
J3200
(2 OF 2)
74B3 14C1
MEM_B_CKE<0>
IN
DDR3-SODIMM
74B3 14A1
KEY
MTG PINS
MTG
MTG
MTG
MTG
PIN
PIN
PIN
PIN
MTG PIN
MTG PIN
MTG PIN
MTG PIN
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
MEM_B_CKE<1>
IN
14A1 74B3
74B3 14B3
74B3 14B3
MEM_B_A<15>
MEM_B_A<14>
8D2
IN
14C1 74B3
IN
14C1 74B3
74B3 14B3
BI
IN
14C1 74B3
74B3 14B3
BI
IN
14B1 74B3
74B3 14B3
BI
IN
14B1 74B3
74B3 14B3
BI
MEM_B_A<2>
MEM_B_A<0>
IN
14B1 74B3
74A3 14D1
BI
IN
14B1 74B3
74A3 14D1
BI
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
IN
14B1 74C3
74B3 14B3
BI
IN
14B1 74C3
74B3 14B3
BI
MEM_B_BA<1>
MEM_B_RAS_L
IN
14C1 74B3
74B3 14C3
BI
IN
14C1 74B3
74B3 14B3
BI
MEM_B_CS_L<0>
MEM_B_ODT<0>
IN
14B1 74B3
74A3 14D1
BI
IN
14B1 74B3
74A3 14D1
BI
MEM_B_ODT<1>
IN
14B1 74B3
74B3 14C3
BI
74B3 14B3
BI
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
74B3 14A3
126
128
132
134
136
138
140
MEM_B_DQ<36>
MEM_B_DQ<33>
MEM_B_DM<4>
BI
14C3 74B3
BI
14C3 74B3
IN
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQ<40>
MEM_B_DQ<44>
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
BI
14D1 74A3
BI
14D1 74A3
MEM_B_DQ<42>
MEM_B_DQ<43>
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQ<52>
MEM_B_DQ<48>
BI
14D3 74B3
BI
14D3 74B3
170
172
MEM_B_DM<6>
IN
174
MEM_B_DQ<51>
MEM_B_DQ<50>
BI
14D3 74B3
BI
14D3 74B3
MEM_B_DQ<63>
MEM_B_DQ<59>
BI
14D3 74B3
BI
14D3 74B3
146
148
150
152
154
156
158
160
162
164
166
168
176
178
180
182
184
186
188
192
194
198
200
202
204
13
15
MEM_B_DQ<3>
MEM_B_DQ<6>
17
19
21
MEM_B_DQ<13>
MEM_B_DQ<14>
23
25
27
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
29
31
MEM_B_DQ<15>
MEM_B_DQ<10>
33
MEM_B_DQ<20>
MEM_B_DQ<17>
39
35
37
41
43
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
45
MEM_B_DQ<22>
MEM_B_DQ<19>
51
53
47
49
55
57
59
MEM_B_DQ<24>
MEM_B_DQ<28>
61
IN
MEM_B_DM<3>
63
65
74B3 14C3
BI
67
74B3 14C3
BI
MEM_B_DQ<26>
MEM_B_DQ<31>
69
71
J3200
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
MEM_B_DQ<4>
MEM_B_DQ<5>
BI
14B3 74B3
BI
14B3 74B3
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
BI
14D1 74A3
BI
14D1 74A3
MEM_B_DQ<7>
MEM_B_DQ<2>
BI
14B3 74B3
BI
14B3 74B3
MEM_B_DQ<12>
MEM_B_DQ<9>
BI
14B3 74B3
MEM_B_DM<1>
MEM_RESET_L
IN
14A3 74B3
IN
26C2 28C5
MEM_B_DQ<8>
MEM_B_DQ<11>
BI
14B3 74B3
BI
14B3 74B3
MEM_B_DQ<16>
MEM_B_DQ<21>
BI
14B3 74B3
BI
14C3 74B3
MEM_B_DM<2>
IN
MEM_B_DQ<18>
MEM_B_DQ<23>
BI
14B3 74B3
BI
14C3 74B3
MEM_B_DQ<29>
MEM_B_DQ<25>
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
BI
14D1 74A3
BI
14D1 74A3
MEM_B_DQ<30>
MEM_B_DQ<27>
BI
14C3 74B3
BI
14C3 74B3
14D1 74A3
MEM_B_DQ<62>
MEM_B_DQ<57>
BI
14D3 74B3
BI
14D3 74B3
BI
14B3 74B3
C
14B3 74B3
KEY
516S0706
B
DDR3 GROUND RETURN CAPS (MCP SIDE)
=PP1V5_S0_MEM_MCP
1
2
PP0V75_S3_MEM_VREFCA_B
1
C3235
1
2.2UF
BI
OUT
11
MEM_B_DM<0>
4
6
C3222
1
0.1UF
BI
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
BI
7
9
2
14B3 74B3
14D1 74A3
196
BI
74B3 14C3
MEM_B_DQ<1>
MEM_B_DQ<0>
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
CRITICAL
DQ1
VSS
VSS
DQS0*
DM0
DQS0
F-RT-BGA3
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
VSS
DQ22
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ24
DQ29
VSS
DQ25
VSS
DQS3*
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
7B6
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
190
IN
74B3 14C3
74B3 14B3
14B3 74B3
MEM_B_DQ<38>
MEM_B_DQ<34>
142
144
BI
IN
124
130
BI
3
5
(1 OF 2)
1
DDR3-SODIMM
D
2
20%
6.3V
CERM
402-LF
25C1
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3223
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3224
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3225
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3226
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3227
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3228
1
20%
6.3V
X6S-CERM
0204-1
2 6.3V
X6S-CERM
0.1UF
2
C3229
0.1UF
20%
0204-1
CRITICAL
CRITICAL
C3236
0.1UF
2
20%
10V
CERM
402
20A4 20B3 26A5 40B8
BI
IN
43C6
"Expansion" (bottom) slot
43C6
=PP0V75_S0_MEM_VTT_B
7C7
DDR3 SO-DIMM Connector B
206
208
1
210
212
C3250
1
2.2UF
2
20%
6.3V
CERM
402-LF
C3251
SYNC_MASTER=BEN
2.2UF
2
SYNC_DATE=05/09/2008
NOTICE OF PROPRIETARY PROPERTY
20%
6.3V
CERM
402-LF
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
516S0706
SIZE
SPD ADDR=0xA2(WR)/0xA3(RD)
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
27
1
81
A
8
6
7
3
4
5
2
1
D
D
DDR3 RESET Support
Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309
MCP_MEM_RESET_L
2
0
1
MEM_RESET_L
R33101
Q3305
1K
5%
1/16W
MF-LF
402 2
1
Q1
S
2
B
0.1UF
3
5
C3300
E
1
MEM_RESET_RC_L
4
R3301
1
R3305
1
6
10K
5%
1/16W
MF-LF
402 2
7A3
SOT-363
D
R3300
=PP3V3_S5_MEMRESET
DMB53D0UDW
5%
1/16W
MF-LF
402 2
1
20K
26C2 27C2
G
=PP1V5_S3_MEMRESET
C
OUT
5%
1/16W
MF-LF
402
C
7D3
IN
Q2
15C3
100K
5%
1/16W
MF-LF
402 2
C
3.3V S5 is used because MEM_RESET
must be high before 1.5V starts to
rise to avoid glitch on MEM_RESET_L.
MEM_RESET
20%
10V
2 CERM
402
B
B
DDR3 Support
A
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
28
1
81
A
8
6
7
16C6
OUT
2
3
4
5
1
PCIE_MINI_PRSNT_L
3
D
Q3401
SSM6N15FEAPE
SOT563
4
S
G
5
AP_PWR_EN
20A3 20C3 32C7
IN
5V S3 WLAN FET
D
16C6
OUT
MINI_CLKREQ_L
6
D
Q3401
SOT563
S
G
TPCP8102
CHANNEL
P-TYPE
RDS(ON)
SSM6N15FEAPE
1
MOSFET
D
26 mOhm @4.5V
LOADING
0.8 A (EDP)
2
CRITICAL
Q3450
TPCP8102
L3404
20347-325E-12
10%
0.1uF
16V
X5R
16V X5R 402
IN
16B3 75D3
402
3
2
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
1
2
OUT
6D5 16B6 75D3
OUT
6D5 16B6 75D3
3
4
75D3 6D5
5
75D3 6D5
PCIE_CLK100M_MINI_CONN_P
6D5 PCIE_CLK100M_MINI_CONN_N
8
75D3
6C5
11
20%
10V
CERM
402
1
2
C3420
10UF
2
2
20%
10V
X5R
805
C3450
0.1UF
2
10%
16V
X5R
402
PLACEMENT_NOTE=Place close to J3401.
C3451
1
10%
16V
X5R
402
2
10K
0.033UF
P5VWLAN_SS
R3451
7C3
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
R3450
1
100K
2
5%
1/16W
MF-LF
402
PM_WLAN_EN_L
2
IN
29A4 32C6
5%
1/16W
MF-LF
402
PCIE_CLK100M_MINI_P
3
C
PLACEMENT_NOTE=Place close to Q3450.
IN
16C3
75D3
PLACEMENT_NOTE=Place close to Q3450.
1
9
10
1
0.1uF
=PP5V_S3_WLAN
1
SYM_VER-1
4
75D3 6D5
PP5V_WLAN_F
1
DLP11S
6
7
20%
10V
CERM
402
AIRPORT
L3401
90-OHM-100MA
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
C3421
1
0.1uF
CRITICAL
29A5
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
C3422
PLACEMENT_NOTE=Place close to J3401.
31
1
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
C3430
F-RT-SM
23V1K-SM
8
0402-LF
PP5V_WLAN
S
IN
16B3 75D3 6C3
6D5
1 2
2
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
0.1uF
4 G
1
10%
2
D
1
1000 mA peak
750 mA nominal max
6 7
C3431
J3401
C
FERR-120-OHM-1.5A
PLACEMENT_NOTE=Place close to J3401.
5
CRITICAL
518S0610
PCIE_CLK100M_MINI_N
2
IN
16C3
75D3
PLACEMENT_NOTE=Place close to J3401.
MINI_CLKREQ_Q_L
PCIE_WAKE_L
OUT
12
6D5 16B6
13
14
15
16
17
NC
NC
6D5
18
19
PP5V_S3_BTCAMERA_F
=I2C_ALS_SDA
=I2C_ALS_SCL
20
BI
IN
43C1
76C3 6D5
22
76C3
CRITICAL
23
L3402
90-OHM
CONN_USB2_BT_P
CONN_USB2_BT_N
24
25
DLP0NS
C3452
=PP5V_S3_BTCAMERA
1
1
0402-LF
7C3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
0.1uF
20%
10V
CERM
402
2
SYM_VER-1
4
3
USB_CAMERA_P
OUT
19D3 76C3
1
2
USB_CAMERA_N
OUT
19D3 76C3
26
27
28
PLACEMENT_NOTE=Place close to J3401.
29
B
2
FERR-120-OHM-1.5A
ALS
CAMERA
43C1
USB_CAMERA_CONN_P
6D5 USB_CAMERA_CONN_N
21
L3405
275 mA peak
206 mA nominal max
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
B
30
BLUETOOTH
CRITICAL
32
L3403
90-OHM
DLP0NS
SYM_VER-1
4
1
3
USB_BT_P
BI
19D3 76C3
2
USB_BT_N
BI
19C3 76C3
PLACEMENT_NOTE=Place close to J3401.
PP5V_WLAN_F
=PP3V3_S3_WLAN
7D3
1
29C3
R3453
33K
U3402
TC7SZ08AFEAPE 5
SOT665
6C5
MINI_RESET_CONN_L
4
74LVC1G17DRL
A
U3401
2
2
SOT-553
4
WLAN_SMIT_BUF
5%
1/16W
MF-LF
402
R3455
2
WLAN_SMIT_RC
NC
Y
B
1
3
3
MINI_RESET_L
A
5
1
NC
C3453
IN
24C1
1
1
1
5%
1/16W
MF-LF
402
2
WLAN_SMIT_DISCHRG
Q3455
3
D
2
2
Right Clutch Connector
SSM3K15FV
SOD-VESM-HF
62K
1UF
10%
6.3V
CERM
402
R3454
1
SYNC_MASTER=YITE
5%
1/16W
MF-LF
402
SYNC_DATE=04/22/2008
NOTICE OF PROPRIETARY PROPERTY
2
S
G 1
PM_WLAN_EN_L
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
29C1 32C6
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
29
1
81
A
8
6
7
R3511
7C3
=PP3V3_S3_CARDREADER
0
1
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
2
3
4
5
1
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
2
30B4 30A7
5%
1/16W
MF-LF
402
PP3V3_S3_CARDREADER_DVDD
C3500
1
1
10UF
1
0.1UF
20%
6.3V
2 X5R
603
D
C3501
C3502
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
1
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
C3503
0.1UF
20%
10V
2 CERM
402
PART NUMBER
516-0225
QTY
1
DESCRIPTION
REFERENCE DES
CONN,SD CARD READER,OPTN B,HF,K19/K24
J3500
CRITICAL
BOM OPTION
D
CRITICAL
L3500
0.22UH
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
1
PP3V3_S3_CARDREADER_AVDD
1
C3514
1
10UF
C3504
1
0.1UF
20%
6.3V
2 X5R
603
2
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
0805-1
MAX CURRENT = 250MA
C3508
PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
1
C3507
2.2UF
20%
6.3V
2 CERM1
603
1
C3505
0.1UF
20%
10V
2 CERM
402
PP1V8_S3_CARDREADER
1
PP3V3_SW_SD_PWR
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
R3505
1
39K
5%
1/16W
MF-LF
2 402
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=1.8V
C3506
0.1UF
OMIT
J3500
C
76B3 19C3
BI
76B3 19C3
BI
30A7
30A6
CARDREADER_GPIO1
CARDREADER_GPIO2
NC
LQFP
48 GPIO1
47 GPIO2
46 GPIO3
CRITICAL
19
SK
NC
20 CS
NC
21 DO
NC
22 DI /IPD
NC
1
10 RREF
CARDREADER_RREF
2
5%
1/16W
MF-LF
402
17 TESTMOD
CARDREADER_TEST_MOD
Y3500
12.000M-100PPM
1
2
IPD/
5%
50V
CERM
402
B
5%
50V
CERM
402
1
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
2
C3513
0.1UF
20%
10V
2 CERM
402
16
1
0
715
33PF
2
D0
D1
D2
D3
D4
D5
D6
D7
40
43
37
29
28
30
32
38
SD_WP
5 G
CARDREADER_RESET
9
1
10
11
12
13
14
16
18
1
NC
NC
42
NC
44
NC
45
NC
19
31
20
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
C
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
24
IPU/ MS_INS
NC
MS_BS 33
NC
PDMOD: POWER DOWN MODES
NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE
B
PP3V3_S3_CARDREADER_DVDD
D 3
1
R3512
10K
SOT563
IN
8
17
SSM6N15FEAPE
16B6
7
4
CARDREADER_PDMOD
30D6 30A7
Q3500
2
15
SD_WP 3
SD_CMD 41
2
IPU/ PDMOD
23
IPU/ SD_CDZ
5
GND
12
1
R3506
C3512
33PF
NO STUFF
R3502
9
C3511
1
1
5
8X4.5X1.4-SM
6
IPU/ XD_CDZ
XD_CE
IPD/ XD_WEZ
IPD/ XD_RBZ
IPD/ XD_WPZ
/IPD
CARDREADER_RESET_L 18 EXTRSTZ* /IPU
CRITICAL
3
SD_CLK
78C3 SD_CMD
78D3 SD_D<0>
78D3 SD_D<1>
78C3 SD_D<2>
78C3 SD_D<3>
78C3 SD_D<4>
78C3 SD_D<5>
78C3 SD_D<6>
78C3 SD_D<7>
SD_CD_L
78C3
34
1M
IPD/
IPD/
27
R3503
F-RT-TH
CLK 39
13 X1
14 X2
CARDREADER_XTAL1
CARDREADER_XTAL2
NO STUFF
36
25
GL137A
SD-CARD-K19
PMOSO
VDD5V
15
26
35
U3500
7 DM
8 DP
USB_CARDREADER_N
USB_CARDREADER_P
DVDD
6
AVDD 11
VDD18O
4
20%
2 10V
CERM
402
5%
1/16W
MF-LF
2 402
S 4
(PDMOD)
CARDREADER_PLT_RST
Q3500
D 6
1
10K
SOT563
24C1
IN
30D6 30B4
R3507
10K
5%
1/16W
MF-LF
2 402
30C6
5%
1/16W
MF-LF
2 402
S 1
PP3V3_S3_CARDREADER_DVDD
1
A
2 G
CARDREADER_PLT_RST_L
NO STUFF
R3513
SSM6N15FEAPE
1
NO STUFF
R3508
10K
SECUREDIGITAL CARD READER
5%
1/16W
MF-LF
2 402
CARDREADER_GPIO1
SYNC_MASTER=VEMURI
1NO
STUFF
R3509
10K
5%
1/16W
MF-LF
2 402
SYNC_DATE=01/30/2009
NOTICE OF PROPRIETARY PROPERTY
CARDREADER_GPIO2 30C6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
1
R3510
10K
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
2 402
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
30
1
81
A
8
6
7
2
3
4
5
=PP1V05_ENET_PHY
D
C3710
C3711
1
0.1UF
7B5
10%
16V
X5R
402
=PP3V3_ENET_PHY
(43mA typ - 1000base-T)
(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
1
1
0.1UF
10%
16V
X5R
402
2
1
7A5
(221mA typ - 1000base-T)
( 7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
D
CRITICAL
L3715
2
FERR-120-OHM-1.5A
0402-LF
1
1
C3700
1
0.1UF
CRITICAL
L3705
2
FERR-120-OHM-1.5A
10%
16V
X5R
402
C3701
1
0.1UF
2
C3702
2
0.1UF
10%
16V
X5R
402
2
PP1V05_ENET_PHYAVDD
10%
16V
X5R
402
C3714
0402-LF
C3715
1
0.1UF
10%
16V
X5R
402
2
C3716
1
2.2UF
20%
6.3V
CERM
402-LF
2
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2.2UF
20%
6.3V
CERM
402-LF
2
2
PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
C3705
1
10%
16V
X5R
402
2
0.1UF
2
C3706
0.1UF
10%
16V
X5R
402
=PP3V3_ENET_PHY_VDDREG
8D2
If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
8D2
IN
=RTL8211_ENSWREG
2
IN
ENET_CLK125M_TXCLK
1
0
2
77D3
22
ENET_CLK125M_TXCLK_R
PLACE R3796 CLOSE TO U1400, PIN D24
IN
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
IN
ENET_TX_CTRL
77D3 17D3
IN
77D3 17C3
BI
ENET_MDC
ENET_MDIO
77D3 17D3
IN
77D3 17D3
IN
77D3 17D3
77D3 17D3
77C3 17D3
ENSWREG
10
40
3
44
45
15
21
37
U3700
ENET_RESET_L
1
0
IN
B
RTL8211_PHYRST_L
2
5%
1/16W
MF-LF
402
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.
2
4.7K
4.7K
=RTL8211_REGOUT
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
If internal switcher is used, must place inductor within 5mm
of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
8D2
C
If internal switcher is not used, VDDREG and REGOUT can float.
REGOUT
48
RXC
19
RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0
RXD[3]/AN1
14
16
17
18
RXCTL
13
RTL8251CA-VB-GR
23
24
25
26
27
30
31
TXC
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RGMII/MII
TXCTL
MDC
MDIO
NO STUFF
1
C3725
0.1UF
2
RTL8211_RSET
20%
10V
CERM
402
8D2
TP_RTL8211_CLK125
29
46
32
PHYRSTB*
RSET
77D3 32A3
IN
RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2
42
43
77D3
77D3
77D3
R3791
R3792
R3793
R3794
ENET_RXD_R<0>
ENET_RXD_R<1>
ENET_RXD_R<2>
ENET_RXD_R<3>
R3795
ENET_RXCTL_R
ENET_MDI_P<0>
ENET_MDI_N<0>
BI
33B8 77C3
BI
33B8 77C3
MDI+[1]
MDI-[1]
4
5
ENET_MDI_P<1>
ENET_MDI_N<1>
BI
33C8 77C3
BI
33C8 77C3
MDI+[2]
MDI-[2]
8
9
ENET_MDI_P<2>
ENET_MDI_N<2>
BI
33C8 77C3
BI
33C8 77C3
MDI+[3]
MDI-[3]
11
12
ENET_MDI_P<3>
ENET_MDI_N<3>
BI
33C8 77C3
BI
33C8 77C3
CLOCK
LED0/PHYAD0
LED1/PHYAD1
LED2/RXDLY
34
35
38
RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY
CKXTAL1
CKXTAL2
2
LED
GND
NO STUFF
C3790
7
20
33
47
1%
1/16W
MF-LF
402
77D3
22
22
22
22
22
22
1
1
2
1
2
1
2
1
2
1
ENET_CLK125M_RXCLK
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RX_CTRL
2
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
B
CLK125
R3730 1
2.49K
77D3
R3790
ENET_CLK125M_RXCLK_R
1
2
RESET MEDIA DEPENDENT
REFERENCE
77D3
MDI+[0]
MDI-[0]
MANAGEMENT
R3724
IN
5%
1/16W
MF-LF
402 2
R3752 1
R3751
TQFP
5%
1/16W
402
MF-LF
77C3 17C3
1
4.7K
CRITICAL
39
R3796
77D3 17D3
AVDD10
5%
1/16W
MF-LF
402
28
36
4.7K
FB10
5%
1/16W
MF-LF
402 2
DVDD10
Alias to =PP3V3_ENET_PHY for internal switcher.
Alias to GND for external 1.05V supply.
VDDREG
10K
C
R3725
DVDD33
1
AVDD33
NO STUFF
R3720 1
6
41
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
R3750 1
1
5%
50V
CERM
402
R3755 1
4.7K
10PF
2
5%
1/16W
MF-LF
402
R3756 1
1
4.7K
5%
1/16W
MF-LF
402
2
2
R3757
4.7K
2
5%
1/16W
MF-LF
402
Reserved for EMI
per RealTek request.
Ethernet PHY (RTL8211CL)
A
SYNC_MASTER=SUMA
SYNC_DATE=05/23/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Configuration Settings:
PHYAD
AN[1:0]
RXDLY
TXDLY
=
=
=
=
01
11
0
0
SIZE
8
DRAWING NUMBER
D
(PHY Address 00001)
(Full auto-negotiation)
(RXCLK transitions with data)
(No TXCLK Delay)
APPLE INC.
SCALE
SHT
NONE
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
31
1
81
A
8
6
7
2
3
4
5
1
3.3V ENET FET
@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
CRITICAL
Q3810
NTR4101P
SOT-23-HF
7A3
=PP3V3_S5_P3V3ENETFET
=PP3V3_ENET_FET
S
2
D
1
R3800 1
5%
1/16W
MF-LF
402
2
R3810
2
P3V3ENET_EN_L
Q3801
C3811
D
3
S
4
1
100K
7B6
3
D
G
0.033UF
10K
D
10%
16V
X5R
402
1
C3810
0.01UF
P3V3ENET_SS
2
2
5%
1/16W
MF-LF
402
1
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
5
8D2
IN
G
=P3V3ENET_EN
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and
=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
C
29A4 29C1
OUT
Q3805
D
6
SSM6N15FEAPE
SOT563
2
29D5 20C3 20A3
IN
G
7B3
S
=PP1V05_ENET_P1V05ENETFET
1.8V Vgs
C3840
1
AP_PWR_EN
Q3805
3
6
D
SSM6N15FEAPE
7A3
Q3801
1
SOT563
41B2 40D5 35B5 20C7
IN
S
4
1
S
G
100K
1%
1/16W
MF-LF
402
SMC_ADAPTER_EN
IN
SI2312BDS
G
Q3841
D
6
SOT23
2
=PP1V05_ENET_FET
7B6
SOT563
2
P1V05ENET_EN_L
PM_SLP_S3_L
Q3841
Q3840
1
SSM6N15FEAPE
69.8K
2
CRITICAL
D
2
S
R3841
70D8 66D5 40C5 35A5 20C3 6C3
3
P1V05ENET_SS
2
5%
1/16W
MF-LF
402
R3842 1
G
20%
10V
CERM
402
R3840
=PP3V3_S5_P1V05ENETFET
SSM6N15FEAPE
SOT563
5
1
0.1UF
AC_OR_S0_L
D
C
1.05V ENET FET
Pull-up is with power FET.
D
3
S
4
1
10K
2
G
S
1
1
2
1%
1/16W
MF-LF
402
C3841
0.01UF
2
10%
16V
CERM
402
P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
5
B
8D2
IN
G
B
=P1V05ENET_EN
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and
=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock
Ethernet & AirPort Support
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
A
SYNC_MASTER=SUMA
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY
R3895
77D3 17C3
IN
MCP_CLK25M_BUF0_R
1
22
2
RTL8211_CLK25M_CKXTAL1
OUT
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
31B6 77D3
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to U1400
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
32
1
81
A
8
6
7
4
5
3
2
1
- COPY THIS PAGE FROM K36 CSA.39
D
D
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
1
C3900
0.1UF
10%
2 16V
X5R
402
1
C3901
0.1UF
10%
2 16V
X5R
402
1
C3902
C3903
1
ETHERNET CONNECTOR
0.1UF
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
CRITICAL
J3900
CRITICAL
77C3 31B3
77C3 31B3
BI
ENET_MDI_P<1>
BI
ENET_MDI_N<1>
T3901
SM
1
RJ45-M97-3
F-RT-TH
12
77C3
2
11
3
10
4
C
77C3
1% 1/16W
TLA-6T213HF
BI
ENET_MDI_P<3>
BI
ENET_MDI_N<3>
5
ENET_MDI_TRAN_N<1>
R3903
2 75
1
ENET_CENTER_TAP<1> 1
2
3
MF-LF 402
R3902
2 75
ENET_CENTER_TAP<3> 1
9
1% 1/16W
77C3 31B3
9
10
TX
77C3 31B3
ENET_MDI_TRAN_P<1>
MF-LF
4
8
6
77C3
ENET_MDI_TRAN_P<3>
7
8
6
7
77C3
ENET_MDI_TRAN_N<3>
RX
11
12
CRITICAL
77C3 31B3
77C3 31B3
C
5
402
BI
ENET_MDI_N<2>
1
BI
ENET_MDI_P<2>
2
T3902
SM
77C3
ENET_MDI_TRAN_N<2>
11
77C3
ENET_MDI_TRAN_P<2>
10 ENET_CENTER_TAP<2> 1
1% 1/16W
TX
TLA-6T213HF
9
BI
ENET_MDI_N<0>
5
77C3 31B3
BI
ENET_MDI_P<0>
6
MF-LF 402
R3900
2 75
ENET_CENTER_TAP<0> 1
1% 1/16W
77C3 31B3
514-0636
R3901
2 75
3
4
12
MF-LF 402
8
7
77C3
ENET_MDI_TRAN_N<0>
77C3
ENET_MDI_TRAN_P<0>
RX
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
1
B
1
C3911
10PF
5%
2 50V
CERM
402-1
CRITICAL
1
C3913
10PF
CRITICAL
1CRITICAL
C3912
CRITICAL
1
10PF
5%
50V
2 CERM
402-1
C3915
10PF
1
5%
50V
2 CERM
402-1
5%
2 50V
CERM
402-1
5%
50V
2 CERM
402-1
1
CRITICAL
1
C3916
10PF
5%
50V
2 CERM
402-1
C3910
B
1000PF
5%
2 50V
CERM
402-1
CRITICAL
C3914
10PF
CRITICAL
C3917
10PF
10%
2KV
2 CERM
1206
CRITICAL
CRITICAL
1
C3918
10PF
5%
50V
2 CERM
402-1
PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS
ETHERNET CONNECTOR
A
SYNC_MASTER=SUMA
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
33
1
81
A
8
6
7
2
3
4
5
=PP3V3_FW_FWPHY
7 mA I/O
C4120
C4121
1
1UF
PART NUMBER
D
114S0558
QTY
1
DESCRIPTION
REFERENCE DES
RES,0.68 OHM,1%,0402,SMD
R4100
CRITICAL
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
1
10%
6.3V
CERM
402
PP1V0_FW_R
2
1
10%
6.3V
CERM
402
2
1UF
2
L4130
OMIT
1
C4131
2
10%
6.3V
CERM
402
PP3V3_FW_FWPHY_VDDA
C4132
1
1UF
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
1UF
10%
6.3V
CERM
402
2
2
L4135
120-OHM-0.3A-EMI
1
120-OHM-0.3A-EMI
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
0402-LF
1
C4110
1
10%
6.3V
CERM
402
2
1UF
2
17 mA PCIe SerDes
C4111
1UF
C4135
1
10%
6.3V
CERM
402
2
C4100
1
1UF
2
10%
6.3V
CERM
402
C4101
2
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
0402-LF
1UF
10%
6.3V
CERM
402
2
0 mA VReg PWR
1
1UF
10%
6.3V
CERM
402
PP3V3_FW_FWPHY_VP25
C4136
1UF
10%
6.3V
CERM
402
110 mA Digital Core
1
D
2
0402-LF
L4110
5%
1/16W
MF-LF
402
135 mA
2
C4124
120-OHM-0.3A-EMI
R4100
=PP1V0_FW_FWPHY
10%
6.3V
CERM
402
114 mA FireWire PHY
1UF
35D3 7A1
1
1UF
BOM OPTION
CRITICAL
C4130
0
C4123
1
1UF
2
7B1 34B1 35D8 36B6 36D5
138 mA
C4122
1
1UF
10%
6.3V
CERM
402
1
C4102
1
1UF
2
10%
6.3V
CERM
402
C4103
1
1UF
2
10%
6.3V
CERM
402
C4104
1
1UF
2
C4105
1
1UF
10%
6.3V
CERM
402
2
C4106
1UF
10%
6.3V
CERM
402
2
C4141
1
1
20%
10V
CERM
402
2
2
0.1UF
10%
6.3V
CERM
402
C4140
1UF
10%
6.3V
CERM
402
C
C
VDD10
2
5%
50V
CERM
402
R4162 1
C4162
J2
L13
D12
D1
A10
H13
K13
2
J12
NC
0.33UF
2
N13
TP_FW643_OCR10_CTL
1
470K
5%
1/16W
MF-LF
402
M13
J13
K12
L9
L6
L10
L5
D6
D5
A12
M2
L11
L3
J1
D8
NT-16 (IPD) SCIFCLK
NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
CHIP RESET
NT-5 PERST*
C41751
10%
2
16V
0.1UF
X5R 402
C41761
10%
2
16V
IN
16C3
IN
16C3
16B3 75D3
IN
16B3 75D3
PCIE_FW_D2R_N
OUT
16B6 75D3
PCIE_FW_D2R_P
OUT
16B6 75D3
X5R 402
PLACEMENT_NOTE=Place C4175 close to U4000
PLACEMENT_NOTE=Place C4176 close to U4000
=PP3V3_FW_FWPHY
C2
D13
E1
D2
L2
7B1 34D2 35D8 36B6 36D5
FW643_LDO
R4165 1
=FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
=FW_CLKREQ_L
G2
G1
H1
OUT
8C2 35C8
OUT
35C4
5%
1/16W
MF-LF
402 2
1
1
R4166
10K
5%
1/16W
MF-LF
2 402
B
R4164
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
N12
IN
1
35C1
R4163
10K
OCR_CTL_V10
OCR_CTL_V12 (Reserved)
VSS
10%
6.3V
CERM-X5R
402
X5R 402
IN
PCIE_FW_R2D_C_P
MISCELLANEOUS
2
VREG_VSS
K6
3
2
1%
1/16W
MF-LF
402
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
K10
191
G13
NAND_TREE
REXT
XO
XI NT-9
L7
4
1%
1/16W
MF-LF
402
R4170
L8
F13
R0
TPCPS
K9
1
K1
FW643_TRST_L
M1
0.1UF
PCIE_FW_R2D_C_N
5%
1/16W
MF-LF
2 402
K8
R4161 1
2.94K
2
B10
N1
N2
10%
2
16V
10K
K7
SM-3.2X2.5MM
B11
TPBIAS0
TPBIAS1
TPBIAS2
K5
Y4150
24.576MHZ
2
22PF
1
NC
NC
A2
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
2
1%
1/16W
MF-LF
402
C3
K4
1
C4151
412
BI
B7
NT-2 (IPU) TRST*
POWER MANAGEMENT
NT-12 (IPD)
NT-13
J10
CRITICAL
5%
50V
CERM
402
1
36D4
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
M3
FIXME!!! - TYPO IN SYMBOL REGCTL
J9
FW_CLK24P576M_XO
2
BI
FW643_R0
FW643_TPCPS
2
R4150
22PF
1
BI
A4
J5
C4150
36D4
36C8 35A4
B4
J4
1%
1/16W
MF-LF
402
BI
H10
200K
BI
36C4
NT-4 (IPU) TCK
NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
N10
X5R 402
0.1UF
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
NT-10 (IPD)
H8
R4160 1
B
36C4
N6
0.1UF
C41711
10K
H7
=PPVP_FW_PHY_CPS
A6
B2
36C4
BI
B6
N5
PCIE_FW_R2D_N
75D3 PCIE_FW_R2D_P
75D3 PCIE_FW_D2R_C_N
75D3 PCIE_FW_D2R_C_P
75D3
M4
1394 PHY
H6
78D3 36B8
BI
A9
H4
78D3 36B8
B9
G10
BI
G8
BI
G7
BI
78D3 36C4
A3
G6
36C4
78D3 36C4
B3
N7
N9
TEST CONTROLLER
G4
BI
A5
F10
36C4
B5
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
F8
BI
A8
F7
BI
78D3 36B8
B8
F6
78D3 36B8
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
N8
REFCLKN
REFCLKP
PCI EXPRESS PHY
F4
BI
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
BGA
E9
BI
78D3 36C4
E13
E5
78D3 36C4
E12
VREG_PWR
FW643E
DS0 (IPD) NT-19
DS1 (IPD) NT-20
DS2 (IPD) NT-21
E4
IN
VP25
U4100
D10
IN
36D3
F12
VP
CRITICAL
D9
36D3
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
A11
ATBUSB
ATBUSH
ATBUSN
D7
IN
A13
D4
36D3
B13
VDDH
VDD33
10%
2
16V
5%
1/16W
MF-LF
402
L12
NC
NC
NC
G12
F1
C12
C1
N11
N3
M12
L1
K2
H12
H2
E10
E2
C13
B12
B1
A1
PLACEMENT_NOTE=Place C4170 close to U1400
PLACEMENT_NOTE=Place C4171 close to U1400
C41701
FireWire LLC/PHY (FW643)
A
SYNC_MASTER=K19_MLB
SYNC_DATE=11/02/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
34
1
81
A
8
6
7
Page Notes
@ 2.5V Vgs:
- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE
- =PPVP_FW_SUMNODE (power passthru summation node)
7B5
Signal aliases required by this page:
CRITICAL
Q4291
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
=PP3V3_S0_P3V3FWFET
35B1 7B5
R4281
1
SOT-23-HF
=PP3V3_FW_FET
2
1
R4290
BOM options provided by this page:
10K
D 3
5 G
100K
10K
35C7 35C4 35A4 18D7 18D2
IN
FW_WAKE
5
4
7C7
FWPHY_WAKE_YES
=PP3V3_S0_P1V05FWFET
DMB53D0UV
PCIE_FW_PRSNT_L
OUT
MAKE_BASE=TRUE
CRITICAL
DMB53D0UV
4
8C6 16C6
P1V0_RESET_GATE
FW_CLKREQ_L
5 G
R4283
CRITICAL
D 6
2 G
SI2312BDS
6
2 G
FW_RESET_L
S 1
R4296
P1V05_FW_EN_L
Q4293
1
5%
1/16W
MF-LF
402
D 3
P1V05_FW_EN_L_RC
34A2
1
PP1V05_FW PGOOD/FW_RESET_L
7B2
34B2
C4295
IN
=FW_CLKREQ_L
C
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
FireWire Port Power Switch
0.068UF
100K 2
OUT
S
S 1
1
24C1
SOT-563
35D6 35C7 35A4 18D7 18D2
=PP1V0_FW_FET
5%
1/16W
MF-LF
402 2
IN
DMB53D0UV
FW_PWR_EN
2
SSM6N15FEAPE
10K
S
=FW_RESET_L
Q4299
D
SOT563
1
2
SOT23
S
R42951
10K
5%
1/16W
MF-LF
402
2 G
Q4295
G
D 6
1
SOT563
CRITICAL
D
1
16C6
SSM6N15FEAPE
3
P1V05FW_SS
OUT
S 4
Q4264
20%
10V
CERM 2
402
D
Q4299
SOT-563
D 3
0.1UF
220K 2
1
Q4293
=PP3V3_S5_P1V05FWFET
FWPHY_WAKE_YES
C
3
5
1UF
C4296 1
Q4276
7A3
5%
1/16W
MF-LF
2 402
10%
6.3V 2
CERM
402
10%
16V
CERM
402
=PP1V05_FW_P1V05FWFET
5%
1/16W
MF-LF
402
SOT-563
100K
2
P1V0_FW_RC
C4281 1
1
1.05V FW FET
Q4276
6
2 G
10K
SOT563
7B1
=FW_PME_L
2
Q4264
CRITICAL
R4297
8C2
34B2
0.01UF
P3V3FW_SS
S 4
DMB53D0UV
FWPHY_WAKE_YES
D
C4291
FW_PWR_EN
SOT-563
CRITICAL
1
SSM6N15FEAPE
3
5%
1/16W
MF-LF
402 2
100K 2
=PP1V0_FW_FWPHY
1%
1/16W
MF-LF
402
35B1
R4276
1
5%
1/16W
MF-LF
2 402
3
1
5%
1/16W
MF-LF
402
SOT563
FW_PLUG_DET_L 8C1
10%
2 16V
X5R
402
R4291
SSM6N15FEAPE
FWPHY_WAKE_YES
D
G
0.033UF
1
Q4290
C4290
1
P3V3FW_EN_L
=PP3V3_FW_FWPHY
S
R4280
7B2
34D8 7A1
5%
1/16W
MF-LF
402 2
D
=PP3V3_S0_FWPWRCTL
NTR4101P
(NONE)
R42771
1
3.3V FW FET
Power aliases required by this page:
36B6
34D2
34B1
7B1
36D5
2
3
4
5
10%
2 10V
CERM
402
SSM6N15FEAPE
SOT563
5 G
35D6 35C4 35A4 18D7 18D2
S 4
FW_PWR_EN
CRITICAL
Q4260
CRITICAL
FDC638P_G
7C1
6
=PPBUS_S5_FWPWRSW
5
4
1
R4260
Q4262
DMB54D0UV
SOT-563
100K
1
C
NOSTUFF
1
R4275
40D5
20C7
32B7
41B2
Q4261
IN
SMC_ADAPTER_EN
2
G
Q4261
D
2N7002DW-X-G
SOT-363
S
5
G
70D8 66D5 40C5 32B7 20C3 6C3
=PP3V3_FW_LATEVG_ACTIVE
36A5 PP2V4_FW_LATEVG
IN
5%
1/16W
MF-LF
2 402
FW_PWR_EN_L
4
FW_PLUG_DET
FW_DET_MIRROR
PM_SLP_S3_L
3
6
5
BC847CDXV6TXG
SOT563
2
1%
1/16W
MF-LF
2 402
FWLATEGV_3V_REF
2
4
A
R4272
3
CRITICAL
1K
6
D
5%
1/16W
MF-LF
2 402
Q4275
DMB53D0UV
LMC7211
SM-HF
1
LATEVG_EVENT
V+
P2V4_FWLATEVG_RC
U4210
35D6 35C7 35C4 18D7 18D2
IN
FW_PWR_EN
1
Q4270
BC847CDXV6TXG
SOT563
C4270
C4211
100pF
5%
50V
CERM 2
402
10%
16V
2 X5R
402
R4273
12K
5%
1/16W
MF-LF
2 402
SOT-563
2 G
FireWire Port Power
SYNC_MASTER=YUN_K19_MLB
R4213
80.6K
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
1
R4210
200K 2
1%
1/16W
MF-LF
402
SYNC_DATE=12/22/2008
NOTICE OF PROPRIETARY PROPERTY
S
1
DMB53D0UV
4
1
V-
1
1%
1/16W
MF-LF
2 402
CRITICAL
Q4275
0.1UF
5
1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
FWLATEVG Hysteresis:
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
3.08V when port power is on
2.91V when late Vg event and port power is off
36C8 34B6
IN
FW_P1_TPBIAS
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
4.7.0
051-7898
SCALE
SHT
NONE
8
8C1 35D7
FW_DET_EMIT
1
20%
2 10V
CERM
402
CRITICAL
1
FW_P1_TPBIAS_R
is running or on AC.
0.1UF
10K
5
OUT
SOT-563
Q4270
Enables port power when machine
C4210
3
SOT-363
S
4
1
FW_PLUG_DET_L
56K
5%
1/16W
MF-LF
2 402
7A3
10K
R4271
330K
5%
1/16W
MF-LF
2 402
CRITICAL
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
1
R4270
1K
3
B
R4274
1
D
R4212
7B5 35D2
1
=PP1V05_FWPWRCTL
FWPWR_EN_L
6
1
7B2
3
2
G
5
B
LATEVG_FAULT_EVENT
2N7002DW-X-G
R42111
=PPBUS_S5_FW_FET
2
3
7C7
1
36C5
1
CRS08-1.5A-30V
=PP3V3_S0_FWPWRCTL
5%
1/16W
MF-LF
2 402
1UF
10%
10V
X5R 2
402
PPBUS_FW_FWPWRSW_D
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
10%
25V
X5R 2
402
470K
1%
1/16W
MF-LF
402
C4263 1
2
R4261
S
2
1
MINISMDC110H24
1
LATEVG_FAULT_EVENT_PNP
Q1
100
1
1%
1/16W
MF-LF
402
Q2
E
4
1
10K
6
R4263
LATEVG_RETRY_RC
2
D
NOSTUFF
PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
D4260
SM
FWPWR_EN_L_DIV
R4265
B
1.1A-24V
0.1UF
5%
1/16W
MF-LF
2 402
Late-VG Event Detection
2
C4260 1
300K
CRITICAL
CRITICAL
F4260
SM
OF
35
1
81
A
8
Page Notes
6
7
2
3
4
5
1
Power aliases required by this page:
36B6 35D8 34D2 34B1 7B1
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
=PP3V3_FW_FWPHY
R4382 1
R4380 1
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
10K
- =GND_CHASSIS_FW_PORT1
- =GND_CHASSIS_FW_EMI_R
D
10K
FWPHY_DS0
FireWire PHY Config Straps
Signal aliases required by this page:
(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
FWPHY_DS2
Configures PHY for:
FWPHY_DS1
- 1-port Portable Power Class (0)
34C6
R4381 1
- Port "1" Bilingual (1394B)
10K
1%
1/16W
MF-LF
402 2
34B6
34B6
78D3 34C6
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)
78D3 34B6
34B6
34B6
78D3 34B6
Termination
78D3 34B6
34B6
34B6
=PPVP_FW_PHY_CPS_FET
5%
1/16W
MF-LF
402 2
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Cable Power
PPVP_FW_CPS
MAKE_BASE=TRUE
=PPVP_FW_PHY_CPS
CRITICAL
34B7
L4310
7B1
FERR-250-OHM
=PPVP_FW_PORT1
1
"Snapback" & "Late VG" Protection
5
470K
FW_P0_TPB_N
FW_P0_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
G
R4311 1
NC_FW0_TPBIAS
NC_FW2_TPBIAS
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW2_TPAN
NC_FW2_TPAP
C
D
7B1
4
2
10%
6.3V
CERM-X5R
402
S
0.33UF
3
C4360
BSS8402DW
SOT-363
1
(SYM-VER2)
TI PHYs require 1uF even though
FW spec calls out 0.33uF
FW_P0_TPBIAS
FW_P2_TPBIAS
FW_P0_TPA_N
FW_P0_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
Q4300
Place close to FireWire PHY
C
D
34C6
=FW_PHY_DS1
MAKE_BASE=TRUE
NOTE: FireWire TPA/TPB pairs are NOT
constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
FW_P1_TPBIAS
34C6
=FW_PHY_DS2
MAKE_BASE=TRUE
BOM options provided by this page:
(NONE)
35A4 34B6
=FW_PHY_DS0
MAKE_BASE=TRUE
36A5 35A8
SM
PP2V4_FW_LATEVG
1
R4360
R4361
56.2
2
78D3 34B6
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPS_EN_L
2
C4310
FW_PORT1_TPA_P
78D3 34B6
FW_P1_TPA_N
FW_PORT1_TPA_N
78D3 34B6
FW_P1_TPB_P
FW_PORT1_TPB_P
10%
50V
X7R
402
D
36B5
MAKE_BASE=TRUE
FW_PORT1_TPB_N
1
=PP3V3_FW_FWPHY
2
G
PORT 1
3
BILINGUAL
4
S
36B5
CRITICAL
6
J4310
1394B-M97
F-RT-TH
BSS8402DW
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4362
10%
50V
X7R
402
1
36B7
SOT-363
FW_PORT1_TPB_N
9
(FW_PORT1_BREF)
36B7
1
FW_PORT1_TPB_P
NC
36B7 FW_PORT1_TPA_N
FW_PORT1_AREF
220pF
2
5%
25V
CERM
402
DP4311
C4319
CRITICAL
2
10%
50V
X7R
402
10%
50V
X7R
603-1
BAV99DW-X-G
6
1
0.01uF
INPUT
TPA(R)
TPA+
SOT-363
1
11
1
CHASSIS
GND
12
0.1uF
DP4311
4.99K
C4312
TPA<R>
TPA+
10
SOT-363
1%
1/16W
MF-LF
402 2
VG
5
BAV99DW-X-G
R4364 1
B
NCSC/NC
TPA- TPAVG
4
FW_PORT1_TPB_C
C4364
7
3
FW_PORT1_TPA_P
OUTPUT
VP
6
(GND_FW_PORT1_VG)
1%
1/16W
MF-LF
402 2
36B7
1
TPB<R>
8
56.2
1%
1/16W
MF-LF
2 402
TPB(R)
TPB-
TPB+ TPB+
VP
2
R4363 1
56.2
TPB-
1
(SYM-VER1)
MAKE_BASE=TRUE
B
CRITICAL
2
2
Q4300
36B5
36D5 35D8 34D2 34B1 7B1
5
2
SOT-363
1
0.01uF
6
36B5
MAKE_BASE=TRUE
FW_P1_TPB_N
2
PPVP_FW_PORT1_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V
BAV99DW-X-G
MAKE_BASE=TRUE
78D3 34B6
10%
50V
X7R
402
DP4310
2
FW_P1_TPA_P
1
330K
1
56.2
1%
1/16W
MF-LF
402
C4311
0.01uF
R4312 1
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
BAV99DW-X-G
SOT-363
C4314
Note: Trace PPVP_FW_PORT1 must handle up to 5A
0.01UF
DP4310
CPS_EN_L_DIV
2
13
2
5
2
C4313
10%
50V
X7R
402
3
1
0.01uF
1
2
R4319
1M
4
2
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
AREF needs to be isolated from all
local grounds per 1394b spec
514S0605
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
Late-VG Protection Power
A
7A3
=PP3V3_FW_LATEVG
R4390
1
332
FireWire Ports
SYNC_MASTER=K19_MLB
PP2V4_FW_LATEVG
1%
1/16W
MF-LF
402
3
CRITICAL
D4390
NOTICE OF PROPRIETARY PROPERTY
ESD and late-VG rail
for snap-back diodes
(Common to all ports)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MMBZ5227BLT1H
PP2V4_FWLATEVG needs to be biased
to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4390 should be 390 Ohms max for a 3.3V rail
SYNC_DATE=11/02/2008
35A8 36C5
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.4V
2
II NOT TO REPRODUCE OR COPY IT
SOT23
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
36
1
81
A
8
6
7
2
3
4
5
1
CRITICAL
Q4590
ODD Power Control
6C3 6B7
=PP3V3_S0_ODD
D
1
100K
100K
5%
1/16W
MF-LF
402
Q4596
10%
2 10V
CERM
402
R4595
ODD_PWR_EN_LS5V_L
1
D
4
0.068UF
5%
1/16W
MF-LF
402
R4597
C4595
G
R4596
100K 2
C4596
0.01UF
ODD_PWR_SS
1
5%
1/16W
MF-LF
402
D 6
5 6
S
7
37C7 7C5
1
2
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.
PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V
8
=PP5V_S3_ODD
3
7C3
TPCP8102
23V1K-SM
D
2
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
ODD_PWR_EN
Q4596
2 G
D 3
S 1
SSM6N15FEAPE
SOT563
5 G
20B3
IN
S 4
ODD_PWR_EN_L
CRITICAL
SATA ODD
FL4520
DLP11S
SYM_VER-1
4 75A3 SATA_ODD_R2D_UF_P
3
2
J4500
1 75A3 SATA_ODD_R2D_UF_N
54722-0164
=PP3V3_S0_ODD
R45901
33K
5%
1/16W
MF-LF
402 2
2
1
4
3
1
19D6 75A3
C4520
SATA_ODD_R2D_C_N
IN
19D6 75A3
2
10% 16V CERM 402
C
6
5
8
7
10
9
75A3 6B7
12
11
75A3 6B7
14
13
16
15
SATA_ODD_R2D_P
6A7 SATA_ODD_R2D_N
75A3 6B7
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
FL4525
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
C4526 1
0.01UF
C4525 1
0.01UF
90-OHM-100MA
DLP11S
SYM_VER-1
2
75A3 SATA_ODD_D2R_UF_N
10% 16V CERM 402
4
2
75A3 SATA_ODD_D2R_UF_P
10% 16V CERM 402
1
CRITICAL
3
SATA_ODD_D2R_N
2
SATA_ODD_D2R_P
OUT
19D6 75A3
OUT
19D6 75A3
PLACEMENT_NOTE=Place FL4525 close to J4500
Indicates disc presence
1
SATA HDD/IR/SIL
B
IN
75A3 6B7
SMC_ODD_DETECT
OUT
SATA_ODD_R2D_C_P
PLACEMENT_NOTE=Place FL4520 close to J4500
516S0616
40B8 6B7
C4521
2
10% 16V CERM 402
0.01UF
F-ST-SM
37D6 7C5
1
0.01UF
CRITICAL
C
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
90-OHM-100MA
C4501
1
0.1UF
20%
2 10V
CERM
402
C4502
0.1UF
CRITICAL
L4500
20%
2 10V
CERM
402
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
B
FERR-70-OHM-4A
6C3 6B7
PP5V_S0_HDD_FLT
1
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
=PP5V_S0_HDD
2
7D5
0603
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
CRITICAL
FL4502
90-OHM-100MA
L4502
CRITICAL
FERR-220-OHM
7D3
1
=PP1V5_S3_HDD
2
PP1V5_S3_HDD_FLT
0402
1
C4503
1UF
R4531
39D7 7C3
SYS_LED_ANODE
=PP5V_S3_IR
2
R4532
2
402
10
5%
MF-LF
75A3 6B7
4.7
1
402
5% 1/16W
MF-LF
1
1/16W
SYS_LED_ANODE_R
IR_RX_OUT
6A7
39D4
6A7 PP5V_S3_IR_R
6A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
75A3 6B7
SATA_HDD_D2R_C_P
C4532
1
0.1UF
2
10%
16V
X7R-CERM
402
4
SATA_HDD_D2R_N
3
OUT
19D6 75A3
OUT
19D6 75A3
2
SATA_HDD_R2D_C_N
10% 16V CERM 402
IN
19D6 75A3
2
SATA_HDD_R2D_C_P
10% 16V CERM 402
IN
C4516 1
2
1
2
75A3 SATA_HDD_D2R_UF_P
SATA_HDD_D2R_P
10% 16V CERM 402
0.01UF
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516
PLACEMENT_NOTE=Place C4516 close to J4501
CRITICAL
FL4501
90-OHM-100MA
PLACEMENT_NOTE=Place C4511 next to C4510
PLACEMENT_NOTE=Place C4510 close to MCP79
DLP11S
SYM_VER-1
75A3 6B7
SATA_HDD_R2D_N
3
4
75A3
SATA_HDD_R2D_UF_N
C4511 1
0.01UF
75A3 6B7
1
2
75A3 SATA_HDD_D2R_UF_N
10% 16V CERM 402
0.01UF
SATA_HDD_R2D_P
2
1
75A3
SATA_HDD_R2D_UF_P
PLACEMENT_NOTE=Place FL4501 close to J4501
516S0687
A
DLP11S
SYM_VER-1
C4515 1
SATA_HDD_D2R_C_N
54722-0224
F-ST-SM
10%
2 6.3V
CERM
402
PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501
41A6
J4501
C4510 1
0.01UF
SATA Connectors
SYNC_MASTER=K19_MLB
C4531
SYNC_DATE=12/04/2008
NOTICE OF PROPRIETARY PROPERTY
0.001UF
2
10%
50V
CERM
402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
37
1
81
A
8
6
7
2
3
4
5
1
D
D
Port Power Switch
USB PORT A (FRONT PORT)
PLACEMENT_NOTE=NEAR J4600
CRITICAL
CRITICAL
L4605
U4690
2
OUT
USB_EXTA_OC_L
8
OUT
USB_EXTB_OC_L
7C3
19C2
19C2
TPS2064DGN
IN
OUT1
FERR-220-OHM-2.5A
7
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
MSOP
OC1*
3
OUT2
EN1
5 OC2*
4
EN2
1
PP5V_S3_RTUSB_A_ILIM
6
C4605
PP5V_S3_RTUSB_B_ILIM
0.01uF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
20%
16V
CERM
402
2
1
C4690
1
1
10UF
20%
6.3V
X5R
603
2
2
1
10UF
20%
10V
CERM
402
20%
6.3V
X5R
603
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
J4600
PLACEMENT_NOTE=NEAR J4600
CRITICAL
USB
F-RT-TH-M97-4
5
L4600
90-OHM
6
SYM_VER-1
CRITICAL
C4695
0.1UF
CRITICAL
DLP0NS
9
C4691
1
C4696
100UF
2
20%
2 6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
C4617
1
10UF
20%
6.3V
X5R
603
1
USB_EXTA_MUXED_N
4
3
76C3
CONN_USB_EXTA_N
USB_EXTA_MUXED_P
1
2
76C3
CONN_USB_EXTA_P
20%
2 6.3V
POLY-TANT
CASE-B2-SM
76C3
3
4
2
5
3
4
7
8
514-0638
1 GND
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
=USB_PWR_EN
IN
1
2
C4616
100UF
2
76C3
6 VBUS
66B6
C
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
1
GND TPAD
NOSTUFF
2
0603
NC
IO
NC
IO
C
=PP5V_S3_EXTUSB
D4600
RCLAMP0502N
SLP1210N6
STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE)
STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)
PLACEMENT_NOTE=NEAR J4610
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1
2
0603
1
USB/SMC Debug Mux
B
0.01uF
2
7D1
C4615
20%
16V
CERM
402
CRITICAL
=PP3V42_G3H_SMCUSBMUX
J4610
USB
SMC_DEBUG_YES
C4650
1
1
10K
0.1UF
2
2
42C3 41B2 40C5 40B8
42C5 41C2 40C5 40B8
IN
DLP0NS
OUT
5 M+
4 M-
USB_EXTA_P
USB_EXTA_N
7 D+
6 D-
76B3 19C3
U4650
1
SYM_VER-1
BI
VCC
SMC_DEBUG_YES
SMC_RX_L
SMC_TX_L
6
L4610
90-OHM
5%
1/16W
MF-LF
402
9
20%
10V
CERM
402
F-RT-TH-M97-4
5
PLACEMENT_NOTE=NEAR J4610
CRITICAL
R4650
USB_EXTB_N
4
3
76B3
76B3
Y+ 1
Y- 2
76B3 19C3
BI
USB_EXTB_P
1
76C3 19D3
BI
BI
6 VBUS
CRITICAL
SEL 10
USB_DEBUGPRT_EN_L
5
3
4
8
514-0638
1 GND
IN
40B8
SEL=0 Choose SMC
SEL=1 Choose USB
D4610
3
GND
3
7
2
TQFN
8 OE*
2
4
2
PI3USB102ZLE
76C3 19D3
CONN_USB_EXTB_N
CONN_USB_EXTB_P
NC
IO
NC
IO
B
Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
RCLAMP0502N
SLP1210N6
A
External USB Connectors
CRITICAL
SMC_DEBUG_NO
SYNC_MASTER=YUAN.MA
R4651
1
0
5%
1/16W
MF-LF
402
USB PORT B (BACK PORT)
SMC_DEBUG_NO
R4652
1
0
SYNC_DATE=01/18/2008
NOTICE OF PROPRIETARY PROPERTY
2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
2
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5%
1/16W
MF-LF
402
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
38
1
81
A
8
6
7
4
5
3
2
1
37A8 7C3 =PP5V_S3_IR
1
C4801
0.1UF
2
10%
16V
X7R-CERM
402
D
16
D
76B3 19D3
BI
76B3 19D3
BI
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_P
14
USB_IR_N
15
DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
18
20
1
C4803
1UF
2
10%
10V
X5R
402-1
23
24
25
26
P1_0/D+
P1_1/DP1_2/VREG
P1_3/SSEL
P1_4/SCLK
P1_5/SMOSI
P1_6/MISO
P1_7
VDD
P0_0
P0_1
P0_2/INT0
P0_3/INT1
P0_4/INT2
P0_5/TIO0
P0_6/TIO1
P0_7
7
6
5
4
R4800
3
2
1
IR_RX_OUT_RC
1
32
U4800
21
22
P3_0
P3_1
CY7C63833
QFN
CRITICAL
OMIT
P2_0
P2_1
10
2
IR_RX_OUT
IN
6A7 37A7
C4804
0.001UF
10%
50V
CERM
402
11
28
29
1
8
2
P/N 338S0375
27
9
100
5%
1/16W
MF-LF
402
NC
NC
12
17
30
19
31
13
33
THRM_PAD VSS
C
C
CYPRESS ’ENCORE II’ USB CONTROLLER
B
B
Front Flex Support
A
SYNC_MASTER=YUAN.MA
SYNC_DATE=05/28/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
39
1
81
A
8
6
7
2
3
4
5
1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
41C6 6C2
41D8 41C7 41C3 41C1 7D1
D
PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC
D
C4902
1
1
20%
6.3V
CERM
805
2
2
22UF
IN
20B7
OUT
62C7
OUT
20C7
OUT
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
41D5
OUT
ESTARLDO_EN
41D5
41D5
SMC_P24
SMC_P26
NC
NC
NC
NC
NC
NC
C
76C3 42D5 18B3
BI
76C3 42D5 18B3
BI
76C3 42D3 18B3
BI
76C3 42D3 18B3
BI
76C3 42D5 18C3
IN
24D1
IN
76C3 24B1
42D3 18B7
IN
BI
P10
P11
P12
P13
P14
P15
P16
P17
D13
E11
D12
F11
E13
E12
F13
E10
P20
P21
P22
P23
P24
P25
P26
P27
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
A9
D9
C8
B7
A8
D8
D7
D6
NC
41D5
43B5
50B7
BI
OUT
41D5
OUT
49A6
OUT
42C5 41C2 40C5 38A8
OUT
42C3 41B2 40C5 38A8
43D6
(DEBUG_SW_1)
(DEBUG_SW_2)
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
SMC_PA0
SMC_PA1
PM_SYSRST_L
OUT
USB_DEBUGPRT_EN_L
OUT
MEM_EVENT_L
BI
41A2 SMC_PA5
SYS_ONEWIRE
BI
PM_BATLOW_L
OUT
NC
NC
(OC)
38A6
58D5
20C7
P40
P41
P42
P43
P44
P45
P46
P47
G2
F3
E4
P50
P51
P52
NC
41B2
41C6
IN
41B2
IN
OUT
37C7 6B7
47B5
OUT
41D5
OUT
41D5
OUT
41D5
OUT
47C5
IN
41B2
IN
41B2
IN
41B2
IN
50B4
IN
50B4
IN
50B4
IN
41C5
IN
41D5
IN
41D5
IN
41D5
IN
41C5
IN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
NC
OMIT
N3
N1
M3
M2
N2
L1
K3
L2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
B8
C9
B9
A10
C10
B10
C11
A11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
IN
41C5 SMC_PB3
(See below)
SMC_EXCARD_CP
IN
20C7
A
D4
A5
B4
A1
C2
B2
C1
C3
41C2
27A5 26A5 20B3 20A4
LGA-HF
(1 OF 3)
P30
P31
P32
P33
P34
P35
P36
P37
41C2
24B3
B
IN
BI
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
(OC)
H8S2117
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
G11
G13
F12
H13
G10
G12
H11
J13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
M10
N9
K10
L8
M9
N8
K9
L7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
U4900
H8S2117
LGA-HF
(2 OF 3)
OMIT
L13
K12
K11
J12
K13
J10
J11
H12
P70
P71
P72
P73
P74
P75
P76
P77
N10
M11
L10
N11
N12
M13
N13
L12
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
P80
P81
P82
P83
P84
P85
P86
A7
B6
C7
D5
A6
B5
C6
SMC_WAKE_SCI_L
P90
P91
P92
P93
P94
P95
P96
P97
J4
G3
H2
G1
H4
G4
F4
F1
PE0
PE1
PE2
PE3
PE4
PF0
K1
J3
K2
J1
K4
K5
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
M6
L5
M5
N4
L4
M4
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
N7
K8
K7
K6
N6
M7
L6
PH0
PH1
PH2
PH3
PH4
PH5
E2
F2
J2
A4
B3
C4
NC
NC
NC
NC
NC
20%
10V
CERM
402
2
0.1UF
C4906
0.1UF
20%
10V
CERM
402
PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
2
1
OUT
6C3 60C5 66D8
SMC_VCL
R4999
1
SMC_ADAPTER_EN
OUT
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
(OC)
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
41D1
IN
6A7 58C4
IN
45B1
IN
44D6
IN
41B2
IN
41D5
IN
45B1
IN
44B4
IN
45A4
IN
41B2
OUT
20C7
18B7 42D5
18C3 42D3
OUT
38A8 40B8 41C2 42C5
IN
38A8 40B8 41B2 42C3
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
C4920
1
20%
10V
CERM
402
2
AVCC
VCC
VCL AVREF
U4900
NC
E5
MD1
MD2
D1
H1
NMI
E3
ETRST
H3
AVSS
L9
H8S2117
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PINS M12
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PINS M12
IN
1
10%
6.3V
CERM-X5R
402
2
R4909 1
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
A2
XTAL
EXTAL
5%
1/16W
MF-LF
402 2
IN
41B2 41D5 58D2
IN
41B2
IN
6C3 20C3 32B7 35A5 66D5 70D8
IN
6C3 20C3 41A2 66C8
IN
41A2
IN
24B1 76A3
NOTE: P94 and P95 are shorted, P95 could be spare.
1
R4902
10K
5%
1/16W
MF-LF
2 402
SM
1
R4998
10K
5%
1/16W
MF-LF
2 402
XW4900
2
10K
SMC_MD1
IN
42C5
SMC_NMI
IN
42C3
SMC_TRST_L
IN
42D5
C
NO STUFF
1
43B5
41A3 41C2 41C7 48C3
R4901
SMC_KBC_MDE
VSS
IN
1
10K
NC
LGA-HF
(3 OF 3)
OMIT
42D3 41D6
C4907
0.47UF
0.1UF
41A6
IN
BI
PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
41A6
OUT
BI
2
5%
1/16W
MF-LF
402
20C7 32B7 35B5 41B2
IN
4.7
E1
IN
66B1
B12
A13
A12
B13
D11
C13
C12
D10
20%
10V
CERM
402
0.1UF
C4905
L11
66A4 24B8
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
2
1
B1
M1
H10
OUT
20%
10V
CERM
402
0.1UF
C4904
M12
OUT
1
D2
L3
F10
B11
C5
41D5
41D5
U4900
C4903
R4903
0
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
1
GND_SMC_AVSS
41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7
43D6
IN
41B2
IN
41B2 42D3
IN
41B2 42D3
OUT
41B2 42D5
IN
41B2 42D5
B
NC
NC
NC
SMC_SYS_LED
SMC_LID
OUT
SMC_MCP_SAFE_MODE
OUT
41C4
IN
41C6
IN
41A8
41C2 48A5 58C1
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN
BI
43C6
BI
43C6
BI
43D3
BI
43D3
BI
43C3
BI
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
43C3
OUT
41C2
OUT
41C2
OUT
41C5
41C2
NC
NC
SMC
SYNC_MASTER=T18_MLB
SYNC_DATE=06/26/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SMC_PB3:
II NOT TO REPRODUCE OR COPY IT
SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
40
1
81
A
8
6
7
2
3
4
5
1
SMC FSB to 3.3V Level Shifting
=PP3V3_S0_SMC
41A1 7C5
40A8
SMC_FAN_1_CTL
40A8
SMC_FAN_2_CTL
40A8
SMC_FAN_3_CTL
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
R5061
40C8
SMC_GFX_THROTTLE_L
SMC_IG_THROTTLE_L
40C8
ESTARLDO_EN
10K
5%
1/16W
MF-LF
5%
1/16W
MF-LF
2 402
20A4 20B3
MAKE_BASE=TRUE
41C7 41C3 41C1 40D4 7D1 =PP3V3_S5_SMC
1
100K
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect
R5060
1
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
2 402
58D2 41B2 40C5
SMC_BC_ACOK
=CHGR_ACOK
CPU_PROCHOT_BUF
59C5
D
C5000
1
1
0.1uF
20%
10V
CERM
402
U5000
2
NCP303LSN
SOT23-5-HF
5
SMC_MANUAL_RST_L
NOSTUFF
R5001
2
CD
NC
GND
1
C5001
0
SILK_PART=SMC_RST
4
NC
2
OUT
IN
1
40C8
SMC_P24
40C8
SMC_P26
TP_SMC_P24
SMC_BMON_MUX_SEL
40C8
SMC_P41
TP_SMC_P41
10%
16V
CERM
402
R5062
TO CPU
MAKE_BASE=TRUE
SMC_RESET_L
40A8
SMC_NB_CORE_ISENSE
40A8
SMC_NB_DDR_ISENSE
SMC_MCP_CORE_ISENSE
45D7
73C3 62C8 13B6 9C5
BI
MAKE_BASE=TRUE
40C3 42D3
OUT
2
SMC_MCP_DDR_ISENSE
CPU_PROCHOT_L
40A8
ALS_LEFT
SMC_CPU_FSB_ISENSE
Q5032
D
SMC_GPU_VSENSE
40D8
SMC_EXCARD_PWR_EN
SSM6N15FEAPE
41D8 41C3 41C1 40D4 7D1 =PP3V3_S5_SMC
5
1
40D8
SMC_RSTGATE_L
40B8
SMC_PB3
SOT-563
S
1
SOT563
TP_SMC_RSTGATE_L
G 2
1 S
SMC_PROCHOT
NC_SMC_PB3
4
U5001
40A5
ALS_GAIN
40A8
SMC_ANALOG_ID
40A8
ALS_RIGHT
40A5
IN
MAKE_BASE=TRUE
NC_ALS_GAIN
MAKE_BASE=TRUE
NC_SMC_ANALOG_ID
MAKE_BASE=TRUE
SOT553-5
2
SMC_ONOFF_L
48C3 41C2 41A3 40C5
S
SN74LVC1G02
4
DMB53D0UV
4
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
G
CPU_PROCHOT_L_R
SOT-563
2 G
Q5060
MAKE_BASE=TRUE
SOT563
5
D
Q5060
SSM6N15FEAPE
44D6
MAKE_BASE=TRUE
3
3
5
Q5059
6 D
45B5
SMC_MCP_VSENSE
40C5
3.3K 2
5%
1/16W
MF-LF
402
45C5
MAKE_BASE=TRUE
2
48B1 SMC_TPAD_RST_L
1
MAKE_BASE=TRUE
3
40D5
DMB53D0UV
45A5
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
0.01UF
5%
1/10W
MF-LF
603
D
MAKE_BASE=TRUE
R5000
1K
CRITICAL
OUT
6
MAKE_BASE=TRUE
1
TO SMC
SMC_PROCHOT_3_3_L
NC_ESTARLDO_EN
MAKE_BASE=TRUE
SMC_TPAD_RST
73B3 13B7 9C6
OUT
PM_THRMTRIP_L
NC_ALS_RIGHT
MAKE_BASE=TRUE
02
3
=PP3V3_S5_SMC
3
D
7D1 40D4 41C1 41C7
41D8
Q5059
SSM6N15FEAPE
SOT563
R5095
40B8
OUT
SMC_EXCARD_OC_L
0
1
SMC AVREF Supply
C
40B5
OUT
=SMC_SMS_INT
REF3333
PP3V3_S5_AVREF_SMC
SOT23-3
1
IN
OUT
2
EXCARD_OC_L
IN
10K
19C2
5%
1/16W
MF-LF
4
S
SMS_INT_L
IN
40A5
C
6C2 40D4
41D8 41C7 41C3 40D4 7D1
=PP3V3_S5_SMC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
2
1
3
C5026
0.01UF
2
2
5
IN
GND
1
G
SMC_THRMTRIP
2 402
MAKE_BASE=TRUE
VR5020
=PPVIN_S5_SMCVREF
R5010
5%
1/16W
MF-LF
402
CRITICAL
7D1
1
C5020
C5025
0.47UF
10uF
10%
6.3V
CERM-X5R
402
20%
6.3V
X5R
603
40B8
SMC_PA0
40B8
SMC_PA1
R5091
R5092
100K
1
2
100K
1
2
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
10%
16V
CERM
402
1
RADAR 5925345
1
2
SMC_LID
R5070
R5071
10K
58C1 48A5 40B5
100K
1
2
40A5
SMC_PH2
R5072
10K
1
2
48C3 41C7 41A3 40C5
2
R5011
20C3
GND_SMC_AVSS
MCP_SPKR
0
1
40C2 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7
2
SMC_MCP_SAFE_MODE
42C5 40C5 40B8 38A8
IN
40B5
42C3 40C5 40B8 38A8
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
SMC_ONOFF_L
R5073
R5074
SMC_TX_L
SMC_RX_L
10K
1
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
2
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
42D5 40B5
SMC_TMS
R5077
10K
1
2
42D5 40B5
SMC_TDO
10K
1
2
42D3 40B5
SMC_TDI
R5078
R5079
10K
1
2
42D3 40B5
SMC_TCK
R5080
10K
1
2
SMC_BC_ACOK
R5087
R5050
470K
1
2
TABLE_ALT_ITEM
353S1381
353S1912
ALL
ISL60002-33, INTERSIL
58D2 41D5 40C5
40B8
B
System (Sleep) LED Circuit
7C3
R5031
1
1
523
1%
1/16W
MF-LF
402
R5030
2
2
R5076
100K
1
2
40A8
R5051
10K
1
2
40A8
SMC_FAN_2_TACH
1
2
SMC_FAN_3_TACH
R5052
R5053
10K
40A8
10K
1
2
40C5
SMC_GPU_ISENSE
R5054
10K
1
2
40C5
SMC_NB_MISC_ISENSE
R5055
10K
1
2
40B8
R5085
R5086
SMC_ADAPTER_EN
SMC_CASE_OPEN
R5088
SMC_EXCARD_CP
40C3
SMC_XTAL
1
Y5010
5X3.2-SM
2
SOD
2SA2154MFV-YAE
SYS_LED_L_VDIV
Q5030
1
1
40C3
SMC_EXTAL
SYS_LED_ANODE
1%
1/16W
MF-LF
402 2
SMC_ONOFF_L
OUT
NOSTUFF
1
C5011
15pF
1
SILK_PART=PWR_BTN
2
R5015
40C5
NOSTUFF
1
R5016
0
0
5%
1/10W
MF-LF
603
5%
1/10W
MF-LF
603
2
40C5 41C2 41C7 48C3
2
66C8 40C5 20C3 6C3
10K
1
2
10K
1
2
100K
1
37A8
2
PM_SLP_S4_L
=PP3V3_S0_SMC
41D3 7C5
SILK_PART=PWR_BTN
R5089
SMC_PA5
10K
1
2
5%
1/16W
MF-LF
402
SMC Support
Q5032
SYNC_MASTER=YUAN.MA
D
SYNC_DATE=05/28/2008
NOTICE OF PROPRIETARY PROPERTY
6
SSM6N15FEAPE
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SOT563
IN
2
PLACE R5015,R5001 ON BOTTOM SIDE
PLACE R5016 ON TOP SIDE
40B8
OUT
R5090
PM_SLP_S5_L
SYS_LED_L
40B5
1
5%
50V
CERM
402
3
1.47K
1
20.00MHZ
CRITICAL
2
5%
50V
CERM
402
CRITICAL
2
A
10K
B
15pF
1%
1/16W
MF-LF
402
SYS_LED_ILIM
R5032
2
SMC_FAN_1_TACH
40B5
C5010
20
1
SMC_BS_ALRT_L
40D5 35B5 32B7 20C7
Debug Power "Button"
10K
40C5
=PP5V_S3_SYSLED
SMC Crystal Circuit
SMC_GFX_OVERTEMP_L
SMC_SYS_LED
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2
G
S
II NOT TO REPRODUCE OR COPY IT
1
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
41
1
81
A
8
6
7
3
4
5
2
1
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
D
42C8 42C7 7D1
7D5
76C3 40C8 18B3
BI
76C3 40C8 18B3
BI
76A3 42C5
76A3 42B5
76C3 40C8 18C3
40C5 18B7
41B2 40B5
Alternate SPI ROM Support
41C2 40C5 40B8 38A8
42D5 42C8 7D1
=PP3V3_S5_LPCPLUS
10K
C
76A3 42A5 20B3
IN
IN
OUT
IN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
D
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
24B1 76C3
BI
18B3 40C8 76C3
BI
18B3 40C8 76C3
OUT
42B7
IN
42C5 76A3
IN
42B5
BI
18B7 40C8
IN
18C3 40C5
OUT
40B5 41B2
OUT
40B5 41B2
OUT
40C3 41D6
OUT
40C1
OUT
38A8 40B8 40C5 41B2
OUT
17B7
C5114
516S0573
20%
10V
402
2 CERM
9
LPCPLUS
5%
1/16W
MF-LF
402 2
SPI_CLK_R
OUT
0.1UF
R51901
IN
IN
OUT
1
LPCPLUS
=PP3V3_S5_ROM
1
76A3 42A5 20B3
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
IN
OUT
OUT
40C1
51C6 42B5 7A3
LPC_AD<0>
LPC_AD<1>
IN
40C1
M-ST-SM
31
32
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
VCC
1 Y+
2 Y-
SPI_MOSI_R
U5110
M+ 5
M- 4
PI3USB102ZLE
TQFN
R51911
10K
CRITICAL
5%
1/16W
MF-LF
402 2
10 SEL
D+ 7
D- 6
SPI_ALT_CLK
SPI_ALT_MOSI
OUT
42D3 76A3
OUT
42D5 76A3
SPI_CLK_MUX
SPI_MOSI_MUX
OUT
42A8 51C6
OUT
42A8 51C3
C
OE* 8
3
GND
SEL HIGH OUTPUTS TO D (ON BOARD ROM)
SEL LOW OUTPUTS TO M (FRANKCARD ROM)
=PP3V3_S5_LPCPLUS
42D5 42C7 7D1
LPCPLUS
1
R5140
100K
76A3 42A5 20B3
5%
1/16W
MF-LF
402 2
20C7
76A3 20B3
OUT
IN
1 Y+
2 Y-
9
U5120
SPI_ALT_MISO
M+ 5
M- 4
TQFN
10 SEL
MAKE_BASE=TRUE
R5144
1
42A8 51C3
OUT
51C6
=PP3V3_S5_ROM
B
7A3 42C7 51C6
5%
1/16W
MF-LF
402 2
R5146
0
IN
20K
LPCPLUS_NOT
1
42D5 76A3
SPI_MLB_CS_L
OE* 8
GND
3
B
SPI_MISO_MUX
D+ 7
D- 6
CRITICAL
SPIROM_USE_MLB
IN
Pull-up on debug card
SPI_ALT_CS_L OUT 42D3
PI3USB102ZLE
=SPI_CS1_R_L_USE_MLB
BI
20%
10V
402
2 CERM
VCC
1
SPI_MISO
SPI_CS0_R_L
C5124
0.1UF
LPCPLUS
2
5%
PLACEMENT_NOTE=PLACE NEXT TO U1400
1/16W
MF-LF
402
SPI MUX BYPASS
LPCPLUS_NOT
R5156
51C6 42C5
OUT
SPI_CLK_MUX
1
0
2
5%
1/16W
MF-LF
402
51C3 42C5
OUT
SPI_MOSI_MUX
1
LPCPLUS_NOT
R5158
51C3 42B5
IN
SPI_MISO_MUX
1
0
SPI_CLK_R
IN
20B3 42C8 76A3
SPI_MOSI_R
IN
20B3 42C7 76A3
OUT
20B3 42B7 76A3
LPCPLUS_NOT
R5157
0
2
5%
1/16W
MF-LF
402
SPI_MISO
2
LPC+SPI Debug Connector
5%
1/16W
MF-LF
402
A
SYNC_MASTER=CHANGZHANG
SYNC_DATE=05/09/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
42
1
81
A
8
6
7
MCP79 SMBUS "0" CONNECTIONS
D
7C5
7C5
R5200 1
1K
U1400
(MASTER)
20C3 12B6
76B3
20C3 12B6
76B3
SMC "0" SMBus Connections
=PP3V3_S0_SMBUS_MCP_0
MCP79
5%
1/16W
MF-LF
402 2
SMBUS_MCP_0_CLK
1
R5201
1K
5%
1/16W
MF-LF
2 402
2
3
4
5
SO-DIMM "A"
SMC
J3100
(Write: 0xA0 Read: 0xA1)
U4900
(MASTER)
SMC "A" SMBus Connections
7D3
1
4.7K
=I2C_SODIMMA_SCL
26A5
40B8
SMB_0_S0_CLK
79D3
=I2C_SODIMMA_SDA
26A5
40C5
SMB_0_S0_DATA
79D3
MAKE_BASE=TRUE
R5251
4.7K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMBUS_SMC_0_S0_SCL
=PP3V3_S3_SMBUS_SMC_A_S3
R5270 1
MCP Temp
SMC
EMC1403-5: U5535
(Write: 0x98 Read: 0x99)
U4900
(MASTER)
MAKE_BASE=TRUE
=I2C_MCPTHMSNS_SCL
46B3
40A5
SMB_A_S3_CLK
79D3 6D5 6C5
=I2C_MCPTHMSNS_SDA
46B3
40A5
SMB_A_S3_DATA
79D3 6D5 6C5
27A5
=I2C_ALS_SCL
29B6
=I2C_SODIMMB_SDA
27A5
=I2C_ALS_SDA
29B6
SMC "B" SMBus Connections
=PP3V42_G3H_SMBUS_SMC_BSA
7C5
R5280 1
1
2.0K
U4900
(MASTER)
40B5
SMB_BSA_CLK
79D3 6A7
40B5
SMB_BSA_DATA
79D3 6A7
R5281
2.0K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSA_SCL
BATTERY & BIL
SMC
J6950 & J6955
(See Table)
U4900
(MASTER)
R5260 1
76B3 20C3
SMBUS_MCP_1_CLK
76B3 20C3
SMBUS_MCP_1_DATA
1
4.7K
=SMBUS_BATT_SCL
58A6 58C3
40A5
SMB_B_S0_CLK
79D3
=SMBUS_BATT_SDA
58A6 58C3
40A5
SMB_B_S0_DATA
79D3
R5261
CPU Temp
4.7K
5%
1/16W
MF-LF
402 2
EMC1403-5: U5515
(Write: 0x98 Read: 0x99)
5%
1/16W
MF-LF
2 402
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
=I2C_CPUTHMSNS_SCL
46D3
=I2C_CPUTHMSNS_SDA
46D3
MAKE_BASE=TRUE
Mikey
Battery Charger
U6860
5%
1/16W
MF-LF
2 402
C
=PP3V3_S0_SMBUS_SMC_B_S0
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
2.0K
49C1
=I2C_SODIMMB_SCL
MAKE_BASE=TRUE
R5231
49C1
=I2C_TPAD_SDA
MAKE_BASE=TRUE
J3401
(Write: 0x52 Read: 0x53)
7C5 =PP3V3_S0_SMBUS_MCP_1
1
=I2C_TPAD_SCL
ALS
MCP79 SMBUS "1" CONNECTIONS
5%
1/16W
MF-LF
402 2
SMBUS_SMC_A_S3_SDA
J3200
(Write: 0xA2 Read: 0xA3)
SMC
2.0K
SMBUS_SMC_A_S3_SCL
SO-DIMM "B"
7D1
R5230 1
TRACKPAD
J5800
(Write: 0x90 Read: 0x91)
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
SMC "Battery A" SMBus Connections
U1400
(MASTER?)
R5271
1K
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
C
MCP79
1
1K
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
D
NOTE: SMC RMT bus remains powered and may be active in S3 state
=PP3V3_S0_SMBUS_SMC_0_S0
R5250 1
1
(WRITE: 0X72 READ: 0X73)
=I2C_MIKEY_SCL
57D3
=I2C_MIKEY_SDA
57D3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ISL6258A - U7000
(Write: 0x12 Read: 0x13)
Battery
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
=SMBUS_CHGR_SCL
59C6
=SMBUS_CHGR_SDA
59C6
LED BACKLIGHT
U9701
(WRITE: ?? READ: 0X??)
B
=I2C_BKL_1_SCL
=I2C_BKL_1_SDA
B
SMC "Management" SMBus Connections
71B7
The bus formerly known as "Battery B"
71B7
7D3
=PP3V3_S3_SMBUS_SMC_MGMT
R5290 1
SMC
1
4.7K
U4900
(MASTER)
5%
1/16W
MF-LF
402
40C5
SMB_MGMT_CLK
79D3
40C8
SMB_MGMT_DATA
79D3
2
R5291
Vref DACs
4.7K
2
U2900
(Write: 0x98 Read: 0x99)
5%
1/16W
MF-LF
402
SMBUS_SMC_MGMT_SCL
=I2C_VREFDACS_SCL
25C7
=I2C_VREFDACS_SDA
25C7
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
Margin Control
U2901
(Write: 0x30 Read: 0x31)
=I2C_PCA9557D_SCL
25A8
=I2C_PCA9557D_SDA
25A8
K24 SMBUS CONNECTIONS
A
SYNC_MASTER=BEN
SYNC_DATE=04/21/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
43
1
81
A
8
6
7
4
5
3
2
1
CPU Voltage Sense / Filter
7D7
=PPVCORE_S0_CPU_VSENSE
XW5309
R5309
SM
1
2
CPUVSENSE_IN
1
4.53K
PLACEMENT_NOTE=Place near U1000 center
SMC_CPU_VSENSE
2
1%
1/16W
MF-LF
402
1
40C5
0.22UF
2
D
OUT
C5309
20%
6.3V
X5R
402
GND_SMC_AVSS
D
40C2 41B6 44B5 44C6 45A1 45A4 45B2 45B5 45C5 45D7
Place RC close to SMC
MCP Voltage Sense / Filter
7C6
=PPVCORE_S0_MCP_VSENSE
XW5359
R5359
SM
1
2
MCPVSENSE_IN
1
4.53K
PLACEMENT_NOTE=Place near U1400 center
1%
1/16W
MF-LF
402
SMC_MCP_VSENSE
2
1
OUT
41D4
C5359
0.22UF
2
20%
6.3V
X5R
402
GND_SMC_AVSS
40C2 41B6 44B5 44D6 45A1 45A4 45B2 45B5 45C5 45D7
Place RC close to SMC
C
C
PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315
NTUD3127CXXG
SOT-963
N-CHANNEL
6
D
66C1
IN
=PBUSVSENS_EN
2
PBUSVSENS_EN_L
R5316 1
100K
G
1%
1/16W
MF-LF
402
S
Enables PBUS VSense
divider when high.
1
MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=18.5V
D
5
7C1
R5385 1
27.4K
G
1%
1/16W
MF-LF
402
S
=PPBUS_G3HRS5
2
PPBUS_G3HRS5_VSENSE
3
4
2
RTHEVENIN = 4573 OHMS
P-CHANNEL
B
SMC_PBUS_VSENSE
R53151
100K
1%
1/16W
MF-LF
402
R5386
1
1
5.49K
1%
1/16W
MF-LF
402
2
PBUSVSENS_EN_L_DIV
OUT
B
40C5
C5385
0.22UF
2
2
20%
6.3V
X5R
402
GND_SMC_AVSS
40C2 41B6 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7
Place RC close to SMC
VOLTAGE SENSING
A
SYNC_MASTER=YUNWU
SYNC_DATE=02/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
44
1
81
A
8
6
7
2
3
4
5
1
MCP VCore Current Sense Filter
R5416
63D8
MCPCORES0_IMON
1
4.53K
1%
1/16W
MF-LF
402
SMC_MCP_CORE_ISENSE
2
1
41D4
C5472
0.22UF
20%
6.3V
X5R
402
2
D
OUT
D
GND_SMC_AVSS
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5
Place RC close to SMC
MCP MEM VDD Current Sense
=PP3V3_S0_MCPDDRISNS
7B5
67D1
IN
67D1
IN
P1V5_S0_KELVIN
P1V5_S0_SENSE
1
5
1
R5410
C5434
5%
1/16W
MF-LF
2 402
C
0.1uF
20%
10V
CERM
402
3
0.1UF
2
P1V5_S0_SENSE_E
Q5401
SOD
1
MCP MEM VDD Current Sense Filter
Gain: 50x
10%
16V
X5R
402
R5417
1
2SA2154MFV-YAE
CRITICAL
C5400
OPA348
SC70-5
4
0
2
U5400
R5411
P1V5_S0_SENSE_B
0
1
3
SMC_MCP_DDR_ISENSE
2
1%
1/16W
MF-LF
402
P1V5_S0_SENSE_AMP
2
5%
1/16W
MF-LF
402
4.53K
C
20%
6.3V
X5R
402
P1V5_S0_SENSE_C
GND_SMC_AVSS
R5412
41D4
0.22UF
2
1
OUT
C5435
1
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45D7
Place RC close to SMC
118
1%
1/16W
MF-LF
2 402
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE
7C5
=PP3V3_S0_CPUVTTISNS
1
R5492
0.1uF
7C1
IN
=PPCPUVCORE_VTT_ISNS_R 1
3
Place RC close to SMC
20%
3
0.5%
CRITICAL 1W
MF
0612-1
CPU VCore Load Side Current Sense / Filter
C5417
0.01
2 10V
CERM
2 =PPCPUVCORE_VTT_ISNS OUT
4
R5471
V+
402
U5402
7C2
80D3
ISNS_CPUVTT_N
5 IN-
80D3
ISNS_CPUVTT_P
4 IN+
SC70
62C7
R5418
INA213
OUT 6
CPUVTT_IOUT
1
4.53K
1
6.19K
1
SMC_CPU_ISENSE
2
1/16W
OUT
R5480
MF-LF
41D4
402
1%
1/16W
MF-LF
402
20%
6.3V
X5R
402
2
2
1
1
OUT
40C5
C5470
0.22UF
17.4K
C5436
0.22UF
GND
2
20%
6.3V
X5R
402
2
GND_SMC_AVSS
GND_SMC_AVSS
B
IMVP6_IMON
1%
SMC_CPU_FSB_ISENSE
2
1%
1/16W
MF-LF
402
REF 1
IN
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B5 45C5 45D7
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45C5 45D7
B
Place RC close to SMC
DC-IN (AMON) CURRENT SENSE
BMON CURRENT SENSE
R5481
IN
PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)
7D1
BMON_ENG
C5418
20%
10V
REGULATOR SIDE
402
3
0.1uF
2 CERM
NC7SB3157P6XG
SC70
1 B1
SEL 6
BMON_INA_OUT
2 GND
BMON_ENG
U5403
80D3 59B3
80D3 59B3
OUT
IN
CHGR_CSO_R_P
CHGR_CSO_R_N
LOAD SIDE
SC70
4 IN+
1
40C5
0.22UF
2
C5459
OUT
C5487
20%
6.3V
X5R
402
GND_SMC_AVSS
20%
10V
40C2 41B6 44B5 44C6 44D6 45A4 45B2 45B5 45C5 45D7
2 CERM
SMC_BMON_MUX_SEL
IN
402
41D4
VCC 5
R5401
0
OUT
6
59C5
IN
3
CHGR_BMON
4
B0 BMON_ENG
REF 1
BMON_PROD
BMON_AMUX_OUT
A
VER 1
1 BMON_ENG
R5423
R5431
100K
0
GND
2
A
5 IN-
SMC_DCIN_ISENSE
2
1
V+
INA213
4.53K
0.1uF
U5413
BMON_ENG
1
1
1%
1/16W
MF-LF
402
=PP3V42_G3H_BMON_ISNS
1
CHGR_AMON
5%
1/16W
MF-LF
402
NOTE: MONITORING CURRENT FROM
BATTERY TO PBUS (BATTERY DISCHARGE)
ACROSS R7008
2
5%
1/16W
MF-LF
402
1
4.53K
1%
1/16W
MF-LF
402
SMC_BATT_ISENSE
2
1
OUT
40C5
C5490
Current Sensing
0.22UF
2
20%
6.3V
X5R
402
GND_SMC_AVSS
SYNC_MASTER=YUNWU
SYNC_DATE=12/17/2008
NOTICE OF PROPRIETARY PROPERTY
40C2 41B6 44B5 44C6 44D6 45A1 45B2 45B5 45C5
45D7
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PLACE R5491 AND C5390 CLOSE TO SMC
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
INA213 has gain of 50V/V
For engineering, stuff U5313 and unstuff R5330
For production, stuff R5330 and unstuff U5313
PLACE U5403 AND C5418 NEAR R7008
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
45
1
81
A
8
6
7
3
4
5
2
1
CPU T-Diode Thermal Sensor
7C5
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
R5515
=PP3V3_S0_CPUTHMSNS
47
1
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
D
80D3 9C6
1
VDD
1
C5521
DETECT CPU DIE TEMPERATURE
0.0022uF
10%
50V
CERM
402
80D3 9C6
80D3
Q5501
D
R5517
10K
2
2
5%
1/16W
MF-LF
402
DFN
2 DP1
THERM*/ADDR
CRITICAL
3 DN1
ALERT*
7
CPUTHMSNS_THERM_L
8
CPUTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
43C1
5 DN2/DP3
GND
6
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
43C1
THRM_PAD
11
SIGNAL_MODOL=EMPTY
1
PLACEMENT NOTE: PLACE U5515 NEAR CPU
C5520
1
0.0022uF
BC846BMXXH
SOT732-3
1
10K
1%
1/16W
MF-LF
402
20%
10V
CERM
402
CPUTHMSNS_D2_P
3
DETECT FIN-STACK TEMPERATURE
2
CPU_THERMD_N
BI
2
EMC1413
SIGNAL_MODOL=EMPTY
R5516 1
C5515
0.1uF
U5515
CPU_THERMD_P
BI
1
10%
50V
CERM
402
2
80D3
2
CPUTHMSNS_D2_N
C
C
MCP T-Diode Thermal Sensor
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
7C5
R5535
=PP3V3_S0_MCPTHMSNS
47
1
PP3V3_S0_MCPTHMSNS_R
2
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
80D3 20C3
BI
1
VDD
C5522
B
80D3 20C3
BI
2
EMC1413
SIGNAL_MODOL=EMPTY
1
0.0022uF
10%
50V
CERM
402
2
MCP_THMDIODE_N
CRITICAL
2 DP1
C5535
R5536 1
0.1uF
U5535
MCP_THMDIODE_P
DETECT MCP DIE TEMPERATURE
1
DFN
20%
10V
CERM
402
10K
1%
1/16W
MF-LF
402 2
1
R5537
10K
5%
1/16W
MF-LF
2 402
THERM*/ADDR
7
MCPTHMSNS_THERM_L
3 DN1 CRITICAL ALERT*
8
MCPTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
9
=I2C_MCPTHMSNS_SDA
BI
43D3
5 DN2/DP3
GND
6
SMCLK
10
=I2C_MCPTHMSNS_SCL
BI
43D3
THRM_PAD
11
B
J5590
78171-0002
M-RT-SM
NOSTUFF
3
80D3 6C7
MCPTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
DETECT HEAT-PIPE TEMPERATURE
C5540
1
1
PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
2
10%
50V
NOSTUFFCERM
2
402
4
80D3 6C7
MCPTHMSNS_D2_N
REPLACED 518S0521 WITH 518S0519
Thermal Sensors
A
SYNC_MASTER=YUNWU
SYNC_DATE=03/20/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
46
1
81
A
8
7
6
3
4
5
2
1
D
D
7D5
7C5
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
R5660 1
C
47K
5%
R5665
40A8
1/16W
MF-LF
402
CRITICAL
J5601
78171-0004
M-RT-SM
NC 5
2
1
2
3
4
147K2 FAN_RT_TACH
SMC_FAN_0_TACH
6D7
5%
1/16W
MF-LF
402
NC
R5661 1
6
518S0521
SSM3K15FV
D
3
SMC_FAN_0_CTL
5V DC
TACH
MOTOR CONTROL
GND
SOD-VESM-HF
2
40B8
Q5660
G
2
S
1/16W
MF-LF
402
1
100K
5%
C
6D7
FAN_RT_PWM
B
B
Fan
A
SYNC_MASTER=CHANGZHANG
SYNC_DATE=01/18/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
47
1
81
A
6
7
PSOC USB CONTROLLER
PIN NAME
CURRENT
R_SNS
V_SNS
POWER
10UA
2.55 KOHM
0.0255 V
0.255E-6 W
0.204 V
16.32E-6 W
D
V+
3V3 LDO
VDD
60MA MAX
10 OHM
VOUT
60MA MAX
0.2 OHM
0.012 V
1.5 OHM
0.012 V
96E-6 W
0.021 V
294E-6 W
PSOC
VDD
18V BOOSTER
VIN
8MA (TYP)
0.6 V
14MA (MAX)
PP3V3_S3_PSOC
49C1 6C5
49C3 6C5
49C3 6C5
49C3 6C5
49C3 6C5
C
APN 518S0637
NC
36E-3 W
4.7 OHM
0.0188 V
75.2E-6 W
45
43
44
OMIT
R5714
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
42
WS_KBD17 6B5 48C2
WS_KBD16N 48C3
WS_KBD15_C 48D3
WS_KBD14 6B5 48C2
WS_KBD13 6B5 48D2
WS_KBD12 6B5 48D2
WS_KBD11 6B5 48D2
WS_KBD10 6B5 48D2
WS_KBD9 6B5 48D2
WS_KBD8 6B5 48D2
WS_KBD7 6B5 48D2
WS_KBD1 6B5 48D2
WS_KBD2 6B5 48D2
WS_KBD3 6B5 48D2
41
40
39
38
37
36
35
34
33
32
31
30
29
48C6
WS_KBD15_C
1
R5715
48C6
WS_KBD16N
10K
1
2
1%
1/16W
MF-LF
402
41C7 41C2 41A3 40C5
OUT
SMC_ONOFF_L
C5710
0.1UF
2
ISOLATION CIRCUIT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
C
3
2
1
NC
PLACEMENT_NOTE=NEAR J5713
31
F-RT-SM
FF14-30A-R11B-B-3H
C5725
6B5 48D2
0.1UF
6B5 48D2
=PP3V42_G3H_TPAD
TP_ISSP_SDATA_P1_0
48D2 48B5 48A6 7C3
6C5 49C3
48C2 48B3 6A5
=PP3V3_S3_TPAD
2
WS_LEFT_SHIFT_KBD
1
5
TC7SZ08AFEAPE
SOT665
A
2
1
SMC_MANUAL_RESET LOGIC
20%
10V
CERM
402
CRITICAL
ISSP SDATA/I2C SDA
Z2_CLKIN
20%
10V
CERM
402
D
30
WS_KBD1
48C6 6B5 WS_KBD2
48C6 6B5 WS_KBD3
WS_KBD4
48C6 6B5
48C6 6B5 WS_KBD5
48C6 6B5 WS_KBD6
48C6 6B5 WS_KBD7
48C6 6B5 WS_KBD8
48C6 6B5 WS_KBD9
48C6 6B5 WS_KBD10
48C6 6B5 WS_KBD11
48C6 6B5 WS_KBD12
48C6 6B5 WS_KBD13
48C6 6B5 WS_KBD14
6B5 WS_KBD15_CAP
6B5 WS_KBD16_NUM
48D6 6B5 WS_KBD17
48D7 6B5 WS_KBD18
48D7 6B5 WS_KBD19
48D7 6B5 WS_KBD20
48D7 6B5 WS_KBD21
48D7 6A5 WS_KBD22
R5710
48D7 6A5 WS_KBD23
1K
1
2
6A5 WS_KBD_ONOFF_L
5%
48C5 48C3 48B5 7D1 =PP3V42_G3H_TPAD
1/16W
WS_LEFT_SHIFT_KBD
MF-LF
48B5 48B3 6A5
402
48B5 48B3 6A5 WS_LEFT_OPTION_KBD
48B5 48B3 6A5 WS_CONTROL_KBD
6B5 48D2
48C3 48C2 48B5 7D1
TP_PSOC_P1_3
2
1%
1/16W
MF-LF
402
57
WS_KBD4
WS_KBD5
WS_KBD6
TP_PSOC_SDA
470
1
TP_PSOC_SCL
=PP3V3_S3_TPAD
IN
48C6 6B5
4MA (MAX)
32
0.72E-3 W
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
46
47
48
49
50
51
52
53
54
APN 337S2983
P7_7
P7_0
25
P1_0
26
P1_2
27
P1_4
28
P1_6
49C1 6C5
J5713
24
49C1 6C5
MLF
(SYM-VER2)
23
49C1 6C5
CY8C24794
22 VDD
49C1 6C5
U5701
21 D-
49C3 6C5
TP_P4_5
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
CRITICAL
20 D+
NC
P2_3
2
P2_1
3
P4_7
4
P4_5
5
P4_3
6
P4_1
7
P3_7
8
P3_5
9 P3_3
10
P3_1
11
P5_7
12
P5_5
13
P5_3
14
P5_1
19 VSS
49C1 6C5
1
WS_CONTROL_KEY
Z2_KEY_ACT_L
15 P1_7
48B4
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
56
48B4
55
48C4
18 P1_1
49C3 6C5
17 P1_3
48A5
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
16 P1_5
49C1 6C5
48A8 48B6
CRITICAL
TMP102
80UA
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
1
KEYBOARD CONNECTOR
IC
USB INTERFACES TO MLB
SPI HOST TO Z2
2
3
4
5
48C5 48B5 48A6 7C3
8
48C5 48C2 48B5 7D1
WS_LEFT_SHIFT_KEY 48D8
4
U5725 Y
=PP3V42_G3H_TPAD
1
C5758
0.1UF
B
10%
16V
2 X7R-CERM
3
402
TP_P7_7
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
C5726
=PP3V42_G3H_TPAD
48C5 48C3 48C2 48B5 7D1
USB_TPAD_P
76B3 19D3
76B3
24
1
2
48D2 48C5 48B5 48A6 7C3
PP3V3_S3_PSOC
5%
B
TO MLB CONNECTOR
2
48A8 48D7
48C2 48B3 6A5
WS_LEFT_OPTION_KBD
CRITICAL
TC7SZ08AFEAPE
SOT665
A
5
WS_LEFT_OPTION_KEY
4
U5726 Y
1
20%
10V
CERM
402
48C2 48B5 6A5
48D8
B
48C2 48B5 6A5
48C2 48B5 6A5
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
1 A
3 B
6
CRITICAL
SN74LVC1G10
SC70
U5703 Y
4
41C7
SMC_TPAD_RST_L
C
3
B
2
R5702
USB_TPAD_N
76B3 19D3
=PP3V3_S3_TPAD
5
USB_TPAD_R_P
1/16W
MF-LF
402
1
APN 311S0406
DIFFERENTIAL_PAIR=USB2_TPAD
R5701
0.1UF
2
76B3
24
1
2
USB_TPAD_R_N
C5727
5%
1/16W
MF-LF
402
=PP3V42_G3H_TPAD
48C5 48C3 48C2 48B5 7D1
DIFFERENTIAL_PAIR=USB2_TPAD
48D2 48C5 48B5 48A6 7C3
48C2 48B3 6A5
=PP3V3_S3_TPAD
2
WS_CONTROL_KBD
1
5
CRITICAL
TC7SZ08AFEAPE
SOT665
A
U5727 Y
1
0.1UF
2
5%
20%
10V
CERM
402
2
WS_CONTROL_KEY
4
R5769
33K
1
1/16W
MF-LF
402
1
1
R5770
33K
R5771
33K
5%
1/16W
MF-LF
2 402
2
5%
1/16W
MF-LF
402
48D8
B
3
U5701 CHIP DECOUPLING
Alternate Parts
PLACE C5701, C5702 & C5703
CLOSE TO U5701 VDD PIN 22
PLACE C5704, C5705 & C5706
CLOSE TO U5701 VDD PIN 49
TABLE_ALT_HEAD
TPAD BUTTONS DISABLE
R5704
48B6
48D7
PP3V3_S3_PSOC
1
C5701
1
4.7UF
2
20%
6.3V
X5R
603
1
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
C5702
1
100PF
2
5%
50V
CERM
402
C5703
1
0.1UF
2
10%
16V
X7R-CERM
402
C5704
1
100PF
2
5%
50V
CERM
402
C5705
0.1UF
2
10%
16V
X7R-CERM
402
1
C5706
1.5
2
=PP3V3_S3_TPAD
48D8
BUTTON_DISABLE
7C3 48B5 48C5 48D2
5%
1/16W
MF-LF
402
4.7UF
PART NUMBER
ALTERNATE FOR
PART NUMBER
311S0406
311S0447
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
ALL
NXP PART AS ALTERNATE
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
Q5701
20%
6.3V
2 X5R
SSM3K15FV
603
WELLSPRING 1
D 3
SOD-VESM-HF
A
SYNC_MASTER=YUAN.MA
1
SMC_LID
58C1 41C2 40B5
IN
G
S 2
SYNC_DATE=04/22/2008
NOTICE OF PROPRIETARY PROPERTY
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
48
1
81
A
8
6
7
2
3
4
5
1
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
APN 152S0504
D
49B6 7C3
=PP5V_S3_TPAD
CRITICAL
D5802
2
0
5%
1/16W
MF-LF
402
R5806
SOD-323
INPUT_SW
BOOST_SW
VLF3010AT-SM-HF
0.50MM
0.20MM
MIN_NECK_WIDTH=0.20MM
2
39PF
APN 516S0689
CRITICAL
J5800
55560-0228
3
0.1UF
DO
20%
10V
CERM
402
2
5
CTRL
2
1
C5816
2.2UF
10%
16V
X7R-CERM
402
10%
16V
X5R
603
2
PAD
C5817
0.1UF
9
1
Z2_BOOST_EN
6C5 49C3
10%
25V
X5R
603-1
R5813
71.5K
1
48C8 6C5
4
3
48C8
6
5
8
7
10
9
12
11
14
13
48C8
48C8
1%
1
1/16W
R5811
49C5
MF-LF
2
100K
402
48D8
1%
1/16W
MF-LF
402
2
M-ST-SM
2
48C8
1
8
SW
6 GND
THRML
0.50MM
0.20MM
C5819
1UF
BOOST_FB
4
FB
CRITICAL
PLACEMENT_NOTE=NEAR J5800
7 PGND
2
1
TPS61045
QFN
IPD FLEX CONNECTOR
6C3 6C5 49C1
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
2
APN 353S1401
U5805
C5800
PP18V5_S3
R5812
1M
VIN
1
2
402
1
C5818
1
L
0
5%
1/16W
MF-LF
APN 371S0313
PP5V_S3_BOOSTER
1
1
B0520WSXG
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP18V5_S3_SW
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
1
R5805
D
CRITICAL
L5801
3.3UH-870MA
Z2_CS_L
6C5 Z2_DEBUG3
6C5 Z2_MOSI
6C5 Z2_MISO
6C5 Z2_SCLK
6C5 Z2_BOOST_EN
6C5 Z2_HOST_INTN
48C6 6C5
49B4 6C5 6C3
16
15
NC 18
17
Z2_CLKIN
20
19
PP3V3_S3_LDO
22
21
0.50MM
0.20MM
0.50MM
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
PP18V5_S3
6C5 48C8
6C5 48C8
6C5 48C8
6C5 48D8
6C5 48C8
6C5 48C8
6C5 48C8
43D1
43D1
6C3 6C5 49D3
0.20MM
C
C
3V3 LDO FOR IPD
49D7 7C3
=PP5V_S3_TPAD
R5873
1
10
PP5V_S3_VR
2
1%
1/16W
MF-LF
402
49C3 6C5 6C3
PP3V3_S3_LDO
2.2UF
16V
2 X5R
1
CE
1%
1/6W
MF
402-HF
0.2
MM3243DRRE
MLF
10%
1
2
C5854
4.7UF
10%
GND
16V
X7R-CERM
402
2
20%
6.3V
X5R
603
B
4
B
C5838
0.1UF
PP3V3_S3_LDO_R
3
VOUT
603
1
1
VDD
VR5802
C5853
R5836
2
1
2
CRITICAL
APN 353S1364
KEYBOARD BACKLIGHT DRIVNG AND DETECTION
7C5
=PP3V3_S0_TPAD
7D5
KB_BL
CRITICAL
=PP5V_S0_KBDLED
APN 518S0691
L5850
10UH-0.58A-0.35OHM
R5853 1
470K
5%
1/16W
MF-LF
402
LOW = keyboard backlight present
2
A
1UF
10%
10V
X5R
402-1
SMC_SYS_KBDLED
KB_BL
4.7K
5%
1/16W
MF-LF
402 2
F-RT-SM
SMC_KDBLED_PRESENT_L
1
2
2
CTRL
NO STUFF
U5850
R5852 1
LT3491
SW
3
LED
5
3
1
KB_BL
SYNC_MASTER=YUAN.MA
1%
CAP
2
THRML
PAD
4
SYNC_DATE=05/09/2008
NOTICE OF PROPRIETARY PROPERTY
1/16W
2
2
WELLSPRING 2
R5855
MF-LF
GND
4
6A5 KBDLED_ANODE
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
10
DFN
10K
5%
1/16W
MF-LF
402
J5815 pin 1 is grounded
on keyboard backlight flex
FF18-4A-R11AD-B-3H
49A6 6A5
KB_BL
CRITICAL
R5854 1
R5853 ALWAYS PRESENT
J5815
VIN
6
40C8
BOM OPTION: KBDLED_YES
TURNED ON FOR BEST MLB CONFIG
1
KB_BL
CRITICAL
KBDLED_SW
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
1098AS-SM
KB_BL
C5850
HIGH= keyboard backlight not present
IN
2
KBD BACKLIGHT CONNECTOR
402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
KBDLED_CAP
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
7
tristate SMC_SYS_KBDLED:
1
1
To detect Keyboard backlight, SMC will
KB_BL
C5855
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1UF
2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10%
35V
X5R
603
SIZE
SMC_KDBLED_PRESENT_L
DRAWING NUMBER
D
49A4 6A5
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
49
1
81
A
8
6
7
2
3
4
5
1
D
D
C
C
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
7C3
=PP3V3_S3_SMS
14
1
R59211
B
40C8
IN
SMS_ONOFF_L
2
Desired orientation when
20%
4V
X5R
603
placed on board top-side:
AP344ALH
B
LGA
SMS_PWRDN
MAKE_BASE=TRUE
C5926
10UF
10%
2 16V
X5R
402
U5920
5%
1/16W
MF-LF
402 2
1
0.1UF
VDD
10K
C5922
SMS_SELFTEST
1 FS
VOUTX 12
5 PD CRITICAL
VOUTY 10
2 ST
VOUTZ 8
1
R5922
10K
NC
NC
NC
3 NC
6 NC
9 NC
OUT
40A8
SMS_Y_AXIS
OUT
40A8
SMS_Z_AXIS
OUT
40A8
+Y
Front of system
+X
+Z (up)
GND
NC 11 NC
NC 13 NC
NC 16 NC
1
C5923
0.01UF
10%
2 16V
CERM
402
7
2
5%
1/16W
MF-LF
402
NC
15 RES
4 RES
SMS_X_AXIS
1
C5924
0.01UF
10%
2 16V
CERM
402
1
C5925
0.01UF
Circle indicates pin 1 location when placed
in correct orientation
10%
2 16V
CERM
402
SMS
SYNC_MASTER=YUNWU
A
SYNC_DATE=06/26/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
50
1
81
A
8
6
7
2
3
4
5
1
D
D
=PP3V3_S5_ROM
NO STUFF
R61901 R61001
C
10K
R6150
42C5 42A8
IN
SPI_CLK_MUX
PLACEMENT_NOTE=PLACE CLOSE TO U6100
42B5
IN
0
1
SPI_MLB_CS_L
3.3K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
2
76A3
1
R6101
3.3K
C6100 1
8
42C7 42B5 7A3
20%
10V
CERM 2
402
SPI_CLK
5%
1/16W
MF-LF
402
U6100
32MBIT
6 SCLK
R6152
SOP
SI/SIO0 5
MX25L3205DM2I-12G
1 CE*
SPI_WP_L
SPI_HOLD_L
C
CRITICAL
VCC
0.1UF
5%
1/16W
MF-LF
2 402
SO/SIO1 2
SPI_MOSI
1
R6105
OMIT
3 WP*/ACC
7
76A3
76A3
HOLD*
SPI_MISO_R
NO STUFF
1
R6191
10K
GND
1
0
5%
1/16W
MF-LF
402
2
0
5%
1/16W
MF-LF
402
2
SPI_MOSI_MUX
IN
42A8 42C5
PLACEMENT_NOTE=PLACE CLOSE TO U6100
SPI_MISO_MUX
OUT
42A8 42B5
PLACEMENT_NOTE=PLACE CLOSE TO U6100
4
5%
1/16W
MF-LF
2 402
MCP79 SPI Frequency Select
Frequency
B
SPI_MOSI
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
B
25MHz is selected with R5190 and R5191
Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191
SPI ROM
A
SYNC_MASTER=CHANGZHANG
SYNC_DATE=05/02/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
51
1
81
A
8
6
7
2
3
4
5
1
AUDIO CODEC
APPLE P/N 353S2355
L6201
U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL
FERR-220-OHM
7B6
=PP1V8_S0_AUDIO
IN
1
=PP5V_S3_AUDIO
0402
C6210
D
1
1
4.7UF
20%
4V
X5R-1
402
=PP3V3_S0_AUDIO
C6211
0.1UF
PP4V5_AUDIO_ANALOG
10%
2 16V
X5R
402
2
C6216
C6218
10UF
1
1
10UF
20%
6.3V
X5R
603-1
R6210
1
2.67K
10UF
2
20%
6.3V
X5R
603-1
2
CRITICAL
1%
1/16W
MF-LF
2 402
VBIAS_DAC
CS4206_FP
CS4206_FN
14
15
13
SENSE_A
45
43
42
FLYP
FLYC
FLYN
29
56A7
OUT
2
54C5
OUT
12
57D8
IN
AUD_SENSE_A
CS4206_FLYP
CS4206_FLYC
C6222
1
20%
6.3V
CERM
402-LF
2
1
2.2UF
C6223
2.2UF
2
20%
6.3V
CERM
402-LF
CS4206_FLYN
C
76B3 20D2
IN
HDA_BIT_CLK
76B3 20D2
IN
HDA_SYNC
R6211
76A3 20D7
HDA_SDIN0
OUT
76A3 20D2
IN
76A3 20D2
IN
1
HDA_SDOUT
HDA_RST_L
TP_AUD_SPDIF_IN
NC
39
AUD_SDI_R
2
1
VL_IF
6
BITCLK
11
47
48
AUD_SPDIF_OUT_CHIP
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2CRITICAL
2
10UF
MIN_LINE_WIDTH=0.30MM
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM
39
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
AUD_CODEC_MICBIAS
VCOM
28
LINEIN_L+
LINEIN_CLINEIN_R+
22
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
VREF+_ADC
27
CS4206_VREF_ADC
NC
4
TP_AUD_DMIC_CLK
NC
SDI
SDO
RESET*
SPDIF_IN
SPDIF_OUT
IN
=PP3V3_S0_AUDIO
U6200
TPS71745
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
2
4V5_REG_IN
6 IN
4V5_REG_EN
4 EN
0402
R6200
57D3 57B8 56D8 52D2 7C5
2.21K2
C6200
NR/FB 3
2
1UF
10%
2 10V
X5R
402
1
C6201
54B7
IN
56D3
NC
NC
OUT
55B7
OUT
55B7
OUT
55B7
OUT
55A7
OUT
55C7
OUT
55C7
OUT
57C4
FR SPKR AMP. SIG. SOURCE
LFT. SPKR AMP. SIG. SOURCE
RT. SPKR AMP. SIG. SOURCE
AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R
IN
53C3
IN
53B3
IN
53B3
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
IN
57C3
IN
57C3
IN
57B4
IN
57B4
EXT MIC CODEC INPUT
BI MIC CODEC INPUT
1
C6225
NOSTUFF
10UF
R6213
1
20%
2 16V
TANT-POLY
2012-LLP
100K
5%
1/16W
MF-LF
2 402
B
NOTES ON CODEC I/O
OUT
DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
6C2 52D2 52D7
4V5_NR
NC 5
C6202
0.1UF
1UF
XW6200
SM
PP4V5_AUDIO_ANALOG
1
OUT
CRITICAL
GND
1
54C7
OUT
C
23
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V
SON
1
1%
1/16W
MF-LF
402
OUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GND_AUDIO_CODEC
1
52A5 52B7 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1
DGND THRM_PAD AGND
7
=PP5V_S3_AUDIO
52A5 52D7 54C4 54C7 56D2
CS4206_VCOM
21
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2456
IN
AUD_HP_PORT_REF
31
30
32
33
B
56B6 54D5 52D2 7C3
AUD_HP_PORT_L
AUD_HP_PORT_R
TP_AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_N_R
20%
16V 2
TANT
0603-SM
L6200
10UFCRITICAL
20%
6.3V
2 X5R
603-1
35
34
36
37
16
D
6C2 52A5 52D7
C6213
GND_AUDIO_HP_AMP
GND_AUDIO_CODEC
38
40
1UF
FERR-220-OHM
1
10%
16V
X5R 2
402
20%
2 16V
TANT-POLY
2012-LLP
C6224 1
57D1 57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52A5
1
0.1UF
10%
16V 2
X5R
402
MICBIAS
DMIC_SCL
5%
1/16W
MF-LF
402
10%
C6217 10V
X5R
402-1
IN
SYNC
39
AUD_SPDIF_OUT
OUT
VL_HD
8
5
R6212
56D3
3
10
5%
1/16W
MF-LF
402
U6201
1
C6215 1 C6214
0.1UF
7C5 52A8 56D8 57B8 57D3
26
GPIO1 = HP AMP CONTROL
VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206ACNZC HPREF
QFN
GPIO0/DMIC_SDA1 LINEOUT_L1+
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2
GPIO2
LINEOUT_R1+
GPIO3
LINEOUT_R1-
44
41
AUD_GPIO_0
AUD_GPIO_1
TP_AUD_GPIO_2
NC
GPIO3 = SPKR AMP SHDN CONTROL 55C7 OUT AUD_GPIO_3
GPIO0 = ANALOG SW CONTROL
10%
16V 2
X5R
402
25
C6220
46
C6221
24
IN
1
0.1UF
49
52D2 52A5 6C2
20%
16V 2
TANT-POLY
CRITICAL 2012-LLP
9
GND_AUDIO_HP_AMP
PP4V5_AUDIO_ANALOG
1
1UF
C6219 1
56D2 54C7 54C4 52D2 52A5
7C3 52A8 54D5 56B6
PP1V8_S0_AUDIO_DIG
2
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
1
10%
16V
X7R-CERM 2
402
10%
10V
2 X5R
402
1
C6203
1UF
10%
2 10V
X5R
402
GND_AUDIO_CODEC
AUDIO: CODEC/REGULATOR
52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1
NOSTUFF
A
R6201
0
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
XW6201
SM
1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
2
II NOT TO REPRODUCE OR COPY IT
GND_AUDIO_HP_AMP
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
52D2 52D7 54C4 54C7 56D2
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
A
NOTICE OF PROPRIETARY PROPERTY
5%
1/16W
MF-LF
402
4.7.0
OF
52
1
81
8
6
7
2
3
4
5
1
D
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)
FC_HP = 3.6 HZ
FC_LP = 43KHZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6301
R6301
56B7
AUD_LI_L
IN
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
C
7.87K
2.2UF
AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1%
1/16W
MF-LF
402
20%
10V
X5R-CERM
402
NOSTUFF
C6303
R6302
10%
50V
CERM
402
1%
1/16W
MF-LF
402
820PF
AUD_LI_P_L
52C2
OUT
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
C
21.5K
CRITICAL
C6302
2.2UF
20%
10V
X5R-CERM
402
56D2
IN
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
AUD_LI_GND
AUD_LI_REF
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
52C2
1
R6300
10
CRITICAL
1%
1/16W
MF-LF
2 402
57D1 57C8 57C3 57B8 57B4 57A8 56A7 52D2 52B7 52A5
IN
C6312
2.2UF
GND_AUDIO_CODEC
20%
10V
X5R-CERM
402
NOSTUFF
C6313
820PF
10%
50V
CERM
402
B
R6312
B
21.5K
1%
1/16W
MF-LF
402
CRITICAL
C6311
R6311
56A7
IN
AUD_LI_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
7.87K
1%
1/16W
MF-LF
402
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
2.2UF
20%
10V
X5R-CERM
402
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
52C2
AUDIO: LINE INPUT FILTER
A
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
53
1
81
8
6
7
2
3
4
5
1
FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL
RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).
D
D
L6520
FERR-120-OHM-1.5A
=PP5V_S3_AUDIO
HP/LO AMP
APN: 353S1637
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
AUD_PP5V_F
56B6 52D2 52A8 7C3
0402-LF
C6520
C6521
NO STUFF
10%
16V
X7R-CERM
402
20%
6.3V
X5R
603
0
10UF
R6521
5%
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
12
0.1UF
AUD_LO_AMP_INL_M
AUD_HP_PORT_L
0
1
1
10%
16V
X7R-CERM
402
2
0.1UF
NC
C
AUD_HP_ZOBEL_L
OUT
AUD_GPIO_1_R
5 SHDN*
R6522
NO STUFF
CRITICAL
C6501
100K
R65001
56D2 54C4 52D7 52D2 52A5
IN
OUT
54B1 56B7
CRITICAL
C6524
1UF
MAX9724_C1N
C6522
1UF
10%
10V
X5R
402
GND_AUDIO_HP_AMP
56D2 54C7 52D7 52D2 52A5
2
54B1 56B7
MAX9724_C1P
C1P 1
C1N 3
CRITICAL
2
39
5%
1/16W
MF-LF
402
AUD_LO_AMP_OUTR
OUT
10%
10V
X5R
402
MAX9724_SVSS
5%
1/16W
MF-LF
402
1
0.0022UF
10%
50V
CERM
402
MAX9724A
TQFN
5%
1/16W
MF-LF
402
54B4
5%
1/16W
MF-LF
402
CRITICAL
C6500
AUD_HP_L
2
R6520
AUD_GPIO_1 1 0 2
OUTL 11
OUTR 10
4 PVSS
IN
IN
9 SVSS
52D2
52C7
U6500
2 PGND
R6501
AUD_LO_AMP_INR_M
7 SGND
54B3
VDD
CRITICAL
6 INL
8 INR
54B3
13 THRM
PAD
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
AUD_LO_AMP_OUTL
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
CRITICAL
C6523
C
1UF
10%
10V
X5R
402
GND_AUDIO_HP_AMP
R65101
39
5%
1/16W
MF-LF
402 2
NC
NO STUFF
CRITICAL
C6511
AUD_HP_ZOBEL_R
MAX9724 GAIN/FILTER COMPONENTS
1
AV_PB = -1V/V, FC_LPF = 35.2KHZ
0.0022UF
10%
50V
CERM
402
CRITICAL
C6510
1
10%
16V
X7R-CERM
402
2
CRITICAL
2
C6530
0.1UF
52D2
IN
AUD_HP_PORT_R
330PF
R6511
1
0
2
AUD_HP_R
OUT
5%
50V
COG
402
54B4
5%
1/16W
MF-LF
402
R6531
13.7K
1%
1/16W
MF-LF
402
B
AUD_HP_L
54C6
R6530
13.7K
AUD_LO_AMP_INL_M
B
AUD_LO_AMP_OUTL
54C4
IN
OUT
54D1 56B7
OUT
54C1 56B7
1%
1/16W
MF-LF
402
AUD_HP_R
54B6
R6532
13.7K
AUD_LO_AMP_INR_M
AUD_LO_AMP_OUTR
54C4
IN
1%
1/16W
MF-LF
402
R6533
13.7K
1%
1/16W
MF-LF
402
CRITICAL
C6531
330PF
5%
50V
COG
402
AUDIO: HEADPHONE FILTER
A
SYNC_MASTER=AUDIO
SYNC_DATE=02/03/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
54
1
81
A
8
6
7
SATELLITE
3
4
5
2
1
& SUB TWEETER AMPLIFIER
APN:353S2524
D
SATELLITE
169 HZ < FC < 282 HZ
SUB
GAIN
80 HZ < FC < 132 HZ
6DB
D
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
55C7 55B7 7C3
=PP5V_S3_AUDIO_AMP
CRITICAL
C6607 1
1UF
CRITICAL
L6610
52C2
AUD_LO2_P_R
IN
0402
AUD_LO2_N_R
55B7 55A7
2
0.047UF
2
SPKRAMP_INR_N
2
1
10
PVDD
C6601
47UF
20%
2 6.3V
TANT1
2012-LLP
U6610
TDFN
2 IN+
3 IN-
OUT+
8
OUT-
9
6
CRITICAL
SYNC
5 SHDN*
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT
6C7
56B2
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT
6C7
56A2
THRML
1
10%
16V
X7R
402
0
1
C
100K
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
SPKRAMP_SHDN
GND PGND PAD
4
7
11
R6611
R6610
AUD_GPIO_3
IN
MAX9705_R_P
MAX9705_R_N
10%
16V
X7R
402
C6611
0402
C
52C7
1
1
1
VDD
MAX9705A
0.047UF
CRITICAL
FERR-1000-OHM
IN
C6610
FERR-1000-OHM
1
2 SPKRAMP_INR_P
L6611
52C2
10%
10V
X5R 2
402
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
55D7 55B7 7C3
=PP5V_S3_AUDIO_AMP
CRITICAL
1
L6620
52C2
IN
1
AUD_LO1_P_R
2
0402
55C7 55A7
1
AUD_LO1_N_R
MAX9705_SUB_P
MAX9705_SUB_N
SPKRAMP_INSUB_P
2
CRITICAL
10%
16V
X5R
402
L6621
IN
10%
10V
X5R 2
402
0.1UF
FERR-1000-OHM
52C2
1UF
C6620
FERR-1000-OHM
C6621
1
SPKRAMP_INSUB_N
0402
VDD
PVDD
U6620
2
20%
2 6.3V
TANT
CASE-AL1
MAX9705A
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT
6C7
TDFN
IN+
IN-
CRITICAL
SHDN*
0.1UF
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT 6C7 56B2
100UF
C6608 1
CRITICAL
C6603
GND PGND
OUT+
OUT-
56B2
SYNC
THRML
PAD
10%
16V
X5R
402
SPKRAMP_SHDN
B
B
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
55D7 55C7 7C3
=PP5V_S3_AUDIO_AMP
CRITICAL
C6609 1
52C2
IN
AUD_LO2_P_L
1
2
SPKRAMP_INL_P
0402
55C7 55B7
AUD_LO2_N_L
1
2
0402
1
SPKRAMP_INL_N
MAX9705_L_P
MAX9705_L_N
2
10%
16V
X7R
402
FERR-1000-OHM
IN
10%
10V
X5R 2
402
C6630
0.047UF
L6631
52C2
1UF
CRITICAL
L6630
FERR-1000-OHM
1
CRITICAL
C6631
PVDD
U6630
MAX9705A
TDFN
IN+
IN-
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT
6D7
47UF
20%
2 6.3V
TANT1
2012-LLP
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT
OUT+
OUT-
56B2
6D7 56B2
CRITICAL SYNC
SHDN*
0.047UF
1
VDD
C6605
2
GND PGND
THRML
PAD
10%
16V
X7R
402
SPKRAMP_SHDN
AUDI0: SPEAKER AMP
A
SYNC_MASTER=AUDIO
SYNC_DATE=12/18/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
55
1
81
A
8
6
7
2
3
4
5
1
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX
AUD_SPDIF_OUT
IN
52B7
HS_MIC_HI
OUT
57C1
HS_MIC_LO
OUT
57C1
L6701
FERR-1000-OHM
57D3 57B8 52D2 52A8 7C5
1
=PP3V3_S0_AUDIO
2
0402
L6702
FERR-1000-OHM
1
D
2
0402
D
L6706
CRITICAL
FERR-220-OHM
AUD_HP_PORT_REF
APN:514-0671
J6700
0402
SPDIF-TXRX-K24
F-RT-TH
CRITICAL
MIC
DETECT
SWITCH
LEFT
RIGHT
GND
CRITICAL
AUD_CONNJ1_MIC
L6703
AUD_CONNJ1_SLEEVE
1
6
2
1
3
4
C
XW6701
SM
AUD_LI_GND
53B6
L6704
AUD_CONN_GND
FERR-220-OHM
1
56A7 56D2 56A7 56D2
AUD_CONN_L
2
0402
BI
56B3
BI
56A3
CRITICAL
L6705
7
FERR-220-OHM
8
9
1
AUD_CONN_R
2
0402
POF
SHIELD
PINS
52A5 52D2 52D7 54C4 54C7
AUD_CONN_GND
2
GND_AUDIO_HP_AMP
CRITICAL
OPERATING VOLTAGE 3.3
SHELL
XW6700
SM
0402-LF
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
5
AUDIO
A - VIN
B - VCC
C - GND
52D2
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
FERR-120-OHM-1.5A
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
OUT
1
10
11
R6700
C6700
CRITICAL
1UF
12
13
2
DZ6705
10%
2 6.3V
CERM
402
2
6.8V-100PF
CRITICAL
2
CRITICAL
2
402
1
402
1
CRITICAL
1
DZ6700
1
402
1
1
AUD_J1_SLEEVEDET_R
2
OUT
MIC CONNECTOR
57C6 57C8
APN:518S0520
R6701
2
6.8V-100PF
402
10K
5%
1/16W
MF-LF
402
402
6.8V-100PF
6.8V-100PF
DZ6703
6.8V-100PF
DZ6704
DZ6701
1
CRITICAL
1
C6701
100PF
4.7
78171-0003
OUT
57A7 57C8
5%
1/16W
MF-LF
402
57B1 6D7
57B1 6D7
57B1 6D7
BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI
1
2
3
5
CHASSIS GND STITCHES
NOSTUFF
XW6710
SM
R6723
0
NOSTUFF
R6722
XW6711
SM
0
R6725
0
0
=PP3V42_G3H_AUDIO
7D1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SPEAKER CONNECTOR
5%
1/16W
MF-LF
402
NOSTUFF
R6760
R6724
=PP5V_S3_AUDIO
54D1 54B1
OUT
AUD_LO_AMP_OUTL
0
OUT
AUD_LO_AMP_OUTR
IN
IN
AUD_LI_L_SWITCH
0
C2 CB
IN
IN
55C2 6C7
IN
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
EN* B2
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
CRITICAL
B
J6703
78171-0004
M-RT-SM
5
C6761
5%
2 50V
CERM
402
1
2
3
1
4
C6762
33PF
5%
50V
2 CERM
402
AUD_CONN_R
BI
1
56C3
R6713
6
C6763
33PF
55C2 6C7
0.0033UF
C6760
IN
SPKRAMP_R_N_OUT
5%
50V
2 CERM
402
APN:518S0521
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
24K
10%
50V
CERM
402
5%
1/16W
MF-LF
402
R6720
0
AUD_GPIO_0
AUD_SWITCH_CTRL
5%
1/16W
MF-LF
402
A
AUDIO: JACK
R6721
100K
56D2
AUD_CONN_GND
GND STUFFING OPTIONS FOR CMOS SWITCH
57D1 57C8 57C3 57B8 57B4 57A8 53B6 52D2 52B7 52A5
R6715
0
5%
1/16W
MF-LF
402
GND_AUDIO_CODEC
5%
1/16W
MF-LF
402
R6714
0
SYNC_MASTER=AUDIO
ANALOG AUDIO IO SWITCH
GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED
GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
NOSTUFF
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R6727
SIZE
0
5
DRAWING NUMBER
D
5%
1/16W
MF-LF
402
6
SYNC_DATE=03/20/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
AUD_SWITCH_GND
5%
1/16W
MF-LF
402
7
5%
1/16W
MF-LF
402
55B2 6C7
GND
C6711
AUD_LI_R_SWITCH
2
33PF
24K
SWITCH_CP A2
NEG
5%
1/16W
MF-LF
402
52C7
1
COM2 B1
R6719
AUD_LI_R
1
SPKRAMP_SUB_P_OUT
56C3
R6712
COM1 B4
WLP
CRITICAL
A4 NO1
A1 NO2
5%
1/16W
MF-LF
402
53B6
IN
AUD_CONN_L
BI
MAX14504
B3
53C6
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
A3
C4 NC1
C1 NC2
R6718
0
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
APN: 353S2536
U6700
AUD_LO_AMP_OUTR_SWITCH
5%
1/16W
MF-LF
402
AUD_LI_L
IN
5%
50V
2 CERM
402
VCC
R6717
0
M-RT-SM
3
33PF
R6726
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
54C1 54B1
IN
55A2 6D7
NOSTUFF
0
10%
10V
X5R
402
AUD_LO_AMP_OUTL_SWITCH
55B2 6D7
1
C6710
1UF
R6716
55C2 6C7
PP_MAX14504_VCC
C3
B
J6702
4
0
5%
1/16W
MF-LF
402
CRITICAL
78171-0002
APN:518S0519
5%
1/16W
MF-LF
402
54D5 52D2 52A8 7C3
8
C
M-RT-SM
4
AUD_J1_TIPDET_R
2
5%
2 50V
CERM
402
GND_CHASSIS_AUDIO_JACK
CRITICAL
J6701
APPLE INC.
SCALE
SHT
NONE
4
3
2
REV.
051-7898
4.7.0
OF
56
1
81
A
8
6
7
2
3
4
5
1
CODEC OUTPUT SIGNAL PATHS
CONVERTER
0X02 (2)
0X05 (5)
0X04 (4)
0X03 (03)
0X08 (8)
PIN COMPLEX
0X09 (9,A)
0X0C (12)
0X0B (11)
0X0A (10)
0X10 (16)
MUTE CONTROL
GPIO_0 AND GPIO_1
GPIO_0 AND GPIO_1
GPIO_3
GPIO_3
N/A
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=8.82KHZ
DET ASSIGNMENT
0X09 (A)
0X09 (A)AND UI ELEMENT
N/A
N/A
0X0D (B)
MIKEY
L6880
57B8 56D8 52D2 52A8 7C5
=PP3V3_S0_AUDIO
1
2
CONVERTER
0X06 (6)
0X06 (6)
VREF
MIC_BIAS (80%)
MIKEY
PIN COMPLEX
0X0D (13,B,RIGHT)
0X0D (13,V22,B,LEFT)
APN:353S2256
CRITICAL
MIKEY
DET ASSIGNMENT
N/A
MIKEY
C6880
3
FUNCTION
BUILT-IN MIC
HEADSET MIC
1UF
10%
6.3V
CERM
402
AVDD
PORT A DETECT (HEADPHONES)
IN
43B6
BI
=I2C_MIKEY_SDA
18D7
PORT B DETECT(SPDIF DELEGATE)
DRC
43B6
=I2C_MIKEY_SCL
20C3 20A4
6
SCL
MICBIAS
1
HS_MIC_BIAS
5
SDA
DETECT
2
HS_SW_DET
OUT
AUD_I2C_INT_L
7
INT*
IN
AUD_IPHS_SWITCH_EN
8
ENABLE
GND
1
39.2K
APN:376S0613
300K
AUD_OUTJACK_INSERT_L
5%
1/16W
MF-LF
402
2
Q6801
47K
2
5
1
AUD_PORTB_DET_L
NC
Q6801
G
S
SSM6N15FEAPE
C6801
S
2
4
G
S
52C2
1
PP3V3_S0_AUDIO_F
1
220K
2
5%
1/16W
MF-LF
2 402
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
D
Q6800
6
57C8 56C3
1
R6883
1
100K
2
5%
1/16W
MF-LF
402
C6802
2
G
S
1
52C2
IN
AUD_CODEC_MICBIAS
100
1
10%
16V
CERM
402
2
1%
1/16W
MF-LF
402
R6882
2.2K
2
2
5%
1/16W
MF-LF
402
HS_MIC_HI
2
5%
1/16W
MF-LF
402
1
0.0082UF
2
10%
X7R
IN
56D3
IN
56D3
MIKEY
C6885
27PF
25V
402
5%
CERM
2
CRITICAL
50V
402
C
CRITICAL
SM
HS_MIC_LO
2
R6851
MIC_BIAS_FILT
1
1
2
1%
1/16W
MF
402-1
CRITICAL
C6852
2.2UF
GND_AUDIO_CODEC
2.4K
20%
6.3V
TANT
402
CRITICAL
L6850
FERR-1000-OHM
0.1UF
52C2
1
OUT AUD_MIC_INP_R
CRITICAL
C6851
0.1UF
52C2
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
57C8 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
1
OUT AUD_MIC_INN_R
B
GND_AUDIO_CODEC
1
2
2.4K
BI_MIC_HI_F
1
2
BI_MIC_HI
IN
6D7 56C2
BI_MIC_LO
IN
6D7 56C2
BI_MIC_SHIELD
IN
6D7 56C2
0402
10%
25V
X5R
402
1
R6852
CRITICAL
C6853
100K
R6853
1
SM
L6862
2
10%
25V
X5R
402
XW6851
EXTRACTION NOTIFICATION CKT
2
5%
1/16W
MF-LF
2 402
1
1
2
2
0.001UF
50V
402
BI_MIC_LO_F
10%
CERM
CRITICAL
C6854
27PF
5%
CERM
50V
402
L6851
B
FERR-1000-OHM
1
2
0402
1%
1/16W
MF
402-1
2
FERR-1000-OHM
1
2.2K
MIKEY
C6884
C6850
=PP3V3_S0_AUDIO
1%
1/16W
MF-LF
402
PORT B RIGHT(BUILT-IN MIC)
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
IN
1
R6884
1
MIKEY
R6850
2
57D3 56D8 52D2 52A8 7C5
R6881
1
AUD_J1_SLEEVEDET_R
AUD_J1_SLEEVEDET_R
GND_AUDIO_CODEC
52A5 52B7 52D2 53B6 56A7 57A8
57B4 57B8 57C3 57C8
MIKEY
AUD_J1_SLEEVEDET_INV
0.01UF
57C3 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1 57C8
2
MIKEY
10%
25V
X5R
402
1
SOT563
2
MIKEY
XW6880
GND_AUDIO_CODEC
SSM6N15FEAPE
1
10%
CERM
HS_MIC_HI_RC
2
2
10%
25V
X5R
402
10V
402
5%
1/16W
MF-LF
402
R6804
220K
IN
1
OUT AUD_MIC_INN_L
0.1UF
20%
CERM
2
1
SOT563
GND_AUDIO_CODEC
1
57C6 56C3
OUT AUD_MIC_INP_L
0.1UF
G
0.01UF
MIKEY
CRITICAL
MIKEY
CRITICAL
4
5
GND_AUDIO_CODEC
1
C6881
C6883
52C2
R6803
57C8 57B8
MIKEY
16V
402
1K
NC
6
20%
6.3V
TANT
402
THM
0.1UF
D
2.2UF
2
GND_AUDIO_CODEC
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
C6886
AUD_J1_DET_RC
2
57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1 57C3
3
SOT563
5%
1/16W
MF-LF
402
C
D
SSM6N15FEAPE
R6802
1
2
1%
1/16W
MF-LF
402
3
SOT563
AUD_J1_TIPDET_R
R6805
C6882
HS_RX_BP
20.0K
1%
1/16W
MF-LF
402
AUD_PORTA_DET_L
D
Q6800
SSM6N15FEAPE
IN
1
R6806
5%
1/16W
MF-LF
402
MIKEY
CRITICAL
1
10
BYPASS
100K
PP3V3_S0_AUDIO_F
R6801
57A7 56C3
4
MIKEY
R6880 1
OUT AUD_SENSE_A
57C8 57B8
D
MIKEY
U6880
CD3275
PULLUPS ON MCP PAGE
52C7
DRC MIKEY
0402
CODEC INPUT SIGNAL PATHS
D
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
PP3V3_S0_HS_RX
FERR-1000-OHM
11
VOLUME
0X02 (2)
0X05 (5)
0X04 (4)
0X03 (3)
N/A
9
FUNCTION
HP/LINE OUT
LINE IN
SATELLITES
SUB
SPDIF OUT
HP=80HZ
2
0402
R6864
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA
C6861
220K
1
5%
1/16W
MF-LF
402
0.1UF
10V
402
20%
CERM
2
R6865
100K
Q6802
5%
1/16W
MF-LF
402
D 6
SSM6N15FEAPE
2
R6860
57C8 56C3
15K
AUD_J1_TIPDET_R
5%
1/16W
MF-LF
402
A
G
S 1
Q6802
0
AUD_IP_PERIPHERAL_DET OUT
16B6
5%
1/16W
MF-LF
402
D 3
SSM6N15FEAPE
SOT563
TIPDET_FILT
5
C6860
0.1UF
G
AUDIO: JACK TRANSLATORS
S 4
SYNC_MASTER=AUDIO
AUD_J1_TIPDET_INV
20%
10V
CERM
402
57D1 57C8 57C3 57B8 57B4 56A7 53B6 52D2 52B7 52A5
R6861
AUD_PERPH_DET_R
SOT563
SYNC_DATE=03/20/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
GND_AUDIO_CODEC
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
57
1
81
A
8
6
7
2
3
4
5
1
MagSafe DC Power Jack
CRITICAL
J6900
CRITICAL
F6905
78048-0573
M-RT-SM
6AMP-24V
1
6C3
3
ADAPTER_SENSE
0
1
1
2
5%
1/16W
MF-LF
402
518S0656
=PP3V42_G3H_ONEWIRE
C6905
0.01UF
2
1
20%
50V
CERM
603
SMC_BC_ACOK_VCC
R6929
2.0K
402
MF-LF
1/16W
5%
7D2 58C8
U6900
1
SC70-5
4 INT
2
NEAR U6901
1
SMC_BC_ACOK
40C5 41B2 41D5
NC
3
2
GND
U6901
3
EXT 5
20% PLACEMENT_NOTE=PLACE
2 10V
CERM
402
Y
B
MAX9940
SYS_ONEWIRE
BI
4
D
7D1
C6908
0.1UF
SOT665
TC7SZ08AFEAPE
A
VCC
ONEWIRE_PU
40B8
5
1
6B3
=PP18V5_DCIN_CONN
2
5
2
1206-1
R6928
4
D
1
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
2
NC
1-Wire OverVoltage Protection
ADAPTER_SENSE_R
BIL CONNECTOR
C
=PP3V42_G3H_BATT
2
58C2 7D1
J6955
1
10K
CPB6312-0101F
1/16W
402
MF-LF
5%
F-ST-SM
14
2
CRITICAL
D6905
R6905
47
2
5%
1/8W
MF-LF
805
5
1
C6954
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=12.6V
NC
2
10%
50V
CERM
402
PPVIN_G3H_P3V42G3H
NC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
C6990
10%
25V
X5R
805
VIN
2
NC
7 NC
SW 4
DFN
CRITICAL
5
GND
BIAS 2
C6994
1
20%
6.3V
X5R
402
2
0.22uF
LT3470A
8 SHDN*
B
BOOST
U6990
33UH
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE DIDT=TRUE
C6953
2
=PP3V42_G3H_REG
2
5
8
7
10
9
12
11
58C4 7D1
1
47PF
5%
50V
CERM
402
5%
50V
CERM
402
100
1
2
1/16W
SMC_LID
402
40B5 41C2 48A5
5%
MF-LF
1
NC
C6951
16
R6961
=PP3V42_G3H_BATT
SMC_LID_R
6A7
2
0.1UF
15
10%
25V
X5R
402
2
C6955
0.001UF
1
10%
50V
CERM
402
2
2
7D2
Vout = 3.425V
CDPH4D19FHF-SM
250MA MAX OUTPUT
C6995
22pF
2
NC
3
6
L6995
1
1
1
4
CRITICAL
P3V42G3H_SW
FB 1
THRM
PAD
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
13
1
47PF
DIDT=TRUE
10UF
BI
1
P3V42G3H_BOOST
1
BI
58A6 43C3
SMC_BIL_BUTTON_L
0.001UF
4
BATT_POS_F
58A6 43C3
C6952
Supply needs to guarantee 3.31V delivered to SMC VRef generator
3
59A3 58A7 6A7
TO SMC
3.425V "G3Hot" Supply
SOT665
PPDCIN_S5_P3V42G3H
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
3
1
9
=PP18V5_DCIN_CONN
6
58D1 7D2
HN2D01JEAPE
C
516S0523
CRITICAL
R6960
5%
50V
CERM
402
<Ra>
R6995 1
B
(Switcher limit)
348K
1%
1/16W
MF-LF
402 2
CRITICAL
1
C6999
22UF
P3V42G3H_FB
<Rb>
R6996 1
2
20%
6.3V
CERM
805
200K
1%
1/16W
MF-LF
402 2
Vout = 1.25V * (1 + Ra / Rb)
518-0359
BATTERY CONNECTOR
CRITICAL
J6950
BAT-K24
M-RT-TH
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
1
2
59A3 58B8 6A7
6
7
8
9
6A7
=SMBUS_BATT_SCL
SYS_DETECT_L
=SMBUS_BATT_SDA
43C3 58C3
DC-In & Battery Connectors
43C3 58C3
CRITICAL
D6950
RCLAMP2402B
SC-75
2
5
1
3
4
BATT_POS_F
R6950 1
10K
5%
1/16W
MF-LF
402
10
11
SYNC_MASTER=YUNWU
C6950
12
13
SYNC_DATE=12/11/2008
NOTICE OF PROPRIETARY PROPERTY
1
0.1UF
10%
25V
X5R
402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
2
2
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
3
A
P1
P2
P3
P4
P5
P6
P7
P8
P9
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
58
1
81
A
8
6
7
2
3
4
5
1
PBUS SUPPLY / BATTERY CHARGER
CRITICAL
Q7001
CRITICAL
HAT1127H
MIN_NECK_WIDTH=0.3 MM
PPVDCIN_G3H_PRE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
R7098 1
1
100K
5%
0.1UF
1/16W
MF-LF
402 2
10%
25V 2
X5R
402
CRITICAL
R7010
1%
1/16W
MF-LF
402
59C5
G
R7060
R7001
62K
1
CHGR_SGATE
57.6K
5%
1/16W
MF-LF
402
2
59C5
45B3
59B8
R7061 1
CHGR_AMON
1
VCC
1UF
9.31K
1%
10%
10V 2
X5R
402-1
VDD
2
C
43B3
43B3
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
NC
CHGR_ACIN
1
10%
16V
X5R
402
2
0.033UF
1
R7045
1
56.2K
1%
1/16W
MF-LF
402 2
C7044
0.01UF
10%
16V
2 CERM
402
59C4 59B6
CHGR_ICOMP 5
CHGR_VCOMP 7
CHGR_VNEG 8
CHGR_CSOP 18
CHGR_CSON 17
CHGR_VCOMP_R
C7045 1
C7043
0.1UF
1
2
10%
16V
X5R
402
ICOMP
VCOMP
VNEG
CSOP
CSON
5%
1/16W
MF-LF
402
1
2
C7040
10%
2 10V
X5R
402-1
QFN
2
1
CHGR_AGATE
CHGR_CSIP
CHGR_CSIN
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
LGATE 21
CHGR_LGATE
5%
1/16W
MF-LF
402
2
1
2
2
1
2
0.1UF
MIN_NECK_WIDTH=0.3 MM
0.5%
1W
MF
2 0612-1
MIN_LINE_WIDTH=0.6 MM
PP18V5_S5_CHGR_SW_R
CRITICAL
CRITICAL
10%
25V
X5R
402
2
10%
25V
X5R
402
GND_CHGR_SGND 59B6
C7020
2
20%
25V
POLY-TANT
CASE-D2-SM
5
1
C7021
2
20%
25V
2
POLY-TANT
CASE-D2-SM
2
1 2 3
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
PPVBAT_G3H_CHGR_REG
2
4.7UH-9.5A
IHLP4040DZ-SM
5
1
CHGR_VNEG_R
DIDT=TRUE
2
1
2
4
PPVBAT_G3H_CHGR_OUT
1
RJK0305DPB
LFPAK-HF
10%
2 50V
X7R
402
GND_CHGR_SGND
C7011 1
1UF
C7008
10%
25V
2 X5R
20%
16V
POLY-TANT
CASED2E-SM
603-1
CRITICAL
2
59A5
C7028
0.001UF
20%
50V
CERM
402
PWM FREQ. = 400 kHz
MAX CURRENT = 7A
1 2 3
(??? limited)
R7031
10
5%
1/16W
MF-LF
402
470PF
10%
50V
CERM 2
402
1
3
1206
Q7021
C7026
0.001UF
(CHGR_CSOP)
C7046 1
CRITICAL
0.5%
1W
MF
0612-1
33UF
3.01K
59C4 59B8
7AMP
0.01
L7000
TO SYSTEM
7C2
F7000
R7008
CRITICAL
=PPBUS_G3H
2
CRITICAL
DIDT=TRUE
C
20%
50V
CERM
402
1
C7025 1
10%
25V
X5R
402
XW7000
SM
1%
1/16W
MF-LF
402 2
2
C7027
0.001UF
CRITICAL
4
R7046
1
1UF
LFPAK-HF
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
1
2
C7023
10%
25V
X5R
603-1
RJK0305DPB
0.1UF
CHGR_AMON 59D4
45B3
59B8
CHGR_BMON 45A6
=CHGR_ACOK 41D4
C7022 1
1UF
10%
25V
X5R
603-1
Q7020
2
1
1
22UF
CRITICAL
59B8
4
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
1
22UF
0.1UF
DIDT=TRUE
10%
50V
CERM 2
402
B
R7020
0.02
XW7021
SM
0.001UF
GND_CHGR_SGND
1CRITICAL
C7061 1 C7062
TRKL* 13 NC
AMON 9
BMON 15
ACOK 14
1
CHGR_CSIN_XW7021
CHGR_BGATE
CHGR_DCIN 59D8
BOOT 25
UGATE 24
PHASE 23
TL331
XW7020
SM
R7021
10
0.047UF
10%
10V
CERM
402
16
59A3
BGATE
DCIN 2
U7060
CHGR_CSIP_XW7020
C7024 1
VDDP
U7000
4 VREF
3 ACIN
R7023
10
1UF
12 VHST
AGATE 1
11 SCL
CSIP 28
10 SDA CRITICALCSIN 27
29 THRM_PAD
C7042
1
CHGR_LOWCURRENT_GATE
SOT23-5
CHGR_VDDP
5%
1/16W
MF-LF
402
1UF
10%
ISL6258A
R7011
C7041
10V
X5R
402-1
C7047 1
1
1/16W
MF-LF
402
=PP3V42_G3H_CHGR
2
R7040
4.7
26
6 AGND
59D5 59A8 7D1
2 CHGR_VDD 1
19
10%
25V 2
X5R
402
1
20
59A8
22 PGND
(CHGR_ACIN)
62K
CRITICAL
2
1%
1/16W
MF-LF
402
2
2
5%
1/16W
MF-LF
402
2
4
GND
3
CHGR_LOWCURRENT_REF
100K
5%
1/16W
MF-LF
402
R7062 1
10%
25V
X5R
402
5
1.82K
0.1UF
0.1UF
2
1%
1/16W
MF-LF
402 2
2
CHGR_LOWCURRENT_GATE_R 1
C7060
1
1
1
C7010 1
R7099
59C6 59A8 7D1
30.1K
CHGR_DCIN
D
5
=PP3V42_G3H_CHGR
4
C7063
G
2
SOD-723-HF
4
1SS418
1
D
1
D7010
S
D
2
1
3
D
5
MIN_LINE_WIDTH=0.6 MM
LFPAK-SM
2 3
LFPAK-SM
PPVDCIN_G3H_PRE2
HAT1127H
=PP18V5_G3H_CHGR
S
Q7000
7C1
(CHGR_CSON)
80D3 45A8
B
CHGR_CSO_R_P
R7047
10
80D3 45A8
CHGR_CSO_R_N
5%
1/16W
MF-LF
402
(CHGR_CSO_R_N)
AMON PULLDOWN LOGIC
=PP3V42_G3H_CHGR
R70751
1M
Q7050
SI7137DP
59C1
1
CHGR_VDD_L
C7050
0.01uF
Q7070
10%
2 16V
CERM
402
D 3
SSM6N15FEAPE
SOT563
A
59C6
1
CRITICAL
SO-8
PPVBAT_G3H_CHGR_OUT
C7051
0.1UF
D
S 1
5%
1/16W
MF-LF
402
2
S
5%
1/16W
MF-LF
402 2
2 G
BATTERY CHARGE LIMITING FETS
NOSTUFF
5
D 6
2 3
1M
Q7070
SSM6N15FEAPE
SOT563
BATT_POS_F
6A7 58A7 58B8
1
R70741
10%
2 16V
X5R
402
PBUS Supply/Battery Charger
G
59D5 59C6 7D1
CHGR_AMON
4
59D4 59C5 45B3
SYNC_MASTER=RAYMOND
R70731
5 G
CHGR_BGATE
S 4
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
59C5
1K
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
402 2
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
CHGR_VDD_R
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
SYNC_DATE=01/31/2008
NOTICE OF PROPRIETARY PROPERTY
CHGR_VDD
4.7.0
OF
59
1
81
A
8
6
7
2
3
4
5
1
5V_S3/3.3V_S5 POWER SUPPLY
D
VOUT = (2 * RA / RB) + 2
ROUTING NOTE:
Place XW7203 by Pin1 OF L7260.
SM
2
1%
1/16W
MF-LF
402
5V_S3_VFB_XW7203
1
VOUT = (2 * RC / RD) + 2
<RA>
<RB>
<RD>
<RC>
R7267
R7268
R7269
15.0K
10K
10K
XW7203
2
1
R7270
6.49K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1
D
2
1
1%
1/16W
MF-LF
402
2
1
Place XW7204 by Pin 2 of L7220.
SM
3V3S5_VFB_R7270
2
ROUTING NOTE:
XW7204
2
1
60B5
GND_5V3V3S5_SGND
XW7205
66D8 40D5 6C3
C
60C7 7C1
ROUTING NOTE:
2
1
R7273
C7272
1UF
100K
5%
1/16W
MF-LF
402
10%
2 25V
X5R
603-1
1
1
=PPVIN_S3_5VS3
2
5V3V3S5_REG3
5VS3_3V3S5_VREF
C7260
0.1UF
10%
5
CRITICAL
16V
X5R
402
D
Q7260
2
SI7110DN
PWRPK-1212-8-HF
B
1
3 2 1
DIDT=TRUE
DIDT=TRUE
5V_S3_DRVH
21 DRVH1
5V_S3_LL
20 LL1
5
VOLTAGE=5V
5V_S3_ENTRIP
D
50V
CERM
402
2 6.3V
X5R
0.001UF
20%
2
C7290
10UF
C7293
1
20%
603
CRITICAL
1
Q7261
C7291
G
SI7108DN
220UF
20%
2 6.3V
ELEC
D1A-SM
QFN
2 VFB1
DIDT=TRUE
1
3 2 1
CRITICAL
2
1/16W
MF-LF
402
9 4 3 2
1
VO2 7 3V3S5VO2
ENTRIP2 6
0.001UF
1
PWM FREQ. = 375 KHZ
MAX CURRENT = 4A
2
CRITICAL
4.7UH-5.5A
=PP3V3_S5_REG
IHLP2525CZ
3V3S5_ENTRIP
EN0 13 5V3V3_REG_EN
GND THRM_PAD
1
C7273
10UF
20%
2 6.3V
X5R
603
GND_5V3V3S5_SGND
1
1
R7272
2
1/16W
MF-LF
402
1
C7250
10UF
1
20%
20%
2 6.3V
POLY
B1A-SM
7 6 5
1
C7251
150UF
75K
1%
B
7B4
VOLTAGE=3.3V
CRITICAL
Q2
NC
PGOOD 23
C7242
20%
2 50V
CERM
402
Q7220
10
SW
8
VFB2 5 3V3S5_VFB
2
20%
16V
POLY
B1A-SM
L7220
Q1
DIDT=TRUE
1
39UF-0.027OHM
FDMS9600S
MLP
CRITICAL
1
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
1 C7240
10%
2 25V
X5R
603-1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDT=0.2 DIDT=TRUE
DRVL2 12 3V3S5DRVL
1 ENTRIP1
60C4
D 6
DRVH2 10 3V3S5_DRVH
CRITICAL
C7241
1UF
C7220
2
DIDT=TRUE
LL2 11 3V3S5_LL
R7271
86.6K
1%
1
16V
X5R
402
VBST2 9 3V3S5_VBST
VCLK 18
4
S
PWRPK-1212-8-HF
U7200
=PPVIN_S5_3V3S5
0.1UF
10%
VREG3 8
VREG5 17 5V3V3S5_REG5
24 VO1
5V_S3_VFB
PCMB104E4R7-SM
VREF
CRITICAL
19 DRVL1
5V_S3_DRVL
7C4
1
22 VBST1
5V_S3_VO1
CRITICAL
4.7UH-13A-15MOHM
=PP5V_S3_REG
5V_S3_VBST
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
603
4 TONSEL
7C1
10UF
20%
2 6.3V
X5R
VIN
14 SKIPSEL
10%
2 10V
CERM
402
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2
C7271
0.22UF
MIN_LINE_WIDTH=0.6 MM
DIDT=TRUE
S
L7260
MAX CURRENT = 8A
PWM FREQ. = 300 KHZ
4
G
1
1
C7270
3
2
C7281
1UF
10%
2 25V
X5R
603-1
20%
16V
POLY
B1A-SM
25
39UF-0.027OHM
1
16
20%
50V
2 CERM
402
1
TPS51125
C7282
0.001UF
CRITICAL
1 C7280
15
1
1
C
SM
2
60C6 7C1
SMC_PM_G2_EN
ROUTING NOTE:
Place XW7205 by C7252.
=PPVIN_S3_5VS3
XW7202
Place XW7202 by C7292.
SM
2 6.3V
X5R
603
2
C7253
0.001UF
20%
50V
CERM
402
2
XW7201
SM
Q7221
SSM6N15FEAPE
P5V3V3_PGOOD
66A5
SOT563
ROUTING NOTE:
=P5VS3_EN_L
66C6
IN
2
G
S 1
D 3
Q7221
Place XW7201 between Pin 15 and Pin 25 of U7200.
SSM6N15FEAPE
5V/3.3V SUPPLY
SOT563
A
=P3V3S5_EN_L 5
66D6
IN
SYNC_MASTER=RAYMOND
G
S 4
SYNC_DATE=02/08/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
60
1
81
A
8
6
7
2
3
4
5
1
1.5V/0.75V(DDR3) POWER SUPPLY
D
402
25D3 7C4 =PPVTT_S3_DDR_BUF
1
1
50V
CERM
402
0.1%
1/16W
MF
402
2
2
C7340
0.033UF
1
10%
16V
X5R
402
1
1V5S3_V5FILT
2
10%
10V
X5R
402-1
C7301
10UF
20%
2 6.3V
X5R
603
1
C7300
1UF
=PP5V_S3_1V5S30V75S0
2
R7307
4.7
5%
1/16W
MF-LF
402
7C3
C7302
1
10UF
20%
6.3V
X5R
603
2
1V5S3_VDDQSNS
=PP0V75_S0_REG
ROUTING NOTE:
XW7301
SM
1V5S3_VTTSNS
1
Place XW7301 by L7320.
2
C
7C8
1
R7310
10.7K
VDDQSET VTTREF VLDOIN VTT V5FILT
0
PGOOD
CRITICAL
QFN
CS
ROUTING NOTE:
ROUTING NOTE:
Place XW7303 by C7308.
C7308
22UF
20%
6.3V
2 X5R-CERM-1
603
19 1V5S3_DRVL
MODE
4
NC0
NC1
C7309
0.1uF
10%
16V
X5R
402
D
4
CS_GND
B
GND
PGND
VTTGND
GND_1V5S3_SGND
S
1 2 3
DIDT=TRUE
GND_1V5S3_CSGND
PWRPK-1212-8-HF
2
C7330
1
CRITICAL
20%
16V
POLY
B1A-SM
1
20%
16V
POLY
B1A-SM
10%
2 25V
X5R
603-1
39UF-0.027OHM
2
C7332
C7331
1
1UF
C7333
0.001UF
2
20%
50V
CERM
402
MAX CURRENT = 12A
PWM FREQ. = 400 KHZ
PUT ONE BULK CAP NEXT TO THE LOAD
=PP1V5_S3_REG
VOLTAGE=1.5V
MIN_LINE_WIDTH=1.5 mm
MIN_NECK_WIDTH=0.25 mm
2
7D4
CRITICAL
5
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
1
CRITICAL
DIDT=TRUE
7 NC
12 NC
CRITICAL
39UF-0.027OHM
SM-IHLP-1
1
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
D
4
G
CRITICAL
1
SI7108DN
20%
2 2.5V
TANT
CASE-B2-SM
Q7321
PWRPK-1212-8-HF
1
C7342
330UF
C7343
1
330UF
C7341
10UF
20%
2 2.5V
TANT
CASE-B2-SM
20%
2 6.3V
X5R
603
C7344
0.001UF
2
20%
50V
CERM
402
1 2 3
1
1
DDRREG_PGOOD
2
XW7300
SM
ROUTING NOTE:
PUT 6 VIAS UNDER THE THERMAL PAD
1
7C1
CRITICAL
L7320
1.0UH-13A-5.6M-OHM
G
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
CRITICAL
Q7320
SI7110DN
S
THRM_PAD
1
CRITICAL
DIDT=TRUE
2
21 1V5S3_DRVH
20 1V5S3_LL
DRVL
CONNECT CS_GND TO
Q7321 PIN1,2.3
USING KEVIN CONNECTION.
25
C7307
22UF
20%
6.3V
2 X5R-CERM-1
603
1
13
5
1V8S3_VBST_RC
DIDT=TRUE
18
16
COMP
3
1V5S3_CS
DRVH
LL
TPS51116
17
SM
2
6
CRITICAL
1
S3
S5
U7300
SYM (1 OF 2)
1
=DDRREG_EN
=PPVIN_S5_1V5S30V75S0
1
10
11
XW7303
66C6
=DDRVTT_EN
2
5%
1/16W
MF-LF
402
VBST V5IN VDDQSNS VTTSNS
1%
1/16W
MF-LF
2 402
67A3 24C1
1
R7300
2
8
15
22
14
24
5
23
1V5S3_VBST
DIDT=TRUE
9
C
D
VOUT = 0.75V * (1 + RA / RB)
NO STUFF
<RB>
1
2
1
2
1V5S3_VDDQSET
R7322
<RA> C7303
20K
0.1%
100PF
R7321 5%
1/16W
MF
20K
R7399
100K
ROUTING NOTE:
Place XW7300 between
Pin 3 and Pin 25
of U7300.
1
2
XW7302
SM
B
66A2
5%
1/16W
MF-LF
402
2
=PP3V3_S3_PDCISENS
7D3
ROUTING NOTE:
Place XW7302 by Q7321.
STATE
PM_SLP_S4_L
PM_SLP_S3_L
PP1V5_S3
PP0V75_S0
S0
HIGH
HIGH
1.5V
0.75V
S3
HIGH
LOW
1.5V
0.0V
S5/G3HOT
LOW
LOW
0.0V
0.0V
1.5V/0.75V DDR3 SUPPLY
A
SYNC_MASTER=RAYMOND
SYNC_DATE=01/31/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
61
1
81
A
8
62D8 62C3 7B1
1
R7412
1
10
5%
1/16W
MF-LF
402
1UF
10%
6.3V
CERM
402
1
R7420
10
2
C7430
R7421
0.1uF
GND_IMVP6_SGND
NO STUFF
R7427
1
73A3
1
2
73A3
2
R7445
1
NO STUFF
C7410
0.01uF
1
1%
1/16W
MF-LF
2 402
IMVP6_NTC_R
10%
16V
CERM
402
C
499
ERT-J0EV474J
73A3
73A3
R7447
2
NO STUFF
R7406
45B3
0
5%
2 402
CPU_VID<6>
10B6 CPU_VID<5>
10B6 CPU_VID<4>
10B6 CPU_VID<3>
73A3
10B6 CPU_VID<2>
73A3
10B6 CPU_VID<1>
10B6 CPU_VID<0>
1
1
FROM SMC
24A8
2
OUT
147K
1%
0.015uF
1
QFN
2 PSI*
3 IMON
48 3V3
47 CLK_EN*
DIDT=TRUE
IMVP6_UGATE1
62A8
34
IMVP6_PHASE1
62A8
32
33
IMVP6_LGATE1
(GND)
24
IMVP6_ISEN1
62A8
UGATE2 27
IMVP6_UGATE2
62A6
PHASE2 28
IMVP6_PHASE2
62A6
30
IMVP6_LGATE2
(GND)
PHASE1
LGATE1
PGND1
ISEN1
LGATE2
PGND2
29
IMVP6_ISEN2
IMVP6_SOFT
7 SOFT
VSUM
OCSET 8
19
62A4
IMVP6_RBIAS
4 RBIAS
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
62A4
IMVP6_VDIFF
13 VDIFF
VO
18
DROOP 16
1
R7409
1%
1/16W
MF-LF
2 402
1
0.001UF
10%
50V
CERM
402
2
1K
DFB
C7406
1
62A4
62A4
R7413
1K
IMVP6_VDIFF_RC
1
IMVP6_FB2
IMVP6_FB
62A4 IMVP6_COMP
62A4 IMVP6_VW
2
NO STUFF
R7411
1%
1/16W
MF-LF
402
12 FB2
11 FB
VSEN
10 COMP
9 VW
RTN
GND
1%
1/16W
MF-LF
2 402
62A4
62C8
1
IMVP6_COMP_RC
2
1
R7414
C7413
220PF
1
5%
25V
CERM
402
2
C7407
1
1%
1/16W
MF-LF
2 402
0.001UF
R7410
DIDT=TRUE
2
62A4
1
2
C7427
1
0.1UF
C7431
0.068UF
10%
10V
CERM
402
62A4
0.1UF
62C6
62C6
62C6
62C6
62C6
NO STUFF
62A4
C7416
1
R7418 R7417
1%
1/16W
MF-LF
2 402
10%
50V
CERM
402
2
5.36K
1%
1/16W
MF-LF
402
1
C7429
180pF
5%
2 50V
CERM
402
1
2
1
2
R7404
1
0.22uF
5%
1/16W
MF-LF
10%
6.3V
CERM-X5R
402
402
=PPVIN_S5_CPU_IMVP
CRITICAL
CRITICAL
C7401
33UF
20%
16V
POLY-TANT
CASED2E-SM
1
402
1
2
C7408
33UF
C
C7411
1
10%
25V
X5R
603-1
2
1
20%
16V
POLY-TANT 2
CASED2E-SM
1UF
C7422
0.001UF
20%
50V
CERM
402
RJK0305DPB
LFPAK-HF
(IMVP6_PHASE2)
1
R7401
3.65K
1%
1/16W
MF-LF
2 402
1
5
L7401
CRITICAL
DIDT=TRUE
MPC1055-SM
MPC1055LR36
DCR=0.8MOHM
RJK0328DPB
4
1%
1/16W
MF-LF
402
1 2 3
R7430
3.92K
C7428
10%
16V
CERM
402
2
10%
10.0V
CERM-X5R 2
402
10%
6.3V
CERM-X5R
402
0.12UF
1
2
R7405
10K
C7434 1
1
0.22UF
R7415
11K
1%
1/16W
MF-LF
2 402
2
1
1
2
CRITICAL
R7431
1
C7404
20%
50V
CERM
402
2
1
0.22uF
5%
1/16W
MF-LF
402
B
NO STUFF
2
1
C7402
1
0.0022UF
R7452
10K
R7443
3.65K
10%
50V
CERM
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
10KOHM-5%
(IMVP6_ISEN2)
2
(IMVP6_VSUM)
ERT-J1VR103J
(IMVP6_VO)
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
2
C7421
1
10%
6.3V
CERM-X5R
402
5%
1/16W
MF-LF
2 402
0.22uF
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
R7423
0
1
R7422
0
5%
1/16W
MF-LF
2 402
CPU_VCCSENSE_P
CPU_VCCSENSE_N
10B5 73A3
10A5 73A3
62C6
62C8 62B7
62C6
62C6
62B6
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
62B7
62B7
62B7
62B7
62B7
IMVP6_OCSET
IMVP6_VSUM
GND_IMVP6_SGND
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
IMVP6_RTN
IMVP6_VSEN
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.50 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.25 MM
IMVP6 CPU VCore Regulator
SYNC_MASTER=RAYMOND
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
0.25 MM
0.25 MM
0.25 MM
0.25 MM
5
4
3
SYNC_DATE=01/31/2008
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
D
APPLE INC.
2
REV.
051-7898
SCALE
SHT
NONE
6
C7423
0.001UF
R7407
10%
6.3V
CERM-X5R
402
NO STUFF
IMVP6_VO_R
2
2
LFPAK-HF
1
1%
1/16W
MF-LF
2 402
1
0.36UH-30A-0.80MOHM
Q7403
1%
1/16W
MF-LF
2 402
1
2
CRITICAL
2
13.7K
(IMVP6_VO)
1 2 3
DIDT=TRUE
R7416
62B5
7
20%
50V
CERM
402
2
Q7402
62A4
62B6
8
C7420
0.001UF
2
C7403
10K
1%
1/16W
MF-LF
10%
50V
CERM
402
CRITICAL
62C7
62C6
C7400
0.0022UF
62A4
62C7
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
1
2
R7400
NO STUFF
4
1
1
2
1
1
1/16W
MF-LF
402
DIDT=TRUE
IMVP6 CPU VCORE REGULATOR
62C6
MPC1055-SM
1
62C6
62C6
0.36UH-30A-0.80MOHM
RJK0328DPB
5
1K
2
7D8
MPC1055LR36
DCR=0.8MOHM
1 2 3
1
D
=PPVCORE_S0_CPU_REG
2
(IMVP6_ISEN1)
0.018UF
1
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
4
C7415
0.001UF
1
PWM FREQ. = 300 KHZ
MAX CURRENT = 44A
1
Q7401
62A4
1
20%
50V
CERM
402
L7400
10%
16V
X7R
402
XW7400
SM
62C6
(IMVP6_PHASE1)
0603-LF
OMIT
62C6
2
NO STUFF
R7451
10K
1%
10%
16V
2 X5R
402
10%
16V
X5R
402
C7433
(IMVP6_COMP)
MIN_LINE_WIDTH
1.5 MM
0.25 MM
1.5 MM
1.5 MM
0.25 MM
20%
16V
POLY-TANT 2
CASED2E-SM
C7419
0.001UF
LFPAK-HF
C7432
1
6.81K
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
A
1
1UF
CRITICAL
62A6
0.01UF
10%
50V
CERM
402
97.6K
1%
1/16W
MF-LF
2 402
C7418
10%
25V
X5R
603-1
CRITICAL
62D8 62D4 7B1
VOLTAGE=0V
(IMVP6_VW)
10%
50V
CERM
402
2
1
1-PHASE DCM
62A6
NO STUFF
470PF
1 2 3
DIDT=TRUE
2
62A4
15
49
1
GND_IMVP6_SGND
C7414
1
2
C7417
33UF
62A8
IMVP6_DFB
14
TPAD
21
(IMVP6_FB)
B
17
25 NC
255
5%
1/16W
MF-LF
402
35
UGATE1
ISEN2 23
62A4
2
26
0
IMVP6_BOOT162A8
IMVP6_BOOT2 62A6
5 VR_TT*
6 NTC
IMVP6_VR_TT
IMVP6_NTC
1/16W
MF-LF
402
10%
16V
X7R
402
CRITICAL
LOAD LINE SLOPE = -2.1 MV/A
2 IMVP6_BOOT2_RC
R7425
DIDT=TRUE
U7400BOOT2
44 VR_ON
IMVP_VR_ON
VR_PWRGOOD_DELAY 1 PGOOD
IN
R7408
C7405
20%
16V
POLY-TANT
CASED2E-SM
1
LFPAK-HF
1-PHASE DCM
DIDT=TRUE
PVCC
BOOT1 36
46 DPRSTP*
45 DPRSLPVR
IMVP6_IMON
40D8
VDD
39 VID2
38 VID1
37 VID0
(NC)
2
2
C7409
33UF
1-PHASE CCM
IMVP6_BOOT1_RC
2
402
1
31
CRITICAL
41 VID4
40 VID3
1/16W
MF-LF
CPU_PROCHOT_L 402
73C3 41D4 13B6 9C5
22
20
43 VID6
42 VID5
IN
OUT
CRITICAL
RJK0305DPB
5%
1/16W
MF-LF
5%
1/16W
MF-LF
2
CPU_DPRSTP_L
73B3 IMVP_DPRSLPVR
9B2
IN CPU_PSI_L
73B3 13A3 9B2
2-PHASE CCM
R7424
2.0K
73A3 10B6
CRITICAL
1
0
1
0
Q7400
4
DIDT=TRUE
0
VIN
R7426
470K
402
OPERATION MODE
DIDT=TRUE
NO STUFF
4.02K
1%
1/16W
MF-LF
402
1
1
1
10%
16V
X5R
402
10
5%
1/16W
MF-LF
402
1
CRITICAL
1
5
PP3V3_S0_IMVP6_3V3
2
PSI*
1
1
0
0
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
=PP3V3_S0_IMVP1
62B7 62A4
0.01UF
10%
16V
CERM
402
IMVP6_VSEN
7C5
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
C7496
1
DPRSTP*
0
0
1
1
20%
6.3V
X5R
603
PPVIN_S5_IMVP6_VIN
2
5%
1/16W
MF-LF
402
PM_DPRSLPVR
DPRSLPVR
10UF
2
=PPVIN_S5_CPU_IMVP
IN
C7435
1
IMVP6_RTN
62D4 62C3 7B1
5
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
C7426
ISL9504BCRZ
D
2
=PPVIN_S5_CPU_IMVP
PP5V_S0_IMVP6_VDD
2
2
3
4
5
=PP5V_S0_CPU_IMVP
7D5
73B3 20C7
6
7
4.7.0
OF
62
1
81
A
8
6
7
2
3
4
5
1
MCP VCORE POWER SUPPLY
7C1
D
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
5V_S0_MCPREG_VIN
R7593
C7550 1
2
1K
20C3 20A3
IN
IN
MCP_VID<0>
1
2
5%
1/16W
MF-LF
402
MCP_VID<1>
R7591
R7592
20C3 20A3
IN
MCP_VID<2>
1
0
0
1
MCPCORES0_SOFT
MCPCORES0_IMON_R
66A5
OUT
5%
1/16W
MF-LF
402
1NOSTUFF 1NOSTUFF
R7580 R7581
20.0K
PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE
PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE
1%
1/16W
MF-LF
2 402
20.0K
66C1
1%
1/16W
MF-LF
2 402
IN
MCPCORES0_PGOOD
MCP_VID0_R
MCP_VID1_R
MCP_VID2_R
MCPCORES0_OS0
MCPCORES0_OS1
=MCPCORES0_EN
MCPCORES0_FDE
MCPCORES0_VW
20.0K
1%
1/16W
MF-LF
2 402
MCPCORES0_COMP
2
1 2 3
MCPCORES0_PHASE
PPMCPCORE_S0_R
1NO
SPM6550T-COMBO
MCPCORES0_LGATE
4
GATE_NODE=TRUE
DIDT=TRUE
2
4
(Q7560 Limit)
=PPMCPCORE_S0_REG
1
3
10UF
20%
4V
X5R 2
603
MCPCORE_SNUBBER
MICROFET3X3
1
S
1
1
NO STUFF
2
C7567
10UF
C7589
2 3
f = 300 kHz
CRITICAL
1
FDMC8678S
G
20%
2 4V
X5R
603
0.001UF
50V 10%
X7R 402
C7565
R7566
20
1
MCPCORES0_RSEN_P
2
1%
1/16W
MF-LF
402
1
R7568
20
1
MCPCORES0_RSEN_N
1%
1/16W
MF-LF
402
2
C7576 1
1%
1/16W
MF-LF
2 402
(MCPCORES0_VSEN)
0.1UF
10%
16V
X7R-CERM 2
402
C7570
ICOMP 10
MCPCORES0_ICOMP
7 VDIFF
20
VSS
1
0.001UF
10%
2 50V
X7R
402
1
R7573
10K C7573 1
1%
1/16W
MF-LF
2 402
47PF
5%
50V
CERM 2
402
R7500
100
1
2
MCPCORES0_ISP_R
1%
1/16W
MF-LF
402
XW7561
SM
2
(MCPCORES0_ISN)
1
R7575
47.0K
1%
1/16W
MF-LF
2 402
1
R7571
100
1
C7575
47PF
5%
2 50V
CERM
402
(MCPCORES0_ICOMP)
1%
1/16W
MF-LF
2 402
B
1%
1/16W
MF-LF
402
150K
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
10%
50V
2 X7R
402
(MCPCORES0_RTN)
C
C7569
0.001UF
11.3K2
THRM_PAD
GND_MCPCORES0_AGND1
20%
2 2V
TANT
CASE-B4-SM
1
R7572
1%
1/16W
MF-LF
2 402
CRITICAL
C7568
270UF
20%
2 2V
TANT
CASE-B4-SM
(MCPCORES0_VO)
MCPCORES0_OCSET
MCPCORES0_ISP
MCPCORES0_ISN
1
270UF
R7569
ISP 13
ISN 11
6 FB
PGND
MCPCORES0_VO
OCSET 3
7C8 63B8 63C7
C7566 1
5%
1/10W
MF-LF
2 603
CRITICAL
Q7565
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
1%
1W
MF-1
0612
1
5
LGATE 21
STUFF
MAX CURRENT: 13A
0.001
L7560
0.82UH-16A
R7589
(MCPCORES0_LGATE)
R7525
CRITICAL
CERM-X7R
10V
603
5%
(MCPCORES0_PHASE)
SWITCHNODE
DIDT=TRUE
D
5 COMP
=PPMCPCORE_S0_REG
OMIT
CRITICAL
S
SWITCH_NODE=TRUE
DIDT=TRUE
VO 12
1%
1/16W
MF-LF
2 402
100
1
0.25 MM
0.2 MM
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
20.0K
R7563
XW7563
SM
1
2
MCPCORES0_BOOT_R
2
10%
2 25V
X5R
603-1
1
1
1
2
=PPMCPCORE_S0_REG
OMIT
PHASE 19
0
5%
1/10W
0.2 MM MF-LF
0.25 MM 603
MCPCORES0_BOOT
1UF
FDMC8676
C7564
0.22UF
R7565
MCPCORES0_UGATE 1
20%
2 16V
POLY-TANT
CASE-D2E-SM
C7561
POWER33-SM
GATE_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
20%
2 16V
POLY-TANT
CASE-D2E-SM
1
Q7560
G
4 VW
MCPCORES0_VDIFF
63C7 63C1 7C8
BOOT 17
68UF
R7582 1R7583
MCPCORES0_FB
PLACE XW NEAR THE MCP,
CONNECT SENSE LINES TO CLOSEST
MCPCORE AND GND BALL
OF MCP
PGOOD
VID0
VID1
VID2
OFFSET0
OFFSET1
VR_ON
AF_EN
FDE
VSEN
RTN
UGATE 18
C7571
1
PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE
PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE
XW7562
SM
28 IMON
4
(MCPCORES0_UGATE)
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VIN 14
QFN
2 SOFT
31
25
26
27
23
24
29
30
32
8
9
MCPCORES0_VSEN
MCPCORES0_RTN
C
63C1 63B8 7C8
1 RBIAS
U7500
2
5%
1/16W
MF-LF
402
2
MCPCORES0_RBIAS
D
PVCC
33
20C3 20A3
VDD
ISL6263D
5%
1/16W
MF-LF
2 402
1
68UF
5
1UF
D
CRITICAL
C7560
1
10%
50V 2
X7R
402
C7562
10%
2 16V
X5R
402
22
R7561
R7590
0
1
10%
16V 2
X5R
402
1
C7563 1
7D5
0.001UF
1UF
5%
1/16W
MF-LF
402
CRITICAL
=PP5V_S0_MCPREG
2
5%
1/10W
MF-LF
603
16
MCPCORES0_IMON
0
2.2
1
15
45D8
1
=PPVIN_S0_MCPCORE
R7560
B
(MCPCORES0_VW)
C7580
68PF
1
2
5%
50V
CERM
402-1
C7579 1
0.001UF
10%
50V 2
X7R
402
C7581
R7577
560PF
133K 2 MCPCORES0_COMP_C
1
2
1
1%
1/16W
MF-LF
402
10%
50V
CERM
402
R7578
1
100
1%
1/16W
MF-LF
402
A
2
1
R7576
VID<2:0>
MCP TARGET
6.98K
1%
1/16W
MF-LF
2 402
(MCPCORES0_COMP)
(MCPCORES0_FB)
C7582
560PF
1
2
MCPCORES0_VDIF_C
10%
50V
CERM
2.21K2
402
1
(MCPCORES0_VDIFF)
1%
1/16W
MF-LF
402
R7579
000
+1.05V
001
+1.00V
010
+0.95V
011
+0.90V
100
+0.85V
101
+0.80V
110
+0.75V
111
+0.70V
MCP CORE REGULATOR
SYNC_MASTER=K19_MLB
SYNC_DATE=12/10/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
63
1
81
A
8
6
7
2
3
4
5
1
CPUVTT POWER SUPPLY
D
7C1
D
=PPVIN_S0_CPUVTTS0
CRITICAL
C7630
1
1
20%
16V
POLY-TANT
CASED2E-SM
C7695
1
1UF
33UF
2
2
10%
25V
X5R
603-1
C7696
0.001UF
20%
50V
CERM
402
2
C
C
Q7620
FDMS9600S
9 4 3 2
MLP
CRITICAL1
7D5
L7620
=PP5V_S0_CPUVTTS0
R7601
Q1
PP5V_S0_CPUVTTS0_V5FILT
R7603 1
C7601
1
10%
10V
X5R
402-1
2
1UF
66C1
66A5
10
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
V5FILT
2
U7600
10%
6.3V
X5R-CERM
603
=CPUVTTS0_EN
1
2
CPUVTTS0_TON
CPUVTTS0_PGOOD
6
PGOOD
VBST
14
CPUVTTS0_VBST
3
VOUT
DRVH
13
5
VFB
LL
12
11
TRIP
DRVL
THRM_PAD
7
1
2
XW7665
Q2
CPUVTTS0_DRVH
GATE_NODE=TRUE
CPUVTTS0_LL
SWITCH_NODE=TRUE
9
CPUVTTS0_DRVL
GATE_NODE=TRUE
PGND
C7603
1
1
7 6 5
0.1UF
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
10%
50V
X7R
603-1
2
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
CPUVTTS0_VSNS
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
R7670
8.45K
R7604
1%
1/16W
MF-LF
2 402
8.87K
1%
1/16W
MF-LF
2 402
XW7600
<Ra>
SM
1
PCMB065T-SM
2
1
15
GND
10
SW
SM
IN
CPUVTTS0_TRIP
1%
1/16W
MF-LF
402
4.7UF
V5DRV
CRITICAL
OUT
CPUVTTS0_VFB
200K
C7604
TPS51117RGY_QFN14
SYM QFN
(2 OF 2)
EN_PSV
TON
(=PPCPUVTT_S0_REG)
B
1
8
8
2
4
301
1%
1/16W
MF-LF
402
2
NO STUFF
C7670
1
100PF
5%
50V
CERM
402
2
(GND)
ROUTING NOTE:
7D8
R7671
1
VOUT = 1.062V
8A max output
F = 320 KHZ
C7665
10UF
2
20%
6.3V
X5R
603
CRITICAL
C7660
330UF
20%
2.5V
TANT
CASE-B2-SM
2
20%
50V
CERM
402
0.001UF
1
2
2
XW7601
1
1%
1/16W
MF-LF
2 402
ROUTING NOTE:
<Rb>
GND_CPUVTTS0_SGND
C7661
B
20.0K
Place XW7600 between Pin 7 and Pin 15 of U7600.
1
SM
1
PLACEMENT_NOTE=Place XW7665 next to L7620
1
=PPCPUVTT_S0_REG
2.2UH-8.0A
1
2 CRITICAL
Place XW7601 by C7660.
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)
(CPUVTTS0_VFB)
CPUVTTS0_VOUT
(=PPCPUVTT_S0_REG)
CPU VTT(1.05V) SUPPLY
A
SYNC_MASTER=RAYMOND
SYNC_DATE=02/08/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
64
1
81
A
8
6
7
2
3
4
5
1
1.8V S0 SWITCHER
D
7B5
D
=PP3V3_S0_P1V8S0
CRITICAL
1
C7760
10uF
20%
6.3V
X5R
603
CRITICAL
VI
L7760
U7760
1
10UH-0.55A-330MOHM
TPS62202
4
2
66C1
=P1V8S0_EN
3
FB
EN
SW 5
MAX CURRENT = 200MA
PCAA031B-SM
SOT23-5
P1V8S0_SW
1
=PP1V8_S0_REG
2
DIDT=TRUE
GND
2
C7762
1
20%
6.3V
X5R
603
2
7B8
10uF
C
C
1.05V S0 PLL LDO
LDO_YES
7B5
=PP3V3_S0_MCP_PLL_VLDO
R7743
1
100
2
PP3V3_S0_MCP_PLL_VLDO_BIAS
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
LDO_NO
C7740 1
=PP1V05_S0_MCP_PLL_UF_R
7C7
1UF
10%
LDO_YES 6.3V
4
CERM 2
402
BIAS
1
0.0022UF
10%
50V
CERM 2
402
CRITICAL
7
FB
U7740
SS
PG
8
3
P1V05S0_LDO_FB
GND THRML_PAD
TP_P1V05S0_LDO_PGOOD
C7750
2
1%
1/16W
MF-LF
402
SON
22UF
=PP3V3_S5_P1V05S5
7A3
<Ra>
LDO_YES
1.37K
P1V05S0_LDO_SS
NOSTUFF
C7743
1
EN
PP1V05_S0_MCP_PLL_UF_LDO
9
10
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
R7746
<Rb>
1%
1/16W
MF-LF
402
MCP 1.05V S5 (AUXC) SUPPLY
5
11
1UF
B
IN0
OUT0
IN1 LDO_YES
OUT1
TPS74701
C7741 1
10%
LDO_YES 6.3V
CERM 2
402
1
2
4.42K
=PP1V5_S0_MCP_PLL_VLDO
6
7B6
0
1
2
5%
1/16W
MF-LF
402
Vout = 1.05V
MAX CURRENT = 0.5A
CRITICAL
R7745
C7742
4.7UF
=PP1V05_S0_MCP_PLL_UF
7B8 22C4
R7744
1
0
2
5%
1/16W
MF-LF
402
LDO_YES
20%
2 4V
X5R
402
B
LDO_YES
LDO_YES
R7747
20%
6.3V
CERM
805
VOUT = 0.8V * (1 + RA / RB)
1
VIN
CRITICAL
L7770
U7750
2.2UH-3.25A
ISL8009B
DFN
66D6
66B1
IN
=P1V05_S5_EN
P1V05_S5_PGOOD
2 EN
IHLP1616BZ-SM
CRITICAL
3 POR
LX 8
VFB 6
4 SKIP
RSI 5
GND
7
THRM_PAD
9
1
1V05S5_SW
DIDT=TRUE
1V05S5_FB
2
1
C7776 1
47PF
=PP1V05_S5_REG
<Ra>
R7780
255K
5%
50V
CERM 2
402
2
1
1%
1/16W
MF-LF
402
<Rb>
R7781
806K
2
A
7B4
Vout = 1.05V
CRITICAL
MAX CURRENT = 0.8A
1
C7771
FREQ = 1.6MHZ
2
20%
6.3V
CERM-X5R
0805
47UF
MISC POWER SUPPLIES
1%
1/16W
MF-LF
402
SYNC_MASTER=RAYMOND
SYNC_DATE=01/23/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
VOUT = 0.8V * (1 + RA / RB)
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
65
1
81
A
8
6
7
3.3V 1.05V S5 ENABLE
100K
2
=PP3V42_G3H_PWRCTL
1
PM_G2_P3V3S5_EN_L
5%
1/16W
MF-LF
402
1
D 3
1
100K
5%
1/16W
MF-LF
402
G
PM_SLP_S3_L
Run (S0)
1
1
1
1
1
0
Soft-Off (S5)
1
0
0
Battery Off (G3Hot)
0
0
0
CERM
1
R7800
PM_SLP_S4_L
Sleep (S3)
10%
10V
SMC_PM_G2_EN
IN
SMC_PM_G2_ENABLE
D
402
SOD-VESM-HF
60C5 40D5 6C3
State
NO STUFF
0.068UF
2
3.3V_S0, 1.8V_S0 ENABLE
MCPDDR, CPUVTT,MCPCORES0 ENABLE
1.5V S0 AND 1.05V S0 ENABLE
60A5
OUT
C7802
Q7800
D
=P3V3S5_EN_L
MAKE_BASE=TRUE
SSM3K15FV
1
Power Control Signals
R7802
66C8 66B3 7D1
2
3
4
5
S 2
R7801
2
2
5.1K
1 PM_G2_P1V05S5_EN
=P1V05_S5_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
1
OUT
65A8
C7801
0.47UF
2
10%
6.3V
CERM-X5R
402
(PM_SLP_S3_L)
70D8 40C5 35A5 32B7 20C3 6C3
IN
PM_SLP_S3_L
R7859
2
100
1
PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R7813
=PP3V42_G3H_PWRCTL
2
68K
5%
41A2 40C5 20C3 6C3
IN
5%
1/16W
MF-LF
402
22K
1
5%
1/16W
MF-LF
402
1
D 3
Q7813
PM_SLP_S3_L_INVERT
SSM3K15FV
=P5VS3_EN_L
MAKE_BASE=TRUE
SOD-VESM-HF
1
PM_SLP_S4_L
MAKE_BASE=TRUE
33K
5%
1/16W
MF-LF
402
1
1
0
=P5VS0_EN
OUT
67A8
=PBUSVSENS_EN
OUT
44B7
R7884
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10K
1
OUT
5.1K
P3V3S0_EN
60A7
G
P1V8S0_EN
C7813
2
S 2
=P3V3S0_EN
OUT
=P1V8S0_EN
OUT
65C7
=MCPDDR_EN
OUT
67C4
=CPUVTTS0_EN
OUT
64B7
=MCPCORES0_EN
OUT
63C6
MAKE_BASE=TRUE
NO STUFF
MAKE_BASE=TRUE
MCPDDR_EN
10%
10V
MAKE_BASE=TRUE
67B8
C
CERM
CPUVTTS0_EN
402
MAKE_BASE=TRUE
(PM_S4_STATE_L)
100K
5%
1/16W
MF-LF
402
1
R7883
2
2
0.068UF
R7810
R7882
2
2
R7881
2
1
1/16W
MF-LF
402
C
R7880
2
100K
S3 ENABLE
66D8 66B3 7D1
1
1
R7879
MCPCORES0_EN
MAKE_BASE=TRUE
2
1
0.47UF
5.1K
1
NO STUFF
C7810
R7811
1
2
2
2
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
C7880
1
MAKE_BASE=TRUE
=DDRREG_EN
OUT
61C8
=USB_PWR_EN
OUT
38B7
1
C7882
0.47UF
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
CERM-X5R
2
402
DDRREG_EN
C7881
0.47UF
CERM-X5R
402
2
1
C7883
1
0.47UF
CERM-X5R
2
CERM-X5R
402
C7884
0.47UF
10%
6.3V
2
402
10%
6.3V
CERM-X5R
402
NO STUFF
C7812
R7812
0.47UF
0
1
1
VOLTAGE MONITOR
2
2
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
66D8 66C8 7D1 =PP3V42_G3H_PWRCTL
P3V3S3_EN
=P3V3S3_EN
MAKE_BASE=TRUE
OUT
67C8
7A3
=PP3V3_S5_PWRCTL
C7840
B
1
1
0.1uF
20%
10V
CERM
402
100K
6
VDD
5 SENSE
U7840
B
R7840
2
2
RESET* 1
5%
1/16W
MF-LF
402
RSMRST_PWRGD
40D8
P1V05_S5_PGOOD
65A8
TPS3808G33DBVRG4
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
=PP5V_S0_VMON
CT
7D5
4 CT
SOT23-6
MR* 3
GND
10K
1%
1/16W
MF-LF
402
C7841
2
7
C7870
VDD
2
20%
50V
CERM
402
OTHER S0 RAILS PGOOD
U7870
20%
10V
CERM
402
TDFN
7D7
=PP1V5_S0_VMON
=PP1V05_S0_VMON
4
GND
MR*
RST*
1
2
1%
1/16W
MF-LF
402
1
7C5 =PP3V3_S0_PWRCTL
2
R7820
NC
1
10K
5%
1/16W
MF-LF
402
S0PGOOD_PWROK
8
2
THRM_PAD
9
7B6
3 V2MON
5 V3MON
6 V4MON
R7871
2
20.0K
0.1uF
ISL88042IRTEZ
7C5 =PP3V3_S0_VMON
1
1
0.001UF
PP3V3_VMON_VDD
353S2310
TPS3808 MR* HAS INTERNAL PULLUP
2
R7870
1
POWER SEQUENCING
Unused PGOOD signal
60A2
A
P5V3V3_PGOOD
IN
TP_DDRREG_PGOOD
DDRREG_PGOOD
61B3
SYNC_MASTER=YUAN.MA
SYNC_DATE=12/11/2008
MAKE_BASE=TRUE
63C6
V2MON THRESHOLD IS 2.866V
V3MON THRESHOLD IS 0.6V
V4MON THRESHOLD IS 0.6V
64B7
MCPCORES0_PGOOD
IN
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
CPUVTTS0_PGOOD
IN
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
ALL_SYS_PWRGD
OUT
MAKE_BASE=TRUE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
24B8 40D8
SIZE
(S0PGOOD_PWROK)
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
66
1
81
A
8
6
7
5
2
3
4
1
1.5V S0 FET
3.3V S3 FET
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
CRITICAL
Q7910
=PP3V3_S3_FET
=PP3V3_S5_P3V3S3FET
D
3.3V S3 FET
7D4
9
5
MOSFET
FDC638P
CHANNEL
P-TYPE
CRITICAL
Q7901
6
DFN
X5R
2
402
402
3
R7910
2
P3V3S3_EN_L
1
47K
48 mOhm @4.5V
LOADING
C7910
0.182 A (EDP)
7C3
1
P3V3S3_SS
2
R7903 1
10%
Q7903
MF-LF
16V
402
CERM
Q7971
5%
1/16W
MF-LF
402
SOD-VESM-HF
66B6
1
S 2
=P3V3S3_EN
IN
Q7971
1
2
3
D
47K
2
5
S
1
1
C7903
10%
10V
CERM
402
MCPDDR_EN_L_RC
7C8
1.5V S0 FET
0.068UF
2
SSM6N15FEAPE
OUT
P1V5_S0_SENSE
2
5%
1/16W
MF-LF
402
3
G
OUT
P1V5_S0_KELVIN
=PP1V5_S0_FET
2
R7971
G
7
6
SOT563
MCPDDR_EN_L
1
D
KELVIN 6
S
SSM6N15FEAPE
100K
402
D 3
4 G
2
MCPDDR_SS
2
5%
1/16W
MF-LF
402
2
5%
SSM3K15FV
10K
1
0.01UF
1/16W
20%
10V
CERM
402
R7901
=PP5V_S3_MCPDDRFET
45D8
RDS(ON)
10%
16V
5%
1/16W
MF-LF
NC 8
0.1UF
1
0.033UF
10K
C7902
GND
1
1
SENSE
R7912
C7911
1
2
D
ROME
D
4
45C8
SM
7A3
=PP1V5_S3_P1V5S0FET
7D3
FDC638P_G
MOSFET
Rome SenseFET
CHANNEL
N-TYPE
RDS(ON)
SOT563
6.3 mOHM @4.5V VGS
LOADING
5
3.3V S0 FET
66C1
IN
G
S
5A (EDP)
4
=MCPDDR_EN
CRITICAL
Q7930
C
C
FDC606P_G
10%
16V
5%
1/16W
X5R
MF-LF
402
P3V3S0_EN_L
1
2
1
D
FDC606P
CHANNEL
P-TYPE
RDS(ON)
26 MOHM @4.5V
LOADING
C7930
R7930
47K
MOSFET
G
2
402
2
3.3V S0 FET
7D6
1
0.033UF
100K
=PP3V3_S0_FET
3
R7932
C7931
1
S
=PP3V3_S5_P3V3S0FET
4
7A3
5 6
SOT-6
1.431 A (EDP)
0.01UF
1
P3V3S0_SS
2
2
5%
10%
1/16W
Q7905
SSM3K15FV
16V
MF-LF
CERM
402
402
D 3
SOD-VESM-HF
MCP79 DDRVTT FET
1
66C1
G
=P3V3S0_EN
IN
S 2
B
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
LOW THROUGH VTT TERMINATION RESISTORS.
5.0V S0 FET
B
CRITICAL
Q7940
10%
16V
5%
1/16W
X5R
MF-LF
402
1
47K
2
5
D
CHANNEL
P-TYPE
7C7
6
TPCP8102
LOADING
C7940
R7940
P5V0S0_EN_L
R7975
MOSFET
RDS(ON)
2
402
2
5.0V S0 FET
7D6
=PPVTT_S0_VTTCLAMP
2
13.5 MOHM @4.5V
7C3
1.7 A (EDP)
1
Q7945
SSM3K15FV
16V
CERM
CKT FROM T18
5%
1/16W
MF-LF
402
D
6
S
1
SOT563
100K
10%
402
90mA max load @ 0.9V
81mW max power
SSM6N15FEAPE
R7976 1
2
MF-LF
VTTCLAMP_L
Q7975
5%
1/16W
1
=PP5V_S3_VTTCLAMP
0.01UF
P5V0S0_SS
10
5%
1/10W
MF-LF
603
G
1
0.033UF
47K
=PP5V_S0_FET
4
R7942
C7941
1
S
3
=PP5V_S3_P5VS0FET
1 2
7C3
7 8
TPCP8102
376S0778
23V1K-SM
2
2
G
402
D 3
VTTCLAMP_EN
SOD-VESM-HF
Q7975
D
3
SSM6N15FEAPE
1
66C1
IN
=P5VS0_EN
G
S 2
A
5
61C8 24C1
IN
G
NO STUFF
C7976
1
0.001UF
SOT563
20%
50V
CERM
402
S
POWER FETS
2
SYNC_MASTER=YUAN.MA
4
SYNC_DATE=12/11/2008
NOTICE OF PROPRIETARY PROPERTY
=DDRVTT_EN
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
.
.
REV.
051-7898
4.7.0
OF
67
1
81
A
8
6
7
2
3
4
5
1
D
D
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP
17B6
LCD
LVDS_IG_PANEL_PWR
LVDS CONNECTOR:518S0650
R9014
1K
1
CRITICAL
J9000
5%
1/16W
MF-LF
2402
20474-030E-11
C9015
CRITICAL
FPF1009
1 ON
=PP3V3_S5_LCD
C
1
C9009
0.1UF
10%
50V
X7R
402
L9004
MFET-2X2
FERR-120-OHM-1.5A
2 VIN_1
VOUT_1 4
PP3V3_LCDVDD_SW
3 VIN_2
VOUT_2 5
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
GND
6
C9010
1
0.001UF
U9000
7A3
CONNECTOR
THRM
PAD
7
1
C9011
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
1
C9012
1
1
=PP3V3_S0_LCD
1
R9008
100K
5%
1/16W
MF-LF
2 402
17B3 6C7
17A3 6C7
PP3V3_LCDVDD_SW_F
3
MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
CRITICAL
6B7
2
0402-LF
7C5
1
2
6C7 6C3
L9008
32
2
120-OHM-0.3A-EMI
10UF
20%
2 6.3V
X5R
603
10%
50V
X7R
402
2
2
0402-LF
F-RT-SM
31
1
0.001UF
6C7
4
TP_BKL_SYNC
5
PP3V3_S0_LCD_F
C
6
MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V
7
MIN_NECK_WIDTH=0.20 MM
17B3 6C7
75B3
(LVDS DDC POWER)
17B3 6C7
75B3
1
R9009
17B3 6C7
75B3
75B3 17B3 6C7
100K
5%
1/16W
MF-LF
2 402
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
8
9
10
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
11
12
13
75B3 17B3 6C7
75B3 17B3 6C7
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
14
15
16
CRITICAL
L9080
90-OHM-200MA
AMC2012-SM
SYM_VER-1
75B3 17B3
LVDS_IG_A_CLK_N
4
LVDS_IG_A_CLK_F_N
6C7 LVDS_IG_A_CLK_F_P
75B3 6C7
17
75B3
18
1
20
NC
75B3 17B3
LVDS_IG_A_CLK_P
3
2
71B1 6C7
71B1 6C7
71B1 6C7
71B1 6B7
71B1 6B7
71A1 6B7
LVDS I/F
19
71C1 6C7 6C3
21
PPVOUT_S0_LCDBKLT
22
23
NC
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
LED BKLT I/F
24
25
26
27
28
29
30
NC
B
B
33
34
LVDS CONNECTOR
SYNC_MASTER=NMARTIN
SYNC_DATE=04/04/2008
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
68
1
81
A
8
6
7
3
4
5
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
D
17A3
17A3
DP_AUX_CH_C_N
69D1
BI
1
BI
DP_IG_DDC_CLK
0.1UF
1
2
5%
1/16W
MF-LF
402
Display Port Interoperability spec says that sources
or sinks which do both DP and DVI must depend on the
external adapter for pull ups on DDC lines (since DP
AUX CH has 100K pull up/down on the MLB)..
69D1
33
1
33
5%
1/16W
MF-LF
402
C
2
75B3
2
0.1UF
1
2
75B3
4
BI
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
D
70A8
MAKE_BASE=TRUE
DP_IG_DDC_CLK
DP_IG_DDC_DATA
69C8
MAKE_BASE=TRUE
69C8
MAKE_BASE=TRUE
70C8 75B3
DP_AUX_CH_C_P
BI
70C8 75B3
DP_AUX_CH_SW_P
Q9300
D
SOT563
75B3 17B6
70C8 75C3
MAKE_BASE=TRUE
10%
16V
X5R
402
SSM6N15FEAPE
BI
70C8 75C3
MAKE_BASE=TRUE
C9301
3
75B3 17B6
DP_ML_P<3>
DP_ML_N<3>
DP_ML_P<2>
DP_ML_N<2>
DP_ML_P<1>
DP_ML_N<1>
DP_ML_P<0>
DP_ML_N<0>
DP_HPD
DP_AUX_CH_SW_N
10%
16V
X5R
402
R9301
1
C9300
R9300
DP_IG_DDC_DATA
BI
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
=MCP_HDMI_HPD
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
2
S
Q9300
C
D 6
SSM6N15FEAPE
SOT563
G 5
2
G
S 1
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
=PP5V_S0_DP_AUX_MUX
7D5
R9302
1
100K
5%
1/16W
MF-LF
2 402
R9306
1
1K
5%
1/16W
MF-LF
402 2
DDC_CA_DET_LS5V_L
B
B
Q9301
3
D
SSM3K15FV
SOD-VESM-HF
2
70B8
IN
S
G 1
DP_CA_DET
DP_IG_CA_DET
OUT
17B6
DISPLAYPORT SUPPORT
A
SYNC_MASTER=AMASON
SYNC_DATE=04/18/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
69
1
81
A
8
6
7
2
3
4
5
1
Port Power Switch
DP_ESD
CRITICAL
CRITICAL
L9400
7A3
66D5 40C5 35A5 32B7 20C3 6C3
5 IN
=PP3V3_S5_DP_PORT_PWR
IN
4 EN
PM_SLP_S3_L
FERR-120-OHM-3A
TPS2051B
SOT23
OUT 1
PP3V3_S0_DPILIM
OC* 3
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
TP_DPPWR_OC_L
2
0603
1
GND
2
C9400
D9410
RCLAMP0524P
SLP2510P8
SLP2510P8
PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
5 IO
IO
NC
6 NC
4.7UF
2
D
D9410
RCLAMP0524P
20%
6.3V
X5R-CERM
402
4
2 IO
7
9 NC
IO
NC
GND
U9480
GND
D
DP_ESD
CRITICAL
3
3
1
10
CRITICAL
C9480
1
1
22UF
20%
6.3V
X5R-CERM-1
603
C9481
4.7UF
2
2
1
20%
6.3V
X5R-CERM-1
603
2
20%
2 6.3V
X5R-CERM-1
603
22UF
22UF
20%
6.3V
X5R-CERM
402
C9486
C9485
1
R9420
1
100K
5%
1/16W
MF-LF
402
2
CRITICAL
J9400
HDMI_CEC
DSPLYPRT-M97-1
FL9400
F-RT-THSM
1
C
R9425
1M
FL9403
12-OHM-100MA
DP_ML_P<3>
C9414
75C3 69D1
IN
DP_ML_N<3>
C9415
75B3 69C4
BI
DP_AUX_CH_C_P
BI
DP_AUX_CH_C_N
1
2 75C3 DP_ML_C_P<3>
10%
16V
X5R
402
1
2 75C3 DP_ML_C_N<3>
10%
16V
X5R
402
0.1uF
0.1uF
TCM1210-4SM
SYM_VER-2
TOP ROW
TH PINS
SM PINS
2
6
8
2
75B3
DP_ML_CONN_P<3>
DP_ML_CONN_N<3>
10
12
ML_LANE3N
GND
AUX_CHP
AUX_CHN
DP_PWR
14
16
18
75B3 69D4
70B8 7C5
20
DP_ESD
CRITICAL
=PP3V3_S0_DPCONN
R9443 1
5%
1/16W
MF-LF
402
69B7
OUT
DP_CA_DET
100K
5%
1/16W
MF-LF
402
2
R9421
5%
1/16W
MF-LF
402
2
2 IO
2
IO
NC
9 NC
G
2
DP_CA_DET_L_Q
3
SOT-363
DP_ML_CONN_P<2>
75B3
DP_ML_CONN_N<2>
75C3
DP_ML_C_N<0>
19
C9411
1
TCM1210-4SM
SYM_VER-2
DP_ML_C_P<1>
C9412
75C3
DP_ML_C_N<1>
C9413
75C3
DP_ML_C_P<2>
C9416
16V
1
2
10%
DP_ML_N<1>
1
2
DP_ML_P<2>
3
75C3
DP_ML_C_N<2>
C9417
1
0.1uF
16V
16V
X5R
X5R
X5R
X5R
402
402
402
10%
16V
2
DP_ML_N<2>
10%
16V
X5R
C
402
DP_ML_P<1>
0.1uF
2
DP_ML_N<0>
X5R
2
10%
0.1uF
4
2
16V
10%
0.1uF
FL9402
12-OHM-100MA
1
75C3
DP_ML_P<0>
1
0.1uF
3
75B3
3
2
10%
402
402
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
21
514-0637
DP_ESD
CRITICAL
D9411
RCLAMP0524P
SLP2510P8
RCLAMP0504F
SC70-6-1
S
G
DP_CA_DET_Q
5
4
R9422
1
DP to DVI/HDMI
Cable Adapter
(CA) has 100k
pull-up to DP_PWR.
1
1M
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
5%
1/16W
MF-LF
402
2
5 IO
6
IO
NC
6 NC
B
4
7
5
3
3
4
2
=PP3V3_S0_DPCONN
R9445 1
R9444 1
10K
5%
1/16W
MF-LF
402
69D1
2
4
17
D9400
2N7002DW-X-G
70C8 7C5
15
DP_ESD
CRITICAL
D
Q9440
B
2
1
0.1uF
13
10
3
1
DP_ML_CONN_P<1>
DP_ML_CONN_N<1>
C9410
1
GND
D
S
75B3
11
SYM_VER-2
DP_ML_C_P<0>
100K
2N7002DW-X-G
SOT-363
9
12-OHM-100MA
TCM1210-4SM
4
SLP2510P8
6
Q9440
7
ML_LANE1N
GND
ML_LANE2P
ML_LANE2N
RETURN
22
RCLAMP0524P
1
1
SYM_VER-2
75C3
FL9401
5
12-OHM-100MA
TCM1210-4SM
SHIELD PINS
D9411
R9442 1
100K
75B3
3
75B3
1
DP_ML_CONN_P<0>
DP_ML_CONN_N<0>
75B3
1
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
4
1
75B3
3
BOT ROW
GND
IN
75C3 69D1
4
2
5%
1/16W
MF-LF
402
OUT
DP_HPD
10K
5%
1/16W
MF-LF
402
2
2
6
R9446 1
100K
5%
1/16W
MF-LF
402
2
MCP79 requires pull
Q9441
down HPD input with
2N7002DW-X-G
SOT-363
100K if DP_HPD is used.
D
S
G
2
DP_HPD_L_Q
3
1
A
DisplayPort Connector
D
Q9441
2N7002DW-X-G
SYNC_MASTER=AMASON
SOT-363
S
G
5
DP_HPD_Q
SYNC_DATE=06/30/2008
NOTICE OF PROPRIETARY PROPERTY
4
R9423
1
100K
5%
1/16W
MF-LF
402
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
70
1
81
A
8
6
7
2
3
4
5
1
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
BKLT_VLDO_EN_L
NO STUFF
Q9701
NTUD3127CXXG
SOT-963
N-CHANNEL
6
D
NO STUFF
R9701
G
D
BKLT_EN_R
2
0
1
S
BKLT_EN
2
D
71B6
5%
1/16W
MF-LF
402
1
3
D
NO STUFF
R9735
G
5
1
S
100K
2
1%
1/16W
MF-LF
402
4
P-CHANNEL
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
=PP5V_S0_BKL
7D5
NO STUFF
VOLTAGE=5V
1
R9702
0
5%
1/16W
MF-LF
CRITICAL
2 402
C
PPVIN_BKL
2
CRITICAL
0
C9712
1
5%
1/16W
MF-LF
402
1
10UF
2
71B5 71C2
1
C9710
1
1UF
C9711
0.1UF
10%
2 25V
X5R
603-1
10%
2 16V
X5R
402
VDDIO
NC
5%
1/16W
MF-LF
402
20 ADR
2
5%
R9757
0
1
1/16W
BKL_SDA
11 SDA
402
2
5%
MF-LF
402
R9731
PPBUS_S0_LCDBKLT_PWR
71D3
C9723
10%
25V
X5R
402
BKL_ISEN2
OUT3 14
BKL_ISEN3
OUT4 16
BKL_ISEN4
TP_BKL_FAULT
7 FAULT
OUT6 18
4 EN
OUT7 19
BKL_SWGND HIGH CURRENT
NEED 2 VIAS
1%
1/16W
MF-LF
402
1
LVDS_IG_BKL_PWM
1
0
BKL_ISEN5
BKL_ISEN6
R9704 SHOULD BE 47K IF RC FILTER IS USED
10%
2 100V
X7R
1210
1
C9797
C
2.2UF
10%
100V
2 X7R
1210
71B5 71C5
2
1
THRM
PAD
33PF
BKL_SGND
5%
50V
LED_RETURN_2
2
0
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
6C7 68B3
OUT
6C7 68B3
B
LED_RETURN_3
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
0
LED_RETURN_4
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
5%
1/16W
MF-LF
402
OUT
6C7 68B3
OUT
6B7 68B3
OUT
6B7 68B3
OUT
6B7 68B3
R9721
1
XW9710
SM
C9704
OUT
R9720
1
BKL_SWGND
NO STUFF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
1
0
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
71C5
71C2
LED_RETURN_1
2
BKLT_PROD
R9719
NC
2
5%
1/16W
MF-LF
402
2.2UF
R9718
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACEMENT_NOTE=SW9700 PLACE NEAR C9712 C9713
R9704
0
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
XW9700
SM
NO STUFF
IN
OMIT
BKL_ISEN1
OUT2 13
BKLT_EN
R9715
100K
0.1UF
2
72B7 17B6
OUT1 12
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
1
C9799
R9717
FB 21
2
1%
1/16W
MF-LF
402
1
BKL_SWGND
SW 24
OUT5 17
1 GND_SW
301K
2
1
1
72C3 71C7
5%
2 100V
CERM
1206
CRITICAL
2 PWM
LVDS_IG_BKL_PWM_RC
B
200PF
25
=I2C_BKL_1_SDA
MF-LF
10 SCLK
15 GND_L
43B6
1/16W
VIN
3 IF_SEL
BKL_SCL
9 GND_S
1
6 ALSO
5 ALSI
IF_SEL=1 FOR SMBUS
IF_SEL=0 FOR I2C
BKL_IF_SEL
0
VLDO
LP8543SQX
100K
R9753
C9796
LLP
R9714
=I2C_BKL_1_SCL
1
VOLTAGE=50V
U9701
NO STUFF
43B6
23
10%
2 16V
CERM
402
6C3 6C7 68B2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
5%
1/16W
MF-LF
402
22
0.01UF
8
C9714
PPVOUT_S0_LCDBKLT
2
RB160M-40
VOLTAGE=50V
SWITCH_NODE=TRUE
PPVIN_BKL_R
1
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
0
=PP3V3_S0_BKL_VDDIO
5%
1/16W
MF-LF
402
PPBUS_S0_LCDBKLT_PWR_SW
R9703
BKL_VLDO
100K
2
IHLP2525CZ-SM
1
10%
25V
X5R
402
2
R9716
1
VOLTAGE=6V
0.1UF
10%
25V
X5R
805
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
C9713
BKL_SWGND
7B5
D9701
SOD-123
22UH-2.5A
R9700
PPBUS_S0_LCDBKLT_PWR
1
72C3 71B7
CRITICAL
L9701
BKLT_PROD
1
0
LED_RETURN_5
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
5%
1/16W
MF-LF
402
R9722
2
1
2 CERM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
402
0
5%
1/16W
MF-LF
402
LED_RETURN_6
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
LCD BACKLIGHT DRIVER
A
SYNC_MASTER=KIRAN
SYNC_DATE=12/05/2008
NOTICE OF PROPRIETARY PROPERTY
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
103S0198
6
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
R9717,R9718,R9719,R9720,R9721,R9722
BKLT_ENG
116S0005
1
RES,1/16W,0.1 OHM,1%,0402,SM
R9700
BKLT_ENG
PART NUMBER
353S2670
QTY
1
DESCRIPTION
REFERENCE DES
IC,LP8543,WHT LED BKLT CTRLR,QFN24,PROD
U9701
CRITICAL
BOM OPTION
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
CRITICAL
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
71
1
81
A
8
6
7
4
5
2
3
1
CRITICAL
Q9806
FDC638APZ_SBMS001
PPBUS S0 LCDBkLT FET
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
0402-HF
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
R9808
1
301K
FDC638APZ
CHANNEL
P-TYPE
LOADING
0.1UF
10%
16V
X5R
402
1/16W
2
MF-LF
RDS(ON)
D
43 mOhm @4.5V
C9802
1%
2
MOSFET
1
IN
2
402
0.4 A (EDP)
3
D
1
=PPBUS_S0_LCDBKLT
4
2AMP-32V
7C1
6
F9800
2 5
SSOT6-HF
PPBUS_S0_LCDBKLT_EN_DIV
1
R9809
147K
1%
1/16W
MF-LF
2
402
PPBUS_S0_LCDBKLT_EN_L
Q9807
D
3
S
4
SSM6N15FEAPE
SOT563
72B7 17B6
5
LVDS_IG_BKL_ON
IN
G
PPBUS_S0_LCDBKLT_PWR
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
BKLT_EN_L
Q9807
D
6
S
1
OUT
71B7 71C7
SSM6N15FEAPE
SOT563
C
24C1
2
BKLT_PLT_RST_L
IN
G
C
B
B
LVDS_IG_BKL_ON
LVDS_IG_BKL_PWM
1
R9840
1K
2
5%
1/16W
MF-LF
402
17B6 72C8
17B6 71A7
1
R9841
1K
5%
1/16W
MF-LF
2 402
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS
LCD Backlight Support
A
SYNC_MASTER=YITE
SYNC_DATE=06/30/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
.
REV.
051-7898
4.7.0
OF
72
1
81
A
8
6
7
FSB (Front-Side Bus) Constraints
2
3
4
5
1
CPU / FSB Net Properties
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADSTB0
FSB_50S
FSB_ADSTB
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_ADSTB1
FSB_50S
FSB_ADSTB
FSB_1X
FSB_50S
FSB_1X
FSB_BREQ0_L
FSB_50S
FSB_1X
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_BSEL
CPU_50S
CPU_AGTL
CPU_FERR_L
CPU_50S
CPU_8MIL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
CPU_FROM_SB
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
CPU_IERR_L
CPU_50S
PM_DPRSLPVR
CPU_50S
CPU_AGTL
(See above)
CPU_50S
CPU_AGTL
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO
CPU_50S
CPU_ITP
XDP_TMS
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L5
CPU_50S
CPU_ITP
(FSB_CPURST_L)
CPU_50S
CPU_ITP
CPU_50S
CPU_8MIL
TABLE_PHYSICAL_RULE_ITEM
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
*
=2x_DIELECTRIC
?
FSB_DSTB
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
FSB_ADDR
*
=STANDARD
TABLE_SPACING_RULE_ITEM
?
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_ADSTB
*
=2x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_1X
*
=STANDARD
FSB 4X Signal Groups
FSB_DSTB_50S
TABLE_SPACING_RULE_ITEM
?
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
?
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 2X
Signals
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
FSB 1X Signals
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
C
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_AGTL
*
=STANDARD
TABLE_SPACING_RULE_ITEM
?
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
CPU_8MIL
*
8 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_COMP
*
25 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_GTLREF
*
25 MIL
SR DG recommends at least 25 mils, >50 mils preferred
?
TABLE_SPACING_RULE_ITEM
CPU_ITP
*
=2:1_SPACING
?
CPU_VCCSENSE
*
25 MIL
?
TABLE_SPACING_RULE_ITEM
Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_50S
*
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
B
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MCP_FSB_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
CLK_FSB_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
CLK_FSB
*
=3x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
A
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<35..17>
FSB_ADSTB_L<1>
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
CPU_50S
CPU_8MIL
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
(CPU_VCCSENSE)
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
9C4 13D3
9C4 13D6
9C4 13D6
9C4 13D6
9B4 9C4 13C3 13D3
9B4 13D6
9B4 13D6
D
9B4 13D6
9C2 13B3 13C3
9C2 13D6
9C2 13D6
9C2 13D6
9B2 9C2 13B3
9B2 13D6
9B2 13D6
9B2 13D6
9D8 13C6 13D6
9D8 13B6
9D8 13B6
9C8 9D8 13C6
9C8 13B6
9D6 13B6
9D6 13B6
13B6
9D6 13B6
9D6 13B3
9D6 13B6
9D6 13B3
9D6 13B6
9D6 13B6
9D6 13B6
C
9D6 13B6
9D6 12C2 13A3
9D6 13A6
9D6 13B6
9C8 13A3
8B2 9B4
9C8 13B7
9C8 13A3
9D6 13A3
9C8 13A3
9B8 13A3
9C5 13B6 41D4 62C8
9B2 12C7 13A3
9B8 13A3
9C8 13A3
9C6 13B7 41C4
9B2 13A3
9B2 13A3
9B2 13A3 62C7
9B2 13A3
13A6
13A6
13A6
13A6
9B6 13B3
B
9B6 13B3
12C3 13B3
12C3 13B3
13A4
13A4
9D6
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
20C7 62D8
62C7
9B4 25B1
9B3
9B3
9B3
9B3
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
9B6 9C6 12B3
9B6 9C6 12B3
9B6 9C6 12B3
9A6 9C6 12B6
9A6 9C6 12B3
9C6 12C6
9C5 12C6
12C4
10B6 62C7
CPU/FSB Constraints
10B5 62A5
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
10A5 62A5
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
73
1
81
A
8
6
7
Memory Bus Constraints
2
3
4
5
1
Memory Net Properties
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
TABLE_PHYSICAL_RULE_ITEM
MEM_40S_VDD
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
14B5 26C5 26C7
14B5 26C5 26C7
TABLE_PHYSICAL_RULE_ITEM
MEM_70D
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
D
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=2:1_SPACING
?
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
14A5 26D5 26D7
14B5 26C5 26C7
14B5 26C5
14B5 14C5 26C5 26C7
D
14C5 26C5 26C7
14C5 26C5
14C5 26C7
14C5 26C7
TABLE_SPACING_RULE_ITEM
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
MEM_CMD2CMD
*
=1.5:1_SPACING
?
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MCP MEM COMP Signal Constraints
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DATA2DATA
*
=1.5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DATA2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
14B7 26C2 26C4 26D2 26D4
14B7 26C2 26C4
14B7 14C7 26B2 26B4 26C2 26C4
14C7 26C2 26C4
14C7 26B5 26B7 26C5 26C7
14C7 14D7 26B5 26B7
14D7 26B5 26B7
14D7 26A5 26A7 26B5 26B7
TABLE_SPACING_RULE_ITEM
MEM_2OTHER
*
25 MIL
?
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CLK
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CTRL
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CMD
*
MEM_CLK2MEM
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
MEM_CLK
MEM_DQS
*
MEM_CLK2MEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
MEM_CMD
MEM_DATA
*
MEM_CMD2MEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
C
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CTRL
*
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_CTRL
*
MEM_DATA2MEM
MEM_DATA
MEM_CMD
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DATA
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DATA
*
MEM_DATA2DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DQS
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DQS
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
*
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
*
*
MEM_2OTHER
MEM_CTRL
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DATA
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DQS
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
*
*
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR2:
B
DQ signals should be matched within 20 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DDR3:
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
MCP_MEM_COMP
*
Y
7 MIL
7 MIL
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MCP_MEM_COMP
*
8 MIL
14A7 26C2
14B7 26B4
14B7 26C2
14B7 26B5
14B7 26B7
14B7 26B5
14B7 26A7
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
14D5 26C2
14D5 26D2
14D5 26C4
14D5 26C4
14D5 26B2
14D5 26C2
C
14D5 26C4
14D5 26C4
14D5 26B7
14D5 26B7
14D5 26B5
14D5 26B5
14D5 26B7
14D5 26B7
14D5 26A5
14D5 26A5
14B1 27C5 27C7
14B1 27C5 27C7
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
14A7 26C4
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
A
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
14A1 27D5 27D7
14B1 27C5 27C7
14B1 27C5
14B1 14C1 27C5 27C7
14C1 27C5 27C7
14C1 27C5
14C1 27C7
14C1 27C7
14B3 27C2 27C4 27D2 27D4
14B3 27C2 27C4
14B3 14C3 27C2 27C4
14C3 27B2 27B4 27C2 27C4
B
14C3 27B5 27B7 27C5 27C7
14C3 14D3 27B5 27B7
14D3 27B5 27B7
14D3 27A5 27A7 27B5 27B7
14A3 27C4
14A3 27C2
14B3 27C2
14B3 27B4
14B3 27B5
14B3 27B7
14B3 27B5
14B3 27A7
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
14D1 27C2
14D1 27D2
14D1 27C4
14D1 27C4
14D1 27C4
14D1 27C4
14D1 27B2
14D1 27C2
14D1 27B7
14D1 27B7
14D1 27B5
Memory Constraints
14D1 27B5
14D1 27B7
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
14D1 27B7
NOTICE OF PROPRIETARY PROPERTY
14D1 27A5
14D1 27A5
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
15C6
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
15C6
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
74
1
81
A
8
6
7
2
3
4
5
1
NET_TYPE
PCI-Express
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
PCIE_MINI_R2D
TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PCIE_MINI_D2R
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
MCP_PEX_COMP
MCP_PEX_CLK_COMP
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE
*
=3X_DIELECTRIC
?
CLK_PCIE
*
20 MIL
?
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
D
PCIE_FW_R2D
TABLE_SPACING_RULE_ITEM
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
PCIE_FW_D2R
MCP_PE1_REFCLK
MCP_PE4_REFCLK
MCP_PEX_CLK_COMP
C
6D5 29C7
6D5 29C7
16B3 29C5
16B3 29C5
6D5 16B6 29C7
6D5 16B6 29C7
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MCP_PEX_COMP
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_90D
TABLE_PHYSICAL_RULE_ITEM
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N
34C3
34C3
D
16B3 34C1
16B3 34C1
16B6 34C1
16B6 34C1
34C3
34C3
16C3 29C5
16C3 29C5
6D5 29C7
6D5 29C7
16A6
C
Digital Video Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
DP_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
*
Y
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
*
=3x_DIELECTRIC
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
*
?
=3x_DIELECTRIC
DISPLAYPORT
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
TABLE_SPACING_RULE_ITEM
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
LVDS
DP_100D
TMDS_IG_TXC
DP_ML
TABLE_SPACING_RULE_ITEM
?
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
DP_AUX_CH
SATA Interface Constraints
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
DP_ML_P<3..0>
DP_ML_C_P<3..0>
DP_ML_N<3..0>
DP_ML_C_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
DP_AUX_CH_SW_P
DP_AUX_CH_SW_N
DP_AUX_CH_C_P
DP_AUX_CH_C_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE
MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_VPROBE
MCP_DV_COMP
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
DP_ML
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD_N<2..0>
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
DISPLAYPORT
TMDS_IG_TXC
69D1 70C1 70C8
70C2 70C7
69D1 70C1 70C8
70C2 70C7
17B6 69C7
17B6 69C7
69C6
69C5
69C4 70C8
69D4 70C8
17A6 23C7
17A6 23C7
TABLE_PHYSICAL_RULE_ITEM
SATA_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SATA_90D_HDD
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
LVDS_IG_A_CLK
B
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA
*
TABLE_SPACING_RULE_ITEM
SATA
TOP,BOTTOM
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_F_P
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_F_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
17B3 68B3
6C7 68C2
17B3 68B3
6C7 68C2
B
6C7 17B3 68C2
6C7 17B3 68C2
TABLE_SPACING_RULE_ITEM
SATA_TERMP
*
8 MIL
?
I183
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
I182
MCP_IFPAB_RSET
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MCP_DV_COMP
MCP_IFPAB_VPROBE
SATA_HDD_R2D
SATA_HDD_D2R
SATA_ODD_R2D
A
SATA_ODD_D2R
MCP_SATA_TERMP
8
7
6
5
4
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_TERMP
MCP_SATA_TERMP
3
70C3 70C4 70C5
70C3 70C4 70C5
17A3 23C6
17A3 23C6
19D6 37A2
19D6 37A2
6B7 37A5
6B7 37A5
37A4
37A4
19D6 37B2
19D6 37B2
6B7 37B5
6B7 37B5
37B4
MCP Constraints 1
37B4
19D6 37C3
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
19D6 37C3
NOTICE OF PROPRIETARY PROPERTY
6B7 37C6
6A7 6B7 37C6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
37C4
37C4
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
19D6 37C3
II NOT TO REPRODUCE OR COPY IT
19D6 37C3
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
6B7 37C6
SIZE
6B7 37C6
37C4
DRAWING NUMBER
D
37C4
APPLE INC.
19A6
SCALE
SHT
NONE
2
REV.
051-7898
4.7.0
OF
75
1
81
A
8
6
7
2
3
4
5
1
PCI Bus Constraints
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_DEBUG
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD24
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_C_BE_L
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_REQ0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_55S
PCI
PCI_REQ1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_55S
PCI
PCI_INTW_L
PCI_55S
PCI
PCI_INTX_L
PCI_55S
PCI
PCI_INTY_L
PCI_55S
PCI
PCI_INTZ_L
PCI_55S
PCI
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI
CLK_PCI_55S
CLK_PCI
LPC_AD
LPC_55S
LPC
LPC_FRAME_L
LPC_55S
LPC
LPC_RESET_L
LPC_55S
LPC
MCP_LPC_CLK0
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
TABLE_PHYSICAL_RULE_ITEM
CLK_PCI_55S
*
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCI
*
=STANDARD
?
TABLE_SPACING_RULE_ITEM
CLK_PCI
D
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
6 MIL
?
TABLE_SPACING_RULE_ITEM
LPC
*
TABLE_SPACING_RULE_ITEM
CLK_LPC
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.
USB 2.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MCP_DEBUG<7..0>
PCI_AD<23..8>
PCI_AD<24>
PCI_AD<31..25>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
12C3 18D7
D
18D2 18D7
18D2 18D7
18C5
18C5
18B3 40C8 42D3 42D5
18C3 40C8 42D5
18C3 24D4
TABLE_PHYSICAL_RULE_ITEM
MCP_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB
C
*
USB_EXTA
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.
SMBus Interface Constraints
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
CONN_USB_EXTA_P
CONN_USB_EXTA_N
18B3 24B4
24B1 40C8
24B1 42D3
19D3 38A8
19D3 38A8
38C4
C
38C4
38C3
38C3
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SMB_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
USB_CAMERA
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SMB
*
=2x_DIELECTRIC
?
USB_BT
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.
HD Audio Interface Constraints
USB_TPAD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
HDA_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_IR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
HDA
*
=2x_DIELECTRIC
?
USB_EXTB
TABLE_SPACING_RULE_ITEM
MCP_HDA_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
B
USB_SD
SIO Signal Constraints
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
CONN_USB2_BT_P
CONN_USB2_BT_N
USB_TPAD_P
USB_TPAD_N
USB_TPAD_R_P
USB_TPAD_R_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
CONN_USB_EXTB_P
CONN_USB_EXTB_N
USB_CARDREADER_P
USB_CARDREADER_N
19D3 29B5
19D3 29B5
6D5 29B7
6D5 29B7
19D3 29B5
19C3 29B5
6D5 29B7
6D5 29B7
19D3 48B8
19D3 48B8
48B7
48B7
19D3 39D7
19D3 39D7
19C3 38A4
19C3 38B4
38B3
38B3
19C3 30C7
B
19C3 30C7
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
CLK_SLOW_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_USB_RBIAS_GND
MCP_USB_RBIAS
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_DATA
SMB_55S
SMB
SMBUS_MCP_1_CLK
SMB_55S
SMB
SMBUS_MCP_1_DATA
SMB_55S
SMB
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.
HDA_BIT_CLK
HDA_55S
HDA
SPI Interface Constraints
HDA_55S
HDA
HDA_SYNC
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
8 MIL
?
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
HDA_RST_L
TABLE_PHYSICAL_RULE_ITEM
HDA_SDIN0
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
8 MIL
?
HDA_SDOUT
TABLE_SPACING_RULE_ITEM
SPI
*
MCP_HDA_PULLDN_COMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.
MCP_SUS_CLK
SPI_CLK
A
SPI_MOSI
SPI_MISO
SPI_CS0
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
SPI_CLK_R
SPI_CLK
SPI_ALT_CLK
SPI_MOSI_R
SPI_MOSI
SPI_ALT_MOSI
SPI_MISO
SPI_MISO_R
SPI_ALT_MISO
SPI_CS0_R_L
SPI_CS0_L
SPI_CS1_R_L
SPI_CS1_R_L_USE_MLB
19C4
12B6 20C3 43D8
12B6 20C3 43D8
20C3 43B8
20C3 43B8
20D2 52C7
20A7 20D4
20D2 52C7
20A7 20D4
20A7 20D4
20D2 52C7
20D7 52C7
20D2 52C7
20A7 20D4
20C7
20B3 24B4
24B1 40C5
MCP Constraints 2
20B3 42A5 42C8
51C5
SYNC_MASTER=T18_MLB
42C5 42D3
20B3 42A5 42C7
SYNC_DATE=12/14/2007
NOTICE OF PROPRIETARY PROPERTY
51C4
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
42C5 42D5
20B3 42A5 42B7
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
51C4
II NOT TO REPRODUCE OR COPY IT
42B5 42D5
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20B3 42B7
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
76
1
81
A
8
6
7
2
3
4
5
1
MCP RGMII (Ethernet) Constraints
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MCP_MII_COMP
*
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S
MCP_BUF0_CLK
ENET_MII_55S
MCP_BUF0_CLK
ENET_INTR_L
ENET_MII_55S
ENET_MII
ENET_MDIO
ENET_MII_55S
ENET_MII
ENET_MDC
ENET_MII_55S
ENET_MII
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_RXD_STRAP
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_TXCLK
ENET_MII_55S
ENET_MII
ENET_TXD0
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK_R
ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MII_55S
ENET_MII
ENET_RESET_L
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
TABLE_PHYSICAL_RULE_ITEM
ENET_MII_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1
17C6
17C6
17C3 32A5
31B6 32A3
TABLE_SPACING_RULE_ITEM
MCP_BUF0_CLK
*
=3:1_SPACING
?
ENET_MII
*
12 MIL
?
TABLE_SPACING_RULE_ITEM
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_RXCLK
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_MDI_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
25 MIL
?
TABLE_SPACING_RULE_ITEM
ENET_MDI
*
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
ENET_MDI
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R<3..0>
ENET_RXD<0>
ENET_RXD<3..1>
ENET_RX_CTRL
ENET_RXCTL_R
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
ENET_MDI_TRAN_P<3..0>
ENET_MDI_TRAN_N<3..0>
17C3 31B6
D
17D3 31B6
31C4
17D6 31C1
31C4
17D6 31C1
17D6 31C1
17D6 31B1
31B4
31C6
17D3 31C8
17D3 31C6
17D3 31C6
17D3 31B6
17C3 31B7
31B3 33B8 33C8
31B3 33B8 33C8
33B4 33C4 33C5
33B4 33C4 33C5
C
C
B
B
Ethernet Constraints
A
SYNC_MASTER=T18_MLB
SYNC_DATE=03/19/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
77
1
81
A
8
6
7
FireWire Interface Constraints
2
3
4
5
1
FireWire Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FW_110D
*
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
FW_TP
*
=3:1_SPACING
?
D
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
34B6 36C4
34C6 36C4
34B6 36C4
34B6 36C4
34B6 36B8
34B6 36B8
34B6 36B8
D
34B6 36B8
Port 2 Not Used
SD CARD NET PROPERTIES
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SD CARD INTERFACE CONSTRAINTS
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I23
SD_DATA
I24
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SD_INTERFACE
*
=3X_DIELECTRIC
?
SPACING
SD_55S
SD_INTERFACE
SD_DATA
SD_55S
SD_INTERFACE
I25
SD_DATA
SD_55S
SD_INTERFACE
I26
SD_DATA
SD_55S
SD_INTERFACE
I27
SD_DATA
SD_55S
SD_INTERFACE
I28
SD_DATA
SD_55S
SD_INTERFACE
I29
SD_DATA
SD_55S
SD_INTERFACE
I30
SD_DATA
SD_55S
SD_INTERFACE
I32
SD_CLK
SD_55S
SD_INTERFACE
I31
SD_CMD
SD_55S
SD_INTERFACE
TABLE_PHYSICAL_RULE_ITEM
SD_55S
PHYSICAL
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
30C2
30C2
30C2
30C2
30C2
30C2
30C2
30C2
SD_CLK
SD_CMD
30C2
30C2
C
C
B
B
FireWire Constraints
A
SYNC_MASTER=K19_MLB
SYNC_DATE=12/01/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
78
1
81
A
8
6
7
2
3
4
5
1
SMC SMBus Net Properties
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
D
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
6C5 6D5 43D2
6C5 6D5 43D2
43C2
43C2
43D5
43D5
6A7 43C5
D
6A7 43C5
43B5
43B5
SMBus Charger Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO_P
CHGR_CSO_N
C
C
B
B
SMC Constraints
A
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
79
1
81
A
8
6
7
2
3
4
5
1
K24 SENSOR NET PROPERTIES
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
D
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
CHGR_CSO_R_P
CHGR_CSO_R_N
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
ISNS_CPUVTT_P
ISNS_CPUVTT_N
ISNS_P1V5S0MCP_P
ISNS_P1V5S0MCP_N
ISNS_PVCORES0MCP_P
ISNS_PVCORES0MCP_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
MCP_THMDIODE_P
MCP_THMDIODE_N
45A8 59B3
45A8 59B3
46C5
46C5
9C6 46D5
9C6 46D5
45B7
D
45B7
6C7 46B5
6C7 46B5
20C3 46B5
20C3 46B5
C
C
B
B
K24 SPECIAL CONSTRAINTS
A
A
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
80
1
81
8
6
7
2
3
4
5
1
K24 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.5.1
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_RULE_ITEM
DEFAULT
*
0.1 MM
?
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
*
*
BGA_P1MM
STANDARD
*
=DEFAULT
?
BGA_P1MM
*
=DEFAULT
?
DEFAULT
*
Y
=50_OHM_SE
0.100MM
30 MM
0 MM
0 MM
STANDARD
*
Y
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
BGA_P2MM
*
=DEFAULT
?
*
BGA_P1MM
BGA_P2MM
CLK_FSB
*
BGA_P1MM
BGA_P2MM
*
=DEFAULT
?
CLK_LPC
*
BGA_P1MM
BGA_P2MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
WEIGHT
TOP,BOTTOM
Y
STANDARD
MEM_40S_VDD
BGA_P1MM
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CLK_PCI
*
BGA_P1MM
BGA_P2MM
CLK_PCIE
*
BGA_P1MM
BGA_P2MM
CLK_SLOW
*
BGA_P1MM
BGA_P2MM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
D
TABLE_SPACING_ASSIGNMENT_ITEM
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
BGA_P1MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
D
MEM_40S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
BGA_P3MM
PHYSICAL_RULE_SET
BGA_P1MM
MEM_CLK
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
SPACING_RULE_SET
0.090 MM
0.090 MM
LAYER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
1.5:1_SPACING
*
0.15 MM
?
2:1_SPACING
*
0.2 MM
?
TABLE_SPACING_ASSIGNMENT_ITEM
FSB_DSTB
FSB_DSTB
BGA_P1MM
BGA_P3MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
50_OHM_SE
TOP,BOTTOM
Y
0.115 MM
0.115 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAP
2.5:1_SPACING
*
0.25 MM
?
3:1_SPACING
*
0.3 MM
?
4:1_SPACING
*
0.4 MM
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
TABLE_SPACING_RULE_ITEM
0.100 MM
2X_DIELECTRIC
TOP,BOTTOM
0.140 MM
?
3X_DIELECTRIC
TOP,BOTTOM
0.210 MM
?
4X_DIELECTRIC
TOP,BOTTOM
0.280 MM
?
5X_DIELECTRIC
TOP,BOTTOM
0.350 MM
?
2X_DIELECTRIC
*
0.126 MM
?
3X_DIELECTRIC
*
0.189 MM
?
4X_DIELECTRIC
*
0.252 MM
?
5X_DIELECTRIC
*
0.315 MM
?
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
*
Y
0.126 MM
0.100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.310 MM
27P4_OHM_SE
*
Y
0.222 MM
0.222 MM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
70_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.151 MM
0.100 MM
=STANDARD
0.224 MM
0.224 MM
70_OHM_DIFF
TOP,BOTTOM
Y
0.185 MM
0.100 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.095 MM
0.095 MM
0.234 MM
0.234 MM
90_OHM_DIFF
TOP,BOTTOM
Y
0.112 MM
0.112 MM
0.220 MM
0.220 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.244 MM
0.244 MM
100_OHM_DIFF
TOP,BOTTOM
Y
0.091 MM
0.091 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.330 MM
0.330 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
C
C
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
B
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
110_OHM_DIFF
TOP,BOTTOM
Y
0.077 MM
0.077 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
0.330 MM
0.330 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
K24 RULE DEFINITIONS
A
A
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
81
1
81
6
7
2
3
4
5
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
K24 MLB SCHEMATIC
A
K24 MLB PVT RELEASE
0000713283
5/6/09
DATE
?
PVT RELEASE
D
D
5/6/2009
(.csa)
Page
1
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C
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TABLE_TABLEOFCONTENTS_ITEM
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
25
26
28
29
31
32
33
34
35
37
38
39
41
42
Date
Contents
Sync
Table of Contents
(.csa)
Page
08/22/2007
TABLE_TABLEOFCONTENTS_HEAD
12/12/2007
TABLE_TABLEOFCONTENTS_ITEM
T17_MLB
System Block Diagram
T18_MLB
03/13/2008
Power Block Diagram
TABLE_TABLEOFCONTENTS_ITEM
DRAGON
TABLE_TABLEOFCONTENTS_ITEM
BOM Configuration
M97_MLB
TABLE_TABLEOFCONTENTS_ITEM
Revision History
M97_MLB
TABLE_TABLEOFCONTENTS_ITEM
FUNC TEST
M97_MLB
04/21/2008
Power Aliases
TABLE_TABLEOFCONTENTS_ITEM
BEN
TABLE_TABLEOFCONTENTS_ITEM
SIGNAL ALIAS
M97_MLB
CPU FSB
T18_MLB
12/12/2007
CPU Power & Ground
T18_MLB
CPU Decoupling
RAYMOND
eXtended Debug Port(MiniXDP)
TABLE_TABLEOFCONTENTS_ITEM
12/12/2007
TABLE_TABLEOFCONTENTS_ITEM
03/31/2008
TABLE_TABLEOFCONTENTS_ITEM
11/07/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
K19_MLB
MCP CPU Interface
T18_MLB
MCP Memory Interface
T18_MLB
MCP Memory Misc
T18_MLB
MCP PCIe Interfaces
T18_MLB
MCP Ethernet & Graphics
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
06/26/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
12/12/2007
TABLE_TABLEOFCONTENTS_ITEM
T18_MLB
MCP PCI & LPC
T18_MLB
MCP SATA & USB
T18_MLB
MCP HDA & MISC
T18_MLB
MCP Power & Ground
T18_MLB
MCP Standard Decoupling
T18_MLB
MCP Graphics Support
T18_MLB
SB Misc
04/05/2008
TABLE_TABLEOFCONTENTS_ITEM
03/31/2008
TABLE_TABLEOFCONTENTS_ITEM
06/30/2008
TABLE_TABLEOFCONTENTS_ITEM
05/09/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
04/22/2008
TABLE_TABLEOFCONTENTS_ITEM
01/30/2009
TABLE_TABLEOFCONTENTS_ITEM
05/23/2008
TABLE_TABLEOFCONTENTS_ITEM
07/01/2008
TABLE_TABLEOFCONTENTS_ITEM
04/04/2008
TABLE_TABLEOFCONTENTS_ITEM
11/02/2008
TABLE_TABLEOFCONTENTS_ITEM
12/22/2008
TABLE_TABLEOFCONTENTS_ITEM
RAYMOND
FSB/DDR3 Vref Margining
BEN
DDR3 SO-DIMM Connector A
BEN
DDR3 SO-DIMM Connector B
BEN
DDR3 Support
T18_MLB
Right Clutch Connector
YITE
SECUREDIGITAL CARD READER
VEMURI
Ethernet PHY (RTL8211CL)
SUMA
Ethernet & AirPort Support
SUMA
ETHERNET CONNECTOR
SUMA
FireWire LLC/PHY (FW643)
K19_MLB
FireWire Port Power
YUN_K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
43
45
46
48
49
50
51
52
53
54
55
56
57
58
59
61
62
63
65
66
67
68
69
70
72
73
74
75
76
77
78
79
90
93
94
Date
Contents
(.csa)
Sync
FireWire Ports
Page
11/02/2008
TABLE_TABLEOFCONTENTS_HEAD
12/04/2008
TABLE_TABLEOFCONTENTS_ITEM
K19_MLB
SATA Connectors
K19_MLB
External USB Connectors
01/18/2008
TABLE_TABLEOFCONTENTS_ITEM
05/28/2008
TABLE_TABLEOFCONTENTS_ITEM
06/26/2008
TABLE_TABLEOFCONTENTS_ITEM
05/28/2008
TABLE_TABLEOFCONTENTS_ITEM
05/09/2008
TABLE_TABLEOFCONTENTS_ITEM
04/21/2008
TABLE_TABLEOFCONTENTS_ITEM
02/04/2008
TABLE_TABLEOFCONTENTS_ITEM
YUAN.MA
Front Flex Support
YUAN.MA
SMC
T18_MLB
SMC Support
YUAN.MA
LPC+SPI Debug Connector
CHANGZHANG
K24 SMBUS CONNECTIONS
BEN
VOLTAGE SENSING
YUNWU
Current Sensing
YUNWU
Thermal Sensors
YUNWU
Fan
CHANGZHANG
WELLSPRING 1
YUAN.MA
WELLSPRING 2
YUAN.MA
SMS
YUNWU
SPI ROM
CHANGZHANG
AUDIO: CODEC/REGULATOR
AUDIO
AUDIO: LINE INPUT FILTER
AUDIO
AUDIO: HEADPHONE FILTER
AUDIO
AUDI0: SPEAKER AMP
AUDIO
AUDIO: JACK
AUDIO
AUDIO: JACK TRANSLATORS
AUDIO
DC-In & Battery Connectors
YUNWU
PBUS Supply/Battery Charger
RAYMOND
5V/3.3V SUPPLY
RAYMOND
1.5V/0.75V DDR3 SUPPLY
RAYMOND
IMVP6 CPU VCore Regulator
RAYMOND
MCP CORE REGULATOR
K19_MLB
12/17/2008
TABLE_TABLEOFCONTENTS_ITEM
03/20/2008
TABLE_TABLEOFCONTENTS_ITEM
01/18/2008
TABLE_TABLEOFCONTENTS_ITEM
71
72
73
74
75
76
77
78
79
80
81
97
98
100
101
102
103
104
105
106
107
109
Date
Contents
Sync
12/05/2008
LCD BACKLIGHT DRIVER
KIRAN
LCD Backlight Support
YITE
CPU/FSB Constraints
T18_MLB
Memory Constraints
T18_MLB
MCP Constraints 1
T18_MLB
MCP Constraints 2
T18_MLB
Ethernet Constraints
T18_MLB
FireWire Constraints
K19_MLB
SMC Constraints
T18_MLB
K24 SPECIAL CONSTRAINTS
M97_MLB
K24 RULE DEFINITIONS
M97_MLB
06/30/2008
01/04/2008
01/04/2008
01/04/2008
12/14/2007
03/19/2008
12/01/2008
01/04/2008
C
04/22/2008
05/09/2008
06/26/2008
05/02/2008
03/04/2009
01/31/2009
02/03/2009
12/18/2008
03/20/2009
03/20/2009
12/11/2008
01/31/2008
02/08/2008
01/31/2008
01/31/2008
B
12/10/2008
02/08/2008
CPU VTT(1.05V) SUPPLY
RAYMOND
MISC POWER SUPPLIES
RAYMOND
POWER SEQUENCING
YUAN.MA
POWER FETS
YUAN.MA
LVDS CONNECTOR
NMARTIN
DISPLAYPORT SUPPORT
AMASON
DisplayPort Connector
AMASON
01/23/2008
12/11/2008
12/11/2008
04/04/2008
04/18/2008
06/30/2008
TABLE_TABLEOFCONTENTS_ITEM
DIMENSIONS ARE IN MILLIMETERS
A
APPLE INC.
METRIC
XX
X.XX
DRAFTER
Schematic / PCB #’s
PART NUMBER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
QTY
DESCRIPTION
REFERENCE DES
051-7898
1
SCHEM,MLB,K24
SCH
CRITICAL
820-2530
1
PCBF,MLB,K24
PCB
CRITICAL
CRITICAL
7
TITLE
DO NOT SCALE DRAWING
BOM OPTION
SCHEM,MLB,K24
NONE
THIRD ANGLE PROJECTION
8
ENG APPD
6
A
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
5
4
3
MATERIAL/FINISH
NOTED AS
APPLICABLE
SIZE
D
2
DRAWING NUMBER
REV.
051-7898
SHT
1
1
A
OF
81
8
6
7
2
3
4
5
1
U1000
U1300
INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
PG 9
D
FSB
D
J6950
64-Bit
800/1067/1333 MHz
DC/BATT
PG 13
2 UDIMMs
MAIN
FSB INTERFACE
GPIOs
POWER SUPPLY
PG 60
J2900
DDR2-800MHZ
DDR3-1067/1333MHZ
MEMORY
DIMM
PG 14
U4900
PG 25,26
TEMP SENSOR
PG 41
Misc
CLK
PG 24
U6100
SYNTH
POWER SENSE
PG 45
SPI
J4510
Boot ROM
SPI
SATA
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
PG 52
Conn
1.05V/3GHZ.
PG 48,49
PG 20
PG 38
HD
NVIDIA
J4520
SATA
Conn
PG 38
C
J4900
B,0
ADC
BSB
MCP79
SATA
1.05V/3GHZ.
Ser
Fan
LPC
PG 19
ODD
J5100
Prt
SMC
LPC Conn
Port80,serial
PG 41
C
PG 43
PG 18
U1400
J9000
PWR
LVDS
CONN
CTRL
LVDS OUT
PG 71
RGB OUT
J3500
DP OUT
J4720
SD CARD READER
J4700
J9400
HDMI OUT
J4710
PG 40
PG 40
IR
J3900,4635,4655
CAMERA
PG 40
PG 40
EXTERNAL
USB
Connectors
PG 16
PG 34
7
6
5
4
0
PCI-E
B
PG 34
UP TO 20 LANES3
FIREWIRE PORT
FW643
CONN
1
2
J4310
3
USB
PG 17
PG 19
TMDS OUT
PG 71
11
PG 39
DVI OUT
(UP TO 12 DEVICES)
DISPLAY PORT
CONN
PG 30
J4710
TRACKPAD/
KEYBOARD
Bluetooth
B
SMB
SMB
PG 20
PG 34
CONN
RGMII
HDA
PCI
(UP TO FOUR PORTS)
PG 44
DIMM’s
PG 17
PG 18
PG 20
J3400
Mini PCI-E
AirPort
U6200
Audio
PG 28
Codec
PG 53
U6301
U3700
A
U6400
U6500
GB
Line In
Line Out
Speaker
E-NET
Amp
Amp
Amp
Amps
PG 54
PG 55
PG 56
PG 57
RTL8211CL
HEADPHONE
System Block Diagram
U6600,6605,6610,6620
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PG 31
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
U3900
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
J6800,6801,6802,6803
E-NET
Conn
Audio
SIZE
Conns
D
PG 33
APPLE INC.
PG 56
DRAWING NUMBER
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
2
1
81
A
8
6
7
D6905
PPVIN_G3H_P3V42G3H
D6905
01
02
ENABLE
PPBUS_G3H
V
Q5315
02
CPUVTTS0_EN
(S0)
VOUT
CPUVTT
U5403
VOUT
SMC_BATT_ISENSE
PP1V05_S0
(8A MAX CURRENT)
31
CPUVTTS0_PGOOD
V
CPU VCORE
IMVP_VR_ON
Q7050
29
26
06 P1V05ENET_EN
1.05V SO
PP1V05_ENET_FET
FETS
PPBUS_G3H
(Q3841)
4.5V AUDIO
TPS7174S
VIN
EN
PM_SLP_S4_L
ISL8009
06
P1V05_S5_EN
U7750
SLP_S3#
11-3
P60
P5VRTS0_EN_L
04
U4900
DDRREG_EN
RC
DELAY
U1400
SMC_PM_G2_EN
PP4V5_AUDIO_ANALOG
RESET*
VOUT
U1000
P3V3S5_EN_L
02
11-2
15-1
SMC_PM_G2_EN
P5VLTS3_EN
RC
DELAY
Q7940
PP5V_S3_REG
VIN
EN1
5V
(RT)
VOUT1
VOUT2
EN2
3.3V
PP5V_S3
PP5V_S3_REG
PP5V_S0_FET
PP3V3_S5_REG
PP3V3_S5
BKLT_EN
LP8543
U9701
ENA
Q7910
PP3V3_S3_FET
13
VREG3
P3V3S3_EN
P5V3V3_PGOOD
PPVOUT_S0_LCDBKLT
VOUT
PP3V3_S0_FET
18
09
MCPCORESO_PGOOD
CPUVTTS0_PGOOD
WOL_EN
04-1
02
=DDRREG_EN
RC
DELAY
RC
DELAY
RC
DELAY
RC
DELAY
P1V8S0_EN
16-3
=DDTVTT_EN
MCPDDR_EN
16-2
CPUVTTS0_EN
MCPCORES0_EN
8
16-3
16-4
P1V05S0_EN
(S0)
P3V3S0_EN
(S0)
16-2
16-2
PBUSVSENS_EN
(S0)
16-2
P5VRTS0_EN_L
(S0)
16-1
7
SLP_S5_L
VIN
S5
S3
1.5V
PP1V5_S0_FET
PP1V5_S0
21
TPS62202
U7760
PP1V5_S3_REG
(12A MAX CURRENT)
14
TPS51116
U7300
20
VOUT2
EN2
SLP_S3_L(P93)
U4900
PPVCORE_S0_MCP_REG_R
R7572
PP1V8_S0_REG
19-1
PP3V3_S0
V1
PP1V5_S0
V2
PP1V05_S0
V3
Power Block Diagram
SYNC_MASTER=DRAGON
LTC2909
U7870
SYNC_DATE=03/13/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PPVCORE_S0_MCP
(25A MAX CURRENT)
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5V (LT)
VIN
6
SMC_RESET_L
II NOT TO REPRODUCE OR COPY IT
EN1
02
PM_PWRBTN_L
RST*
PP0V75_S0_REG
(1A MAX CURRENT)
MCP_CORE
25
1.8V LDO
VOUT1
MCPCORES0_EN
B
SLP_S4_L(P94)
SLP_S3_L
S0PGOOD_PWROK
(Q7901 & Q7971)
0.75V
VOUT2
IMVP_VR_ON(P16)
RSMRST_IN(P13)
PLT_RST*
PWR_BUTTON(P90)
P17(BTN_OUT)
IMVP_VR_ON
10
SLP_S5_L(P95)
SLP_S4_L
P5V_LT_S3_PGOOD
S3 TO S0
FETS
PM_RSMRST_L
99ms DLY
RST*
P3V3ENET_EN_L
PM_SLP_S3_L
RSMRST_PWRGD
05
P5V3V3_PGOOD
Q3802
PWRGD(P12)
SMC_ONOFF_L
P3V3S0_EN
Q3810
P3V3_ENET_FET
16
RSMRST_OUT(P15)
ALL_SYS_PWRGD
Q3801
SMC_ADAPTER_EN
SMC
24
Q7930
PM_ENET_EN_L
P5VS0_EN
07
(4A MAX CURRENT)
TPS51125
U7200
PGOOD1,2
17
(4A MAX CURRENT)
VIN
B
A
32
VOUT
08
05
Q7800
(S5)
PCI_RESET0#
PM_SLP_S3_L
U6200
P16
15
15
C
PWRGOOD
PP1V05_S5_REG
02
SMC
CPU_RESET#
CPU
22
1.05V (S5)
RC
DELAY
30
U2850
28
VR_PWRGOOD_DELAY
PGOOD
U7400
P3V3S3_EN
CPU_PWRGD
CPUPWRGD(GPIO49)
U1400
VR_ON
25
PPVBAT_G3H_CHGR_OUT
RSMRST*
FSB_CPURST_L
ISL9504B
11-1
LPC_RESET_L
MCP_PS_PWRGD PS_PWRGD
SMC_CPU_VSENSE
PPVCORE_S0_CPU
(44A MAX CURRENT)
SMC_CPU_ISENSE
VOUT
VIN
11
06-1
PWRBTN*
PLTRST*
01
CHGR_BGATE
MCP79
PGOOD
A
J6950
MCP79
D
TPS51117
U7600
02
BATT_POS_F
U5000
(1.05V)
VIN
ISL6258A
U7000
(9 TO 12.6V)
EN_PSV
ENABLES
PBUS SUPPLY/
BATTERY CHARGER
C
04
PP5V_S0_CPUVTTS0
VIN
3S2P
SMC PWRGD
RN5VD30A-F
23 R5492 PPBUS_G3H_CPU_ISNS
PPBUS_G3H_CPU_ISNS_R
F7000
CHGR_EN
(S5)
PP3V42_G3H_REG 03
3.425V G3HOT
LT3470
VOUT
U6990
PBUS_VSENSE
7A FUSE
PPVBAT_G3H_CHGR_REG
D
AC
DCIN(16.5V)
ADAPTER
IN
1
K24 POWER SYSTEM ARCHITECTURE
PP18V5_DCIN_CONN
F6905
6A FUSE
2
3
4
5
VOUT1
SIZE
DRAWING NUMBER
D
APPLE INC.
ISL6236
U7500
SCALE
SHT
NONE
5
4
3
2
REV.
051-7898
4.7.0
OF
3
1
81
A
8
6
7
BOM Variants
2
3
4
5
1
Bar Code Labels / EEE #’s
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
630-9923
PCBA,MLB,BETTER,K24
K24_COMMON,CPU_2_26GHZ,EEE_6GC,KB_BL
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_BOMGROUP_ITEM
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:6G4]
CRITICAL
EEE_6G4
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:6GC]
CRITICAL
EEE_6GC
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEE:6GD]
CRITICAL
EEE_6GD
TABLE_BOMGROUP_ITEM
630-9924
PCBA,MLB,BEST,K24
K24_COMMON,CPU_2_53GHZ,EEE_6GD,KB_BL
085-0741
K24 MLB DEVELOPMENT BOM
K24_DEVEL_PVT
TABLE_BOMGROUP_ITEM
D
BOM Groups
D
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
K24_COMMON
COMMON,ALTERNATE,K24_MCP,K24_MISC,K24_DEBUG_PVT,K24_PROGPARTS
K24_MCP
MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC
K24_MISC
ONEWIRE_PU,DP_ESD,MIKEY,BKLT_PROD,SUPERCAP_NO,LDO_NO
K24_PROGPARTS
BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG
K24_DEBUG_ENG
DEVEL_BOM,SMC_DEBUG_YES,XDP
K24_DEBUG_PVT
DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN
K24_DEBUG_PROD
BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
K24_DEVEL_ENG
BMON_ENG,XDP_CONN,LPCPLUS,VREFMRGN,FWPHY_WAKE_YES
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
K24 BOARD STACK-UP
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Top
2
3
4
5
6
7
8
9
10
11
BOTTOM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
K24_DEVEL_PVT
LPCPLUS
Module Parts
PART NUMBER
C
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
337S3646
1
PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA
U1000
CRITICAL
CPU_2_0GHZ
337S3704
1
PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA
U1000
CRITICAL
CPU_2_26GHZ
337S3639
1
PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA
U1000
CRITICAL
CPU_2_4GHZ
337S3756
1
PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA
U1000
CRITICAL
CPU_2_53GHZ
337S3761
1
PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA
U1000
CRITICAL
CPU_2_66GHZ
338S0710
1
IC,GMCP,MCP79,35X35MM,BGA1437,B03
U1400
CRITICAL
MCP_B03
Programmable Parts
338S0563
1
IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900
CRITICAL
SMC_BLANK
341S2445
1
IC,SMC,K24
U4900
CRITICAL
SMC_PROG
335S0610
1
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
U6100
CRITICAL
BOOTROM_BLANK
341S2441
1
IC,PRGRM,EFI BOOTROM,UNLOCK,K24
U6100
CRITICAL
BOOTROM_PROG
338S0375
1
IC,CY7C63833,ENCORE II,USB CONTROLLER
U4800
CRITICAL
IR_BLANK
341S2093
1
IC,IR CONTROLLER,M97
U4800
CRITICAL
IR_PROG
337S2983
1
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
U5701
CRITICAL
WELLSPRING_BLANK
341S2503
1
IC,PRGRM,WELLSPRING CONTROLLER
U5701
CRITICAL
WELLSPRING_PROG
SIGNAL
GROUND
SIGNAL(High
SIGNAL(High
GROUND
POWER
POWER
GROUND
SIGNAL(High
SIGNAL(High
GROUND
SIGNAL
Speed)
Speed)
C
Speed)
Speed)
LOCKED BOOTROM APN IS 341S2443
Alternate Parts
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
152S0778
152S0693
ALL
CYNTEC AS ALTERNATE
152S0796
152S0685
ALL
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
B
B
TABLE_ALT_ITEM
TABLE_ALT_ITEM
157S0058
157S0055
ALL
DELTA AS ALTERNATE
104S0018
104S0023
ALL
DALE/VISHAY AS ALTERNATE
128S0093
128S0218
ALL
KEMET AS ALTERNATE
152S0874
152S0516
ALL
MAGLAYERS AS ALTERNATE
152S0847
152S0586
ALL
MAGLAYERS AS ALTERNATE
516-0213
516-0201
ALL
MOLEX AS ALTERNATE
516S0709
516S0706
ALL
MOLEX AS ALTERNATE
152S1025
152S1024
ALL
TOKO AS ALTERNATE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM Configuration
A
SYNC_MASTER=M97_MLB
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
DEVELOPMENT BOM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
085-0741
QTY
1
DESCRIPTION
REFERENCE DES
K24 MLB DEVELOPMENT BOM
DEVEL
CRITICAL
BOM OPTION
CRITICAL
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DEVEL_BOM
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
4
1
81
8
7
6
5
4
3
2
1
Revision History
D
D
C
C
B
B
Revision History
A
A
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
NOTE: All page numbers are .csa, not PDF.
8
7
6
SCALE
SHT
NONE
See page 1 for .csa -> PDF mapping.
5
4
3
2
REV.
051-7898
4.7.0
OF
5
1
81
8
6
7
2
3
4
5
1
Functional Test Points
Fan Connectors
D
I12
I15
I16
PP5V_S0
FAN_RT_PWM
FAN_RT_TACH
TRUE
TRUE
TRUE
(NEED 3 TP)
6D3 7D5
I303
47B4
I301
I302
47C4
(NEED TO ADD 3 GND TP)
I238
I237
I239
I227
I226
I228
I230
I229
I231
I232
I233
I259
I258
C
I260
I245
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249
I395
MIC FUNC_TEST
TRUE
BI_MIC_LO
TRUE
BI_MIC_HI
TRUE
BI_MIC_SHIELD
SPEAKER
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I300
I299
I298
I293
56C2 57B1
I297
56C2 57B1
I294
56C2 57B1
FUNC_TEST
SPKRAMP_L_N_OUT
SPKRAMP_L_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_SUB_P_OUT
I288
I292
I296
55A2 56B2
I291
55B2 56B2
I295
55C2 56A2
I290
55C2 56B2
I271
55B2 56B2
I289
THERMAL FUNC_TEST
MCPTHMSNS_D2_P
TRUE
MCPTHMSNS_D2_N
TRUE
LVDS FUNC_TEST
PP3V3_LCDVDD_SW_F
TRUE
PP3V3_S0_LCD_F
TRUE
PPVOUT_S0_LCDBKLT
TRUE
LVDS_IG_DDC_CLK
TRUE
LVDS_IG_DDC_DATA
TRUE
LVDS_IG_A_DATA_N<0>
TRUE
LVDS_IG_A_DATA_P<0>
TRUE
LVDS_IG_A_DATA_N<1>
TRUE
LVDS_IG_A_DATA_P<1>
TRUE
LVDS_IG_A_DATA_N<2>
TRUE
LVDS_IG_A_DATA_P<2>
TRUE
LVDS_IG_A_CLK_F_N
TRUE
LVDS_IG_A_CLK_F_P
TRUE
LED_RETURN_1
TRUE
LED_RETURN_2
TRUE
LED_RETURN_3
TRUE
LED_RETURN_4
TRUE
LED_RETURN_5
TRUE
LED_RETURN_6
TRUE
TP_BKL_SYNC
TRUE
46B5 80D3
I375
46B5 80D3
I374
I372
I370
6C3 68C2
I371
68C3
I369
6C3 68B2 71C1
I368
17B3 68C5
I361
17A3 68C5
I366
17B3 68C2 75B3
I365
17B3 68C2 75B3
I363
17B3 68C2 75B3
I364
17B3 68C2 75B3
I362
17B3 68C2 75B3
I360
17B3 68C2 75B3
I359
68C2 75B3
I357
68C2 75B3
I358
68B3 71B1
I377
68B3 71B1
I378
I267
I265
I266
I315
I318
I317
I307
I309
I311
I354
I355
SATA ODD CONN
(NEED
PP5V_SW_ODD
TRUE
SMC_ODD_DETECT
TRUE
SATA_ODD_D2R_C_P
TRUE
SATA_ODD_D2R_C_N
TRUE
SATA_ODD_R2D_P
TRUE
SATA_ODD_R2D_N
TRUE
I347
I349
4 TP) 6C3
I348
37D3
I350
37C7 40B8
I352
37C6 75A3
I351
37C6 75A3
I353
37C6 75A3
I327
6A7 37C6 75A3
(NEED TO ADD 4 GND TP)
I328
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R
IR_RX_OUT
PP5V_S3_IR_R
(NEED TO ADD 4 GND TP)
I343
I342
(NEED 4 TP)
I341
6C3 37B6
I339
37A5 75A3
I340
37A5 75A3
I338
37B5 75A3
I336
37B5 75A3
I337
37A7
I333
37A7 39D4
I335
37A7
I334
I331
A
I320
I305
BATT POWER CONN
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SYS_DETECT_L
TRUE
BATT_POS_F
TRUE
6A7 43C5 79D3
43C5 79D3
I356
58A8
(NEED 3 TP)
58A7 58B8 59A3
I394
(NEED TO ADD 3 GND TP)
I326
I323
I324
I325
I308
I281
29C7 75D3
I282
29C7 75D3
I376
29B7 76C3
29B7 76C3
6C3
29C5
I283
2 TP)
I279
I278
16B6 29C7
I270
6C5 43D2 79D3
I379
6C5 43D2 79D3
I273
29B7 76C3
I274
29B7 76B3
I275
29C7
I276
29A7
(NEED TO ADD 6 GND TP)
I272
IPD_FLEX_CONN
PP3V3_S3_LDO
TRUE
PP18V5_S3
TRUE
Z2_CS_L
TRUE
Z2_DEBUG3
TRUE
Z2_MOSI
TRUE
Z2_MISO
TRUE
Z2_SCLK
TRUE
Z2_BOOST_EN
TRUE
Z2_HOST_INTN
TRUE
Z2_CLKIN
TRUE
Z2_KEY_ACT_L
TRUE
Z2_RESET
TRUE
PSOC_MISO
TRUE
PSOC_MOSI
TRUE
PSOC_SCLK
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
PSOC_F_CS_L
TRUE
PICKB_L
TRUE
I392
I391
I390
6C3 49B4 49C3
I389
6C3 49C1 49D3
I388
48C8 49C3
I387
48C8 49C3
I386
48C8 49C3
I385
48C8 49C3
I383
48C8 49C3
I382
49C3 49C5
I381
48D8 49C3
I380
48C6 49C3
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PPVCORE_S0_CPU
PPVCORE_S0_MCP
PP0V75_S0
PP1V05_S0
PP1V5_S0
PP1V8_S0
PP5V_S0
PP3V3_S0
PP1V5_S3
PP3V3_S3
PP5V_S3
PP1V1R1V05_S5
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET_PHY
PP1V2R1V05_ENET
PP3V3_G3_RTC
PP5V_WLAN
PP5V_SW_ODD
PP5V_S0_HDD_FLT
PP3V3_S5_AVREF_SMC
PP18V5_S3
PP3V3_S3_LDO
PP3V3_LCDVDD_SW_F
PPVOUT_S0_LCDBKLT
PP4V5_AUDIO_ANALOG
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L
D
7D7
7C7
7C7
7D7
7C6
7B6
6D7 7D5
7D5
7D3
6B5 7D3
7C3
7B3
7B3
6A7 6B5 7D1
7C1
7B5
7B5
20C8 21A5 24D4
6D5 29C5
6B7 37D3
6B7 37B6
40D4 41C6
6C5 49C1 49D3
6C5 49B4 49C3
6C7 68C2
6C7 68B2 71C1
52A5 52D2 52D7
C
40D5 60C5 66D8
20C3 40C5 41A2 66C8
20C3 32B7 35A5 40C5 66D5 70D8
(NEED TO ADD 4 GND TP)
48C8 49C1
48C8 49C1
48C8 49C1
48C8 49C1
48C8 49C1
6D5 43D2 79D3
6D5 43D2 79D3
48C8 49C1
48D8 49C1
DC POWER CONN
PP18V5_DCIN_FUSE
TRUE
ADAPTER_SENSE
TRUE
(NEED TO ADD 4 GND TP)
(NEED 3 TP) 58D6
58D7
68B3 71A1
68C2
I330
I321
I280
29C7 75D3
KEYBOARD CONN
68B3 71B1
I332
I322
29C7 75D3
I304
SATA HDD/IR/SIL
I314
I284
68B3 71B1
I329
I319
I285
I312
I346
I269
I287
68B3 71B1
I345
I268
29C7
16B6 29C7 75D3
I393
I344
B
DEBUG VOLTAGE
16B6 29C7 75D3
55C2 56B2
(NEED TO ADD 5 GND TP)
I264
RIGHT CLUTCH CONN
PP5V_S3_BTCAMERA_F
TRUE
PCIE_MINI_D2R_P
TRUE
PCIE_MINI_D2R_N
TRUE
PCIE_MINI_R2D_P
TRUE
PCIE_MINI_R2D_N
TRUE
PCIE_CLK100M_MINI_CONN_P
TRUE
PCIE_CLK100M_MINI_CONN_N
TRUE
USB_CAMERA_CONN_P
TRUE
USB_CAMERA_CONN_N
TRUE
(NEED
PP5V_WLAN
TRUE
PCIE_WAKE_L
TRUE
SMBUS_SMC_A_S3_SCL
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
CONN_USB2_BT_P
TRUE
CONN_USB2_BT_N
TRUE
MINI_CLKREQ_Q_L
TRUE
MINI_RESET_CONN_L
TRUE
BATT SIGNAL CONN
(NEED
PP3V42_G3H
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMBUS_SMC_BSA_SCL
TRUE
SMC_BIL_BUTTON_L
TRUE
SMC_LID_R
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_S3
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
6D3 7D3
6A7 6D3 7D1
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
B
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C6 48D2
48C2 48C6
48C2
48C2
48C2 48D6
48C2 48D7
48C2 48D7
48C2 48D7
48C2 48D7
48C2 48D7
48C2 48D7
48C2
48B3 48B5 48C2
48B3 48B5 48C2
48B3 48B5 48C2
(NEED TO ADD 1 GND TP)
KBD BACKLIGHT CONN
(NEED
KBDLED_ANODE
TRUE
TRUE SMC_KDBLED_PRESENT_L
FUNC TEST
2 TP) 49A4
SYNC_MASTER=M97_MLB
49A4 49A6
(NEED TO ADD 2 GND TP)
3 TP)
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
6B5 6D3 7D1
II NOT TO REPRODUCE OR COPY IT
6A7 43C5 79D3
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
6A7 43C5 79D3
SIZE
40C5 58C4
DRAWING NUMBER
D
58C2
(NEED TO ADD 5 GND TP)
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
4.7.0
OF
6
1
81
8
6
7
"S0,S0M" RAILS
62D1
=PPVCORE_S0_CPU_REG
(CPU VCORE PWR)
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_VSENSE
D
67B6
=PP5V_S0_FET
6D3
61C1
PP5V_S0
=PP5V_S0_HDD
=PP5V_S0_LPCPLUS
=PP5V_S0_FAN_RT
10B5 10D6 11D6
44D8
=PPCPUVTT_S0_REG
PP1V05_S0
=PP1V05_S0_CPU
=PP1V05_S0_MCP_FSB
=PP1V05_S0_SMC_LS
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_HDMI_VDD
=PP1V05_S0_VMON
=PP1V05_S0_MCP_PLL_UF_R
=PP1V05_FW_P1V05FWFET
=PP1V05_FWPWRCTL
63C7 63C1 63B8
=PPMCPCORE_S0_REG
(MCP VCORE AFTER SENSE RES)
9D5 10C6 11B6 12D6
13A2 13B7 21D3 22C8
47C5
62D8
67C6
=PP3V3_S0_FET
17A6 23D7
66A8
65B3
35C6
35B4
PPVCORE_S0_MCP
6D3
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
21D5 22D8
=PPVCORE_S0_MCP_VSENSE
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PPVTT_S0_VTTCLAMP
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
67D1
=PP1V5_S0_FET
PP3V3_S0
26A4
27A4
PP1V5_S0
6D3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V8_S0_REG
10B6 11B6
66A8
15C3 15C7 22C8
27B3
65B6
PP1V8_S0
12D6
20C2 21B3 22B8
=PP3V3R1V8_S0_MCP_IFP_VDD
=PP1V8_S0_AUDIO
B
=PP1V05_S0_MCP_PLL_UF
37B8
43D3
=PP3V3_ENET_FET
37C7 37D6
60B8
=PP5V_S3_REG
PP5V_S3
PP1V05_S0_MCP_PLL_UF
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
43C3
43D8
=PP5V_S3_EXTUSB
=PP5V_S3_IR
=PP5V_S3_BTCAMERA
=PP5V_S3_VTTCLAMP
=PP5V_S3_MCPDDRFET
=PP5V_S3_SYSLED
=PP5V_S3_TPAD
=PP5V_S3_WLAN
=PP5V_S3_1V5S30V75S0
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_P5VS0FET
=PP5V_S3_ODD
47C5
52A8 52D2 56D8 57B8 57D3
62D8
68C5
17C1 18D1 20A4
22B6
20D3 20D8 22A8
41A1 41D3
46B6
46D6
70B8 70C8
26A8
=PP3V3_ENET_PHY
58C2 58C4
40D4 41C1 41C3
41C7 41D8
42C7 42C8 42D5
24D8
45B8
=PP3V42_G3H_ONEWIRE
=PP3V42_G3H_AUDIO
43B5
25D8
58D2
56B6
29A6
20A3
58D1 58C8
48A6 48B5 48C5 48D2
=PP18V5_DCIN_CONN
PP18V5_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
50B7
30D7
=PP18V5_G3H_CHGR
59D8
59C1
=PPBUS_G3H
PPBUS_G3H
6C3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPBUS_S0_LCDBKLT
=PPVIN_S0_MCPCORE
=PPVIN_S5_1V5S30V75S0
=PPVIN_S5_3V3S5
=PPVIN_S3_5VS3
=PPBUS_G3HRS5
=PPBUS_S5_FWPWRSW
=PPCPUVCORE_VTT_ISNS_R
38C7
37A8 39D7
29C3
67A3
67D4
41B8
49B6 49D7
29C1
72D8
63D5
61C2
60C3
60C6 60C7
35B7
45B8
(BEFORE HIGH SIDE SENSING RES.)
61C5
52A8 52D2 54D5 56B6
55B7 55C7 55D7
67B8
37D5
66A5
66A8
61D8 25D3
=PPVTT_S3_DDR_BUF
45C7
49A6
PPVTT_S3_DDR_BUF
45B7
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PPCPUVCORE_VTT_ISNS
PPBUS_G3H_CPU_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
(AFTER HIGH SIDE CPU VCORE
& CPU VTT SENSING RES.)
43C8
=PPVIN_S0_CPUVTTS0
=PPVIN_S5_CPU_IMVP
65D8
64C6
62C3 62D4 62D8
71C7
45D8
65C6
35D6
35B1 35D2
"FIREWIRE" RAILS
=PP1V05_S5_REG
35D4
PP1V1R1V05_S5
PP3V3_FW
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
36D5
36B6
35D8
34B1
34D2
35C7
=PP3V3_FW_FWPHY
=PP3V3_S0_P1V05FWFET
6D3
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_ENET_P1V05ENETFET
17D3 17D7 22A5 22B6
=PP3V3_FW_FET
=PP1V05_ENET_FET
PP1V2R1V05_ENET
32C4
35B1
PPVP_FW
=PPBUS_S5_FW_FET
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE
31D7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
6C3
60B1
=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY
=PP3V3_S5_REG
22A8
17D3 22D6
31D2
=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_AVDD1
PP1V05_S0_MCP_PEX_AVDD
16B3
206 mA (A01)
16A3
MAKE_BASE=TRUE
206 mA (A01)
A
22D8 7D7
=PP1V05_S0_MCP_PEX_DVDD0
=PP1V05_S0_MCP_PEX_DVDD1
=PP1V05_S0_MCP_PEX_DVDD
16B6
57 mA (A01)
16A6
206 mA (A01)
22D2
PP1V05_S0_MCP_SATA_AVDD
=PP1V05_S0_MCP_SATA_AVDD0
=PP1V05_S0_MCP_SATA_AVDD1
MAKE_BASE=TRUE
127 mA (A01)
22D6 7D7
=PP1V05_S0_MCP_SATA_DVDD
19B6
35C5
=PP1V0_FW_FET
19B6
36C6
PP1V05_FW
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
17C7 19C1
42B5 42C7 51C6
=PP1V0_FW_FWPHY
34D8
35D3
68C8
21B3 22B8
24B8
66B3
32C5
67D8
67C8
65B8
28C4
Power Aliases
32D5
70D8
SYNC_MASTER=BEN
A
36A7
NOTICE OF PROPRIETARY PROPERTY
35A8
35C7
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
19B6
=PP1V05_S0_MCP_SATA_DVDD0
=PP1V05_S0_MCP_SATA_DVDD1
127 mA (A01)
127 mA (A01)
36C3
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
=PP3V3_S5_LCD
=PP3V3_S5_MCP
=PP3V3_S5_MCPPWRGD
=PP3V3_S5_PWRCTL
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3S3FET
=PP3V3_S5_P3V3S0FET
=PP3V3_S5_P1V05S5
=PP3V3_S5_MEMRESET
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR
=PP3V3_FW_LATEVG
=PP3V3_FW_LATEVG_ACTIVE
=PP3V3_S5_P1V05FWFET
PEX & SATA AVDD/DVDD aliases
22D1
PP3V3_S5
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
43 mA (A01)
II NOT TO REPRODUCE OR COPY IT
19B6
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
B
21A3 22D8
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
32B2
C
44B8
27A8
6C3
=PP3V3_ENET_MCP_RMGT
D
38B8
48B5 48C2 48C3
48C5
61B3
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
43D5
65A5
PP3V3_ENET_PHY
66B3 66C8 66D8
59A8 59C6 59D5
23C7
"ENET" RAILS
52D7
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_RTC_D
=PP3V42_G3H_BMON_ISNS
6B5 6D3
"S5" RAILS
17B6 23D7
32D2
65B1 22C4
28C6
41C8
43C5
23D4
6D3
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE
27D7
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PDCISENS
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_TPAD
=PP3V3_S3_SMS
=PP3V3_S3_CARDREADER
6A7 6B5 6D3
=PPVIN_S5_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_CHGR
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PP3V42_G3H_BATT
26D7
PP3V3_S3
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_SMC
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_DPCONN
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_PWRCTL
=PP3V3_S0_VMON
=PP3V3_S0_CPUVTTISNS
=PP3V3_S0_TPAD
=PP3V3_S0_SMBUS_MCP_1
=PP3V3_S0_P1V8S0
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_MCPDDRISNS
=PP3V3_S0_MCP_PLL_VLDO
=PP3V3_S0_P3V3FWFET
=PP3V3_S0_FWPWRCTL
67B3
PP3V42_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
67D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
63D4
=PP3V3_S0_LCD
=PP3V3_S0_MCP_GPIO
6D3
=PP1V5_S0_CPU
=PP1V5_S0_VMON
=PP1V8R1V5_S0_MCP_MEM
=PP1V5_S0_MEM_MCP
=PP1V5_S0_MCP_PLL_VLDO
65C5
=PP3V3_S3_FET
66B5
=PP3V3_S0_MCP_PLL_UF
PP0V75_S0
67D6
71D4
=PP3V3_S0_IMVP
44D8
=PP3V42_G3H_REG
69B6
64C8
=PP3V3_S0_XDP
=PP3V3_S0_MCP
=PP3V3_S0_MCP_DAC_UF
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_ODD
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_S0_FAN_RT
=PP3V3_S0_AUDIO
C
=PP0V75_S0_REG
=PP1V5_S3_HDD
58B4
49A5
22D4
7A8 22D6
6D3
=PP1V5_S3_P1V5S0FET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_MEMRESET
37B3
7A8 22D8
=PPVCORE_S0_MCP
61C8
PP1V5_S3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
42D5
=PP5V_S0_KBDLED
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_CPUVTTS0
=PP5V_S0_BKL
=PP5V_S0_MCPREG
=PP5V_S0_VMON
6D3
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V5_S3_REG
6D3 6D7
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
1
"G3H" RAILS
"S3" RAILS
=PP5V_S0_CPU_IMVP
64C2
2
3
4
5
4.7.0
OF
7
1
81
8
6
7
HEATSINK STANDOFFS
Z0902
Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
1
1
16D6 16C6
UNUSED GPU LANES
=PEG_D2R_N<15:0>
NC_PEG_D2R_N<15:0>
16D6 16C6
=PEG_D2R_P<15:0>
NC_PEG_D2R_P<15:0>
16D3 16C3
=PEG_R2D_C_N<15:0>
NC_PEG_R2D_C_N<15:0>
16D3 16C3
LEFT OF CPU
D
ABOVE CPU
16C6
16C3
Z0904
Z0903
STDOFF-4.5OD.98H-1.1-3.48-TH
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
PEG_PRSNT_L
TP_PEG_PRSNT_L
PEG_CLK100M_P
16C3
17C6
17C6
NO_TEST=TRUE
MCP_TV_DAC_VREF
MCP_CLK27M_XTALIN
NC_MCP_CLK27M_XTALOUT
CRT_IG_R_C_PR
NC_CRT_IG_R_C_PR
17C3
CRT_IG_G_Y_Y
NC_CRT_IG_G_Y_Y
PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
TP_PCIE_EXCARD_D2R_N
NC_CRT_IG_B_COMP_PB
NC_CRT_IG_HSYNC
NO_TEST=TRUE
NO_TEST=TRUE
16B3
PCIE_EXCARD_R2D_C_P
TP_PCIE_EXCARD_R2D_C_P
16B3
PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_N
16C6
PCIE_EXCARD_PRSNT_L
TP_PCIE_EXCARD_PRSNT_L
17B3
MAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_P
TP_PCIE_CLK100M_EXCARD_P
16C3
PCIE_CLK100M_EXCARD_N
TP_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
LVDS ALIASES
17B3
TP_EXCARD_CLKREQ_L
16C3
MAKE_BASE=TRUE
NC_CRT_IG_VSYNC
NO_TEST=TRUE
=P3V3ENET_EN
=P1V05ENET_EN
=PP3V3_ENET_PHY_VDDREG
=RTL8211_REGOUT
=RTL8211_ENSWREG
32C5
32B5
31C2
31C2
PM_SLP_RMGT_L
D
20C3
MAKE_BASE=TRUE
TP_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
31B6
NO_TEST=TRUE
R0931
22
LVDS_IG_A_DATA_N<3>
1
5%
1/16W
MF-LF
MAKE_BASE=TRUE
NC_LVDS_IG_A_DATA_N3
NO_TEST=TRUE
2 402
MAKE_BASE=TRUE
LVDS_IG_B_CLK_P
NC_LVDS_IG_B_CLK_P
17B3
LVDS_IG_B_CLK_N
NC_LVDS_IG_B_CLK_N
17B3
LVDS_IG_B_DATA_P<3:0>
NC_LVDS_IG_B_DATA_P<3:0>
17B3
LVDS_IG_B_DATA_N<3:0>
NC_LVDS_IG_B_DATA_N<3:0>
MAKE_BASE=TRUE
TP_RTL8211_CLK125
UNUSED LVDS SIGNALS
LVDS_IG_A_DATA_P<3>
NC_LVDS_IG_A_DATA_P3
17B3
MAKE_BASE=TRUE
1
MAKE_BASE=TRUE
31C6
MAKE_BASE=TRUE
Z0905
MAKE_BASE=TRUE
CRT_IG_HSYNC
CRT_IG_VSYNC
MAKE_BASE=TRUE
ETHERNET ALIASES
MAKE_BASE=TRUE
CRT_IG_B_COMP_PB
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
NO_TEST=TRUE
17C3
17C3
TP_MEM_A_A15
TP_MEM_B_A15
MAKE_BASE=TRUE
MAKE_BASE=TRUE
17C3
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
27D5
MAKE_BASE=TRUE
MCP_CLK27M_XTALOUT
16B6
EXCARD_CLKREQ_L
NO_TEST=TRUE
17C6
TP_PEG_CLK100M_N
MEM_A_A<15>
MEM_B_A<15>
26D5
NC_MCP_CLK27M_XTALIN
17C3
16B6
16C6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FAN STANDOFF
UNUSED ADDRESS PINS
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
NO_TEST=TRUE
1
SO-DIMM ALIASES
UNUSED CRT & TV-OUT INTERFACE
MCP_TV_DAC_RSET
NC_MCP_TV_DAC_RSET
MAKE_BASE=TRUE
UNUSED EXPRESS CARD LANE
BELOW CPU
17C6
TP_PEG_CLK100M_P
PEG_CLK100M_N
1
BELOW MCP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
1
MAKE_BASE=TRUE
NC_PEG_R2D_C_P<15:0>
NO_TEST=TRUE
DACS ALIASES
MAKE_BASE=TRUE
=PEG_R2D_C_P<15:0>
2
3
4
5
PCI-E ALIASES
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
FW ALIASES
MAKE_BASE=TRUE
18B7
FW_PME_L
FW_PLUG_DET_L
=FW_PME_L
FW643_WAKE_L
35B1 35D7
MAKE_BASE=TRUE
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
OMIT
R0950
OMIT
Z0906
3R2P5
Z0907
3R2P5
1
MISC MCP79 ALIASES
FIREWIRE PRESENT SIGNALS
35D3 16C6
PCIE_FW_PRSNT_L
1
0
NOSTUFF
MAKE_BASE=TRUE
CPU_PECI_MCP
TP_CPU_PECI_MCP
16B6
GMUX_JTAG_TCK_L
GMUX_JTAG_TDO
TP_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE
TP_GMUX_JTAG_TDO
18D4
GMUX_JTAG_TDI
TP_GMUX_JTAG_TDI
18D4
GMUX_JTAG_TMS
TP_GMUX_JTAG_TMS
13B6
MAKE_BASE=TRUE
2
5%
1/16W
MF-LF
402
1
35C8 34B2
16B6
C
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB ALIASES
UNUSED USB PORTS
MLB MOUNTING (TO TOPCASE) SCREW HOLES
OMIT
Z0908
3R2P5
OMIT
Z0909
3R2P5
1
19C3
19C3
OMIT
Z0910
3R2P5
1
19D3
19D3
19C3
1
19C3
19D3
OMIT
Z0911
3R2P5
OMIT
Z0912
3R2P5
1
19D3
USB_EXTC_P
USB_EXTC_N
USB_EXTD_P
USB_EXTD_N
USB_EXCARD_P
USB_EXCARD_N
TP_USB_EXTC_P
TP_USB_EXTC_N
TP_USB_EXTD_P
TP_USB_EXTD_N
TP_USB_EXCARD_P
TP_USB_EXCARD_N
USB_MINI_P
TP_USB_MINI_P
LAN ALIASES
MAKE_BASE=TRUE
MAKE_BASE=TRUE
17D6
MAKE_BASE=TRUE
17D6
MAKE_BASE=TRUE
17D6
MCP_MII_PD
MAKE_BASE=TRUE
R0930
1
47K
CPU FSB FREQUENCY STRAPS
5%
1/16W
MF-LF
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BSEL<2..0>
2 402
MAKE_BASE=TRUE
USB_MINI_N
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
TP_USB_MINI_N
DP HOTPLUG PULL-DOWN
MAKE_BASE=TRUE
1
17B6
=DVI_HPD_GMUX_INT
73C3 9B4
IN
CPU_BSEL<0:2>
MAKE_BASE=TRUE
=MCP_BSEL<0:2>
OUT
13A7
HPLUG_DET2
MAKE_BASE=TRUE
R0940
20K
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
FSB MHZ
0
1
0
1
0
1
0
1
266
133
200
(166)
333
100
(400)
(RSVD)
1
5%
1/16W
MF-LF
2 402
B
B
EMI IO POGO PINS
ZS0900
1.4DIA-SHORT-EMI-MLB-M97-M98
SM OMIT
ZS0901
SM OMIT
1.4DIA-SHORT-EMI-MLB-M97-M98
1
ZS0902
SM OMIT
1.4DIA-SHORT-EMI-MLB-M97-M98
1
PART NUMBER
870-1801
QTY
6
ZS0903
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1
DESCRIPTION
REFERENCE DES
POGO PIN,SHORT,EMI,MLB,K19/K24
CRITICAL
ZS0900,ZS0901,ZS0902,ZS0903,ZS0908,ZS0909
1
OMIT
ZS0908
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1
OMIT
ZS0909
SM OMIT
1.4DIA-SHORT-EMI-MLB-M97-M98
1
BOM OPTION
SIGNAL ALIAS
CRITICAL
A
SYNC_MASTER=M97_MLB
A
NOTICE OF PROPRIETARY PROPERTY
EMI POGO PINS
ZS0904
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
ZS0905
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ZS0906
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
ZS0907
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2.0DIA-TALL-EMI-MLB-M97-M98
II NOT TO REPRODUCE OR COPY IT
SM
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
8
1
81
8
6
7
2
3
4
5
1
OMIT
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13C6
BI
73D3 13B6
BI
73D3 13B6
BI
73D3 13B6
BI
73D3 13B6
BI
73D3 13B6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
73C3 13C6
BI
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
C
BI
73D3 13B6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13C6
BI
73C3 13B6
BI
73C3 13A3
73C3 13B7
73C3 13A3
K3
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
Y2
IN CPU_A20M_L
OUT CPU_FERR_L
IN CPU_IGNNE_L
73B3 13A3
IN
73C3 13A3
IN
73C3 13A3
IN
73B3 13A3
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
IN
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD_M4
TP_CPU_RSVD_N5
TP_CPU_RSVD_T2
TP_CPU_RSVD_V3
TP_CPU_RSVD_B2
TP_CPU_RSVD_F6
TP_CPU_RSVD_D2
TP_CPU_RSVD_D22
TP_CPU_RSVD_D3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
H2
K2
J3
L1
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
F6
D2
D22
D3
FCBGA
1 OF 4
DEFER*
DRDY*
DBSY*
BR0*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*
G5
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
H5
F21
E1
FSB_BREQ0_L
F1
BI
13B6 73C3
BI
13B6 73C3
BI
13B3 73C3
BI
13B3 73C3
BI
13B6 73C3
BI
13B6 73C3
BI
B3
CPU_IERR_L
CPU_INIT_L
IN
LOCK*
H4
FSB_LOCK_L
BI
RESET*
RS0*
RS1*
RS2*
TRDY*
C1
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
IERR*
INIT*
D20
HIT*
HITM*
BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
73B3
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
PROCHOT*
THERMDA
THERMDC
1%
1/16W
MF-LF
402
THERMTRIP*
13B6 73C3
12C2 13A3 73C3
13A6 73C3
IN
13A6 73C3
IN
13A6 73C3
IN
13B6 73C3
BI
13B6 73C3
BI
13B6 73C3
OMIT
12C6 73A3
BI
12C6 73A3
BI
12C6 73A3
BI
12C6 73A3
R1001 1
BI
73D3 13D3
73D3 13D3
BI
73D3 13D3
BI
73D3 13D3
BI
2
12C6 73A3
BI
73D3 13D3
BI
IN
9B6 12B3 73A3
73D3 13D3
BI
OUT
9B6 12B3 73A3
73D3 13D3
IN
9B6 12B3 73A3
73D3 13D3
BI
IN
9A6 12B3 73A3
73D3 13D3
BI
73D3 13D3
BI
12B3 24A3
R1002 1
46D5 80D3
C7
PM_THRMTRIP_L
OUT
13B7 41C4 73B3
73D3 13D3
5%
1/16W
MF-LF
402
73D3 13D3
BI
73D3 13D3
BI
73D3 13D6
BI
73D3 13D6
BI
73D3 13D6
BI
73D3 13D3
BI
73D3 13D3
BI
73D3 13D3
BI
2
OUT
IN
IN
13B6 41D4 62C8 73C3
13B3 73B3
13B3 73B3
BI
73D3 13D3
BI
73D3 13C3
BI
1K
CPU JTAG Support
R1090
1
73A3 12B3 9C6
73A3 12B3 9C6
XDP_TDI
1
2
1%
1/16W
MF-LF
402
XDP_TDO
BI
73D3 13C3
BI
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
54.9
BI
73D3 13C3
BI
73D3 13C3
BI
1%
1/16W
MF-LF
2 402
C1014
2
1
R1094
73A3 12B3 9C6
XDP_TRST_L
1
649
2
1%
1/16W
MF-LF
402
73D3 13D6
BI
73D3 13D6
BI
73D3 13D6
BI
10%
16V
X5R
402
R1010
2
0
5%
1/16W
MF-LF
402
R1011 1
1K
5%
1/16W
MF-LF
402 2
1
0.1uF
NO STUFF
NO STUFF
XDP_TCK
BI
NO STUFF
1
73A3 12B6 9C6
BI
73D3 13C3
R1006
1%
1/16W
MF-LF
402
54.9
BI
73D3 13C3
2.0K
R1093
BI
73D3 13C3
2
NO STUFF
1
2
73C3 8B2
73C3 8B2
73C3 8B2
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
E22
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>
N22
CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7
OUT CPU_BSEL<0>
OUT CPU_BSEL<1>
OUT CPU_BSEL<2>
73B3 25B1
1
R1092
1
2
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
R1091
54.9
54.9
R1005
BI
73D3 13C3
73D3 13C3
1
BI
73D3 13D3
73D3 13C3
XDP_TMS
BI
68
73D3 13C3
73A3 12B3 9C6
BI
IN
OUT
B
BI
73D3 13D3
OUT
FSB_CLK_CPU_P
FSB_CLK_CPU_N
73D3 13D3
9A6 12B6 73A3
B25
A21
BI
1%
1/16W
MF-LF
402
12C6 73A3
46D5 80D3
A22
73D3 13D3
54.9
H CLK
BCLK0
BCLK1
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
2
D
OUT
A24
1
54.9
CPU_PROCHOT_L
CPU_THERMD_P
CPU_THERMD_N
D21
7D7 10C6 11B6 12D6
13A3 73C3
IN
BI
R1000
13B6 73C3
IN
BI
=PP1V05_S0_CPU
THERMAL
A20M*
FERR*
IGNNE*
STPCLK*
LINT0
LINT1
SMI*
FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L
H1
E2
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*
D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2
U1000
PENRYN
FCBGA
2 OF 4
DATA GRP 2
BI
ADS*
BNR*
BPRI*
PENRYN
DATA GRP 3
BI
73D3 13C6
M3
U1000
DATA GRP 0
73D3 13D6
K5
A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*
DATA GRP 1
BI
L4
CONTROL
73D3 13D6
L5
XDP/ITP SIGNALS
BI
J4
ADDR GROUP0
BI
73D3 13D6
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>
ADDR GROUP1
BI
73D3 13D6
ICH
BI
73D3 13D6
RESERVED
D
73D3 13D6
D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
Y22
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
AE24
COMP0
COMP1
COMP2
COMP3
MISC
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13C3 73D3
BI
13B3 73D3
BI
13D6 73D3
BI
13D6 73D3
BI
13D6 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13B3 73D3
BI
13D6 73D3
BI
13D6 73D3
BI
13D6 73D3
C
B
R26 73A3 CPU_COMP<0>
U26 73B3 CPU_COMP<1>
AA1 73B3 CPU_COMP<2>
Y1
E5
B5
D24
D6
D7
AE6
73B3
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
IN
13A3 62C7 73B3
IN
13A3 73B3
IN
13A3 73B3
IN
12C7 13A3 73C3
IN
13A3 73B3
OUT
R1023 1
R1021 1
54.9
1%
1/16W
MF-LF
402
54.9
1%
1/16W
MF-LF
402
2
62C7
1
5%
1/16W
MF-LF
2 402
1
R1022
R1020
27.4
R1012
1K
2
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.
PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
2
27.4
1%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
PLACEMENT_NOTE (all 4 resistors):
1%
1/16W
MF-LF
402
Place within 12.7mm of CPU
CPU FSB
A
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SYNC FROM T18
CHANGE CPU FROM SOCKET TO BGA SYMBOL
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
9
1
81
A
8
6
7
5
2
3
4
A4
(CPU CORE POWER)
D
A9
A10
OMIT
AB7
U1000
AC7
A
A
A
A
(SV
(SV
(SV
(LV
Design Target)
HFM)
LFM)
Design Target)
A14
U1000
A16
PENRYN
P24
R2
R5
FCBGA
A19
R25
AF2
T1
B6
T4
B8
T23
AC12
B11
T26
3 OF 4
AC13
B13
U3
A17
AC15
B16
U6
A18
AC17
B19
U21
A20
AC18
B21
U24
B7
AD7
B24
V2
B9
AD9
C5
V5
A15
B10
AD10
C8
V22
B12
AD12
C11
V25
B14
AD14
C14
W1
B15
AD15
C16
W4
B17
AD17
C19
W23
B18
AD18
C2
W26
B20
AE9
C22
Y3
Y6
VCC
C9
AE10
C25
C10
AE12
D1
Y21
C12
AE13
D4
Y24
C13
AE15
D8
AA2
C15
AE17
D11
AA5
C17
AE18
D13
AA8
C18
AE20
D16
AA11
AF9
D19
AA14
D10
AF10
D23
AA16
D12
AF12
D26
AA19
D14
AF14
E3
AA22
D15
AF15
D9
VCC
E6
AA25
D17
AF17
E8
AB1
D18
AF18
E11
AB4
E7
AF20
(CPU IO POWER 1.05V)
E14
=PP1V05_S0_CPU
E9
7D7 9D5 11B6 12D6
G21
E10
4500 mA (before VCC stable)
2500 mA (after VCC stable)
VSS
VSS
AB11
E19
AB13
E21
AB16
V6
E13
J6
E24
AB19
E15
K6
F5
AB23
E17
M6
F8
AB26
E18
J21
F11
AC3
E20
K21
F13
AC6
F7
M21
F16
AC8
N21
F19
AC11
VCCP
F10
N6
F2
AC14
F12
R21
F22
AC16
F14
R6
F25
AC19
F15
T21
G4
AC21
F17
T6
G1
AC24
F18
V21
F20
W21
AA7
AD2
G26
AD5
H3
AD8
H6
AD11
H21
AD13
H24
AD16
62C7 73A3
J2
AD19
OUT
62C7 73A3
J5
AD22
OUT
62C7 73A3
J22
AD25
OUT
62C7 73A3
J25
AE1
OUT
62C7 73A3
K1
AE4
OUT
62C7 73A3
K4
AE8
OUT
62C7 73A3
=PP1V5_S0_CPU
(BR1#)
AA9
B26
VCCA
AA10
G23
(CPU INTERNAL PLL POWER 1.5V)
7B6 11B6
130 mA
C26
AA12
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
OUT
=PPVCORE_S0_CPU
1
2
AB14
VCCSENSE
AF7
R1100
100
AB10
AB12
7D7 10D6 11D6
CPU_VCCSENSE_P
1%
1/16W
MF-LF
402
OUT
62A5 73A3
AB15
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
AB17
AB18
VSSSENSE
AE7
CPU_VCCSENSE_N
OUT
1
62A5 73A3
R1101
100
2
1%
1/16W
MF-LF
402
K23
AE11
K26
AE14
L3
AE16
L6
AE19
L21
AE23
L24
AE26
M2
A2
M5
AF6
M22
AF8
M25
AF11
N1
AF13
N4
AF16
N23
AF19
N26
AF21
P3
B1
C
AB8
E16
E12
F9
D
R22
4 OF 4
A23
AC9
PENRYN
A13
B
44
41
30.4
23
P21
OMIT
FCBGA
A12
C
7D7 10B5 11D6
AB20
A7
P6
A8
A11
=PPVCORE_S0_CPU
1
B
A25
(Socket-P KEY)
AF25
CPU Power & Ground
A
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SYNC FROM T18
CHANGE CPU FROM SOCKET TO BGA SYMBOL
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
SCALE
SHT
NONE
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
10
1
81
A
8
6
7
2
3
4
5
1
CPU VCore HF and Bulk Decoupling
4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219):
10D6 10B5 7D7
=PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D
CRITICAL
1
CRITICAL
C1200
1
20%
6.3V
CERM-X5R
805
2
22UF
2
20%
6.3V
CERM-X5R
805
2
1
2
1
20%
6.3V
CERM-X5R
805
2
1
1
20%
6.3V
CERM-X5R
805
2
C1213
1
2
20%
6.3V
CERM-X5R
805
2
1
20%
6.3V
CERM-X5R
805
2
1
20%
6.3V
CERM-X5R
805
2
1
C1215
2
20%
6.3V
CERM-X5R
805
1
20%
6.3V
CERM-X5R
805
2
C1216
20%
6.3V
CERM-X5R
805
1
20%
6.3V
CERM-X5R
805
2
C1217
2
20%
6.3V
CERM-X5R
805
1
20%
6.3V
CERM-X5R
805
2
20%
6.3V
CERM-X5R
805
CRITICAL
C1218
1
22UF
2
C1209
22UF
CRITICAL
1
22UF
D
CRITICAL
C1208
22UF
CRITICAL
1
22UF
2
CRITICAL
C1207
22UF
CRITICAL
1
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1206
22UF
CRITICAL
C1214
22UF
2
CRITICAL
C1205
22UF
CRITICAL
1
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1204
22UF
CRITICAL
C1212
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1203
22UF
CRITICAL
C1211
22UF
20%
6.3V
CERM-X5R
805
CRITICAL
C1202
22UF
CRITICAL
C1210
22UF
2
1
22UF
CRITICAL
1
CRITICAL
C1201
C1219
22UF
20%
6.3V
CERM-X5R
805
2
20%
6.3V
CERM-X5R
805
C
C
PLACEMENT_NOTE (C1240-C1243):
Place on secondary side.
NOSTUFF
CRITICAL
1
1
C1240
470UF-4MOHM
3
2
Place on secondary side.
CRITICAL
20%
2.0V
POLY-TANT
D2T-SM
CRITICAL
1
C1241
470UF-4MOHM
3
2
20%
2.0V
POLY-TANT
D2T-SM
Place on secondary side.
CRITICAL
1
C1242
470UF-4MOHM
3
2
20%
2.0V
POLY-TANT
D2T-SM
C1243
470UF-4MOHM
3
20%
2.0V
POLY-TANT
D2T-SM
2
Place on secondary side.
VCCA (CPU AVdd) DECOUPLING
1x 10uF, 1x 0.01uF
10B6 7B6
=PP1V5_S0_CPU
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
C1250
1
1
2
2
10uF
20%
6.3V
X5R
603
C1251
0.01UF
10%
16V
CERM
402
B
B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
12D6 10C6 9D5 7D7
=PP1V05_S0_CPU
PLACEMENT_NOTE=Place C1260 between CPU & NB.
CRITICAL
C1260
1
1
20%
2.0V
POLY-TANT
D2T-SM2
C1261
1
0.1UF
330UF
2
3
2
20%
10V
CERM
402
C1262
1
0.1UF
2
20%
10V
CERM
402
C1263
1
0.1UF
2
20%
10V
CERM
402
C1264
1
0.1UF
2
20%
10V
CERM
402
C1265
1
0.1UF
2
20%
10V
CERM
402
C1266
0.1UF
2
20%
10V
CERM
402
CPU Decoupling
A
SYNC_MASTER=RAYMOND
SYNC_DATE=03/31/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SYNC FROM T18
REMOVE NO STUFF CAPS C1220 TO C1231
REMOVE C1244 & C1245
CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
11
1
81
A
8
6
7
2
3
4
5
1
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
D
Use with 920-0620 adapter board to support CPU, MCP debugging.
D
MCP79-specific pinout
7C5
11B6 10C6 9D5 7D7
=PP3V3_S0_XDP
=PP1V05_S0_CPU
XDP
XDP_CONN
CRITICAL
R1315 1
J1300
54.9
1%
1/16W
MF-LF
402 2
73A3 9C5
73A3 9C6
73A3 9C6
73A3 9C6
BI
BI
BI
IN
73A3 9C6
IN
73A3 9C6
IN
C
LTH-030-01-G-D-NOPEGS
F-ST-SM
XDP_BPM_L<5>
XDP_BPM_L<4>
OBSFN_A0
OBSFN_A1
XDP_BPM_L<3>
XDP_BPM_L<2>
OBSDATA_A0
OBSDATA_A1
XDP_BPM_L<1>
XDP_BPM_L<0>
OBSDATA_A2
OBSDATA_A3
TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
OBSFN_B0
OBSFN_B1
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
OBSDATA_B0
OBSDATA_B1
TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3
XDP
OBSDATA_B2
OBSDATA_B3
R1399
73C3 13A3 9B2
IN
CPU_PWRGD
1
1K
XDP_PWRGD
2
XDP_OBS20
5%
1/16W
MF-LF
402
18C4
20B7
IN
OUT
76B3 43D8 20C3
BI
76B3 43D8 20C3
BI
73A3 9C6 9A6
OUT
PM_LATRIGGER_L
JTAG_MCP_TCK
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
SDA
SCL
TCK1
TCK0
XDP_TCK
NC
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
1
1
2
2
0.1uF
10%
16V
X5R
402
JTAG_MCP_TRST_L
OBSDATA_C0
OBSDATA_C1
MCP_DEBUG<0>
MCP_DEBUG<1>
BI
18D7 76D3
BI
18D7 76D3
OBSDATA_C2
OBSDATA_C3
MCP_DEBUG<2>
MCP_DEBUG<3>
BI
18D7 76D3
OBSFN_D0
OBSFN_D1
JTAG_MCP_TDI
JTAG_MCP_TMS
OUT
20B7
OUT
20B7
OBSDATA_D0
OBSDATA_D1
MCP_DEBUG<4>
MCP_DEBUG<5>
BI
18D7 76D3
BI
18D7 76D3
OBSDATA_D2
OBSDATA_D3
MCP_DEBUG<6>
MCP_DEBUG<7>
BI
18D7 76D3
BI
18D7 76D3
FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
73A3 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
XDP_TDO
TDO
XDP_TRST_L
TRSTn
XDP_TDI
TDI
XDP_TMS
TMS
XDP_PRESENT#
XDP
XDP
C1300
JTAG_MCP_TDO
OBSFN_C0
OBSFN_C1
IN
20B7
OUT
20B7
BI
18D7 76D3
IN
13B3 73B3
IN
13B3 73B3
C
XDP
R1303
1
OUT
9C6 24A3
IN
9B6 9C6 73A3
OUT
9A6 9C6 73A3
OUT
9B6 9C6 73A3
OUT
9B6 9C6 73A3
1K
5%
1/16W
MF-LF
402
2
FSB_CPURST_L
IN
9D6 13A3 73C3
PLACEMENT_NOTE=Place close to CPU to minimize stub.
C1301
0.1uF
B
10%
16V
X5R
402
B
998-1571
Direction of XDP module
Please avoid any obstructions
on even-numbered side of J1300
eXtended Debug Port(MiniXDP)
A
SYNC_MASTER=K19_MLB
SYNC_DATE=11/07/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
12
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
BI
73D3 9C4
BI
73D3 9C4
73D3 9B4
D
C
73D3 9B4
BI
73D3 9C2
BI
73D3 9C2
BI
73D3 9C2
BI
73D3 9B2
BI
73D3 9B2
BI
73D3 9B2
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73D3 9D8
BI
73C3 9D8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
BI
73C3 9C8
73D3 9D8
R1410 1
B
73B3 41C4 9C6
73C3 9C8
IN
IN
R1415 1
54.9
62
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
2
2
73D3 9D8
BI
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
73C3 9D6
R1420
8B1
IN
8B1
IN
8B1
IN
1
NO STUFF
R1421
1K
1K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
R1422
1K
2
BI
2
U40
V41
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
W39
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
N37
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
M39
W37
V35
L36
N35
M41
J41
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
AC34
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
AE36
AE38
AE34
AC37
AE37
AE35
AB35
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AJ34
AL38
AL35
AN34
AR39
AN35
AK35
AC38
AA33
AC39
AC33
AC35
FSB_ADS_L
FSB_BNR_L
BI
FSB_BREQ0_L
BI
73C3 FSB_BREQ1_L
FSB_DBSY_L
BI
FSB_DRDY_L
BI
FSB_HIT_L
BI
FSB_HITM_L
BI
FSB_LOCK_L
IN
FSB_TRDY_L
OUT
AD42
BI
NO STUFF
1
T40
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
BI
BI
73C3 9D6
NO STUFF
BI
BI
73C3 9D6
PM_THRMTRIP_L
CPU_FERR_L
BI
73D3 9D8
62
5%
1/16W
MF-LF
402
BI
73D3 9D8
73D3 9D8
R1416
BI
73C3 9C8
73D3 9D8
=PP1V05_S0_MCP_FSB
BI
BI
73C3 9C8
22C8 21D3 13A2 7D7
BI
73D3 9B4
73C3 9C8
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
8C4
OUT
73C3 62C8 41D4 9C5
OUT
AD43
AE40
AL32
AD39
AD41
AB42
AD40
AC43
AE41
CPU_PECI_MCP
CPU_PROCHOT_L
E41
AJ41
AG43
5%
1/16W
MF-LF
402
AH40
=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>
(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)
F42
D42
F41
CPU_DSTBP0#
CPU_DSTBN0#
CPU_DBI0#
CPU_DSTBP1#
CPU_DSTBN1#
CPU_DBI1#
CPU_DSTBP2#
CPU_DSTBN2#
CPU_DBI2#
CPU_DSTBP3#
CPU_DSTBN3#
CPU_DBI3#
CPU_A3#
CPU_A4#
CPU_A5#
CPU_A6#
CPU_A7#
CPU_A8#
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A33#
CPU_A34#
CPU_A35#
FSB
73D3 9C4
CPU_ADSTB0#
CPU_ADSTB1#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADS#
CPU_BNR#
CPU_BR0#
CPU_BR1#
CPU_DBSY#
CPU_DRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_TRDY#
CPU_PECI
CPU_PROCHOT#
CPU_THERMTRIP#
CPU_FERR#
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_BPRI#
CPU_DEFER#
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43
AA41
AA40
BCLK_OUT_CPU_P
BCLK_OUT_CPU_N
G42
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
AL43
BCLK_OUT_NB_P
BCLK_OUT_NB_N
AL41
BCLK_IN_N
BCLK_IN_P
AK41
CPU_A20M#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_SMI#
AF41
CPU_PWRGD
CPU_RESET#
AH43
CPU_SLP#
CPU_DPSLP#
CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#
AM33
G41
AL42
AK42
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9C4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9B4 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9C2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
BI
9B2 73D3
FSB_BPRI_L
FSB_DEFER_L
OUT
9D6 73C3
OUT
9D6 73C3
FSB_CLK_CPU_P
FSB_CLK_CPU_N
OUT
9B6 73B3
OUT
9B6 73B3
FSB_CLK_ITP_P
FSB_CLK_ITP_N
OUT
12C3 73B3
OUT
12C3 73B3
D
C
B
FSB_CLK_MCP_P
73B3 FSB_CLK_MCP_N
73B3
Loop-back clock for delay matching.
R1430
1
1
R1435
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
2
73C3 9D6
OUT
73C3 9D6
OUT
73C3 9D6
OUT
22C2
73B3
73B3
73B3
1
73B3
R1436
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
2
AC41
AB41
AC42
CPU_RS0#
CPU_RS1#
CPU_RS2#
PP1V05_S0_MCP_PLL_FSB
270 mA (A01)
A
R1431 1
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
206
20
29
15
mA
mA
mA
mA
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
AG27
AH27
AG28
AH28
AM39
AM40
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
AM43
AM42
+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU
BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND
AJ40
AH39
AH42
AF42
AG41
AH41
H38
AN33
AM32
AG42
AN32
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L
OUT
9C8 73C3
OUT
9C8 73C3
OUT
9D6 73C3
OUT
9C8 73C3
OUT
9B8 73C3
OUT
9B8 73B3
=PP1V05_S0_MCP_FSB
R1440
150
2
9D6 12C2 73C3
OUT
9B2 73B3
OUT
9B2 73B3
OUT
9B2 73B3
OUT
9C8 73B3
OUT
9B2 62C7 73B3
MCP CPU Interface
5%
1/16W
MF-LF
402
OUT
OUT
7D7 13B7 21D3 22C8
NO STUFF
1
SYNC_MASTER=T18_MLB
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
7
DRAWING NUMBER
D
APPLE INC.
8
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
9B2 12C7 73C3
4.7.0
OF
13
1
81
A
6
7
5
2
3
4
OMIT
U1400
MCP79-TOPO-B
MCP79-TOPO-B
BGA
BGA
(2 OF 11)
BI
74D3 26A5
BI
74D3 26B7
D
BI
74D3 26A7
BI
74D3 26A7
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B7
BI
BI
74D3 26B7
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26C5
BI
74D3 26B5
BI
74D3 26B5
BI
74D3 26B7
BI
74D3 26B7
BI
74D3 26C7
BI
74D3 26C2
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26C4
74D3 26C4
74D3 26C4
BI
BI
BI
74D3 26B4
BI
74D3 26B2
BI
74D3 26C4
BI
74D3 26C4
BI
74D3 26B2
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26B4
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C2
B
BI
74D3 26B5
74D3 26B5
C
BI
74D3 26A7
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C4
BI
74D3 26C2
BI
74D3 26C4
BI
74D3 26C4
BI
74D3 26C4
BI
74D3 26D2
BI
74D3 26D2
BI
74D3 26C2
BI
74D3 26C2
BI
74D3 26D4
BI
74D3 26D4
BI
74C3 26A7
OUT
74C3 26B5
OUT
74C3 26B7
OUT
74C3 26B5
OUT
74C3 26C2
OUT
74C3 26B4
OUT
74C3 26C2
OUT
74D3 26C4
OUT
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34
MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0
MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0
(3 OF 11)
MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N
MEMORY PARTITION 0
74D3 26A5
1
OMIT
U1400
MRAS0#
MCAS0#
MWE0#
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
AV17
AP17
AR17
BI
26A5 74C3
74B3 27B5
BI
BI
26A5 74C3
74B3 27A5
BI
BI
26B7 74C3
74B3 27A7
BI
26B7 74C3
74B3 27A7
BI
BI
26B5 74C3
74B3 27B5
BI
BI
26B5 74C3
74B3 27A7
BI
BI
26B7 74C3
74B3 27A5
BI
BI
26B7 74C3
74B3 27B7
BI
BI
26C4 74C3
74B3 27B7
BI
BI
26C4 74C3
74B3 27B7
BI
26B2 74C3
74B3 27B7
BI
BI
26C2 74C3
74B3 27B5
BI
BI
26C4 74C3
74B3 27B5
BI
MA0_14
MA0_13
MA0_12
MA0_11
MA0_10
MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
AP23
AP19
AW17
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19
26C4 74C3
74B3 27B5
BI
26C2 74C3
74B3 27B7
BI
BI
26D2 74C3
74B3 27B5
BI
74B3 27B7
BI
74B3 27B7
BI
74B3 27B7
BI
74B3 27B5
BI
74B3 27B5
BI
OUT
74B3 27B5
BI
OUT
26C7 74D3
74B3 27B7
BI
OUT
26C7 74D3
74B3 27B5
BI
AV33
MCLK0A_1_P
MCLK0A_1_N
BA24
MCLK0A_0_P
MCLK0A_0_N
BB20
MCS0A_1#
MCS0A_0#
AY24
BC20
AR18
BI
74B3 27C7
BI
74B3 27C5
BI
74B3 27B7
BI
26C7 74D3
74B3 27B5
BI
OUT
26C5 74D3
74B3 27B5
BI
OUT
74B3 27B7
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C7 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C5 74D3
OUT
26C7 74D3
OUT
26C5 74D3
BI
74B3 27B2
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27B2
BI
74B3 27B4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C4
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27C2
BI
74B3 27C2
BI
74B3 27C2
BI
74B3 27C4
BI
74B3 27D2
BI
OUT
26C5 74D3
74B3 27D2
BI
OUT
26C5 74D3
74B3 27C4
BI
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
74B3 27C2
OUT
26C7 74D3
BI
OUT
26C7 74D3
OUT
26C7 74D3
74B3 27A7
OUT
OUT
26C5 74D3
74B3 27B5
OUT
74B3 27D4
BI
74B3 27D4
BI
74B3 27B7
MODT0A_1
MODT0A_0
MEM_A_ODT<1>
MEM_A_ODT<0>
AP15
AV15
MEM_A_CKE<1>
MEM_A_CKE<0>
AU23
AT23
OUT
OUT
26C5 74D3
74B3 27B5
OUT
OUT
26C5 74D3
74B3 27B4
OUT
74B3 27C2
MCKE0A_1
MCKE0A_0
BI
74B3 27B4
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
AT15
BI
74B3 27B5
OUT
TP_MEM_A_CLK2P
TP_MEM_A_CLK2N
AW33
BI
26C5 74D3
MEMORY
CONTROL
0A
MCLK0A_2_P
MCLK0A_2_N
BI
BI
74B3 27B7
MBA0_2
MBA0_1
MBA0_0
BI
OUT
OUT
26D5 74D3
74B3 27C2
OUT
OUT
26D7 74D3
74B3 27C4
OUT
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42
MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0
MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0
MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MEMORY PARTITION 1
8
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43
MRAS1#
MCAS1#
MWE1#
AW16
MBA1_2
MBA1_1
MBA1_0
BB29
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
BA29
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
BA15
BA16
BB17
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18
27A5 74A3
BI
27B7 74A3
BI
27B7 74A3
BI
27B5 74A3
BI
27B5 74A3
BI
27B7 74A3
BI
27B7 74A3
BI
27B2 74A3
BI
27C2 74A3
BI
27C4 74A3
BI
27C4 74A3
BI
27C4 74A3
BI
27C4 74A3
BI
27C2 74A3
BI
27D2 74A3
27C5 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
OUT
27C7 74B3
OUT
27C5 74B3
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
OUT
27C5 74C3
OUT
27C5 74C3
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
OUT
27C7 74C3
OUT
27C7 74C3
MEM_B_CS_L<1>
MEM_B_CS_L<0>
OUT
27C7 74B3
OUT
27C5 74B3
MEM_B_ODT<1>
MEM_B_ODT<0>
OUT
27C5 74B3
OUT
27C5 74B3
MEM_B_CKE<1>
MEM_B_CKE<0>
OUT
27D5 74B3
OUT
27D7 74B3
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
BA14
27A5 74A3
BI
OUT
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
BB18
BI
D
C
MEMORY
CONTROL
1A
MCLK1A_2_P
MCLK1A_2_N
BA42
MCLK1A_1_P
MCLK1A_1_N
BB22
MCLK1A_0_P
MCLK1A_0_N
BA19
MCS1A_1#
MCS1A_0#
BB14
MODT1A_1
MODT1A_0
BB13
MCKE1A_1
MCKE1A_0
AY31
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
BB42
BA22
AY19
BB16
AY15
BB30
B
MCP Memory Interface
A
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
14
1
81
A
8
6
7
3
4
5
2
1
OMIT
U1400
MCP79-TOPO-B
BGA
22C8 15C3 7B6
22B2
=PP1V8R1V5_S0_MCP_MEM
TP_MEM_A_CLK4P
TP_MEM_A_CLK4N
BB24
TP_MEM_A_CLK3P
TP_MEM_A_CLK3N
BA21
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
AU17
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
AN17
TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>
AV23
BC24
BB21
AR15
AN15
AN25
MCLK0B_1_P
MCLK0B_1_N
MCLK0B_0_P
MCLK0B_0_N
MCS0B_0#
MCS0B_1#
MODT0B_0
MODT0B_1
MCKE0B_0
MCKE0B_1
R1610 1
40.2
74A3
17
12
19
39
mA
mA
mA
mA
T27
U28
U27
T28
+V_PLL_XREF_XS
+V_PLL_DP
+V_PLL_CORE
+V_VPLL
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
AN41
AM41
MCLK1B_1_P
MCLK1B_1_N
AY23
MCLK1B_0_P
MCLK1B_0_N
BA20
MCS1B_0#
MCS1B_1#
BC16
MODT1B_0
MODT1B_1
AY16
MCKE1B_0
MCKE1B_1
BA30
MRESET0#
AY32
BB41
BA23
AY20
BA13
BC13
BA31
TP_MEM_B_CLK5P
TP_MEM_B_CLK5N
D
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
MCP_MEM_RESET_L
OUT
28C6
TP or NC for DDR2.
MEM_COMP_VDD
MEM_COMP_GND
R1611 1
40.2
1%
1/16W
MF-LF
402
BA41
2
74A3
C
MCLK1B_2_P
MCLK1B_2_N
PP1V05_S0_MCP_PLL_CORE
87 mA (A01)
1%
1/16W
MF-LF
402
AU34
MCLK0B_2_P
MCLK0B_2_N
MEMORY CONTROL 1B
D
AU33
MEMORY CONTROL 0B
(4 OF 11)
TP_MEM_A_CLK5P
TP_MEM_A_CLK5N
AA22
AP12
2
G30
P10
T10
T6
V10
V34
W5
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
AR36
AU10
F28
BC21
AY9
B
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
A
T24
T26
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
=PP1V8R1V5_S0_MCP_MEM
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
AM17
7B6 15C7 22C8
4771 mA (A01, DDR3)
AM19
C
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
B
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31
T33
T34
T35
T37
T38
T7
MCP Memory Misc
T9
U18
SYNC_MASTER=T18_MLB
U20
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
U22
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
15
1
81
A
8
6
7
3
4
5
2
1
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
D
IN
8D6
IN
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
IN
8D6
8D6
C
IN
8D6
8D6
8D6
=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>
IN
IN
IN
29D7
IN
35D3
IN
35D3 8C6
IN
8D6
IN
8D6
IN
57A4
B
8C4
OUT
30B7
OUT
E7
D7
C7
E6
F6
E5
F5
E4
E3
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4
PEG_PRSNT_L
IN
29D7
F7
C9
Int PU
D5
PEB_CLKREQ#/GPIO_49
D9
PEB_PRSNT# Int PU
FW_CLKREQ_L
PCIE_FW_PRSNT_L
E8
PEC_CLKREQ#/GPIO_50
Int PU
PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>
C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
OUT
8D6
PEG_CLK100M_P
PEG_CLK100M_N
OUT
8D6
OUT
8D6
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
OUT
29C5 75D3
OUT
29C5 75D3
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
OUT
34C2
OUT
34C2
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
OUT
8D6
OUT
8C6
PE0_REFCLK_P
PE0_REFCLK_N
E11
PE1_REFCLK_P
PE1_REFCLK_N
G11
PE2_REFCLK_P
PE2_REFCLK_N
J11
PE3_REFCLK_P
PE3_REFCLK_N
G13
PE4_REFCLK_P
PE4_REFCLK_N
J13
PE5_REFCLK_P
PE5_REFCLK_N
L14
PE6_REFCLK_P
PE6_REFCLK_N
N14
M14
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N
D11
F11
C
B10
PED_PRSNT# Int PU
TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L
L16
PEE_CLKREQ#/GPIO_16
PEE_PRSNT#/GPIO_46
AUD_IP_PERIPHERAL_DET
GMUX_JTAG_TCK_L
M16
M17
M19
PEG_CLKREQ#/GPIO_18
PEG_PRSNT#/GPIO_48
F17
Int PU
PE_WAKE# Int PU (S5)
PEX_RST0#
K11
PCIE_RESET_L
OUT
24C4
PE1_RX0_P
PE1_RX0_N
PE1_TX0_P
PE1_TX0_N
D8
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
OUT
29C5 75D3
OUT
29C5 75D3
PE1_RX1_P
PE1_RX1_N
PE1_TX1_P
PE1_TX1_N
B8
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
OUT
34C1 75D3
OUT
34C1 75D3
PE1_RX2_P
PE1_RX2_N
PE1_TX2_P
PE1_TX2_N
A7
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
OUT
8D6
OUT
8D6
PE1_RX3_P
PE1_RX3_N
PE1_TX3_P
PE1_TX3_N
B6
L18
M18
75D3 29C7 6D5
IN
K9
75D3 29C7 6D5
IN
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
75D3 34C1
IN
H9
75D3 34C1
IN
PCIE_FW_D2R_P
PCIE_FW_D2R_N
8D6
IN
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
F9
TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN
H7
J9
G9
E9
G7
Int PU
Int PU
Int PU
F13
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
H13
Int PU
PEF_CLKREQ#/GPIO_17
PEF_PRSNT#/GPIO_47
Int PU
J10
D
PED_CLKREQ#/GPIO_51
PCIE_WAKE_L
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N
K14
Int PU
C8
A8
B7
C6
=PP1V05_S0_MCP_PEX_AVDD0
57 mA (A01, DVDD0 & 1)
T17
W19
U17
V19
W16
W17
W18
U16
+DVDD0_PEX1
+DVDD0_PEX2
+DVDD0_PEX3
+DVDD0_PEX4
+DVDD0_PEX5
+DVDD0_PEX6
+DVDD0_PEX7
+DVDD0_PEX8
=PP1V05_S0_MCP_PEX_DVDD1
U19
+DVDD1_PEX1
+DVDD1_PEX2
T16
+V_PLL_PEX
T19
PP1V05_S0_MCP_PLL_PEX
84 mA (A01)
MCP_PEX_CLK_COMP
A11
PEX_CLK_COMP
+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13
7A6
206 mA (A01, AVDD0 & 1)
Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12
=PP1V05_S0_MCP_PEX_AVDD1
+AVDD1_PEX1
+AVDD1_PEX2
+AVDD1_PEX3
B
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
=PP1V05_S0_MCP_PEX_DVDD0
75C3
8D6
OUT
M15
IN
22C2
8D6
OUT
EXCARD_CLKREQ_L
PCIE_EXCARD_PRSNT_L
29C7 6D5
7A6
8D6
OUT
PEC_PRSNT# Int PU
IN
7A6
OUT
C10
CARDREADER_RESET
GMUX_JTAG_TDO
IN
Int PU
PE0_PRSNT_16#
MINI_CLKREQ_L
PCIE_MINI_PRSNT_L
8C4
8D6
PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N
PCI EXPRESS
8D6
7A6
M13
N13
MCP PCIe Interfaces
P13
NO STUFF
A
1
SYNC_MASTER=T18_MLB
R1710
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
2.37K
2
1%
1/16W
MF-LF
402
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PLACEMENT_NOTE=Place within 12.7mm of U1400
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
16
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
MCP79-TOPO-B
BGA
=PP3V3_ENET_MCP_RMGT
(6 OF 11)
22B6 22A5 17D3 7B5
=PP3V3_ENET_MCP_RMGT
77D3 31C1
IN
77D3 31C1
IN
77D3 31C1
IN
77D3 31C1
IN
77D3 31C1
IN
77D3 31B1
IN
8C4
IN
8C4
IN
8C4
IN
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
B23
E24
A24
49.9
A23
RGMII_RXC/MII_RXCLK
C22
RGMII_RXCTL/MII_RXDV
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
F23
MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK
B26
B22
J22
5 mA (A01)
K24
+V_DUAL_RMGT1
+V_DUAL_RMGT2
U23
MII_VREF
E28
MCP_MII_VREF
RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3
B24
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
RGMII_TXC/MII_TXCLK
D24
RGMII_TXCTL/MII_TXEN
C26
RGMII_MDC
RGMII_MDIO
D21
RGMII_PWRDWN/GPIO_37
=PP1V05_ENET_MCP_RMGT
RGMII_INTR/GPIO_35
T23
+V_DUAL_MACPLL
C27
MII_COMP_VDD
MII_COMP_GND
2
MCP_MII_COMP_VDD
77D3 MCP_MII_COMP_GND
B27
8D4
OUT
8D4
OUT
1
47K
42C3
8D4
IN
8D4
OUT
MCP Signal
TMDS/HDMI
DisplayPort
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
31C6 77D3
ENET_CLK125M_TXCLK
ENET_TX_CTRL
OUT
31C8 77D3
OUT
31B6 77C3
OUT
31B6 77D3
C21
ENET_MDC
ENET_MDIO
G23
TP_ENET_PWRDWN_L
BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
MII_RESET#
J23
ENET_RESET_L
E36
A35
TV_DAC_RSET
TV_DAC_VREF
MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT
C38
D38
XTALIN_TV
XTALOUT_TV
TV
C
Y
Comp
K32
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
B39
RGB_DAC_HSYNC
RGB_DAC_VSYNC
Component
Pr
TV_DAC_RED
Y
TV_DAC_GREEN
Pb
TV_DAC_BLUE
A40
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45
D36
IFPA_TXC_P
IFPA_TXC_N
B35
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N
B32
IFPB_TXC_P
IFPB_TXC_N
L31
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
J29
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
C30
DDC_CLK3
DDC_DATA3
D31
IFPAB_RSET
IFPAB_VPROBE
E32
/
/
/
/
103 mA
103 mA
J32
BI
32A5 77D3
OUT
31B7 77C3
206 mA (A01)
1
MII
0
=PP3V3_S0_MCP_GPIO
R1860 1
23D2
ENET_TXD<0>
RGMII
NOTE: All Apple products set strap to
MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.
31B6 77D3
OUT
Interface
1
100K
5%
1/16W
MF-LF
402
7C5 18D1 20A4
R1861
100K
2
2
5%
1/16W
MF-LF
402
MCP_DDC_CLK0
MCP_DDC_DATA0
A31
B40
C
RGB DAC Disable:
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
A39
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
A41
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
A36
B36
C36
C37
TV DAC Disable:
OUT
8D4
OUT
8D4
OUT
8D4
CRT_IG_HSYNC
CRT_IG_VSYNC
OUT
8D4
OUT
8D4
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
OUT
68B3 75B3
OUT
68B3 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
6C7 68C2 75B3
OUT
8D4
OUT
8D4
OUT
8D4
OUT
8D4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
OUT
8C4
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
6C7 68C5
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
OUT
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
OUT
23C6 75B3
OUT
23C6 75B3
Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.
2
LPCPLUS_GPIO
DP_IG_CA_DET
BI
69A5
Interface Mode
31C6 77D3
OUT
D25
B31
IN
72B7 71A7
OUT
72C8 72B7
OUT
68C8
OUT
69D3
OUT
69D3
OUT
69D3
69D3
OUT
OUT
69D3
OUT
69D3
OUT
69D3
OUT
75B3 69C7
OUT
OUT
8B4
IN
69D3
IN
G39
F40
D35
E35
G35
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
D43
F35
F33
G33
J33
H33
C43
(See below)
C31
F31
LCD_BKL_CTL/GPIO_57
LCD_BKL_ON/GPIO_59
LCD_PANEL_PWR/GPIO_58
HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
HDMI_TXD1_P/ML0_LANE1_P
HDMI_TXD1_N/ML0_LANE1_N
HDMI_TXD2_P/ML0_LANE0_P
HDMI_TXD2_N/ML0_LANE0_N
DP_AUX_CH0_P
DP_AUX_CH0_N
HPLUG_DET2/GPIO_22
HPLUG_DET3
=PP3V3R1V8_S0_MCP_IFP_VDD
190 mA (A01, 1.8V)
M27
M26
PP3V3_S0_MCP_VPLL
23C5
16 mA (A01)
23D7 7D7
75B3 23C7
GPIO_7/NFERR*/IGPU_GPIO_7
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD
23D7 7B6
75B3 23C7
GPIO_6/FERR*/IGPU_GPIO_6
B15
E37
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
OUT
69D3
75B3 69C7
LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
(See below)
E16
=PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
MCP_HDMI_RSET
OUT
MCP_HDMI_VPROBE
OUT
8 mA
8 mA
M28
M29
+VDD_IFPA
+VDD_IFPB
+V_PLL_IFPAB
+V_PLL_HDMI
T25
+VDD_HDMI
J31
HDMI_RSET
HDMI_VPROBE
J30
FLAT PANEL
5%
1/16W
MF-LF
402
B
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
=PP3V3_S5_MCP_GPIO
R1820
OUT
C25
DDC_CLK0
DDC_DATA0
RGB ONLY
B38
RGB_DAC_RSET
RGB_DAC_VREF
C
19C1 7A3
31C6 77D3
31C6 77D3
+V_RGB_DAC
+V_TV_DAC
DACS
2
C39
22A4
OUT
PP3V3_S0_MCP_DAC
TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF
IN
OUT
C24
1
49.9
1%
1/16W
MF-LF
402
D
7A5 22D6
131 mA (A01)
V23
Network Interface Select
PP1V05_ENET_MCP_PLL_MAC
22A6
77D3
R1811
RGMII_RXD0
RGMII_RXD1
RGMII_RXD2
RGMII_RXD3
ENET_CLK125M_RXCLK
ENET_RX_CTRL
TP_ENET_INTR_L
R1810 1
1%
1/16W
MF-LF
402
C23
J24
+3.3V_DUAL_RMGT2
LAN
D
7B5 17D7 22A5 22B6
83 mA (A01)
+3.3V_DUAL_RMGT1
C35
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
A32
D32
C32
D33
C33
B34
C34
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
K31
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
H29
L29
K29
L30
K30
N30
M30
B30
E31
G31
1
BI
6C7 68C5
69D3
69D3
R1850
10K
GPIOs 57-59 (if LCD panel is used):
In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
A
BI
B
2
5%
1/16W
MF-LF
402
MCP Ethernet & Graphics
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
17
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
20A4 17C1 7C5
=PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
(7 OF 11)
35D6 35C7 35C4 35A4 18D2
57D3
D
OUT
OUT
18D2
IN
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
76D3 12C3
BI
C
42D5 40C5
8C2
42D3 40C8
IN
IN
BI
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>
T2
V9
T3
U9
T4
AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7
PCI_REQ0#
PCI_REQ1#/FANRPM2
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L
P2
N1
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
TP_PCI_TRDY_L
Y3
PCI_TRDY#
PM_CLKRUN_L
N3
N2
AD11
FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ
AE2
AE1
AE6
PCI_CLKRUN#/GPIO_42
LPC_DRQ1#/GPIO_19 Int PU
LPC_DRQ0#
Int PU
LPC_SERIRQ Int PU
18D4
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
U10
R4
U11
P3
AA3
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_PAR
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_SERR#
PCI_STOP#
AA9
PCI_PME#/GPIO_30
Int PU (S5)
PCI_RESET0#
PCI_RESET1#
PCI_CLK0
PCI_CLK1
PCI_CLK2
TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L
R3
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI
76D3 18D2
PCI_REQ0_L
PCI_REQ1_L
FW_PWR_EN
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
U39
U4
U8
V16
B
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
A
Y24
Y25
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97
8C4
OUT
8C4
OUT
18D2
35D6 35C7 35C4 35A4 18D7
18D7
AA11
W10
Y2
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L
T1
PM_LATRIGGER_L
OUT
12C6
R10
MEM_VTT_EN_R
TP_PCI_RESET1_L
OUT
24C4
Y4
AA10
Y1
AB9
AA7
R11
R6
R7
R8
R1989
8.2K
1
2
PCI_REQ0_L
PCI_REQ1_L
FW_PWR_EN
MCP_RS232_SIN_L
R1990
R1991
R1992
R1994
8.2K
8.2K
8.2K
8.2K
1
2
1
2
1
2
1
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
76C3
2
PCI_CLKIN
R9
76C3
PCI_CLK33M_MCP
LPC_FRAME#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
AD4
AE12
LPC_FRAME_R_L
LPC_PWRDWN_L
LPC_RESET0#
AE5
LPC_RESET_L
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AD3
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_CLK0
AE9
AD2
AD1
AD5
GND98
GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
R1910
C
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to pin R8
R1960
22
1
LPC_FRAME_L
2
5%
R1950
R1951
R1952
R1953
22
22
22
22
1
2
1
2
1
2
1
2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
OUT
40C8 42D5 76C3
OUT
40C5 42D3
OUT
24D4 76C3
BI
40C8 42D5 76C3
BI
40C8 42D5 76C3
BI
40C8 42D3 76C3
BI
402
LPC_CLK33M_SMC_R
Y26
OUT
40C8 42D3 76C3
24B4 76C3
R1961
10K
Y27
AB18
2
H34
5%
1/16W
MF-LF
402
Strap for Boot ROM Selection (See HDA_SDOUT)
AB20
AB21
B
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
MCP PCI & LPC
AD28
AD33
SYNC_MASTER=T18_MLB
AD34
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
D
TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R
22
GND
U26
76D3 18D7
OUT
MCP_RS232_SOUT_L
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
AA6
1
U24
76D3 18D7
1
LPC
76D3 18D2
4.7.0
OF
18
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
75A3 37A2
75A3 37A2
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
OUT
OUT
75A3 37B2
IN
75A3 37B2
IN
SATA_HDD_D2R_N
SATA_HDD_D2R_P
AJ7
AJ6
AJ5
AJ4
SATA_A0_TX_P
SATA_A0_TX_N
USB0_P
USB0_N
USB1_P
USB1_N
SATA_A0_RX_N
SATA_A0_RX_P
D
USB2_P
USB2_N
OUT
75A3 37C3
OUT
75A3 37C3
75A3 37C3
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_D2R_N
SATA_ODD_D2R_P
IN
IN
AJ10
AJ9
AK9
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
TP_SATA_C_D2RN
TP_SATA_C_D2RP
AK2
AJ3
AJ2
AJ1
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_D2RN
TP_SATA_D_D2RP
C
AJ11
AM4
AL3
AL4
AK3
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_E_D2RN
TP_SATA_E_D2RP
AN1
AM1
AM2
AM3
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
AP3
TP_SATA_F_D2RN
TP_SATA_F_D2RP
AN3
AP2
AN2
SATA_A1_TX_P
SATA_A1_TX_N
SATA_A1_RX_N
SATA_A1_RX_P
SATA_B1_TX_P
SATA_B1_TX_N
SATA_B1_RX_N
SATA_B1_RX_P
SATA_C0_TX_P
SATA_C0_TX_N
PP1V05_S0_MCP_PLL_SATA
22B2
AE16
AF19
AG17
AG19
B
SATA_C1_TX_P
SATA_C1_TX_N
SATA_C1_RX_N
SATA_C1_RX_P
SATA_LED#
+V_PLL_SATA
+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4
=PP1V05_S0_MCP_SATA_DVDD1
AH17
AH19
+DVDD1_SATA1
+DVDD1_SATA2
=PP1V05_S0_MCP_SATA_AVDD0
7A6
127 mA (A01, AVDD0 & 1)
AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13
AN14
AL14
AM13
AM14
75A3
1
MCP_SATA_TERMP
38A8 76C3
BI
8C6
BI
8C6
External D
USB_EXTD_P
USB_EXTD_N
BI
8C6
BI
8C6
USB_CAMERA_P
USB_CAMERA_N
BI
29B5 76C3
BI
29B5 76C3
USB_IR_P
USB_IR_N
BI
39D7 76B3
BI
39D7 76B3
Geyser Trackpad/Keyboard
USB_TPAD_P
USB_TPAD_N
BI
48B8 76B3
BI
48B8 76B3
Bluetooth
USB_BT_P
USB_BT_N
BI
29B5 76C3
BI
29B5 76C3
External B
USB_EXTB_P
USB_EXTB_N
BI
38A4 76B3
BI
38B4 76B3
ExpressCard
USB_EXCARD_P
USB_EXCARD_N
BI
8C6
BI
8C6
External C
USB_EXTC_P
USB_EXTC_N
BI
8C6
BI
8C6
D
F29
USB4_P
USB4_N
K27
USB5_P
USB5_N
J26
USB6_P
USB6_N
F27
G29
USB7_P
USB7_N
USB8_P
USB8_N
L27
J27
G27
D27
E27
K25
L25
USB9_P
USB9_N
H25
USB10_P
USB10_N
F25
USB11_P
USB11_N
K23
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
L21
+V_PLL_USB
L28
J25
=PP3V3_S5_MCP_GPIO
1
8.2K
TP_USB_10P
TP_USB_10N
G25
2
USB_CARDREADER_P
USB_CARDREADER_N
L23
BI
30C7 76B3
BI
30C7 76B3
1
R2051
R2050
1
R2053
8.2K
5%
1/16W
MF-LF
402
2
R2052
8.2K
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
C
1
2
USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L
K21
J21
H21
PP3V3_S0_MCP_PLL_USB
7A3 17C7
IN
38C7
IN
38C7
IN
IN
41C4
22B4
19 mA (A01)
A27
76B3
MCP_USB_RBIAS_GND
AE3
+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4
SATA_TERMP
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
AD35
AD37
AD38
806
1%
1/16W
MF-LF
402
2
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
B
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
R2010
2.49K
2
+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9
=PP1V05_S0_MCP_SATA_AVDD1
7A6
B28
38A8 76C3
BI
R2060 1
E12
AG16
7A6
A28
BI
AirPort (PCIe Mini-Card)
USB_MINI_P
USB_MINI_N
SATA_C0_RX_N
SATA_C0_RX_P
84 mA (A01)
7A6 =PP1V05_S0_MCP_SATA_DVDD0
43 mA (A01, DVDD0 & 1)
D28
USB3_P
USB3_N
USB_RBIAS_GND
TP_MCP_SATALED_L
C28
External A
USB_EXTA_P
USB_EXTA_N
IR
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
D29
Camera
SATA
USB
75A3 37C3
C29
1%
1/16W
MF-LF
402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
MCP SATA & USB
A
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
19
1
81
A
8
6
7
2
3
4
5
1
OMIT
U1400
=PP3V3R1V5_S0_MCP_HDA
MCP79-TOPO-B
7C5 20D8 22A8
7 mA (A01)
BGA
(9 OF 11)
HDA
+V_DUAL_HDA1
+V_DUAL_HDA2
D
76A3 52C7
HDA_SDIN0
IN
G15
TP_MLB_RAM_SIZE
TP_MLB_RAM_VENDOR
=PP3V3R1V5_S0_MCP_HDA
22A8 20D3 7C5
J14
J15
(MXM_OK for MXM systems)
1
HDA_SDATA_IN0
Int PD
HDA_SDATA_OUT
HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
Int PD
HDA_BITCLK
OUT
IN
R2121
49.9K
2
2
MCP_HDA_PULLDN_COMP
A15
76B3 20A7
1%
1/16W
MF-LF
402
40C5
IN
40B8
IN
HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
Int PD
HDA_RESET*
20 mA
17 mA
=SPI_CS1_R_L_USE_MLB
SMC_ADAPTER_EN
TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L
AE18
AE17
K15
L15
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA
K17
SLP_S3*
SLP_RMGT*
SLP_S5*
G17
THERM_DIODE_P
THERM_DIODE_N
B11
+V_PLL_NV_H
+V_PLL_SP_SPREF
L24
GPIO_1/PWRDN_OK/SPI_CS1
L26
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
C18
A20GATE
Int PU
KBRDRSTIN* Int PU
SIO_PME*
Int PU (S5)
EXT_SMI/GPIO_32* Int PU (S5)
B20
INTRUDER*
K13
L13
C19
40B8
IN
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR
40C8
IN
C16
24A1
IN
PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
D16
PWRBTN* Int PU (S5)
RSTBTN* Int PU
RTC_RST_L
C20
RTC_RST*
76A3 20A7
76B3 20A7
H17
M21
SPKR
C13
MCP_SPKR
M25
M24
LID* Int PU (S5)
LLB* Int PU (S5)
SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT*/GPIO_64
L19
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN
(MGPIO2)
FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62
B12
C12
MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT
(MGPIO3)
CPUVDD_EN
D17
MCP_CPUVDD_EN
SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R
K19
G21
F21
M23
A12
D12
E20
MCP_CPU_VLD
C17
CPU_VLD
JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK
E19
JTAG_TDI Int PU
JTAG_TDO
JTAG_TMS Int PU
JTAG_TRST*
JTAG_TCK
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
C14
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
A16
XTALIN
XTALOUT
SUS_CLK/GPIO_34
BUF_SIO_CLK
B18
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
A19
TEST_MODE_EN
PKG_TEST
K22
IN
OUT
12C3
IN
12C3
IN
12B6
IN
IN
OUT
IN
OUT
D20
F19
J19
J18
G19
B16
B19
1
10K
5%
1/16W
MF-LF
402
XTALIN_RTC
XTALOUT_RTC
D13
C15
B14
52C7 76B3
2
2
2
20D4 76A3
2
R2140
1
R2141
1
1
R2142
OUT
6C3 32B7 35A5 40C5 66D5 70D8
OUT
8D1
OUT
6C3 40C5 41A2 66C8
OUT
46B5 80D3
OUT
46B5 80D3
OUT
20A3 63D8
OUT
20A3 63C8
OUT
20A3 63C8
OUT
BI
OUT
BI
OUT
IN
OUT
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
20D4 76B3
MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L
20D4 76A3
20D4 76B3
ARB_DETECT
=PP3V3_S0_MCP
1
C2173
10PF
5%
50V
CERM
402
5%
50V
CERM
402
2
0
1
1
NOTE: MCP79 rev A01 does not support
SPI1 option. Rev B01 will.
7C5 21B3 22B8
1
R2180
5%
1/16W
MF-LF
402
IN
12B6 43D8 76B3
Frequency
41C5
R2181
10K
12B6 43D8 76B3
43B8 76B3
2
43B8 76B3
5%
1/16W
MF-LF
402
20A3 29D5 32C7
1
14.31818 MHz
0
SPI Frequency Select
Connects to SMC for
automatic recovery.
Frequency
37D6
20A4 41D4
24A8
42B7 76A3
OUT
42A5 42C8 76A3
IN
42A5 42B7 76A3
OUT
42A5 42C7 76A3
OUT
24B4 76A3
2
SPI_DO
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
NOTE: Straps not provided on this page.
B
1
R2163
R2190
1K
5%
1/16W
MF-LF
402
2
1%
1/16W
MF-LF
402
7C5 17C1 18D1
2
7D3
R2154
100K
1
5%
1/16W
MF-LF
402
AP_PWR_EN
20C3
20C3 29D5 32C7
20C3 57D3
MCP HDA & MISC
20B3 26A5 27A5 40B8
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
20B3 41D4
20B3
20C3 63D8
SYNC_MASTER=T18_MLB
1
R2147
R2155
1
R2156
100K
22K
22K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
1
NOTICE OF PROPRIETARY PROPERTY
20C3 63C8
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
R2157
22K
2
SYNC_DATE=06/26/2008
20C3 63C8
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
402
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
HDA_SYNC
24 MHz
USER mode: Normal
SAFE mode: For ROMSIP
recovery
20A4 26A5 27A5 40B8
OUT
C
BUF_SIO_CLK Frequency
10K
2
10PF
1
SPI1
20A4
1
1
SPI0
NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.
1
OUT
R2143
10K
2
1
R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.
20A4 57D3
=PP3V3_S3_MCP_GPIO
1
0
MCP_TEST_MODE_EN
5%
1/16W
MF-LF
402
10PF
2
OUT
0
PCI
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
10K
For EMI Reduction on HDA interface
C2171
HDA_SYNC
LPC_FRAME#
0
L22
100K
HDA Output Caps
1
52C7 76A3
OUT
PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK
AE7
R2151
=PP3V3_S0_MCP_GPIO
2
OUT
HDA_SDOUT
LPC
BOOT_MODE_USER
IN
IN
R2150 1
5%
50V
CERM
402
HDA_RST_L
I/F
BOOT_MODE_SAFE
MCP_VID<0>
MCP_VID<1>
MCP_VID<2>
M20
1
C2172
2
5%
1/16W
MF-LF
402
IN
L20
IN
24C8
5%
50V
CERM
402
52C7 76B3
20A4
MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15
24A5
24C8
10PF
22
2
MCP_THMDIODE_P
MCP_THMDIODE_N
C11
24A5
24B8
C2170
22
OUT
R2172
1
1
52C7 76A3
BIOS Boot Select
HDA_BIT_CLK
HDA_RST_R_L
HDA_SYNC_R
OUT
5%
1/16W
MF-LF
402
2
PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L
J17
PWRGD_SB
PS_PWRGD
24C8
A
22
MCP_GPIO_4
AUD_I2C_INT_L
L17
PM_RSMRST_L
MCP_PS_PWRGD
12C3
1
1
HDA_SDOUT
2
73B3 62D8
12C3
B
HDA_PULLDN_COMP
TP_MCP_LID_L
PM_BATLOW_L
40D8
HDA_RST_R_L
HDA_SYNC_R
HDA_BIT_CLK_R
2
PP1V05_S0_MCP_PLL_NV
SM_INTRUDER_L
HDA_SDOUT_R
HDA_BIT_CLK_R
22
1
5%
1/16W
MF-LF
402
MISC
42B8
1%
1/16W
MF-LF
402
HDA_SDOUT_R
5%
1/16W
MF-LF
402
41B2 40D5 35B5 32B7
49.9K
E15
D
R2170
76A3 20A7
R2173
PP3V3_G3_RTC
C
5%
1/16W
MF-LF
402
R2171
HDA_SYNC
37 mA (A01)
1
8.2K
1%
1/16W
MF-LF
402
22A2
R2120 1
F15
R2160
R2110
76A3
24D4 21A5 6C3
1
K16
2
49.9
2
J16
4.7.0
OF
20
1
81
A
8
7
6
MCP79-TOPO-B
AH37
AH38
AJ39
D
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
C
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
B
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
A
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301
GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341
GND342
GND343
22D8 7C6
BGA
(10 OF 11)
=PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
AV40
BA1
AA25
AC23
BA4
U25
AW31
AH12
AY6
AG10
L35
AG5
BC33
Y21
BC37
Y23
BC41
AA16
AY14
AA26
BC5
AA27
C2
AA28
D10
AC16
D14
AC17
D15
AC18
D18
AC19
D19
AC20
D22
AC21
D23
AA17
D26
AC24
D30
AC25
D37
AC26
D6
AC27
E13
AC28
E17
AD21
E21
AD23
E25
W27
E29
V25
E33
AA18
F12
AE19
F16
AE21
F32
AE23
F8
AE25
G10
AE26
G12
AE27
G14
AE28
G16
AF10
BC12
AF11
G22
AA19
G24
AF2
AW20
AF21
G34
AF23
G4
AF25
G43
AF3
G6
AF4
G8
AF7
H11
AH23
H15
AF9
AW35
AA20
H23
AG11
AN8
AG12
G40
AG21
J12
AG23
J8
AG25
K10
AG3
K12
AG4
K18
AA21
K26
AG6
K37
AG7
K4
AG8
K40
AG9
K8
AH1
AU1
AH10
L40
AH11
L43
W26
L5
AH2
M10
AA23
M34
W28
M35
AH25
M37
AH21
Y28
AH3
Y33
AH4
Y34
AH5
Y35
AH6
Y37
AH7
Y38
AH9
AB17
AA24
AB16
W21
AN26
W23
AD7
W25
M11
AF12
+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81
POWER
AH34
GND
BGA
(11 OF 11)
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
GND223
GND224
GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232
GND233
GND234
GND235
GND236
GND237
GND238
GND239
GND240
GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
1
U1400
MCP79-TOPO-B
AH33
2
OMIT
OMIT
U1400
AH26
3
4
5
=PP1V05_S0_MCP_FSB
+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8
+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36
+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52
24D4 20C8 6C3
AY13
PP3V3_G3_RTC
10 uA (G3)
80 uA (S0)
P11
A20
+VBAT
7D7 13A2 13B7 22C8
1182 mA (A01)
AC32
E40
J36
N32
T32
D
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
C
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32
+VTT_CPUCLK
AG32
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8
AD10
43 mA
=PP3V3_S0_MCP
7C5 20C2 22B8
450 mA (A01)
B
AE8
AB10
AD9
Y10
AB11
AA8
Y9
=PP3V3_S5_MCP
+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4
G18
+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
G26
+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3
T21
16 mA
7A3 22B8
266 mA (A01)
H19
J20
K20
250 mA
H27
J28
K28
=PP1V05_S5_MCP_VDD_AUXC
AA4
AB19
1139 mA
R32
7B3 22D8
105 mA (A01)
MCP Power & Ground
U21
V21
SYNC_MASTER=T18_MLB
Y6
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
T11
V11
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
Y11
AH16
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
T22
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
8
7
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
6
5
4
3
2
REV.
051-7898
4.7.0
OF
21
1
81
A
8
MCP Core Power
21D5 7C6
6
7
2
3
4
5
1
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
(No IG vs. EG data)
C2500
20%
4V
X5R-1
402
D
C2501
1
4.7UF
C2502
1
4.7UF
20%
4V
X5R-1
402
2
C2503
1
4.7UF
20%
4V
X5R-1
402
2
1
1
4.7UF
20%
4V
X5R-1
402
2
C2504
1
1UF
2
2
2
MCP PCIE (DVDD) Power
7D7 7A8
C2505
1
1UF
10%
10V
X5R
402-1
C2506
1
1UF
10%
10V
X5R
402-1
2
C2507
1
1UF
10%
10V
X5R
402-1
2
C2508
1
0.1UF
10%
10V
X5R
402-1
2
C2509
1
0.1UF
20%
10V
CERM
402
2
20%
10V
CERM
402
C2510
1
0.1UF
2
C2511
1
0.1UF
20%
10V
CERM
402
2
C2512
1
20%
10V
CERM
402
2
0.1UF
20%
10V
CERM
402
2
C2513
0.1UF
20%
10V
CERM
402
MCP SATA (DVDD) Power
=PP1V05_S0_MCP_PEX_DVDD
57 mA (A01)
7D7
43 mA (A01)
30-OHM-5A
=PP1V05_S0_MCP_AVDD_UF
C2515
1
20%
4V
X5R-1
402
2
2
4.7UF
C2516
1
1UF
C2517
1
10%
10V
X5R
402-1
2
1UF
10%
10V
X5R
402-1
2
C2518
1
333 mA (A01)
20%
10V
CERM
402
2
0.1uF
C2519
C2520
0.1uF
1
2
2
4.7UF
20%
10V
CERM
402
20%
4V
X5R-1
402
MCP 1.05V AUX Power
21A3 7B3
1
1
2
C2521
1
20%
10V
CERM
402
2
0.1uF
17D3 7A5
105 mA (A01)
C2570
1
20%
6.3V
CERM
402-LF
C2525
0.1uF
2
MCP FSB (VTT) Power
21D3 13B7 13A2 7D7
C2526
C2528
0.1uF
20%
10V
CERM
402
1
2
2
4.7UF
20%
10V
CERM
402
2
1
20%
4V
X5R-1
402
C2529
20%
10V
CERM
402
2
0.1uF
C2575
20%
6.3V
CERM
402-LF
1
1
2
C2531
1
2.2UF
20%
6.3V
CERM
402-LF
2
C2532
1
2.2UF
20%
6.3V
CERM
402-LF
2
20%
6.3V
CERM
402-LF
C2533
1
2.2UF
2
C2534
1
2.2UF
20%
6.3V
CERM
402-LF
2
C2535
1
2.2UF
20%
6.3V
CERM
402-LF
2
20%
6.3V
CERM
402-LF
C2536
2
1
20%
6.3V
X5R
603
2
C2540
1
1
4.7UF
20%
4V
X5R-1
402
C2541
1
0.1UF
2
2
C2542
1
0.1UF
20%
10V
CERM
402
2
C2543
1
0.1UF
20%
10V
CERM
402
2
C2544
1
0.1UF
20%
10V
CERM
402
2
C2545
1
0.1UF
20%
10V
CERM
402
2
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)
C2546
1
0.1UF
20%
10V
CERM
402
2
C2547
1
0.1UF
20%
10V
CERM
402
2
C2548
1
0.1UF
20%
10V
CERM
402
2
1
1
2.2UF
2
B
=PP3V3_S5_MCP
C2551
1
2.2UF
20%
6.3V
CERM
402-LF
1
2.2UF
20%
6.3V
CERM
402-LF
2
C2552
2
20%
6.3V
CERM
402-LF
C2553
1
2.2UF
2
2
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
MCP 3.3V Ethernet Power
22A5 17D7 17D3 7B5
2
1
1
2
2
13A6
270 mA (A01)
C
C2581
0.1UF
20%
10V
CERM
402
=PP3V3_ENET_MCP_RMGT
1
2
20%
10V
CERM
402
PP1V05_S0_MCP_PLL_SATA
C2584
1
1
20%
4V
X5R-1
402
2
2
4.7UF
20%
6.3V
CERM
402-LF
C2585
0.1UF
20%
10V
CERM
402
L2586
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_CORE
C2564
C2586
1
1
20%
4V
X5R-1
402
2
2
4.7UF
20%
6.3V
CERM
402-LF
15C6
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
87 mA (A01)
C2587
0.1UF
20%
10V
CERM
402
L2588
30-OHM-1.7A
1
PP1V05_S0_MCP_PLL_NV
C2562
C2588
2.2UF
22B6 17D7 17D3 7B5
1
1
4.7UF
MCP79 Ethernet VRef
20%
6.3V
CERM
402-LF
20%
4V
X5R-1
402
20C7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
2
19B6
84 mA (A01)
B
2.2UF
20%
6.3V
CERM
402-LF
C2583
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
C2560
16A6
84 mA (A01)
0.1UF
0402
C2555
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
1
C2589
1
20%
10V
CERM
402
2
0.1UF
2
2
37 mA (A01)
C2590
0.1UF
20%
10V
CERM
402
=PP3V3_ENET_MCP_RMGT
R2591 1
MCP Standard Decoupling
1.47K
A
1%
1/16W
MF-LF
402
L2595
30-OHM-1.7A
=PP1V05_ENET_MCP_PLL_MAC
5 mA (A01)
20%
6.3V
CERM
402-LF
L2584
7 mA (A01)
7B5
2.2UF
127 mA (A01)
PP1V05_S0_MCP_PLL_PEX
30-OHM-1.7A
19 mA (A01)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
2.2UF
=PP3V3R1V5_S0_MCP_HDA
2
20%
4V
X5R-1
402
1
83 mA (A01)
1
20D8 20D3 7C5
2
4.7UF
2.2UF
20%
6.3V
CERM
402-LF
266 mA (A01)
MCP 3.3V/1.5V HDA Power
1
C2582
20%
10V
CERM
402
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
0402
C2550
C2549
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
19C3
L2555
30-OHM-1.7A
19 mA (A01)
1
21B3 7A3
1
20%
4V
X5R-1
402
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0.1UF
20%
10V
CERM
402
2
=PP3V3_S0_MCP_PLL_UF
7C5
450 mA (A01)
MCP 3.3V AUX/USB Power
C2574
L2582
1
0402
=PP3V3_S0_MCP
2
20%
6.3V
CERM
402-LF
C2580
30-OHM-1.7A
=PP1V8R1V5_S0_MCP_MEM
MCP 3.3V Power
20%
6.3V
CERM
402-LF
2.2UF
4.7UF
10UF
20%
6.3V
CERM
402-LF
4771 mA (A01, DDR3)
21B3 20C2 7C5
C2573
2.2UF
PP1V05_S0_MCP_PLL_FSB
C2592
2.2UF
MCP Memory Power
15C7 15C3 7B6
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
2.2UF
20%
6.3V
CERM
402-LF
1
PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0402
C2595
1
1
4.7UF
20%
4V
X5R-1
402
MCP_MII_VREF
2
OUT
17D3
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
5 mA (A01)
C2596
R2590 1
1
1%
1/16W
MF-LF
402 2
2
1.47K
20%
10V
CERM
402
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
2
17C6
0.1UF
2
SYNC_MASTER=T18_MLB
C2591
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0.1UF
II NOT TO REPRODUCE OR COPY IT
20%
10V
CERM
402
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
206 mA (A01)
C2576
2
30-OHM-1.7A
=PP1V05_S0_MCP_PLL_UF
562 mA (A01)
C2530
C2572
2.2UF
2
1
L2580
65B1 7B8
1
1
2.2UF
1182 mA (A01)
C
20%
6.3V
CERM
402-LF
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
1
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)
=PP1V05_S0_MCP_FSB
2.2UF
2
0603
1
C2571
1
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
PP1V05_S0_MCP_SATA_AVDD
7A8
L2575
30-OHM-5A
=PP1V05_ENET_MCP_RMGT
131 mA (A01)
1
1
2.2UF
MCP 1.05V RMGT Power
=PP1V05_S5_MCP_VDD_AUXC
7A8
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
0603
1
D
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
PP1V05_S0_MCP_PEX_AVDD
L2570
=PP1V05_S0_MCP_SATA_DVDD
7D7 7A8
4.7.0
OF
22
1
81
A
8
6
7
5
2
3
4
1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
17B6 7B6
NO STUFF
7C5
190 mA (A01, 1.8V)
30-OHM-1.7A
=PP3V3_S0_MCP_DAC_UF
206 mA (A01)
1
1
C2610
2
D
17A6 7D7
NO STUFF
0402
2.2UF
2
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
PP3V3_S0_MCP_DAC
L2650
=PP3V3R1V8_S0_MCP_IFP_VDD
1
20%
6.3V
CERM
402-LF
C2650
2.2UF
2
20%
6.3V
CERM
402-LF
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
17C3
206 mA (A01)
1
R2651
0
5%
1/16W
MF-LF
D
2 402
=PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
C2615
1
1
2
2
4.7UF
20%
4V
X5R-1
402
75B3 17A6
75B3 17A6
0.1UF
20%
10V
CERM
402
MCP_HDMI_RSET
MCP_HDMI_VPROBE
C
75B3 17A3
75B3 17A3
NO STUFF
C2620
1
1
20%
10V
CERM
402
=PP3V3_S0_MCP_VPLL_UF
16 mA (A01)
2
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
2
NO STUFF
NO STUFF
R2620
C2630
1K
0.1UF
7C5
C2616
1%
1/16W
MF-LF
402
1
1
20%
10V
CERM
402
2
C
R2630
1K
0.1UF
2
1%
1/16W
MF-LF
402
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640
Apple: ???
30-OHM-1.7A
PP3V3_S0_MCP_VPLL
17B6
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
0402
C2640
1
1
20%
6.3V
CERM
603
2
2
4.7UF
16 mA (A01)
C2641
0.1uF
20%
10V
CERM
402
B
B
MCP Graphics Support
A
SYNC_MASTER=T18_MLB
SYNC_DATE=12/12/2007
NOTICE OF PROPRIETARY PROPERTY
SYNC FROM T18
REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672
NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)
CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC
REMOVE HDCP ROMS
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
8
DRAWING NUMBER
D
4.7.0
OF
23
1
81
A
8
6
7
1
RTC Power Sources
U2801
MIC5232-2.8YD5
LPC Reset (Unbuffered)
TSOT-23-5
PP3V3_G3_RTC
NC
D
1
C2870
2
10%
10V
X5R
402
R2819
0.47UF
C2819
10%
100
10%
10V
X5R
402
2
GND
1UF
SUPERCAP_YES
C2871
1
4
2
SUPERCAP_YES
SUPERCAP_YES
402
PP3V3_G3_SUPERCAP
6C3 20C8 21A5
R2881
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
76C3 18C3
1
PLACEMENT_NOTE=Place close to U1400
LPC_RESET_L
IN
33
1
CERM
402
2
5%
1/16W
MF-LF
402
1UF
6.3V
1
MF-LF
=PP3V42_G3H_RTC_D
5
2
7D1
CRITICAL VOUT
EN
1
Platform Reset Connections
VIN
3
2
3
4
5
2
33
1
OUT
42D5
2
SMC_LRESET_L
OUT
40C8
BKLT_PLT_RST_L
OUT
72C8
MINI_RESET_L
OUT
29A6
PCA9557D_RESET_L
OUT
25A5
=FW_RESET_L
OUT
35D1
D
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to U1400
SUPERCAP_YES
1
DEBUG_RESET_L
R2883
C2800
0.08F
2%
2 3.3V
XHHG
SM
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79
PLACE C2819 CLOSE TO MCP79
PLACE C2800 AT COOLEST SPOT ON MLB
PCIE Reset (Unbuffered)
SUPERCAP_NO
R2820
0
1
R2892
2
16B3
PCIE_RESET_L
MAKE_BASE=TRUE
IN
5%
1/16W
MF-LF
402
0
RTC Crystal
2
5%
1/16W
MF-LF
402
C2810
R2871
RTC_CLK32K_XTALOUT
1
R28101
R2811 1
OUT
Y2810
32.768K
2
1
C2815
1
R2815
1
R2870
R2816
1M
5%
1/16W
MF-LF
402 2
OUT
33
1
MEM_VTT_EN
MAKE_BASE=TRUE
2
5%
1/16W
MF-LF
402
=DDRVTT_EN
IN
PLACEMENT_NOTE=Place close to U1400
LPC_CLK33M_SMC_R
1
3
4
33
2
5%
1/16W
MF-LF
402
NC
NC
C2816
OUT
61C8 67A3
LPC_CLK33M_SMC
OUT
40C8 76C3
LPC_CLK33M_LPCPLUS
OUT
42D3 76C3
1
PM_CLK32K_SUSCLK
OUT
40C5 76A3
R2826
1
PLACEMENT_NOTE=Place close to U1400
12pF
2
5%
50V
CERM
402
MCP S0 PWRGD & CPU_VLD
7A3
MEM_VTT_EN_R
R2825
1
Y2815
25.0000M
2
CRITICAL
IN
MCP_CLK25M_XTALOUT_R
MCP_CLK25M_XTALIN
B
18C4
76C3 18B3
SM-3.2X2.5MM
20B7
2
5%
50V
CERM
402
0
5%
1/16W
MF-LF
402 2
1
30A7
5%
50V
CERM
402
MCP_CLK25M_XTALOUT
NO STUFF
OUT
12pF
1
12pF
IN
CARDREADER_PLT_RST_L
2
C2811
7X1.5X1.4-SM
RTC_CLK32K_XTALIN
MCP 25MHz Crystal
20B7
0
5%
1/16W
MF-LF
402
4
10M
C
R2895
1
CRITICAL
5%
1/16W
MF-LF
402 2
2
5%
1/16W
MF-LF
402
RTC_CLK32K_XTALOUT_R
NO STUFF
20B7
2
5%
50V
CERM
402
0
5%
1/16W
MF-LF
402 2
C
0
1
12pF
IN
2
5%
1/16W
MF-LF
402
R2891
1
20B7
0
1
33
2
5%
1/16W
MF-LF
402
B
R2829
76A3 20B3
IN
PM_CLK32K_SUSCLK_R
1
PLACEMENT_NOTE=Place close to U1400
=PP3V3_S5_MCPPWRGD
22
2
5%
1/16W
MF-LF
402
MCPSEQ_SMC
1
C2850
0.1UF
2
20%
10V
CERM
402
Reset Button
40B8
IN
PM_SYSRST_L
MCPSEQ_SMC
66A4 40D8
IN
62C7
IN
ALL_SYS_PWRGD
VR_PWRGOOD_DELAY
2
1
5 TC7SZ08AFEAPE
U2850Y
4
XDP
R2853
SOT665
A
S0_AND_IMVP_PGOOD
1
0
R2898
MCP_PS_PWRGD
2
OUT
20B7
12B3 9C6
IN
XDP_DBRESET_L
1
5%
1/16W
MF-LF
402
B
3
5%
1/16W
MF-LF
402
R2852
1
A
0
5%
1/16W
MF-LF
402
20B3
IN
1
R28901
NO STUFF
0
33
5%
1/16W
MF-LF
402
SILK_PART=SYS RST
OUT
20C7
NO STUFF
1
C2899
1UF
2
10%
10V
X5R
402
MCP_CPU_VLD
OUT
20B7
MCPSEQ_SMC
MCP_CPUVDD_EN
SB Misc
R2850
1
0
SYNC_MASTER=RAYMOND
2
SYNC FROM T18
CHANGE RESET BUTTOM TO RESET PADS
REMOVE UNUSED PCIE RESET SIGNALS
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A
CHANGE RTC COIN CELL TO LDO & SUPERCAP
ALIAS MEM_VTT_EN TO =DDRVTT_EN
CHANGE Y2810 AND U2850 TO SMALLER PARTS
5%
1/16W
MF-LF
402
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.
MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
SYNC_DATE=04/05/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
7
PM_SYSRST_DEBOUNCE_L
2
2
PLACEMENT_NOTE=Place close to U1400
8
10K pull-up to 3.3V S0 inside MCP
2
5%
1/16W
MF-LF
402
R2851
1
0
R2899
2
5%
1/16W
MF-LF
402 2
MCPSEQ_MIX
MCPSEQ_MIX
0
4.7.0
OF
24
1
81
A
8
6
7
2
3
4
5
1
Page Notes
MEM A VREF DQ
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF
DAC channel
Min DAC code
Max DAC code
Max sink I
Max source I
Nominal Vref
Min Vref
Max Vref
Vref Stepping
(per DAC LSB)
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
D
BOM options provided by this page:
VREFMRGN
NO_VREFMRGN
MEM A VREF CA
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
MEM B VREF DQ
MEM B VREF CA
A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV
CPU FSB VREF
C
0x00
0x55
-0.91 mA
0.52 mA
0.70 V
0.091 V
1.044 V
11.2 mV
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
61D8 7C4
=PPVTT_S3_DDR_BUF
D
10mA max load
R2903
1
A2
C2903
V+
0.1UF
7D3
A3
VREFMRGN
R2901
C2901
0.1UF
20%
2 10V
CERM
402
C2
V+
=I2C_VREFDACS_SCL
6 SCL
BI
=I2C_VREFDACS_SDA
7 SDA
9 A0
ADDR=0x98(WR)/0x99(RD)
C
10 A1
VOUTB 2
VREFMRGN_CA_SODIMM
VOUTC 4
VREFMRGN_CPUFSB
VOUTD 5
NC
VREFMRGN_DQ_SODIMMB_BUF
1
R2902
100K
5%
1/16W
MF-LF
402
VREFMRGN
1
GND
3
A2
C2904
U2903
B1
V+
0.1UF
20%
10V
2 CERM
402
A3
1
VREFMRGN_CA_SODIMMA_BUF
R2907
VREFMRGN_CA_SODIMMB_BUF
R2908
100K
VREFMRGN
1
A2
C2905
0.1UF
A3
Place close to J3100.126
200
VREFMRGN
2
PP0V75_S3_MEM_VREFCA_B
100
27B3
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VREFMRGN
2
1%
1/16W
MF-LF
402
Place close to J3200.126
5%
1/16W
MF-LF
402
VREFMRGN
MAX4253
VREFMRGN
20%
2 10V
CERM
402
2
1
U2904
B1
V+
1
25A5 VREFMRGN_CA_SODIMMB_EN
B4
26B3
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VREFMRGN
1%
1/16W
MF-LF
402
C4
V-
100
C
PP0V75_S3_MEM_VREFCA_A
R2912
MAX4253
UCSP
C1
VREFMRGN
C3
5%
1/16W
MF-LF
402
VREFMRGN
2
2
V+
Place close to J3200.1
R2911
VREFMRGN
1
U2903
B1
200
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
2
1%
1/16W
MF-LF
402
1
100K
C2
1
25B5 VREFMRGN_CA_SODIMMA_EN
B4
27D5
R2910
A4
V-
100
VREFMRGN
1%
1/16W
MF-LF
402
MAX4253
UCSP
A1
VREFMRGN
PP0V75_S3_MEM_VREFDQ_B
R2909
VREFMRGN
VREFMRGN
2
1%
1/16W
MF-LF
402
25A5 VREFMRGN_DQ_SODIMMB_EN
B4
VREFMRGN_DQ_SODIMM
200
R2906
C4
V-
Place close to J3100.1
1%
1/16W
MF-LF
402
1
43B3
IN
DAC5574
43B3
C3
5%
1/16W
MF-LF
402
MAX4253
UCSP
C1
VREFMRGN
VREFMRGN
8 U2900
VDD
MSOP VOUTA 1
U2902
B1
1
20%
6.3V
CERM
402-LF
VREFMRGN
26D5
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VREFMRGN
2
R2905
1
100K
2
1
2.2UF
100
1%
1/16W
MF-LF
402
2
C2900
1
25A5 VREFMRGN_DQ_SODIMMA_EN
B4
VREFMRGN
VREFMRGN_DQ_SODIMMA_BUF
A4
V-
PP0V75_S3_MEM_VREFDQ_A
R2904
MAX4253
UCSP
A1
VREFMRGN
20%
10V
2 CERM
402
=PP3V3_S3_VREFMRGN
U2902
B1
2
1%
1/16W
MF-LF
402
2
VREFMRGN
1
200
VREFMRGN
UCSP
A1
NC
A4
VB4
B
B
16
C2902
0.1UF
U2901
A0
A1
5 A2
4
43A3
IN
BI
1
2
SCL
SDA
THRM
17
PAD
NC
7
VREFMRGN_DQ_SODIMMA_EN
10
VREFMRGN_CA_SODIMMB_EN
11
VREFMRGN_DQ_SODIMMB_EN
12
5%
1/16W
MF-LF
402
25C3
25D3
100
1%
1/16W
MF-LF
402
25B5 VREFMRGN_CPUFSB_EN
100K
25B3
1
C4
R2913
VREFMRGN_CPUFSB_EN
VREFMRGN_CA_SODIMMA_EN
9
R2914
VREFMRGN_CPUFSB_BUF
VREFMRGN
CPU_GTLREF
2
OUT
9B4 73B3
Place close to U1000.AD26
VREFMRGN
25B3
25C3
13
NC
NC
14
RESET* 15
PCA9557D_RESET_L
GND
IN
24C1
8
43A3
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
6
UCSP
C1
1
P0
P1
P2
P3
P4
P5
P6
P7
3
VB4
PCA9557
QFN
ADDR=0x30(WR)/0x31(RD)
C3
U2904
MAX4253
VREFMRGN
VCC
20%
2 10V
CERM
402
B1
V+
VREFMRGN
2
C2
VREFMRGN
1
FSB/DDR3 Vref Margining
A
SYNC_MASTER=BEN
SYNC_DATE=03/31/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
Required zero ohm resistors when no VREF margining circuit stuffed
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2903
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2905
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2909
CRITICAL
NO_VREFMRGN
116S0004
1
RES,MTL FILM,0,5%,0402,SM,LF
R2911
CRITICAL
NO_VREFMRGN
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
25
1
81
A
8
6
7
Page Notes
7D3
2
3
4
5
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
=PP1V5_S3_MEM_A
Power aliases required by this page:
- =PP1V5_S0_MEM_A
1
- =PP1V5_S3_MEM_A
- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
2
C3100
1
C3101
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
2
1
C3110
1
0.1UF
2
2
CRITICAL
Signal aliases required by this page:
C3111
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
C3112
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
20%
6.3V
X6S-CERM
0204-1
1
0.1UF
2
CRITICAL
C3113
C3114
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
20%
6.3V
X6S-CERM
0204-1
1
0.1UF
2
CRITICAL
C3115
C3116
1
20%
6.3V
X6S-CERM
0204-1
2 6.3V
X6S-CERM
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
C3117
0.1UF
20%
0204-1
CRITICAL
CRITICAL
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
BOM options provided by this page:
25D1
D
PP0V75_S3_MEM_VREFDQ_A
(NONE)
C3130
1
C3131
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
2
20%
10V
CERM
402
1
C
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14B5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14C5
IN
74D3 14B5
IN
73
MEM_A_CKE<0>
MEM_A_BA<2>
NC
B
7C5
BI
74D3 14C7
BI
74C3 14D5
BI
74C3 14D5
BI
74D3 14C7
BI
74D3 14C7
BI
79
81
83
MEM_A_A<12>
MEM_A_A<9>
85
87
89
MEM_A_A<8>
MEM_A_A<5>
91
93
95
MEM_A_A<3>
MEM_A_A<1>
97
99
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
101
MEM_A_A<10>
MEM_A_BA<0>
107
MEM_A_WE_L
MEM_A_CAS_L
113
MEM_A_A<13>
MEM_A_CS_L<1>
119
121
103
105
109
111
115
117
123
NC
74D3 14C7
75
77
125
127
MEM_A_DQ<32>
MEM_A_DQ<33>
129
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
135
MEM_A_DQ<34>
MEM_A_DQ<38>
141
143
131
133
137
139
145
147
149
74D3 14C7
BI
74D3 14C7
BI
MEM_A_DQ<44>
MEM_A_DQ<45>
74C3 14B7
IN
MEM_A_DM<5>
153
155
74D3 14D7
BI
157
74D3 14D7
BI
MEM_A_DQ<47>
MEM_A_DQ<46>
74D3 14D7
BI
74D3 14D7
BI
MEM_A_DQ<49>
MEM_A_DQ<52>
163
165
74C3 14D5
BI
74C3 14D5
BI
74D3 14D7
BI
74D3 14D7
BI
74D3 14D7
BI
74D3 14D7
BI
151
159
161
167
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
169
171
173
MEM_A_DQ<54>
MEM_A_DQ<51>
175
177
179
MEM_A_DQ<61>
MEM_A_DQ<60>
181
183
185
187
74C3 14B7
IN
MEM_A_DM<7>
74D3 14D7
BI
74D3 14D7
BI
MEM_A_DQ<58>
MEM_A_DQ<59>
189
191
193
195
MEM_A_SA<0>
197
199
MEM_A_SA<1>
201
=PPSPD_S0_MEM_A
203
1
A
C3140
1
2.2UF
2
20%
6.3V
CERM
402-LF
2
1
R3140
J3100
74
MEM_A_CKE<1>
76
78
IN
14A5 74D3
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
74D3 14B7
74D3 14B7
MEM_A_A<15>
MEM_A_A<14>
80
82
84
MEM_A_A<11>
MEM_A_A<7>
86
88
90
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
8D2
IN
14C5 74D3
74D3 14A7
74D3 14B7
BI
14C5 74D3
74D3 14B7
BI
IN
14B5 74D3
74D3 14B7
BI
IN
14B5 74D3
74D3 14B7
BI
MEM_A_A<2>
MEM_A_A<0>
IN
14B5 74D3
74C3 14D5
BI
IN
14B5 74D3
74C3 14D5
BI
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
IN
14B5 74D3
74D3 14B7
BI
IN
14B5 74D3
74D3 14B7
BI
MEM_A_BA<1>
MEM_A_RAS_L
IN
14C5 74D3
74D3 14C7
BI
IN
14C5 74D3
74D3 14C7
BI
MEM_A_CS_L<0>
MEM_A_ODT<0>
IN
14B5 74D3
74C3 14D5
BI
IN
14B5 74D3
74C3 14D5
BI
MEM_A_ODT<1>
IN
14B5 74D3
74D3 14C7
BI
74D3 14C7
BI
126
128
136
138
140
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DM<4>
BI
14C7 74D3
BI
14C7 74D3
IN
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQ<40>
MEM_A_DQ<41>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
BI
14D5 74C3
BI
14D5 74C3
MEM_A_DQ<43>
MEM_A_DQ<42>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQ<53>
MEM_A_DQ<48>
BI
14D7 74D3
BI
14D7 74D3
170
172
MEM_A_DM<6>
IN
174
MEM_A_DQ<55>
MEM_A_DQ<50>
BI
14D7 74D3
BI
14D7 74D3
MEM_A_DQ<57>
MEM_A_DQ<56>
BI
14D7 74D3
BI
14D7 74D3
146
148
150
152
154
156
158
160
162
164
166
168
176
178
180
182
184
186
188
192
194
198
200
BI
BI
14D5 74C3
MEM_A_DQ<62>
MEM_A_DQ<63>
BI
14D7 74D3
BI
14D7 74D3
202
204
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
OUT
BI
MEM_A_DQ<0>
MEM_A_DQ<1>
7
9
11
MEM_A_DM<0>
13
15
MEM_A_DQ<6>
MEM_A_DQ<7>
17
19
21
MEM_A_DQ<8>
MEM_A_DQ<12>
23
25
27
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
29
31
MEM_A_DQ<10>
MEM_A_DQ<15>
33
MEM_A_DQ<25>
MEM_A_DQ<24>
39
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
45
MEM_A_DQ<26>
MEM_A_DQ<30>
51
53
35
37
41
43
47
49
55
57
59
MEM_A_DQ<20>
MEM_A_DQ<21>
61
IN
MEM_A_DM<2>
63
65
74D3 14C7
BI
67
74D3 14B7
BI
MEM_A_DQ<23>
MEM_A_DQ<16>
69
71
VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
VSS
DQ1
VSS
DQS0*
DM0
DQS0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
VSS
DQ22
DQ18
DQ23
DQ19
VSS
VSS
DQ28
DQ24
DQ29
VSS
DQ25
VSS
DQS3*
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
J3100
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
MEM_A_DQ<4>
MEM_A_DQ<5>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
BI
14D5 74C3
BI
14D5 74C3
MEM_A_DQ<3>
MEM_A_DQ<2>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQ<9>
MEM_A_DQ<13>
BI
14B7 74D3
MEM_A_DM<1>
MEM_RESET_L
IN
14A7 74C3
IN
27C2 28C5
MEM_A_DQ<11>
MEM_A_DQ<14>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQ<29>
MEM_A_DQ<28>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DM<3>
IN
MEM_A_DQ<27>
MEM_A_DQ<31>
BI
14C7 74D3
BI
14C7 74D3
MEM_A_DQ<18>
MEM_A_DQ<17>
BI
14B7 74D3
BI
14B7 74D3
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
BI
14D5 74C3
BI
14D5 74C3
MEM_A_DQ<19>
MEM_A_DQ<22>
BI
14B7 74D3
BI
14C7 74D3
BI
14B7 74D3
C
14B7 74C3
KEY
516-0201
B
PP0V75_S3_MEM_VREFCA_A
1
C3135
1
2.2UF
14D5 74C3
196
BI
74D3 14C7
3
5
14B7 74C3
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
190
74D3 14C7
74C3 14B7
14B7 74C3
MEM_A_DQ<35>
MEM_A_DQ<39>
142
144
IN
14C5 74D3
NC
132
134
BI
IN
124
130
BI
IN
MEM_A_A<6>
MEM_A_A<4>
92
IN
2
20%
6.3V
CERM
402-LF
25C1
C3136
0.1UF
2
20%
10V
CERM
402
20A4 20B3 27A5 40B8
BI
IN
"Factory" (top) slot
43D6
43D6
=PP0V75_S0_MEM_VTT_A
7C7
DDR3 SO-DIMM Connector A
R3141
10K
2
CKE0
CKE1
VDD
VDD
NC
A15
A14
BA2
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
(SYMBOL 2 OF 2)
74D3 14C5
IN
DDR3-SODIMM-DUAL-M97-3
74D3 14A5
KEY
(SYMBOL 1 OF 2)
1
DDR3-SODIMM-DUAL-M97-3
D
1
C3150
1
2.2UF
2
20%
6.3V
CERM
402-LF
C3151
SYNC_MASTER=BEN
2.2UF
2
SYNC_DATE=06/30/2008
NOTICE OF PROPRIETARY PROPERTY
20%
6.3V
CERM
402-LF
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
516-0201
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SPD ADDR=0xA0(WR)/0xA1(RD)
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
26
1
81
A
8
6
7
Page Notes
7D3
2
3
4
5
1
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
=PP1V5_S3_MEM_B
Power aliases required by this page:
- =PP1V5_S0_MEM_B
1
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
2
C3200
1
C3201
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
2
1
C3210
1
0.1UF
2
2
CRITICAL
Signal aliases required by this page:
C3211
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
C3212
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
CRITICAL
20%
6.3V
X6S-CERM
0204-1
C3213
1
0.1UF
2
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
CRITICAL
CRITICAL
C3214
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
C3215
1
0.1UF
2
C3216
1
0.1UF
20%
6.3V
X6S-CERM
0204-1
2
20%
2 6.3V
X6S-CERM
0204-1
CRITICAL
CRITICAL
C3217
0.1UF
20%
6.3V
X6S-CERM
0204-1
CRITICAL
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
BOM options provided by this page:
25C1
D
PP0V75_S3_MEM_VREFDQ_B
(NONE)
C3230
1
C3231
2.2UF
2
0.1UF
20%
6.3V
CERM
402-LF
2
20%
10V
CERM
402
1
C
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14B1
IN
74B3 14B1
IN
74B3 14B1
IN
74C3 14B1
IN
74C3 14B1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14C1
IN
74B3 14B1
75
77
MEM_B_BA<2>
IN
74B3 14C1
73
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
IN
79
81
83
85
87
89
91
93
95
97
99
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
101
MEM_B_A<10>
MEM_B_BA<0>
107
MEM_B_WE_L
MEM_B_CAS_L
113
MEM_B_A<13>
MEM_B_CS_L<1>
119
121
103
105
109
111
115
117
123
125
127
B
1
R3240
74B3 14C3
BI
74B3 14C3
BI
74A3 14D1
BI
74A3 14D1
BI
74B3 14C3
BI
74B3 14C3
BI
MEM_B_DQ<37>
MEM_B_DQ<32>
129
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
135
MEM_B_DQ<35>
MEM_B_DQ<39>
2
7C5
137
139
141
143
145
147
149
74B3 14C3
BI
74B3 14C3
BI
MEM_B_DQ<45>
MEM_B_DQ<41>
74B3 14B3
IN
MEM_B_DM<5>
153
155
74B3 14D3
BI
157
74B3 14D3
BI
MEM_B_DQ<46>
MEM_B_DQ<47>
74B3 14D3
BI
74B3 14D3
BI
74A3 14D1
BI
74A3 14D1
BI
74B3 14D3
BI
74B3 14D3
BI
74B3 14D3
BI
74B3 14D3
BI
151
MEM_B_DQ<53>
MEM_B_DQ<49>
159
161
163
165
167
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
169
171
173
MEM_B_DQ<55>
MEM_B_DQ<54>
175
177
179
MEM_B_DQ<56>
MEM_B_DQ<58>
181
183
185
187
74B3 14B3
IN
MEM_B_DM<7>
74B3 14D3
BI
74B3 14D3
BI
MEM_B_DQ<61>
MEM_B_DQ<60>
189
10K
5%
1/16W
MF-LF
402
131
133
191
193
195
MEM_B_SA<0>
197
199
MEM_B_SA<1>
201
=PPSPD_S0_MEM_B
203
1
A
1
C3240
2
R3241
10K
2.2UF
20%
6.3V
CERM
402-LF
2
5%
1/16W
MF-LF
402
205
207
209
211
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
VDD F-RT-BGA3 VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
J3200
(2 OF 2)
74B3 14C1
MEM_B_CKE<0>
IN
DDR3-SODIMM
74B3 14A1
KEY
MTG PINS
MTG
MTG
MTG
MTG
PIN
PIN
PIN
PIN
MTG PIN
MTG PIN
MTG PIN
MTG PIN
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
MEM_B_CKE<1>
IN
14A1 74B3
74B3 14B3
74B3 14B3
MEM_B_A<15>
MEM_B_A<14>
8D2
IN
14C1 74B3
IN
14C1 74B3
74B3 14B3
BI
IN
14C1 74B3
74B3 14B3
BI
IN
14B1 74B3
74B3 14B3
BI
IN
14B1 74B3
74B3 14B3
BI
MEM_B_A<2>
MEM_B_A<0>
IN
14B1 74B3
74A3 14D1
BI
IN
14B1 74B3
74A3 14D1
BI
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
IN
14B1 74C3
74B3 14B3
BI
IN
14B1 74C3
74B3 14B3
BI
MEM_B_BA<1>
MEM_B_RAS_L
IN
14C1 74B3
74B3 14C3
BI
IN
14C1 74B3
74B3 14B3
BI
MEM_B_CS_L<0>
MEM_B_ODT<0>
IN
14B1 74B3
74A3 14D1
BI
IN
14B1 74B3
74A3 14D1
BI
MEM_B_ODT<1>
IN
14B1 74B3
74B3 14C3
BI
74B3 14B3
BI
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
74B3 14A3
126
128
132
134
136
138
140
MEM_B_DQ<36>
MEM_B_DQ<33>
MEM_B_DM<4>
BI
14C3 74B3
BI
14C3 74B3
IN
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQ<40>
MEM_B_DQ<44>
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
BI
14D1 74A3
BI
14D1 74A3
MEM_B_DQ<42>
MEM_B_DQ<43>
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQ<52>
MEM_B_DQ<48>
BI
14D3 74B3
BI
14D3 74B3
170
172
MEM_B_DM<6>
IN
174
MEM_B_DQ<51>
MEM_B_DQ<50>
BI
14D3 74B3
BI
14D3 74B3
MEM_B_DQ<63>
MEM_B_DQ<59>
BI
14D3 74B3
BI
14D3 74B3
146
148
150
152
154
156
158
160
162
164
166
168
176
178
180
182
184
186
188
192
194
198
200
202
204
13
15
MEM_B_DQ<3>
MEM_B_DQ<6>
17
19
21
MEM_B_DQ<13>
MEM_B_DQ<14>
23
25
27
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
29
31
MEM_B_DQ<15>
MEM_B_DQ<10>
33
MEM_B_DQ<20>
MEM_B_DQ<17>
39
35
37
41
43
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
45
MEM_B_DQ<22>
MEM_B_DQ<19>
51
53
47
49
55
57
59
MEM_B_DQ<24>
MEM_B_DQ<28>
61
IN
MEM_B_DM<3>
63
65
74B3 14C3
BI
67
74B3 14C3
BI
MEM_B_DQ<26>
MEM_B_DQ<31>
69
71
J3200
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
MEM_B_DQ<4>
MEM_B_DQ<5>
BI
14B3 74B3
BI
14B3 74B3
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
BI
14D1 74A3
BI
14D1 74A3
MEM_B_DQ<7>
MEM_B_DQ<2>
BI
14B3 74B3
BI
14B3 74B3
MEM_B_DQ<12>
MEM_B_DQ<9>
BI
14B3 74B3
MEM_B_DM<1>
MEM_RESET_L
IN
14A3 74B3
IN
26C2 28C5
MEM_B_DQ<8>
MEM_B_DQ<11>
BI
14B3 74B3
BI
14B3 74B3
MEM_B_DQ<16>
MEM_B_DQ<21>
BI
14B3 74B3
BI
14C3 74B3
MEM_B_DM<2>
IN
MEM_B_DQ<18>
MEM_B_DQ<23>
BI
14B3 74B3
BI
14C3 74B3
MEM_B_DQ<29>
MEM_B_DQ<25>
BI
14C3 74B3
BI
14C3 74B3
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
BI
14D1 74A3
BI
14D1 74A3
MEM_B_DQ<30>
MEM_B_DQ<27>
BI
14C3 74B3
BI
14C3 74B3
14D1 74A3
MEM_B_DQ<62>
MEM_B_DQ<57>
BI
14D3 74B3
BI
14D3 74B3
BI
14B3 74B3
C
14B3 74B3
KEY
516S0706
B
DDR3 GROUND RETURN CAPS (MCP SIDE)
=PP1V5_S0_MEM_MCP
1
2
PP0V75_S3_MEM_VREFCA_B
1
C3235
1
2.2UF
BI
OUT
11
MEM_B_DM<0>
4
6
C3222
1
0.1UF
BI
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
BI
7
9
2
14B3 74B3
14D1 74A3
196
BI
74B3 14C3
MEM_B_DQ<1>
MEM_B_DQ<0>
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
CRITICAL
DQ1
VSS
VSS
DQS0*
DM0
DQS0
F-RT-BGA3
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
VSS
DQ22
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ24
DQ29
VSS
DQ25
VSS
DQS3*
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
7B6
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
190
IN
74B3 14C3
74B3 14B3
14B3 74B3
MEM_B_DQ<38>
MEM_B_DQ<34>
142
144
BI
IN
124
130
BI
3
5
(1 OF 2)
1
DDR3-SODIMM
D
2
20%
6.3V
CERM
402-LF
25C1
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3223
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3224
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3225
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3226
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3227
1
0.1UF
2
20%
6.3V
X6S-CERM
0204-1
CRITICAL
C3228
1
20%
6.3V
X6S-CERM
0204-1
2 6.3V
X6S-CERM
0.1UF
2
C3229
0.1UF
20%
0204-1
CRITICAL
CRITICAL
C3236
0.1UF
2
20%
10V
CERM
402
20A4 20B3 26A5 40B8
BI
IN
43C6
"Expansion" (bottom) slot
43C6
=PP0V75_S0_MEM_VTT_B
7C7
DDR3 SO-DIMM Connector B
206
208
1
210
212
C3250
1
2.2UF
2
20%
6.3V
CERM
402-LF
C3251
SYNC_MASTER=BEN
2.2UF
2
SYNC_DATE=05/09/2008
NOTICE OF PROPRIETARY PROPERTY
20%
6.3V
CERM
402-LF
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
516S0706
SIZE
SPD ADDR=0xA2(WR)/0xA3(RD)
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
27
1
81
A
8
6
7
3
4
5
2
1
D
D
DDR3 RESET Support
Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309
MCP_MEM_RESET_L
2
0
1
MEM_RESET_L
R33101
Q3305
1K
5%
1/16W
MF-LF
402 2
1
Q1
S
2
B
0.1UF
3
5
C3300
E
1
MEM_RESET_RC_L
4
R3301
1
R3305
1
6
10K
5%
1/16W
MF-LF
402 2
7A3
SOT-363
D
R3300
=PP3V3_S5_MEMRESET
DMB53D0UDW
5%
1/16W
MF-LF
402 2
1
20K
26C2 27C2
G
=PP1V5_S3_MEMRESET
C
OUT
5%
1/16W
MF-LF
402
C
7D3
IN
Q2
15C3
100K
5%
1/16W
MF-LF
402 2
C
3.3V S5 is used because MEM_RESET
must be high before 1.5V starts to
rise to avoid glitch on MEM_RESET_L.
MEM_RESET
20%
10V
2 CERM
402
B
B
DDR3 Support
A
SYNC_MASTER=T18_MLB
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
28
1
81
A
8
6
7
16C6
OUT
2
3
4
5
1
PCIE_MINI_PRSNT_L
3
D
Q3401
SSM6N15FEAPE
SOT563
4
S
G
5
AP_PWR_EN
20A3 20C3 32C7
IN
5V S3 WLAN FET
D
16C6
OUT
MINI_CLKREQ_L
6
D
Q3401
SOT563
S
G
TPCP8102
CHANNEL
P-TYPE
RDS(ON)
SSM6N15FEAPE
1
MOSFET
D
26 mOhm @4.5V
LOADING
0.8 A (EDP)
2
CRITICAL
Q3450
TPCP8102
L3404
20347-325E-12
10%
0.1uF
16V
X5R
16V X5R 402
IN
16B3 75D3
402
3
2
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
1
2
OUT
6D5 16B6 75D3
OUT
6D5 16B6 75D3
3
4
75D3 6D5
5
75D3 6D5
PCIE_CLK100M_MINI_CONN_P
6D5 PCIE_CLK100M_MINI_CONN_N
8
75D3
6C5
11
20%
10V
CERM
402
1
2
C3420
10UF
2
2
20%
10V
X5R
805
C3450
0.1UF
2
10%
16V
X5R
402
PLACEMENT_NOTE=Place close to J3401.
C3451
1
10%
16V
X5R
402
2
10K
0.033UF
P5VWLAN_SS
R3451
7C3
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
R3450
1
100K
2
5%
1/16W
MF-LF
402
PM_WLAN_EN_L
2
IN
29A4 32C6
5%
1/16W
MF-LF
402
PCIE_CLK100M_MINI_P
3
C
PLACEMENT_NOTE=Place close to Q3450.
IN
16C3
75D3
PLACEMENT_NOTE=Place close to Q3450.
1
9
10
1
0.1uF
=PP5V_S3_WLAN
1
SYM_VER-1
4
75D3 6D5
PP5V_WLAN_F
1
DLP11S
6
7
20%
10V
CERM
402
AIRPORT
L3401
90-OHM-100MA
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
C3421
1
0.1uF
CRITICAL
29A5
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
C3422
PLACEMENT_NOTE=Place close to J3401.
31
1
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
C3430
F-RT-SM
23V1K-SM
8
0402-LF
PP5V_WLAN
S
IN
16B3 75D3 6C3
6D5
1 2
2
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
0.1uF
4 G
1
10%
2
D
1
1000 mA peak
750 mA nominal max
6 7
C3431
J3401
C
FERR-120-OHM-1.5A
PLACEMENT_NOTE=Place close to J3401.
5
CRITICAL
518S0610
PCIE_CLK100M_MINI_N
2
IN
16C3
75D3
PLACEMENT_NOTE=Place close to J3401.
MINI_CLKREQ_Q_L
PCIE_WAKE_L
OUT
12
6D5 16B6
13
14
15
16
17
NC
NC
6D5
18
19
PP5V_S3_BTCAMERA_F
=I2C_ALS_SDA
=I2C_ALS_SCL
20
BI
IN
43C1
76C3 6D5
22
76C3
CRITICAL
23
L3402
90-OHM
CONN_USB2_BT_P
CONN_USB2_BT_N
24
25
DLP0NS
C3452
=PP5V_S3_BTCAMERA
1
1
0402-LF
7C3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
0.1uF
20%
10V
CERM
402
2
SYM_VER-1
4
3
USB_CAMERA_P
OUT
19D3 76C3
1
2
USB_CAMERA_N
OUT
19D3 76C3
26
27
28
PLACEMENT_NOTE=Place close to J3401.
29
B
2
FERR-120-OHM-1.5A
ALS
CAMERA
43C1
USB_CAMERA_CONN_P
6D5 USB_CAMERA_CONN_N
21
L3405
275 mA peak
206 mA nominal max
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
B
30
BLUETOOTH
CRITICAL
32
L3403
90-OHM
DLP0NS
SYM_VER-1
4
1
3
USB_BT_P
BI
19D3 76C3
2
USB_BT_N
BI
19C3 76C3
PLACEMENT_NOTE=Place close to J3401.
PP5V_WLAN_F
=PP3V3_S3_WLAN
7D3
1
29C3
R3453
33K
U3402
TC7SZ08AFEAPE 5
SOT665
6C5
MINI_RESET_CONN_L
4
74LVC1G17DRL
A
U3401
2
2
SOT-553
4
WLAN_SMIT_BUF
5%
1/16W
MF-LF
402
R3455
2
WLAN_SMIT_RC
NC
Y
B
1
3
3
MINI_RESET_L
A
5
1
NC
C3453
IN
24C1
1
1
1
5%
1/16W
MF-LF
402
2
WLAN_SMIT_DISCHRG
Q3455
3
D
2
2
Right Clutch Connector
SSM3K15FV
SOD-VESM-HF
62K
1UF
10%
6.3V
CERM
402
R3454
1
SYNC_MASTER=YITE
5%
1/16W
MF-LF
402
SYNC_DATE=04/22/2008
NOTICE OF PROPRIETARY PROPERTY
2
S
G 1
PM_WLAN_EN_L
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
29C1 32C6
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
29
1
81
A
8
6
7
R3511
7C3
=PP3V3_S3_CARDREADER
0
1
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
2
3
4
5
1
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
2
30B4 30A7
5%
1/16W
MF-LF
402
PP3V3_S3_CARDREADER_DVDD
C3500
1
1
10UF
1
0.1UF
20%
6.3V
2 X5R
603
D
C3501
C3502
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
1
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
C3503
0.1UF
20%
10V
2 CERM
402
PART NUMBER
516-0225
QTY
1
DESCRIPTION
REFERENCE DES
CONN,SD CARD READER,OPTN B,HF,K19/K24
J3500
CRITICAL
BOM OPTION
D
CRITICAL
L3500
0.22UH
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN
1
PP3V3_S3_CARDREADER_AVDD
1
C3514
1
10UF
C3504
1
0.1UF
20%
6.3V
2 X5R
603
2
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
0805-1
MAX CURRENT = 250MA
C3508
PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE
0.1UF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
1
C3507
2.2UF
20%
6.3V
2 CERM1
603
1
C3505
0.1UF
20%
10V
2 CERM
402
PP1V8_S3_CARDREADER
1
PP3V3_SW_SD_PWR
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
R3505
1
39K
5%
1/16W
MF-LF
2 402
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=1.8V
C3506
0.1UF
OMIT
J3500
C
76B3 19C3
BI
76B3 19C3
BI
30A7
30A6
CARDREADER_GPIO1
CARDREADER_GPIO2
NC
LQFP
48 GPIO1
47 GPIO2
46 GPIO3
CRITICAL
19
SK
NC
20 CS
NC
21 DO
NC
22 DI /IPD
NC
1
10 RREF
CARDREADER_RREF
2
5%
1/16W
MF-LF
402
17 TESTMOD
CARDREADER_TEST_MOD
Y3500
12.000M-100PPM
1
2
IPD/
5%
50V
CERM
402
B
5%
50V
CERM
402
1
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
2
C3513
0.1UF
20%
10V
2 CERM
402
16
1
0
715
33PF
2
D0
D1
D2
D3
D4
D5
D6
D7
40
43
37
29
28
30
32
38
SD_WP
5 G
CARDREADER_RESET
9
1
10
11
12
13
14
16
18
1
NC
NC
42
NC
44
NC
45
NC
19
31
20
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
C
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
24
IPU/ MS_INS
NC
MS_BS 33
NC
PDMOD: POWER DOWN MODES
NC = DISABLE (DEFAULT)
10K LOW = POWER SAVING MODE ENABLE
10K HIGH = REMOTE WAKE UP ENABLE
B
PP3V3_S3_CARDREADER_DVDD
D 3
1
R3512
10K
SOT563
IN
8
17
SSM6N15FEAPE
16B6
7
4
CARDREADER_PDMOD
30D6 30A7
Q3500
2
15
SD_WP 3
SD_CMD 41
2
IPU/ PDMOD
23
IPU/ SD_CDZ
5
GND
12
1
R3506
C3512
33PF
NO STUFF
R3502
9
C3511
1
1
5
8X4.5X1.4-SM
6
IPU/ XD_CDZ
XD_CE
IPD/ XD_WEZ
IPD/ XD_RBZ
IPD/ XD_WPZ
/IPD
CARDREADER_RESET_L 18 EXTRSTZ* /IPU
CRITICAL
3
SD_CLK
78C3 SD_CMD
78D3 SD_D<0>
78D3 SD_D<1>
78C3 SD_D<2>
78C3 SD_D<3>
78C3 SD_D<4>
78C3 SD_D<5>
78C3 SD_D<6>
78C3 SD_D<7>
SD_CD_L
78C3
34
1M
IPD/
IPD/
27
R3503
F-RT-TH
CLK 39
13 X1
14 X2
CARDREADER_XTAL1
CARDREADER_XTAL2
NO STUFF
36
25
GL137A
SD-CARD-K19
PMOSO
VDD5V
15
26
35
U3500
7 DM
8 DP
USB_CARDREADER_N
USB_CARDREADER_P
DVDD
6
AVDD 11
VDD18O
4
20%
2 10V
CERM
402
5%
1/16W
MF-LF
2 402
S 4
(PDMOD)
CARDREADER_PLT_RST
Q3500
D 6
1
10K
SOT563
24C1
IN
30D6 30B4
R3507
10K
5%
1/16W
MF-LF
2 402
30C6
5%
1/16W
MF-LF
2 402
S 1
PP3V3_S3_CARDREADER_DVDD
1
A
2 G
CARDREADER_PLT_RST_L
NO STUFF
R3513
SSM6N15FEAPE
1
NO STUFF
R3508
10K
SECUREDIGITAL CARD READER
5%
1/16W
MF-LF
2 402
CARDREADER_GPIO1
SYNC_MASTER=VEMURI
1NO
STUFF
R3509
10K
5%
1/16W
MF-LF
2 402
SYNC_DATE=01/30/2009
NOTICE OF PROPRIETARY PROPERTY
CARDREADER_GPIO2 30C6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
1
R3510
10K
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
2 402
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
30
1
81
A
8
6
7
2
3
4
5
=PP1V05_ENET_PHY
D
C3710
C3711
1
0.1UF
7B5
10%
16V
X5R
402
=PP3V3_ENET_PHY
(43mA typ - 1000base-T)
(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
1
1
0.1UF
10%
16V
X5R
402
2
1
7A5
(221mA typ - 1000base-T)
( 7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek
D
CRITICAL
L3715
2
FERR-120-OHM-1.5A
0402-LF
1
1
C3700
1
0.1UF
CRITICAL
L3705
2
FERR-120-OHM-1.5A
10%
16V
X5R
402
C3701
1
0.1UF
2
C3702
2
0.1UF
10%
16V
X5R
402
2
PP1V05_ENET_PHYAVDD
10%
16V
X5R
402
C3714
0402-LF
C3715
1
0.1UF
10%
16V
X5R
402
2
C3716
1
2.2UF
20%
6.3V
CERM
402-LF
2
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2.2UF
20%
6.3V
CERM
402-LF
2
2
PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
C3705
1
10%
16V
X5R
402
2
0.1UF
2
C3706
0.1UF
10%
16V
X5R
402
=PP3V3_ENET_PHY_VDDREG
8D2
If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
8D2
IN
=RTL8211_ENSWREG
2
IN
ENET_CLK125M_TXCLK
1
0
2
77D3
22
ENET_CLK125M_TXCLK_R
PLACE R3796 CLOSE TO U1400, PIN D24
IN
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
IN
ENET_TX_CTRL
77D3 17D3
IN
77D3 17C3
BI
ENET_MDC
ENET_MDIO
77D3 17D3
IN
77D3 17D3
IN
77D3 17D3
77D3 17D3
77C3 17D3
ENSWREG
10
40
3
44
45
15
21
37
U3700
ENET_RESET_L
1
0
IN
B
RTL8211_PHYRST_L
2
5%
1/16W
MF-LF
402
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.
2
4.7K
4.7K
=RTL8211_REGOUT
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
If internal switcher is used, must place inductor within 5mm
of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
8D2
C
If internal switcher is not used, VDDREG and REGOUT can float.
REGOUT
48
RXC
19
RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0
RXD[3]/AN1
14
16
17
18
RXCTL
13
RTL8251CA-VB-GR
23
24
25
26
27
30
31
TXC
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RGMII/MII
TXCTL
MDC
MDIO
NO STUFF
1
C3725
0.1UF
2
RTL8211_RSET
20%
10V
CERM
402
8D2
TP_RTL8211_CLK125
29
46
32
PHYRSTB*
RSET
77D3 32A3
IN
RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2
42
43
77D3
77D3
77D3
R3791
R3792
R3793
R3794
ENET_RXD_R<0>
ENET_RXD_R<1>
ENET_RXD_R<2>
ENET_RXD_R<3>
R3795
ENET_RXCTL_R
ENET_MDI_P<0>
ENET_MDI_N<0>
BI
33B8 77C3
BI
33B8 77C3
MDI+[1]
MDI-[1]
4
5
ENET_MDI_P<1>
ENET_MDI_N<1>
BI
33C8 77C3
BI
33C8 77C3
MDI+[2]
MDI-[2]
8
9
ENET_MDI_P<2>
ENET_MDI_N<2>
BI
33C8 77C3
BI
33C8 77C3
MDI+[3]
MDI-[3]
11
12
ENET_MDI_P<3>
ENET_MDI_N<3>
BI
33C8 77C3
BI
33C8 77C3
CLOCK
LED0/PHYAD0
LED1/PHYAD1
LED2/RXDLY
34
35
38
RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY
CKXTAL1
CKXTAL2
2
LED
GND
NO STUFF
C3790
7
20
33
47
1%
1/16W
MF-LF
402
77D3
22
22
22
22
22
22
1
1
2
1
2
1
2
1
2
1
ENET_CLK125M_RXCLK
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RX_CTRL
2
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
OUT
17D6 77D3
B
CLK125
R3730 1
2.49K
77D3
R3790
ENET_CLK125M_RXCLK_R
1
2
RESET MEDIA DEPENDENT
REFERENCE
77D3
MDI+[0]
MDI-[0]
MANAGEMENT
R3724
IN
5%
1/16W
MF-LF
402 2
R3752 1
R3751
TQFP
5%
1/16W
402
MF-LF
77C3 17C3
1
4.7K
CRITICAL
39
R3796
77D3 17D3
AVDD10
5%
1/16W
MF-LF
402
28
36
4.7K
FB10
5%
1/16W
MF-LF
402 2
DVDD10
Alias to =PP3V3_ENET_PHY for internal switcher.
Alias to GND for external 1.05V supply.
VDDREG
10K
C
R3725
DVDD33
1
AVDD33
NO STUFF
R3720 1
6
41
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
R3750 1
1
5%
50V
CERM
402
R3755 1
4.7K
10PF
2
5%
1/16W
MF-LF
402
R3756 1
1
4.7K
5%
1/16W
MF-LF
402
2
2
R3757
4.7K
2
5%
1/16W
MF-LF
402
Reserved for EMI
per RealTek request.
Ethernet PHY (RTL8211CL)
A
SYNC_MASTER=SUMA
SYNC_DATE=05/23/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Configuration Settings:
PHYAD
AN[1:0]
RXDLY
TXDLY
=
=
=
=
01
11
0
0
SIZE
8
DRAWING NUMBER
D
(PHY Address 00001)
(Full auto-negotiation)
(RXCLK transitions with data)
(No TXCLK Delay)
APPLE INC.
SCALE
SHT
NONE
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
31
1
81
A
8
6
7
2
3
4
5
1
3.3V ENET FET
@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
CRITICAL
Q3810
NTR4101P
SOT-23-HF
7A3
=PP3V3_S5_P3V3ENETFET
=PP3V3_ENET_FET
S
2
D
1
R3800 1
5%
1/16W
MF-LF
402
2
R3810
2
P3V3ENET_EN_L
Q3801
C3811
D
3
S
4
1
100K
7B6
3
D
G
0.033UF
10K
D
10%
16V
X5R
402
1
C3810
0.01UF
P3V3ENET_SS
2
2
5%
1/16W
MF-LF
402
1
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
5
8D2
IN
G
=P3V3ENET_EN
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and
=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
C
29A4 29C1
OUT
Q3805
D
6
SSM6N15FEAPE
SOT563
2
29D5 20C3 20A3
IN
G
7B3
S
=PP1V05_ENET_P1V05ENETFET
1.8V Vgs
C3840
1
AP_PWR_EN
Q3805
3
6
D
SSM6N15FEAPE
7A3
Q3801
1
SOT563
41B2 40D5 35B5 20C7
IN
S
4
1
S
G
100K
1%
1/16W
MF-LF
402
SMC_ADAPTER_EN
IN
SI2312BDS
G
Q3841
D
6
SOT23
2
=PP1V05_ENET_FET
7B6
SOT563
2
P1V05ENET_EN_L
PM_SLP_S3_L
Q3841
Q3840
1
SSM6N15FEAPE
69.8K
2
CRITICAL
D
2
S
R3841
70D8 66D5 40C5 35A5 20C3 6C3
3
P1V05ENET_SS
2
5%
1/16W
MF-LF
402
R3842 1
G
20%
10V
CERM
402
R3840
=PP3V3_S5_P1V05ENETFET
SSM6N15FEAPE
SOT563
5
1
0.1UF
AC_OR_S0_L
D
C
1.05V ENET FET
Pull-up is with power FET.
D
3
S
4
1
10K
2
G
S
1
1
2
1%
1/16W
MF-LF
402
C3841
0.01UF
2
10%
16V
CERM
402
P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
5
B
8D2
IN
G
B
=P1V05ENET_EN
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and
=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock
Ethernet & AirPort Support
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
A
SYNC_MASTER=SUMA
SYNC_DATE=07/01/2008
NOTICE OF PROPRIETARY PROPERTY
R3895
77D3 17C3
IN
MCP_CLK25M_BUF0_R
1
22
2
RTL8211_CLK25M_CKXTAL1
OUT
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
31B6 77D3
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to U1400
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
32
1
81
A
8
6
7
4
5
3
2
1
- COPY THIS PAGE FROM K36 CSA.39
D
D
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
1
C3900
0.1UF
10%
2 16V
X5R
402
1
C3901
0.1UF
10%
2 16V
X5R
402
1
C3902
C3903
1
ETHERNET CONNECTOR
0.1UF
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
CRITICAL
J3900
CRITICAL
77C3 31B3
77C3 31B3
BI
ENET_MDI_P<1>
BI
ENET_MDI_N<1>
T3901
SM
1
RJ45-M97-3
F-RT-TH
12
77C3
2
11
3
10
4
C
77C3
1% 1/16W
TLA-6T213HF
BI
ENET_MDI_P<3>
BI
ENET_MDI_N<3>
5
ENET_MDI_TRAN_N<1>
R3903
2 75
1
ENET_CENTER_TAP<1> 1
2
3
MF-LF 402
R3902
2 75
ENET_CENTER_TAP<3> 1
9
1% 1/16W
77C3 31B3
9
10
TX
77C3 31B3
ENET_MDI_TRAN_P<1>
MF-LF
4
8
6
77C3
ENET_MDI_TRAN_P<3>
7
8
6
7
77C3
ENET_MDI_TRAN_N<3>
RX
11
12
CRITICAL
77C3 31B3
77C3 31B3
C
5
402
BI
ENET_MDI_N<2>
1
BI
ENET_MDI_P<2>
2
T3902
SM
77C3
ENET_MDI_TRAN_N<2>
11
77C3
ENET_MDI_TRAN_P<2>
10 ENET_CENTER_TAP<2> 1
1% 1/16W
TX
TLA-6T213HF
9
BI
ENET_MDI_N<0>
5
77C3 31B3
BI
ENET_MDI_P<0>
6
MF-LF 402
R3900
2 75
ENET_CENTER_TAP<0> 1
1% 1/16W
77C3 31B3
514-0636
R3901
2 75
3
4
12
MF-LF 402
8
7
77C3
ENET_MDI_TRAN_N<0>
77C3
ENET_MDI_TRAN_P<0>
RX
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
1
B
1
C3911
10PF
5%
2 50V
CERM
402-1
CRITICAL
1
C3913
10PF
CRITICAL
1CRITICAL
C3912
CRITICAL
1
10PF
5%
50V
2 CERM
402-1
C3915
10PF
1
5%
50V
2 CERM
402-1
5%
2 50V
CERM
402-1
5%
50V
2 CERM
402-1
1
CRITICAL
1
C3916
10PF
5%
50V
2 CERM
402-1
C3910
B
1000PF
5%
2 50V
CERM
402-1
CRITICAL
C3914
10PF
CRITICAL
C3917
10PF
10%
2KV
2 CERM
1206
CRITICAL
CRITICAL
1
C3918
10PF
5%
50V
2 CERM
402-1
PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS
ETHERNET CONNECTOR
A
SYNC_MASTER=SUMA
SYNC_DATE=04/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
33
1
81
A
8
6
7
2
3
4
5
=PP3V3_FW_FWPHY
7 mA I/O
C4120
C4121
1
1UF
PART NUMBER
D
114S0558
QTY
1
DESCRIPTION
REFERENCE DES
RES,0.68 OHM,1%,0402,SMD
R4100
CRITICAL
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
1
10%
6.3V
CERM
402
PP1V0_FW_R
2
1
10%
6.3V
CERM
402
2
1UF
2
L4130
OMIT
1
C4131
2
10%
6.3V
CERM
402
PP3V3_FW_FWPHY_VDDA
C4132
1
1UF
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
1UF
10%
6.3V
CERM
402
2
2
L4135
120-OHM-0.3A-EMI
1
120-OHM-0.3A-EMI
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
0402-LF
1
C4110
1
10%
6.3V
CERM
402
2
1UF
2
17 mA PCIe SerDes
C4111
1UF
C4135
1
10%
6.3V
CERM
402
2
C4100
1
1UF
2
10%
6.3V
CERM
402
C4101
2
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
0402-LF
1UF
10%
6.3V
CERM
402
2
0 mA VReg PWR
1
1UF
10%
6.3V
CERM
402
PP3V3_FW_FWPHY_VP25
C4136
1UF
10%
6.3V
CERM
402
110 mA Digital Core
1
D
2
0402-LF
L4110
5%
1/16W
MF-LF
402
135 mA
2
C4124
120-OHM-0.3A-EMI
R4100
=PP1V0_FW_FWPHY
10%
6.3V
CERM
402
114 mA FireWire PHY
1UF
35D3 7A1
1
1UF
BOM OPTION
CRITICAL
C4130
0
C4123
1
1UF
2
7B1 34B1 35D8 36B6 36D5
138 mA
C4122
1
1UF
10%
6.3V
CERM
402
1
C4102
1
1UF
2
10%
6.3V
CERM
402
C4103
1
1UF
2
10%
6.3V
CERM
402
C4104
1
1UF
2
C4105
1
1UF
10%
6.3V
CERM
402
2
C4106
1UF
10%
6.3V
CERM
402
2
C4141
1
1
20%
10V
CERM
402
2
2
0.1UF
10%
6.3V
CERM
402
C4140
1UF
10%
6.3V
CERM
402
C
C
VDD10
2
5%
50V
CERM
402
R4162 1
C4162
J2
L13
D12
D1
A10
H13
K13
2
J12
NC
0.33UF
2
N13
TP_FW643_OCR10_CTL
1
470K
5%
1/16W
MF-LF
402
M13
J13
K12
L9
L6
L10
L5
D6
D5
A12
M2
L11
L3
J1
D8
NT-16 (IPD) SCIFCLK
NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
CHIP RESET
NT-5 PERST*
C41751
10%
2
16V
0.1UF
X5R 402
C41761
10%
2
16V
IN
16C3
IN
16C3
16B3 75D3
IN
16B3 75D3
PCIE_FW_D2R_N
OUT
16B6 75D3
PCIE_FW_D2R_P
OUT
16B6 75D3
X5R 402
PLACEMENT_NOTE=Place C4175 close to U4000
PLACEMENT_NOTE=Place C4176 close to U4000
=PP3V3_FW_FWPHY
C2
D13
E1
D2
L2
7B1 34D2 35D8 36B6 36D5
FW643_LDO
R4165 1
=FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
=FW_CLKREQ_L
G2
G1
H1
OUT
8C2 35C8
OUT
35C4
5%
1/16W
MF-LF
402 2
1
1
R4166
10K
5%
1/16W
MF-LF
2 402
B
R4164
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
N12
IN
1
35C1
R4163
10K
OCR_CTL_V10
OCR_CTL_V12 (Reserved)
VSS
10%
6.3V
CERM-X5R
402
X5R 402
IN
PCIE_FW_R2D_C_P
MISCELLANEOUS
2
VREG_VSS
K6
3
2
1%
1/16W
MF-LF
402
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
K10
191
G13
NAND_TREE
REXT
XO
XI NT-9
L7
4
1%
1/16W
MF-LF
402
R4170
L8
F13
R0
TPCPS
K9
1
K1
FW643_TRST_L
M1
0.1UF
PCIE_FW_R2D_C_N
5%
1/16W
MF-LF
2 402
K8
R4161 1
2.94K
2
B10
N1
N2
10%
2
16V
10K
K7
SM-3.2X2.5MM
B11
TPBIAS0
TPBIAS1
TPBIAS2
K5
Y4150
24.576MHZ
2
22PF
1
NC
NC
A2
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
2
1%
1/16W
MF-LF
402
C3
K4
1
C4151
412
BI
B7
NT-2 (IPU) TRST*
POWER MANAGEMENT
NT-12 (IPD)
NT-13
J10
CRITICAL
5%
50V
CERM
402
1
36D4
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
M3
FIXME!!! - TYPO IN SYMBOL REGCTL
J9
FW_CLK24P576M_XO
2
BI
FW643_R0
FW643_TPCPS
2
R4150
22PF
1
BI
A4
J5
C4150
36D4
36C8 35A4
B4
J4
1%
1/16W
MF-LF
402
BI
H10
200K
BI
36C4
NT-4 (IPU) TCK
NT-3 (IPU) TDI
(IPU) TDO
NT-1 (IPU) TMS
N10
X5R 402
0.1UF
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
NT-10 (IPD)
H8
R4160 1
B
36C4
N6
0.1UF
C41711
10K
H7
=PPVP_FW_PHY_CPS
A6
B2
36C4
BI
B6
N5
PCIE_FW_R2D_N
75D3 PCIE_FW_R2D_P
75D3 PCIE_FW_D2R_C_N
75D3 PCIE_FW_D2R_C_P
75D3
M4
1394 PHY
H6
78D3 36B8
BI
A9
H4
78D3 36B8
B9
G10
BI
G8
BI
G7
BI
78D3 36C4
A3
G6
36C4
78D3 36C4
B3
N7
N9
TEST CONTROLLER
G4
BI
A5
F10
36C4
B5
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
F8
BI
A8
F7
BI
78D3 36B8
B8
F6
78D3 36B8
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
N8
REFCLKN
REFCLKP
PCI EXPRESS PHY
F4
BI
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
BGA
E9
BI
78D3 36C4
E13
E5
78D3 36C4
E12
VREG_PWR
FW643E
DS0 (IPD) NT-19
DS1 (IPD) NT-20
DS2 (IPD) NT-21
E4
IN
VP25
U4100
D10
IN
36D3
F12
VP
CRITICAL
D9
36D3
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
A11
ATBUSB
ATBUSH
ATBUSN
D7
IN
A13
D4
36D3
B13
VDDH
VDD33
10%
2
16V
5%
1/16W
MF-LF
402
L12
NC
NC
NC
G12
F1
C12
C1
N11
N3
M12
L1
K2
H12
H2
E10
E2
C13
B12
B1
A1
PLACEMENT_NOTE=Place C4170 close to U1400
PLACEMENT_NOTE=Place C4171 close to U1400
C41701
FireWire LLC/PHY (FW643)
A
SYNC_MASTER=K19_MLB
SYNC_DATE=11/02/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
34
1
81
A
8
6
7
Page Notes
@ 2.5V Vgs:
- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE
- =PPVP_FW_SUMNODE (power passthru summation node)
7B5
Signal aliases required by this page:
CRITICAL
Q4291
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)
=PP3V3_S0_P3V3FWFET
35B1 7B5
R4281
1
SOT-23-HF
=PP3V3_FW_FET
2
1
R4290
BOM options provided by this page:
10K
D 3
5 G
100K
10K
35C7 35C4 35A4 18D7 18D2
IN
FW_WAKE
5
4
7C7
FWPHY_WAKE_YES
=PP3V3_S0_P1V05FWFET
DMB53D0UV
PCIE_FW_PRSNT_L
OUT
MAKE_BASE=TRUE
CRITICAL
DMB53D0UV
4
8C6 16C6
P1V0_RESET_GATE
FW_CLKREQ_L
5 G
R4283
CRITICAL
D 6
2 G
SI2312BDS
6
2 G
FW_RESET_L
S 1
R4296
P1V05_FW_EN_L
Q4293
1
5%
1/16W
MF-LF
402
D 3
P1V05_FW_EN_L_RC
34A2
1
PP1V05_FW PGOOD/FW_RESET_L
7B2
34B2
C4295
IN
=FW_CLKREQ_L
C
FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
FireWire Port Power Switch
0.068UF
100K 2
OUT
S
S 1
1
24C1
SOT-563
35D6 35C7 35A4 18D7 18D2
=PP1V0_FW_FET
5%
1/16W
MF-LF
402 2
IN
DMB53D0UV
FW_PWR_EN
2
SSM6N15FEAPE
10K
S
=FW_RESET_L
Q4299
D
SOT563
1
2
SOT23
S
R42951
10K
5%
1/16W
MF-LF
402
2 G
Q4295
G
D 6
1
SOT563
CRITICAL
D
1
16C6
SSM6N15FEAPE
3
P1V05FW_SS
OUT
S 4
Q4264
20%
10V
CERM 2
402
D
Q4299
SOT-563
D 3
0.1UF
220K 2
1
Q4293
=PP3V3_S5_P1V05FWFET
FWPHY_WAKE_YES
C
3
5
1UF
C4296 1
Q4276
7A3
5%
1/16W
MF-LF
2 402
10%
6.3V 2
CERM
402
10%
16V
CERM
402
=PP1V05_FW_P1V05FWFET
5%
1/16W
MF-LF
402
SOT-563
100K
2
P1V0_FW_RC
C4281 1
1
1.05V FW FET
Q4276
6
2 G
10K
SOT563
7B1
=FW_PME_L
2
Q4264
CRITICAL
R4297
8C2
34B2
0.01UF
P3V3FW_SS
S 4
DMB53D0UV
FWPHY_WAKE_YES
D
C4291
FW_PWR_EN
SOT-563
CRITICAL
1
SSM6N15FEAPE
3
5%
1/16W
MF-LF
402 2
100K 2
=PP1V0_FW_FWPHY
1%
1/16W
MF-LF
402
35B1
R4276
1
5%
1/16W
MF-LF
2 402
3
1
5%
1/16W
MF-LF
402
SOT563
FW_PLUG_DET_L 8C1
10%
2 16V
X5R
402
R4291
SSM6N15FEAPE
FWPHY_WAKE_YES
D
G
0.033UF
1
Q4290
C4290
1
P3V3FW_EN_L
=PP3V3_FW_FWPHY
S
R4280
7B2
34D8 7A1
5%
1/16W
MF-LF
402 2
D
=PP3V3_S0_FWPWRCTL
NTR4101P
(NONE)
R42771
1
3.3V FW FET
Power aliases required by this page:
36B6
34D2
34B1
7B1
36D5
2
3
4
5
10%
2 10V
CERM
402
SSM6N15FEAPE
SOT563
5 G
35D6 35C4 35A4 18D7 18D2
S 4
FW_PWR_EN
CRITICAL
Q4260
CRITICAL
FDC638P_G
7C1
6
=PPBUS_S5_FWPWRSW
5
4
1
R4260
Q4262
DMB54D0UV
SOT-563
100K
1
C
NOSTUFF
1
R4275
40D5
20C7
32B7
41B2
Q4261
IN
SMC_ADAPTER_EN
2
G
Q4261
D
2N7002DW-X-G
SOT-363
S
5
G
70D8 66D5 40C5 32B7 20C3 6C3
=PP3V3_FW_LATEVG_ACTIVE
36A5 PP2V4_FW_LATEVG
IN
5%
1/16W
MF-LF
2 402
FW_PWR_EN_L
4
FW_PLUG_DET
FW_DET_MIRROR
PM_SLP_S3_L
3
6
5
BC847CDXV6TXG
SOT563
2
1%
1/16W
MF-LF
2 402
FWLATEGV_3V_REF
2
4
A
R4272
3
CRITICAL
1K
6
D
5%
1/16W
MF-LF
2 402
Q4275
DMB53D0UV
LMC7211
SM-HF
1
LATEVG_EVENT
V+
P2V4_FWLATEVG_RC
U4210
35D6 35C7 35C4 18D7 18D2
IN
FW_PWR_EN
1
Q4270
BC847CDXV6TXG
SOT563
C4270
C4211
100pF
5%
50V
CERM 2
402
10%
16V
2 X5R
402
R4273
12K
5%
1/16W
MF-LF
2 402
SOT-563
2 G
FireWire Port Power
SYNC_MASTER=YUN_K19_MLB
R4213
80.6K
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
1
R4210
200K 2
1%
1/16W
MF-LF
402
SYNC_DATE=12/22/2008
NOTICE OF PROPRIETARY PROPERTY
S
1
DMB53D0UV
4
1
V-
1
1%
1/16W
MF-LF
2 402
CRITICAL
Q4275
0.1UF
5
1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
FWLATEVG Hysteresis:
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
3.08V when port power is on
2.91V when late Vg event and port power is off
36C8 34B6
IN
FW_P1_TPBIAS
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
4.7.0
051-7898
SCALE
SHT
NONE
8
8C1 35D7
FW_DET_EMIT
1
20%
2 10V
CERM
402
CRITICAL
1
FW_P1_TPBIAS_R
is running or on AC.
0.1UF
10K
5
OUT
SOT-563
Q4270
Enables port power when machine
C4210
3
SOT-363
S
4
1
FW_PLUG_DET_L
56K
5%
1/16W
MF-LF
2 402
7A3
10K
R4271
330K
5%
1/16W
MF-LF
2 402
CRITICAL
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
1
R4270
1K
3
B
R4274
1
D
R4212
7B5 35D2
1
=PP1V05_FWPWRCTL
FWPWR_EN_L
6
1
7B2
3
2
G
5
B
LATEVG_FAULT_EVENT
2N7002DW-X-G
R42111
=PPBUS_S5_FW_FET
2
3
7C7
1
36C5
1
CRS08-1.5A-30V
=PP3V3_S0_FWPWRCTL
5%
1/16W
MF-LF
2 402
1UF
10%
10V
X5R 2
402
PPBUS_FW_FWPWRSW_D
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
10%
25V
X5R 2
402
470K
1%
1/16W
MF-LF
402
C4263 1
2
R4261
S
2
1
MINISMDC110H24
1
LATEVG_FAULT_EVENT_PNP
Q1
100
1
1%
1/16W
MF-LF
402
Q2
E
4
1
10K
6
R4263
LATEVG_RETRY_RC
2
D
NOSTUFF
PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
D4260
SM
FWPWR_EN_L_DIV
R4265
B
1.1A-24V
0.1UF
5%
1/16W
MF-LF
2 402
Late-VG Event Detection
2
C4260 1
300K
CRITICAL
CRITICAL
F4260
SM
OF
35
1
81
A
8
Page Notes
6
7
2
3
4
5
1
Power aliases required by this page:
36B6 35D8 34D2 34B1 7B1
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
=PP3V3_FW_FWPHY
R4382 1
R4380 1
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
10K
- =GND_CHASSIS_FW_PORT1
- =GND_CHASSIS_FW_EMI_R
D
10K
FWPHY_DS0
FireWire PHY Config Straps
Signal aliases required by this page:
(NONE)
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
FWPHY_DS2
Configures PHY for:
FWPHY_DS1
- 1-port Portable Power Class (0)
34C6
R4381 1
- Port "1" Bilingual (1394B)
10K
1%
1/16W
MF-LF
402 2
34B6
34B6
78D3 34C6
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)
78D3 34B6
34B6
34B6
78D3 34B6
Termination
78D3 34B6
34B6
34B6
=PPVP_FW_PHY_CPS_FET
5%
1/16W
MF-LF
402 2
NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Cable Power
PPVP_FW_CPS
MAKE_BASE=TRUE
=PPVP_FW_PHY_CPS
CRITICAL
34B7
L4310
7B1
FERR-250-OHM
=PPVP_FW_PORT1
1
"Snapback" & "Late VG" Protection
5
470K
FW_P0_TPB_N
FW_P0_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
G
R4311 1
NC_FW0_TPBIAS
NC_FW2_TPBIAS
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW2_TPAN
NC_FW2_TPAP
C
D
7B1
4
2
10%
6.3V
CERM-X5R
402
S
0.33UF
3
C4360
BSS8402DW
SOT-363
1
(SYM-VER2)
TI PHYs require 1uF even though
FW spec calls out 0.33uF
FW_P0_TPBIAS
FW_P2_TPBIAS
FW_P0_TPA_N
FW_P0_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
Q4300
Place close to FireWire PHY
C
D
34C6
=FW_PHY_DS1
MAKE_BASE=TRUE
NOTE: FireWire TPA/TPB pairs are NOT
constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
FW_P1_TPBIAS
34C6
=FW_PHY_DS2
MAKE_BASE=TRUE
BOM options provided by this page:
(NONE)
35A4 34B6
=FW_PHY_DS0
MAKE_BASE=TRUE
36A5 35A8
SM
PP2V4_FW_LATEVG
1
R4360
R4361
56.2
2
78D3 34B6
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPS_EN_L
2
C4310
FW_PORT1_TPA_P
78D3 34B6
FW_P1_TPA_N
FW_PORT1_TPA_N
78D3 34B6
FW_P1_TPB_P
FW_PORT1_TPB_P
10%
50V
X7R
402
D
36B5
MAKE_BASE=TRUE
FW_PORT1_TPB_N
1
=PP3V3_FW_FWPHY
2
G
PORT 1
3
BILINGUAL
4
S
36B5
CRITICAL
6
J4310
1394B-M97
F-RT-TH
BSS8402DW
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4362
10%
50V
X7R
402
1
36B7
SOT-363
FW_PORT1_TPB_N
9
(FW_PORT1_BREF)
36B7
1
FW_PORT1_TPB_P
NC
36B7 FW_PORT1_TPA_N
FW_PORT1_AREF
220pF
2
5%
25V
CERM
402
DP4311
C4319
CRITICAL
2
10%
50V
X7R
402
10%
50V
X7R
603-1
BAV99DW-X-G
6
1
0.01uF
INPUT
TPA(R)
TPA+
SOT-363
1
11
1
CHASSIS
GND
12
0.1uF
DP4311
4.99K
C4312
TPA<R>
TPA+
10
SOT-363
1%
1/16W
MF-LF
402 2
VG
5
BAV99DW-X-G
R4364 1
B
NCSC/NC
TPA- TPAVG
4
FW_PORT1_TPB_C
C4364
7
3
FW_PORT1_TPA_P
OUTPUT
VP
6
(GND_FW_PORT1_VG)
1%
1/16W
MF-LF
402 2
36B7
1
TPB<R>
8
56.2
1%
1/16W
MF-LF
2 402
TPB(R)
TPB-
TPB+ TPB+
VP
2
R4363 1
56.2
TPB-
1
(SYM-VER1)
MAKE_BASE=TRUE
B
CRITICAL
2
2
Q4300
36B5
36D5 35D8 34D2 34B1 7B1
5
2
SOT-363
1
0.01uF
6
36B5
MAKE_BASE=TRUE
FW_P1_TPB_N
2
PPVP_FW_PORT1_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V
BAV99DW-X-G
MAKE_BASE=TRUE
78D3 34B6
10%
50V
X7R
402
DP4310
2
FW_P1_TPA_P
1
330K
1
56.2
1%
1/16W
MF-LF
402
C4311
0.01uF
R4312 1
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
BAV99DW-X-G
SOT-363
C4314
Note: Trace PPVP_FW_PORT1 must handle up to 5A
0.01UF
DP4310
CPS_EN_L_DIV
2
13
2
5
2
C4313
10%
50V
X7R
402
3
1
0.01uF
1
2
R4319
1M
4
2
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
AREF needs to be isolated from all
local grounds per 1394b spec
514S0605
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
Late-VG Protection Power
A
7A3
=PP3V3_FW_LATEVG
R4390
1
332
FireWire Ports
SYNC_MASTER=K19_MLB
PP2V4_FW_LATEVG
1%
1/16W
MF-LF
402
3
CRITICAL
D4390
NOTICE OF PROPRIETARY PROPERTY
ESD and late-VG rail
for snap-back diodes
(Common to all ports)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MMBZ5227BLT1H
PP2V4_FWLATEVG needs to be biased
to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4390 should be 390 Ohms max for a 3.3V rail
SYNC_DATE=11/02/2008
35A8 36C5
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.4V
2
II NOT TO REPRODUCE OR COPY IT
SOT23
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
36
1
81
A
8
6
7
2
3
4
5
1
CRITICAL
Q4590
ODD Power Control
6C3 6B7
=PP3V3_S0_ODD
D
1
100K
100K
5%
1/16W
MF-LF
402
Q4596
10%
2 10V
CERM
402
R4595
ODD_PWR_EN_LS5V_L
1
D
4
0.068UF
5%
1/16W
MF-LF
402
R4597
C4595
G
R4596
100K 2
C4596
0.01UF
ODD_PWR_SS
1
5%
1/16W
MF-LF
402
D 6
5 6
S
7
37C7 7C5
1
2
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.
PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V
8
=PP5V_S3_ODD
3
7C3
TPCP8102
23V1K-SM
D
2
10%
16V
CERM
402
SSM6N15FEAPE
SOT563
ODD_PWR_EN
Q4596
2 G
D 3
S 1
SSM6N15FEAPE
SOT563
5 G
20B3
IN
S 4
ODD_PWR_EN_L
CRITICAL
SATA ODD
FL4520
DLP11S
SYM_VER-1
4 75A3 SATA_ODD_R2D_UF_P
3
2
J4500
1 75A3 SATA_ODD_R2D_UF_N
54722-0164
=PP3V3_S0_ODD
R45901
33K
5%
1/16W
MF-LF
402 2
2
1
4
3
1
19D6 75A3
C4520
SATA_ODD_R2D_C_N
IN
19D6 75A3
2
10% 16V CERM 402
C
6
5
8
7
10
9
75A3 6B7
12
11
75A3 6B7
14
13
16
15
SATA_ODD_R2D_P
6A7 SATA_ODD_R2D_N
75A3 6B7
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
FL4525
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
C4526 1
0.01UF
C4525 1
0.01UF
90-OHM-100MA
DLP11S
SYM_VER-1
2
75A3 SATA_ODD_D2R_UF_N
10% 16V CERM 402
4
2
75A3 SATA_ODD_D2R_UF_P
10% 16V CERM 402
1
CRITICAL
3
SATA_ODD_D2R_N
2
SATA_ODD_D2R_P
OUT
19D6 75A3
OUT
19D6 75A3
PLACEMENT_NOTE=Place FL4525 close to J4500
Indicates disc presence
1
SATA HDD/IR/SIL
B
IN
75A3 6B7
SMC_ODD_DETECT
OUT
SATA_ODD_R2D_C_P
PLACEMENT_NOTE=Place FL4520 close to J4500
516S0616
40B8 6B7
C4521
2
10% 16V CERM 402
0.01UF
F-ST-SM
37D6 7C5
1
0.01UF
CRITICAL
C
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
90-OHM-100MA
C4501
1
0.1UF
20%
2 10V
CERM
402
C4502
0.1UF
CRITICAL
L4500
20%
2 10V
CERM
402
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
B
FERR-70-OHM-4A
6C3 6B7
PP5V_S0_HDD_FLT
1
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
=PP5V_S0_HDD
2
7D5
0603
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
CRITICAL
FL4502
90-OHM-100MA
L4502
CRITICAL
FERR-220-OHM
7D3
1
=PP1V5_S3_HDD
2
PP1V5_S3_HDD_FLT
0402
1
C4503
1UF
R4531
39D7 7C3
SYS_LED_ANODE
=PP5V_S3_IR
2
R4532
2
402
10
5%
MF-LF
75A3 6B7
4.7
1
402
5% 1/16W
MF-LF
1
1/16W
SYS_LED_ANODE_R
IR_RX_OUT
6A7
39D4
6A7 PP5V_S3_IR_R
6A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
75A3 6B7
SATA_HDD_D2R_C_P
C4532
1
0.1UF
2
10%
16V
X7R-CERM
402
4
SATA_HDD_D2R_N
3
OUT
19D6 75A3
OUT
19D6 75A3
2
SATA_HDD_R2D_C_N
10% 16V CERM 402
IN
19D6 75A3
2
SATA_HDD_R2D_C_P
10% 16V CERM 402
IN
C4516 1
2
1
2
75A3 SATA_HDD_D2R_UF_P
SATA_HDD_D2R_P
10% 16V CERM 402
0.01UF
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516
PLACEMENT_NOTE=Place C4516 close to J4501
CRITICAL
FL4501
90-OHM-100MA
PLACEMENT_NOTE=Place C4511 next to C4510
PLACEMENT_NOTE=Place C4510 close to MCP79
DLP11S
SYM_VER-1
75A3 6B7
SATA_HDD_R2D_N
3
4
75A3
SATA_HDD_R2D_UF_N
C4511 1
0.01UF
75A3 6B7
1
2
75A3 SATA_HDD_D2R_UF_N
10% 16V CERM 402
0.01UF
SATA_HDD_R2D_P
2
1
75A3
SATA_HDD_R2D_UF_P
PLACEMENT_NOTE=Place FL4501 close to J4501
516S0687
A
DLP11S
SYM_VER-1
C4515 1
SATA_HDD_D2R_C_N
54722-0224
F-ST-SM
10%
2 6.3V
CERM
402
PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501
41A6
J4501
C4510 1
0.01UF
SATA Connectors
SYNC_MASTER=K19_MLB
C4531
SYNC_DATE=12/04/2008
NOTICE OF PROPRIETARY PROPERTY
0.001UF
2
10%
50V
CERM
402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
37
1
81
A
8
6
7
2
3
4
5
1
D
D
Port Power Switch
USB PORT A (FRONT PORT)
PLACEMENT_NOTE=NEAR J4600
CRITICAL
CRITICAL
L4605
U4690
2
OUT
USB_EXTA_OC_L
8
OUT
USB_EXTB_OC_L
7C3
19C2
19C2
TPS2064DGN
IN
OUT1
FERR-220-OHM-2.5A
7
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
MSOP
OC1*
3
OUT2
EN1
5 OC2*
4
EN2
1
PP5V_S3_RTUSB_A_ILIM
6
C4605
PP5V_S3_RTUSB_B_ILIM
0.01uF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
20%
16V
CERM
402
2
1
C4690
1
1
10UF
20%
6.3V
X5R
603
2
2
1
10UF
20%
10V
CERM
402
20%
6.3V
X5R
603
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
J4600
PLACEMENT_NOTE=NEAR J4600
CRITICAL
USB
F-RT-TH-M97-4
5
L4600
90-OHM
6
SYM_VER-1
CRITICAL
C4695
0.1UF
CRITICAL
DLP0NS
9
C4691
1
C4696
100UF
2
20%
2 6.3V
POLY-TANT
CASE-B2-SM
CRITICAL
C4617
1
10UF
20%
6.3V
X5R
603
1
USB_EXTA_MUXED_N
4
3
76C3
CONN_USB_EXTA_N
USB_EXTA_MUXED_P
1
2
76C3
CONN_USB_EXTA_P
20%
2 6.3V
POLY-TANT
CASE-B2-SM
76C3
3
4
2
5
3
4
7
8
514-0638
1 GND
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
=USB_PWR_EN
IN
1
2
C4616
100UF
2
76C3
6 VBUS
66B6
C
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
1
GND TPAD
NOSTUFF
2
0603
NC
IO
NC
IO
C
=PP5V_S3_EXTUSB
D4600
RCLAMP0502N
SLP1210N6
STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE)
STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)
PLACEMENT_NOTE=NEAR J4610
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1
2
0603
1
USB/SMC Debug Mux
B
0.01uF
2
7D1
C4615
20%
16V
CERM
402
CRITICAL
=PP3V42_G3H_SMCUSBMUX
J4610
USB
SMC_DEBUG_YES
C4650
1
1
10K
0.1UF
2
2
42C3 41B2 40C5 40B8
42C5 41C2 40C5 40B8
IN
DLP0NS
OUT
5 M+
4 M-
USB_EXTA_P
USB_EXTA_N
7 D+
6 D-
76B3 19C3
U4650
1
SYM_VER-1
BI
VCC
SMC_DEBUG_YES
SMC_RX_L
SMC_TX_L
6
L4610
90-OHM
5%
1/16W
MF-LF
402
9
20%
10V
CERM
402
F-RT-TH-M97-4
5
PLACEMENT_NOTE=NEAR J4610
CRITICAL
R4650
USB_EXTB_N
4
3
76B3
76B3
Y+ 1
Y- 2
76B3 19C3
BI
USB_EXTB_P
1
76C3 19D3
BI
BI
6 VBUS
CRITICAL
SEL 10
USB_DEBUGPRT_EN_L
5
3
4
8
514-0638
1 GND
IN
40B8
SEL=0 Choose SMC
SEL=1 Choose USB
D4610
3
GND
3
7
2
TQFN
8 OE*
2
4
2
PI3USB102ZLE
76C3 19D3
CONN_USB_EXTB_N
CONN_USB_EXTB_P
NC
IO
NC
IO
B
Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
RCLAMP0502N
SLP1210N6
A
External USB Connectors
CRITICAL
SMC_DEBUG_NO
SYNC_MASTER=YUAN.MA
R4651
1
0
5%
1/16W
MF-LF
402
USB PORT B (BACK PORT)
SMC_DEBUG_NO
R4652
1
0
SYNC_DATE=01/18/2008
NOTICE OF PROPRIETARY PROPERTY
2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
2
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5%
1/16W
MF-LF
402
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
38
1
81
A
8
6
7
4
5
3
2
1
37A8 7C3 =PP5V_S3_IR
1
C4801
0.1UF
2
10%
16V
X7R-CERM
402
D
16
D
76B3 19D3
BI
76B3 19D3
BI
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_P
14
USB_IR_N
15
DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
18
20
1
C4803
1UF
2
10%
10V
X5R
402-1
23
24
25
26
P1_0/D+
P1_1/DP1_2/VREG
P1_3/SSEL
P1_4/SCLK
P1_5/SMOSI
P1_6/MISO
P1_7
VDD
P0_0
P0_1
P0_2/INT0
P0_3/INT1
P0_4/INT2
P0_5/TIO0
P0_6/TIO1
P0_7
7
6
5
4
R4800
3
2
1
IR_RX_OUT_RC
1
32
U4800
21
22
P3_0
P3_1
CY7C63833
QFN
CRITICAL
OMIT
P2_0
P2_1
10
2
IR_RX_OUT
IN
6A7 37A7
C4804
0.001UF
10%
50V
CERM
402
11
28
29
1
8
2
P/N 338S0375
27
9
100
5%
1/16W
MF-LF
402
NC
NC
12
17
30
19
31
13
33
THRM_PAD VSS
C
C
CYPRESS ’ENCORE II’ USB CONTROLLER
B
B
Front Flex Support
A
SYNC_MASTER=YUAN.MA
SYNC_DATE=05/28/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
39
1
81
A
8
6
7
2
3
4
5
1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
41C6 6C2
41D8 41C7 41C3 41C1 7D1
D
PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC
D
C4902
1
1
20%
6.3V
CERM
805
2
2
22UF
IN
20B7
OUT
62C7
OUT
20C7
OUT
PM_RSMRST_L
IMVP_VR_ON
PM_PWRBTN_L
41D5
OUT
ESTARLDO_EN
41D5
41D5
SMC_P24
SMC_P26
NC
NC
NC
NC
NC
NC
C
76C3 42D5 18B3
BI
76C3 42D5 18B3
BI
76C3 42D3 18B3
BI
76C3 42D3 18B3
BI
76C3 42D5 18C3
IN
24D1
IN
76C3 24B1
42D3 18B7
IN
BI
P10
P11
P12
P13
P14
P15
P16
P17
D13
E11
D12
F11
E13
E12
F13
E10
P20
P21
P22
P23
P24
P25
P26
P27
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ
SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L
A9
D9
C8
B7
A8
D8
D7
D6
NC
41D5
43B5
50B7
BI
OUT
41D5
OUT
49A6
OUT
42C5 41C2 40C5 38A8
OUT
42C3 41B2 40C5 38A8
43D6
(DEBUG_SW_1)
(DEBUG_SW_2)
SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK
SMC_PA0
SMC_PA1
PM_SYSRST_L
OUT
USB_DEBUGPRT_EN_L
OUT
MEM_EVENT_L
BI
41A2 SMC_PA5
SYS_ONEWIRE
BI
PM_BATLOW_L
OUT
NC
NC
(OC)
38A6
58D5
20C7
P40
P41
P42
P43
P44
P45
P46
P47
G2
F3
E4
P50
P51
P52
NC
41B2
41C6
IN
41B2
IN
OUT
37C7 6B7
47B5
OUT
41D5
OUT
41D5
OUT
41D5
OUT
47C5
IN
41B2
IN
41B2
IN
41B2
IN
50B4
IN
50B4
IN
50B4
IN
41C5
IN
41D5
IN
41D5
IN
41D5
IN
41C5
IN
SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L
NC
OMIT
N3
N1
M3
M2
N2
L1
K3
L2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
B8
C9
B9
A10
C10
B10
C11
A11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
IN
41C5 SMC_PB3
(See below)
SMC_EXCARD_CP
IN
20C7
A
D4
A5
B4
A1
C2
B2
C1
C3
41C2
27A5 26A5 20B3 20A4
LGA-HF
(1 OF 3)
P30
P31
P32
P33
P34
P35
P36
P37
41C2
24B3
B
IN
BI
SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED
(OC)
H8S2117
SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH
G11
G13
F12
H13
G10
G12
H11
J13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT
M10
N9
K10
L8
M9
N8
K9
L7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
U4900
H8S2117
LGA-HF
(2 OF 3)
OMIT
L13
K12
K11
J12
K13
J10
J11
H12
P70
P71
P72
P73
P74
P75
P76
P77
N10
M11
L10
N11
N12
M13
N13
L12
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
P80
P81
P82
P83
P84
P85
P86
A7
B6
C7
D5
A6
B5
C6
SMC_WAKE_SCI_L
P90
P91
P92
P93
P94
P95
P96
P97
J4
G3
H2
G1
H4
G4
F4
F1
PE0
PE1
PE2
PE3
PE4
PF0
K1
J3
K2
J1
K4
K5
PF1
PF2
PF3
PF4
PF5
PF6
PF7
N5
M6
L5
M5
N4
L4
M4
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
M8
N7
K8
K7
K6
N6
M7
L6
PH0
PH1
PH2
PH3
PH4
PH5
E2
F2
J2
A4
B3
C4
NC
NC
NC
NC
NC
20%
10V
CERM
402
2
0.1UF
C4906
0.1UF
20%
10V
CERM
402
PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1
SMC_PM_G2_EN
P60
P61
P62
P63
P64
P65
P66
P67
2
1
OUT
6C3 60C5 66D8
SMC_VCL
R4999
1
SMC_ADAPTER_EN
OUT
SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
(OC)
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK
(OC)
SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA
41D1
IN
6A7 58C4
IN
45B1
IN
44D6
IN
41B2
IN
41D5
IN
45B1
IN
44B4
IN
45A4
IN
41B2
OUT
20C7
18B7 42D5
18C3 42D3
OUT
38A8 40B8 41C2 42C5
IN
38A8 40B8 41B2 42C3
SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
C4920
1
20%
10V
CERM
402
2
AVCC
VCC
VCL AVREF
U4900
NC
E5
MD1
MD2
D1
H1
NMI
E3
ETRST
H3
AVSS
L9
H8S2117
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PINS M12
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PINS M12
IN
1
10%
6.3V
CERM-X5R
402
2
R4909 1
SMC_RESET_L
D3
RES*
SMC_XTAL
SMC_EXTAL
A3
A2
XTAL
EXTAL
5%
1/16W
MF-LF
402 2
IN
41B2 41D5 58D2
IN
41B2
IN
6C3 20C3 32B7 35A5 66D5 70D8
IN
6C3 20C3 41A2 66C8
IN
41A2
IN
24B1 76A3
NOTE: P94 and P95 are shorted, P95 could be spare.
1
R4902
10K
5%
1/16W
MF-LF
2 402
SM
1
R4998
10K
5%
1/16W
MF-LF
2 402
XW4900
2
10K
SMC_MD1
IN
42C5
SMC_NMI
IN
42C3
SMC_TRST_L
IN
42D5
C
NO STUFF
1
43B5
41A3 41C2 41C7 48C3
R4901
SMC_KBC_MDE
VSS
IN
1
10K
NC
LGA-HF
(3 OF 3)
OMIT
42D3 41D6
C4907
0.47UF
0.1UF
41A6
IN
BI
PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
41A6
OUT
BI
2
5%
1/16W
MF-LF
402
20C7 32B7 35B5 41B2
IN
4.7
E1
IN
66B1
B12
A13
A12
B13
D11
C13
C12
D10
20%
10V
CERM
402
0.1UF
C4905
L11
66A4 24B8
SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD
RSMRST_PWRGD
2
1
B1
M1
H10
OUT
20%
10V
CERM
402
0.1UF
C4904
M12
OUT
1
D2
L3
F10
B11
C5
41D5
41D5
U4900
C4903
R4903
0
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
1
GND_SMC_AVSS
41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7
43D6
IN
41B2
IN
41B2 42D3
IN
41B2 42D3
OUT
41B2 42D5
IN
41B2 42D5
B
NC
NC
NC
SMC_SYS_LED
SMC_LID
OUT
SMC_MCP_SAFE_MODE
OUT
41C4
IN
41C6
IN
41A8
41C2 48A5 58C1
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN
BI
43C6
BI
43C6
BI
43D3
BI
43D3
BI
43C3
BI
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
43C3
OUT
41C2
OUT
41C2
OUT
41C5
41C2
NC
NC
SMC
SYNC_MASTER=T18_MLB
SYNC_DATE=06/26/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SMC_PB3:
II NOT TO REPRODUCE OR COPY IT
SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
40
1
81
A
8
6
7
2
3
4
5
1
SMC FSB to 3.3V Level Shifting
=PP3V3_S0_SMC
41A1 7C5
40A8
SMC_FAN_1_CTL
40A8
SMC_FAN_2_CTL
40A8
SMC_FAN_3_CTL
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
R5061
40C8
SMC_GFX_THROTTLE_L
SMC_IG_THROTTLE_L
40C8
ESTARLDO_EN
10K
5%
1/16W
MF-LF
5%
1/16W
MF-LF
2 402
20A4 20B3
MAKE_BASE=TRUE
41C7 41C3 41C1 40D4 7D1 =PP3V3_S5_SMC
1
100K
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect
R5060
1
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
2 402
58D2 41B2 40C5
SMC_BC_ACOK
=CHGR_ACOK
CPU_PROCHOT_BUF
59C5
D
C5000
1
1
0.1uF
20%
10V
CERM
402
U5000
2
NCP303LSN
SOT23-5-HF
5
SMC_MANUAL_RST_L
NOSTUFF
R5001
2
CD
NC
GND
1
C5001
0
SILK_PART=SMC_RST
4
NC
2
OUT
IN
1
40C8
SMC_P24
40C8
SMC_P26
TP_SMC_P24
SMC_BMON_MUX_SEL
40C8
SMC_P41
TP_SMC_P41
10%
16V
CERM
402
R5062
TO CPU
MAKE_BASE=TRUE
SMC_RESET_L
40A8
SMC_NB_CORE_ISENSE
40A8
SMC_NB_DDR_ISENSE
SMC_MCP_CORE_ISENSE
45D7
73C3 62C8 13B6 9C5
BI
MAKE_BASE=TRUE
40C3 42D3
OUT
2
SMC_MCP_DDR_ISENSE
CPU_PROCHOT_L
40A8
ALS_LEFT
SMC_CPU_FSB_ISENSE
Q5032
D
SMC_GPU_VSENSE
40D8
SMC_EXCARD_PWR_EN
SSM6N15FEAPE
41D8 41C3 41C1 40D4 7D1 =PP3V3_S5_SMC
5
1
40D8
SMC_RSTGATE_L
40B8
SMC_PB3
SOT-563
S
1
SOT563
TP_SMC_RSTGATE_L
G 2
1 S
SMC_PROCHOT
NC_SMC_PB3
4
U5001
40A5
ALS_GAIN
40A8
SMC_ANALOG_ID
40A8
ALS_RIGHT
40A5
IN
MAKE_BASE=TRUE
NC_ALS_GAIN
MAKE_BASE=TRUE
NC_SMC_ANALOG_ID
MAKE_BASE=TRUE
SOT553-5
2
SMC_ONOFF_L
48C3 41C2 41A3 40C5
S
SN74LVC1G02
4
DMB53D0UV
4
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
G
CPU_PROCHOT_L_R
SOT-563
2 G
Q5060
MAKE_BASE=TRUE
SOT563
5
D
Q5060
SSM6N15FEAPE
44D6
MAKE_BASE=TRUE
3
3
5
Q5059
6 D
45B5
SMC_MCP_VSENSE
40C5
3.3K 2
5%
1/16W
MF-LF
402
45C5
MAKE_BASE=TRUE
2
48B1 SMC_TPAD_RST_L
1
MAKE_BASE=TRUE
3
40D5
DMB53D0UV
45A5
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
0.01UF
5%
1/10W
MF-LF
603
D
MAKE_BASE=TRUE
R5000
1K
CRITICAL
OUT
6
MAKE_BASE=TRUE
1
TO SMC
SMC_PROCHOT_3_3_L
NC_ESTARLDO_EN
MAKE_BASE=TRUE
SMC_TPAD_RST
73B3 13B7 9C6
OUT
PM_THRMTRIP_L
NC_ALS_RIGHT
MAKE_BASE=TRUE
02
3
=PP3V3_S5_SMC
3
D
7D1 40D4 41C1 41C7
41D8
Q5059
SSM6N15FEAPE
SOT563
R5095
40B8
OUT
SMC_EXCARD_OC_L
0
1
SMC AVREF Supply
C
40B5
OUT
=SMC_SMS_INT
REF3333
PP3V3_S5_AVREF_SMC
SOT23-3
1
IN
OUT
2
EXCARD_OC_L
IN
10K
19C2
5%
1/16W
MF-LF
4
S
SMS_INT_L
IN
40A5
C
6C2 40D4
41D8 41C7 41C3 40D4 7D1
=PP3V3_S5_SMC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
2
1
3
C5026
0.01UF
2
2
5
IN
GND
1
G
SMC_THRMTRIP
2 402
MAKE_BASE=TRUE
VR5020
=PPVIN_S5_SMCVREF
R5010
5%
1/16W
MF-LF
402
CRITICAL
7D1
1
C5020
C5025
0.47UF
10uF
10%
6.3V
CERM-X5R
402
20%
6.3V
X5R
603
40B8
SMC_PA0
40B8
SMC_PA1
R5091
R5092
100K
1
2
100K
1
2
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
10%
16V
CERM
402
1
RADAR 5925345
1
2
SMC_LID
R5070
R5071
10K
58C1 48A5 40B5
100K
1
2
40A5
SMC_PH2
R5072
10K
1
2
48C3 41C7 41A3 40C5
2
R5011
20C3
GND_SMC_AVSS
MCP_SPKR
0
1
40C2 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7
2
SMC_MCP_SAFE_MODE
42C5 40C5 40B8 38A8
IN
40B5
42C3 40C5 40B8 38A8
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
SMC_ONOFF_L
R5073
R5074
SMC_TX_L
SMC_RX_L
10K
1
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
1
2
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
42D5 40B5
SMC_TMS
R5077
10K
1
2
42D5 40B5
SMC_TDO
10K
1
2
42D3 40B5
SMC_TDI
R5078
R5079
10K
1
2
42D3 40B5
SMC_TCK
R5080
10K
1
2
SMC_BC_ACOK
R5087
R5050
470K
1
2
TABLE_ALT_ITEM
353S1381
353S1912
ALL
ISL60002-33, INTERSIL
58D2 41D5 40C5
40B8
B
System (Sleep) LED Circuit
7C3
R5031
1
1
523
1%
1/16W
MF-LF
402
R5030
2
2
R5076
100K
1
2
40A8
R5051
10K
1
2
40A8
SMC_FAN_2_TACH
1
2
SMC_FAN_3_TACH
R5052
R5053
10K
40A8
10K
1
2
40C5
SMC_GPU_ISENSE
R5054
10K
1
2
40C5
SMC_NB_MISC_ISENSE
R5055
10K
1
2
40B8
R5085
R5086
SMC_ADAPTER_EN
SMC_CASE_OPEN
R5088
SMC_EXCARD_CP
40C3
SMC_XTAL
1
Y5010
5X3.2-SM
2
SOD
2SA2154MFV-YAE
SYS_LED_L_VDIV
Q5030
1
1
40C3
SMC_EXTAL
SYS_LED_ANODE
1%
1/16W
MF-LF
402 2
SMC_ONOFF_L
OUT
NOSTUFF
1
C5011
15pF
1
SILK_PART=PWR_BTN
2
R5015
40C5
NOSTUFF
1
R5016
0
0
5%
1/10W
MF-LF
603
5%
1/10W
MF-LF
603
2
40C5 41C2 41C7 48C3
2
66C8 40C5 20C3 6C3
10K
1
2
10K
1
2
100K
1
37A8
2
PM_SLP_S4_L
=PP3V3_S0_SMC
41D3 7C5
SILK_PART=PWR_BTN
R5089
SMC_PA5
10K
1
2
5%
1/16W
MF-LF
402
SMC Support
Q5032
SYNC_MASTER=YUAN.MA
D
SYNC_DATE=05/28/2008
NOTICE OF PROPRIETARY PROPERTY
6
SSM6N15FEAPE
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
SOT563
IN
2
PLACE R5015,R5001 ON BOTTOM SIDE
PLACE R5016 ON TOP SIDE
40B8
OUT
R5090
PM_SLP_S5_L
SYS_LED_L
40B5
1
5%
50V
CERM
402
3
1.47K
1
20.00MHZ
CRITICAL
2
5%
50V
CERM
402
CRITICAL
2
A
10K
B
15pF
1%
1/16W
MF-LF
402
SYS_LED_ILIM
R5032
2
SMC_FAN_1_TACH
40B5
C5010
20
1
SMC_BS_ALRT_L
40D5 35B5 32B7 20C7
Debug Power "Button"
10K
40C5
=PP5V_S3_SYSLED
SMC Crystal Circuit
SMC_GFX_OVERTEMP_L
SMC_SYS_LED
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2
G
S
II NOT TO REPRODUCE OR COPY IT
1
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
41
1
81
A
8
6
7
3
4
5
2
1
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
D
42C8 42C7 7D1
7D5
76C3 40C8 18B3
BI
76C3 40C8 18B3
BI
76A3 42C5
76A3 42B5
76C3 40C8 18C3
40C5 18B7
41B2 40B5
Alternate SPI ROM Support
41C2 40C5 40B8 38A8
42D5 42C8 7D1
=PP3V3_S5_LPCPLUS
10K
C
76A3 42A5 20B3
IN
IN
OUT
IN
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
D
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO
IN
24B1 76C3
BI
18B3 40C8 76C3
BI
18B3 40C8 76C3
OUT
42B7
IN
42C5 76A3
IN
42B5
BI
18B7 40C8
IN
18C3 40C5
OUT
40B5 41B2
OUT
40B5 41B2
OUT
40C3 41D6
OUT
40C1
OUT
38A8 40B8 40C5 41B2
OUT
17B7
C5114
516S0573
20%
10V
402
2 CERM
9
LPCPLUS
5%
1/16W
MF-LF
402 2
SPI_CLK_R
OUT
0.1UF
R51901
IN
IN
OUT
1
LPCPLUS
=PP3V3_S5_ROM
1
76A3 42A5 20B3
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L
IN
OUT
OUT
40C1
51C6 42B5 7A3
LPC_AD<0>
LPC_AD<1>
IN
40C1
M-ST-SM
31
32
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
VCC
1 Y+
2 Y-
SPI_MOSI_R
U5110
M+ 5
M- 4
PI3USB102ZLE
TQFN
R51911
10K
CRITICAL
5%
1/16W
MF-LF
402 2
10 SEL
D+ 7
D- 6
SPI_ALT_CLK
SPI_ALT_MOSI
OUT
42D3 76A3
OUT
42D5 76A3
SPI_CLK_MUX
SPI_MOSI_MUX
OUT
42A8 51C6
OUT
42A8 51C3
C
OE* 8
3
GND
SEL HIGH OUTPUTS TO D (ON BOARD ROM)
SEL LOW OUTPUTS TO M (FRANKCARD ROM)
=PP3V3_S5_LPCPLUS
42D5 42C7 7D1
LPCPLUS
1
R5140
100K
76A3 42A5 20B3
5%
1/16W
MF-LF
402 2
20C7
76A3 20B3
OUT
IN
1 Y+
2 Y-
9
U5120
SPI_ALT_MISO
M+ 5
M- 4
TQFN
10 SEL
MAKE_BASE=TRUE
R5144
1
42A8 51C3
OUT
51C6
=PP3V3_S5_ROM
B
7A3 42C7 51C6
5%
1/16W
MF-LF
402 2
R5146
0
IN
20K
LPCPLUS_NOT
1
42D5 76A3
SPI_MLB_CS_L
OE* 8
GND
3
B
SPI_MISO_MUX
D+ 7
D- 6
CRITICAL
SPIROM_USE_MLB
IN
Pull-up on debug card
SPI_ALT_CS_L OUT 42D3
PI3USB102ZLE
=SPI_CS1_R_L_USE_MLB
BI
20%
10V
402
2 CERM
VCC
1
SPI_MISO
SPI_CS0_R_L
C5124
0.1UF
LPCPLUS
2
5%
PLACEMENT_NOTE=PLACE NEXT TO U1400
1/16W
MF-LF
402
SPI MUX BYPASS
LPCPLUS_NOT
R5156
51C6 42C5
OUT
SPI_CLK_MUX
1
0
2
5%
1/16W
MF-LF
402
51C3 42C5
OUT
SPI_MOSI_MUX
1
LPCPLUS_NOT
R5158
51C3 42B5
IN
SPI_MISO_MUX
1
0
SPI_CLK_R
IN
20B3 42C8 76A3
SPI_MOSI_R
IN
20B3 42C7 76A3
OUT
20B3 42B7 76A3
LPCPLUS_NOT
R5157
0
2
5%
1/16W
MF-LF
402
SPI_MISO
2
LPC+SPI Debug Connector
5%
1/16W
MF-LF
402
A
SYNC_MASTER=CHANGZHANG
SYNC_DATE=05/09/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
42
1
81
A
8
6
7
MCP79 SMBUS "0" CONNECTIONS
D
7C5
7C5
R5200 1
1K
U1400
(MASTER)
20C3 12B6
76B3
20C3 12B6
76B3
SMC "0" SMBus Connections
=PP3V3_S0_SMBUS_MCP_0
MCP79
5%
1/16W
MF-LF
402 2
SMBUS_MCP_0_CLK
1
R5201
1K
5%
1/16W
MF-LF
2 402
2
3
4
5
SO-DIMM "A"
SMC
J3100
(Write: 0xA0 Read: 0xA1)
U4900
(MASTER)
SMC "A" SMBus Connections
7D3
1
4.7K
=I2C_SODIMMA_SCL
26A5
40B8
SMB_0_S0_CLK
79D3
=I2C_SODIMMA_SDA
26A5
40C5
SMB_0_S0_DATA
79D3
MAKE_BASE=TRUE
R5251
4.7K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMBUS_SMC_0_S0_SCL
=PP3V3_S3_SMBUS_SMC_A_S3
R5270 1
MCP Temp
SMC
EMC1403-5: U5535
(Write: 0x98 Read: 0x99)
U4900
(MASTER)
MAKE_BASE=TRUE
=I2C_MCPTHMSNS_SCL
46B3
40A5
SMB_A_S3_CLK
79D3 6D5 6C5
=I2C_MCPTHMSNS_SDA
46B3
40A5
SMB_A_S3_DATA
79D3 6D5 6C5
27A5
=I2C_ALS_SCL
29B6
=I2C_SODIMMB_SDA
27A5
=I2C_ALS_SDA
29B6
SMC "B" SMBus Connections
=PP3V42_G3H_SMBUS_SMC_BSA
7C5
R5280 1
1
2.0K
U4900
(MASTER)
40B5
SMB_BSA_CLK
79D3 6A7
40B5
SMB_BSA_DATA
79D3 6A7
R5281
2.0K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
SMBUS_SMC_BSA_SCL
BATTERY & BIL
SMC
J6950 & J6955
(See Table)
U4900
(MASTER)
R5260 1
76B3 20C3
SMBUS_MCP_1_CLK
76B3 20C3
SMBUS_MCP_1_DATA
1
4.7K
=SMBUS_BATT_SCL
58A6 58C3
40A5
SMB_B_S0_CLK
79D3
=SMBUS_BATT_SDA
58A6 58C3
40A5
SMB_B_S0_DATA
79D3
R5261
CPU Temp
4.7K
5%
1/16W
MF-LF
402 2
EMC1403-5: U5515
(Write: 0x98 Read: 0x99)
5%
1/16W
MF-LF
2 402
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
=I2C_CPUTHMSNS_SCL
46D3
=I2C_CPUTHMSNS_SDA
46D3
MAKE_BASE=TRUE
Mikey
Battery Charger
U6860
5%
1/16W
MF-LF
2 402
C
=PP3V3_S0_SMBUS_SMC_B_S0
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
2.0K
49C1
=I2C_SODIMMB_SCL
MAKE_BASE=TRUE
R5231
49C1
=I2C_TPAD_SDA
MAKE_BASE=TRUE
J3401
(Write: 0x52 Read: 0x53)
7C5 =PP3V3_S0_SMBUS_MCP_1
1
=I2C_TPAD_SCL
ALS
MCP79 SMBUS "1" CONNECTIONS
5%
1/16W
MF-LF
402 2
SMBUS_SMC_A_S3_SDA
J3200
(Write: 0xA2 Read: 0xA3)
SMC
2.0K
SMBUS_SMC_A_S3_SCL
SO-DIMM "B"
7D1
R5230 1
TRACKPAD
J5800
(Write: 0x90 Read: 0x91)
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
SMC "Battery A" SMBus Connections
U1400
(MASTER?)
R5271
1K
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
C
MCP79
1
1K
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
D
NOTE: SMC RMT bus remains powered and may be active in S3 state
=PP3V3_S0_SMBUS_SMC_0_S0
R5250 1
1
(WRITE: 0X72 READ: 0X73)
=I2C_MIKEY_SCL
57D3
=I2C_MIKEY_SDA
57D3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ISL6258A - U7000
(Write: 0x12 Read: 0x13)
Battery
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
=SMBUS_CHGR_SCL
59C6
=SMBUS_CHGR_SDA
59C6
LED BACKLIGHT
U9701
(WRITE: ?? READ: 0X??)
B
=I2C_BKL_1_SCL
=I2C_BKL_1_SDA
B
SMC "Management" SMBus Connections
71B7
The bus formerly known as "Battery B"
71B7
7D3
=PP3V3_S3_SMBUS_SMC_MGMT
R5290 1
SMC
1
4.7K
U4900
(MASTER)
5%
1/16W
MF-LF
402
40C5
SMB_MGMT_CLK
79D3
40C8
SMB_MGMT_DATA
79D3
2
R5291
Vref DACs
4.7K
2
U2900
(Write: 0x98 Read: 0x99)
5%
1/16W
MF-LF
402
SMBUS_SMC_MGMT_SCL
=I2C_VREFDACS_SCL
25C7
=I2C_VREFDACS_SDA
25C7
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
Margin Control
U2901
(Write: 0x30 Read: 0x31)
=I2C_PCA9557D_SCL
25A8
=I2C_PCA9557D_SDA
25A8
K24 SMBUS CONNECTIONS
A
SYNC_MASTER=BEN
SYNC_DATE=04/21/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
43
1
81
A
8
6
7
4
5
3
2
1
CPU Voltage Sense / Filter
7D7
=PPVCORE_S0_CPU_VSENSE
XW5309
R5309
SM
1
2
CPUVSENSE_IN
1
4.53K
PLACEMENT_NOTE=Place near U1000 center
SMC_CPU_VSENSE
2
1%
1/16W
MF-LF
402
1
40C5
0.22UF
2
D
OUT
C5309
20%
6.3V
X5R
402
GND_SMC_AVSS
D
40C2 41B6 44B5 44C6 45A1 45A4 45B2 45B5 45C5 45D7
Place RC close to SMC
MCP Voltage Sense / Filter
7C6
=PPVCORE_S0_MCP_VSENSE
XW5359
R5359
SM
1
2
MCPVSENSE_IN
1
4.53K
PLACEMENT_NOTE=Place near U1400 center
1%
1/16W
MF-LF
402
SMC_MCP_VSENSE
2
1
OUT
41D4
C5359
0.22UF
2
20%
6.3V
X5R
402
GND_SMC_AVSS
40C2 41B6 44B5 44D6 45A1 45A4 45B2 45B5 45C5 45D7
Place RC close to SMC
C
C
PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315
NTUD3127CXXG
SOT-963
N-CHANNEL
6
D
66C1
IN
=PBUSVSENS_EN
2
PBUSVSENS_EN_L
R5316 1
100K
G
1%
1/16W
MF-LF
402
S
Enables PBUS VSense
divider when high.
1
MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=18.5V
D
5
7C1
R5385 1
27.4K
G
1%
1/16W
MF-LF
402
S
=PPBUS_G3HRS5
2
PPBUS_G3HRS5_VSENSE
3
4
2
RTHEVENIN = 4573 OHMS
P-CHANNEL
B
SMC_PBUS_VSENSE
R53151
100K
1%
1/16W
MF-LF
402
R5386
1
1
5.49K
1%
1/16W
MF-LF
402
2
PBUSVSENS_EN_L_DIV
OUT
B
40C5
C5385
0.22UF
2
2
20%
6.3V
X5R
402
GND_SMC_AVSS
40C2 41B6 44C6 44D6 45A1 45A4 45B2 45B5 45C5 45D7
Place RC close to SMC
VOLTAGE SENSING
A
SYNC_MASTER=YUNWU
SYNC_DATE=02/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
44
1
81
A
8
6
7
2
3
4
5
1
MCP VCore Current Sense Filter
R5416
63D8
MCPCORES0_IMON
1
4.53K
1%
1/16W
MF-LF
402
SMC_MCP_CORE_ISENSE
2
1
41D4
C5472
0.22UF
20%
6.3V
X5R
402
2
D
OUT
D
GND_SMC_AVSS
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45C5
Place RC close to SMC
MCP MEM VDD Current Sense
=PP3V3_S0_MCPDDRISNS
7B5
67D1
IN
67D1
IN
P1V5_S0_KELVIN
P1V5_S0_SENSE
1
5
1
R5410
C5434
5%
1/16W
MF-LF
2 402
C
0.1uF
20%
10V
CERM
402
3
0.1UF
2
P1V5_S0_SENSE_E
Q5401
SOD
1
MCP MEM VDD Current Sense Filter
Gain: 50x
10%
16V
X5R
402
R5417
1
2SA2154MFV-YAE
CRITICAL
C5400
OPA348
SC70-5
4
0
2
U5400
R5411
P1V5_S0_SENSE_B
0
1
3
SMC_MCP_DDR_ISENSE
2
1%
1/16W
MF-LF
402
P1V5_S0_SENSE_AMP
2
5%
1/16W
MF-LF
402
4.53K
C
20%
6.3V
X5R
402
P1V5_S0_SENSE_C
GND_SMC_AVSS
R5412
41D4
0.22UF
2
1
OUT
C5435
1
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45B5 45D7
Place RC close to SMC
118
1%
1/16W
MF-LF
2 402
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE
7C5
=PP3V3_S0_CPUVTTISNS
1
R5492
0.1uF
7C1
IN
=PPCPUVCORE_VTT_ISNS_R 1
3
Place RC close to SMC
20%
3
0.5%
CRITICAL 1W
MF
0612-1
CPU VCore Load Side Current Sense / Filter
C5417
0.01
2 10V
CERM
2 =PPCPUVCORE_VTT_ISNS OUT
4
R5471
V+
402
U5402
7C2
80D3
ISNS_CPUVTT_N
5 IN-
80D3
ISNS_CPUVTT_P
4 IN+
SC70
62C7
R5418
INA213
OUT 6
CPUVTT_IOUT
1
4.53K
1
6.19K
1
SMC_CPU_ISENSE
2
1/16W
OUT
R5480
MF-LF
41D4
402
1%
1/16W
MF-LF
402
20%
6.3V
X5R
402
2
2
1
1
OUT
40C5
C5470
0.22UF
17.4K
C5436
0.22UF
GND
2
20%
6.3V
X5R
402
2
GND_SMC_AVSS
GND_SMC_AVSS
B
IMVP6_IMON
1%
SMC_CPU_FSB_ISENSE
2
1%
1/16W
MF-LF
402
REF 1
IN
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B5 45C5 45D7
40C2 41B6 44B5 44C6 44D6 45A1 45A4 45B2 45C5 45D7
B
Place RC close to SMC
DC-IN (AMON) CURRENT SENSE
BMON CURRENT SENSE
R5481
IN
PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)
7D1
BMON_ENG
C5418
20%
10V
REGULATOR SIDE
402
3
0.1uF
2 CERM
NC7SB3157P6XG
SC70
1 B1
SEL 6
BMON_INA_OUT
2 GND
BMON_ENG
U5403
80D3 59B3
80D3 59B3
OUT
IN
CHGR_CSO_R_P
CHGR_CSO_R_N
LOAD SIDE
SC70
4 IN+
1
40C5
0.22UF
2
C5459
OUT
C5487
20%
6.3V
X5R
402
GND_SMC_AVSS
20%
10V
40C2 41B6 44B5 44C6 44D6 45A4 45B2 45B5 45C5 45D7
2 CERM
SMC_BMON_MUX_SEL
IN
402
41D4
VCC 5
R5401
0
OUT
6
59C5
IN
3
CHGR_BMON
4
B0 BMON_ENG
REF 1
BMON_PROD
BMON_AMUX_OUT
A
VER 1
1 BMON_ENG
R5423
R5431
100K
0
GND
2
A
5 IN-
SMC_DCIN_ISENSE
2
1
V+
INA213
4.53K
0.1uF
U5413
BMON_ENG
1
1
1%
1/16W
MF-LF
402
=PP3V42_G3H_BMON_ISNS
1
CHGR_AMON
5%
1/16W
MF-LF
402
NOTE: MONITORING CURRENT FROM
BATTERY TO PBUS (BATTERY DISCHARGE)
ACROSS R7008
2
5%
1/16W
MF-LF
402
1
4.53K
1%
1/16W
MF-LF
402
SMC_BATT_ISENSE
2
1
OUT
40C5
C5490
Current Sensing
0.22UF
2
20%
6.3V
X5R
402
GND_SMC_AVSS
SYNC_MASTER=YUNWU
SYNC_DATE=12/17/2008
NOTICE OF PROPRIETARY PROPERTY
40C2 41B6 44B5 44C6 44D6 45A1 45B2 45B5 45C5
45D7
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PLACE R5491 AND C5390 CLOSE TO SMC
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
INA213 has gain of 50V/V
For engineering, stuff U5313 and unstuff R5330
For production, stuff R5330 and unstuff U5313
PLACE U5403 AND C5418 NEAR R7008
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
45
1
81
A
8
6
7
3
4
5
2
1
CPU T-Diode Thermal Sensor
7C5
INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
R5515
=PP3V3_S0_CPUTHMSNS
47
1
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
D
80D3 9C6
1
VDD
1
C5521
DETECT CPU DIE TEMPERATURE
0.0022uF
10%
50V
CERM
402
80D3 9C6
80D3
Q5501
D
R5517
10K
2
2
5%
1/16W
MF-LF
402
DFN
2 DP1
THERM*/ADDR
CRITICAL
3 DN1
ALERT*
7
CPUTHMSNS_THERM_L
8
CPUTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
43C1
5 DN2/DP3
GND
6
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
43C1
THRM_PAD
11
SIGNAL_MODOL=EMPTY
1
PLACEMENT NOTE: PLACE U5515 NEAR CPU
C5520
1
0.0022uF
BC846BMXXH
SOT732-3
1
10K
1%
1/16W
MF-LF
402
20%
10V
CERM
402
CPUTHMSNS_D2_P
3
DETECT FIN-STACK TEMPERATURE
2
CPU_THERMD_N
BI
2
EMC1413
SIGNAL_MODOL=EMPTY
R5516 1
C5515
0.1uF
U5515
CPU_THERMD_P
BI
1
10%
50V
CERM
402
2
80D3
2
CPUTHMSNS_D2_N
C
C
MCP T-Diode Thermal Sensor
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
7C5
R5535
=PP3V3_S0_MCPTHMSNS
47
1
PP3V3_S0_MCPTHMSNS_R
2
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
80D3 20C3
BI
1
VDD
C5522
B
80D3 20C3
BI
2
EMC1413
SIGNAL_MODOL=EMPTY
1
0.0022uF
10%
50V
CERM
402
2
MCP_THMDIODE_N
CRITICAL
2 DP1
C5535
R5536 1
0.1uF
U5535
MCP_THMDIODE_P
DETECT MCP DIE TEMPERATURE
1
DFN
20%
10V
CERM
402
10K
1%
1/16W
MF-LF
402 2
1
R5537
10K
5%
1/16W
MF-LF
2 402
THERM*/ADDR
7
MCPTHMSNS_THERM_L
3 DN1 CRITICAL ALERT*
8
MCPTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
9
=I2C_MCPTHMSNS_SDA
BI
43D3
5 DN2/DP3
GND
6
SMCLK
10
=I2C_MCPTHMSNS_SCL
BI
43D3
THRM_PAD
11
B
J5590
78171-0002
M-RT-SM
NOSTUFF
3
80D3 6C7
MCPTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
DETECT HEAT-PIPE TEMPERATURE
C5540
1
1
PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
2
10%
50V
NOSTUFFCERM
2
402
4
80D3 6C7
MCPTHMSNS_D2_N
REPLACED 518S0521 WITH 518S0519
Thermal Sensors
A
SYNC_MASTER=YUNWU
SYNC_DATE=03/20/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
46
1
81
A
8
7
6
3
4
5
2
1
D
D
7D5
7C5
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
R5660 1
C
47K
5%
R5665
40A8
1/16W
MF-LF
402
CRITICAL
J5601
78171-0004
M-RT-SM
NC 5
2
1
2
3
4
147K2 FAN_RT_TACH
SMC_FAN_0_TACH
6D7
5%
1/16W
MF-LF
402
NC
R5661 1
6
518S0521
SSM3K15FV
D
3
SMC_FAN_0_CTL
5V DC
TACH
MOTOR CONTROL
GND
SOD-VESM-HF
2
40B8
Q5660
G
2
S
1/16W
MF-LF
402
1
100K
5%
C
6D7
FAN_RT_PWM
B
B
Fan
A
SYNC_MASTER=CHANGZHANG
SYNC_DATE=01/18/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
47
1
81
A
6
7
PSOC USB CONTROLLER
PIN NAME
CURRENT
R_SNS
V_SNS
POWER
10UA
2.55 KOHM
0.0255 V
0.255E-6 W
0.204 V
16.32E-6 W
D
V+
3V3 LDO
VDD
60MA MAX
10 OHM
VOUT
60MA MAX
0.2 OHM
0.012 V
1.5 OHM
0.012 V
96E-6 W
0.021 V
294E-6 W
PSOC
VDD
18V BOOSTER
VIN
8MA (TYP)
0.6 V
14MA (MAX)
PP3V3_S3_PSOC
49C1 6C5
49C3 6C5
49C3 6C5
49C3 6C5
49C3 6C5
C
APN 518S0637
NC
36E-3 W
4.7 OHM
0.0188 V
75.2E-6 W
45
43
44
OMIT
R5714
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
42
WS_KBD17 6B5 48C2
WS_KBD16N 48C3
WS_KBD15_C 48D3
WS_KBD14 6B5 48C2
WS_KBD13 6B5 48D2
WS_KBD12 6B5 48D2
WS_KBD11 6B5 48D2
WS_KBD10 6B5 48D2
WS_KBD9 6B5 48D2
WS_KBD8 6B5 48D2
WS_KBD7 6B5 48D2
WS_KBD1 6B5 48D2
WS_KBD2 6B5 48D2
WS_KBD3 6B5 48D2
41
40
39
38
37
36
35
34
33
32
31
30
29
48C6
WS_KBD15_C
1
R5715
48C6
WS_KBD16N
10K
1
2
1%
1/16W
MF-LF
402
41C7 41C2 41A3 40C5
OUT
SMC_ONOFF_L
C5710
0.1UF
2
ISOLATION CIRCUIT
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
C
3
2
1
NC
PLACEMENT_NOTE=NEAR J5713
31
F-RT-SM
FF14-30A-R11B-B-3H
C5725
6B5 48D2
0.1UF
6B5 48D2
=PP3V42_G3H_TPAD
TP_ISSP_SDATA_P1_0
48D2 48B5 48A6 7C3
6C5 49C3
48C2 48B3 6A5
=PP3V3_S3_TPAD
2
WS_LEFT_SHIFT_KBD
1
5
TC7SZ08AFEAPE
SOT665
A
2
1
SMC_MANUAL_RESET LOGIC
20%
10V
CERM
402
CRITICAL
ISSP SDATA/I2C SDA
Z2_CLKIN
20%
10V
CERM
402
D
30
WS_KBD1
48C6 6B5 WS_KBD2
48C6 6B5 WS_KBD3
WS_KBD4
48C6 6B5
48C6 6B5 WS_KBD5
48C6 6B5 WS_KBD6
48C6 6B5 WS_KBD7
48C6 6B5 WS_KBD8
48C6 6B5 WS_KBD9
48C6 6B5 WS_KBD10
48C6 6B5 WS_KBD11
48C6 6B5 WS_KBD12
48C6 6B5 WS_KBD13
48C6 6B5 WS_KBD14
6B5 WS_KBD15_CAP
6B5 WS_KBD16_NUM
48D6 6B5 WS_KBD17
48D7 6B5 WS_KBD18
48D7 6B5 WS_KBD19
48D7 6B5 WS_KBD20
48D7 6B5 WS_KBD21
48D7 6A5 WS_KBD22
R5710
48D7 6A5 WS_KBD23
1K
1
2
6A5 WS_KBD_ONOFF_L
5%
48C5 48C3 48B5 7D1 =PP3V42_G3H_TPAD
1/16W
WS_LEFT_SHIFT_KBD
MF-LF
48B5 48B3 6A5
402
48B5 48B3 6A5 WS_LEFT_OPTION_KBD
48B5 48B3 6A5 WS_CONTROL_KBD
6B5 48D2
48C3 48C2 48B5 7D1
TP_PSOC_P1_3
2
1%
1/16W
MF-LF
402
57
WS_KBD4
WS_KBD5
WS_KBD6
TP_PSOC_SDA
470
1
TP_PSOC_SCL
=PP3V3_S3_TPAD
IN
48C6 6B5
4MA (MAX)
32
0.72E-3 W
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
46
47
48
49
50
51
52
53
54
APN 337S2983
P7_7
P7_0
25
P1_0
26
P1_2
27
P1_4
28
P1_6
49C1 6C5
J5713
24
49C1 6C5
MLF
(SYM-VER2)
23
49C1 6C5
CY8C24794
22 VDD
49C1 6C5
U5701
21 D-
49C3 6C5
TP_P4_5
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
CRITICAL
20 D+
NC
P2_3
2
P2_1
3
P4_7
4
P4_5
5
P4_3
6
P4_1
7
P3_7
8
P3_5
9 P3_3
10
P3_1
11
P5_7
12
P5_5
13
P5_3
14
P5_1
19 VSS
49C1 6C5
1
WS_CONTROL_KEY
Z2_KEY_ACT_L
15 P1_7
48B4
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
56
48B4
55
48C4
18 P1_1
49C3 6C5
17 P1_3
48A5
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
16 P1_5
49C1 6C5
48A8 48B6
CRITICAL
TMP102
80UA
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
1
KEYBOARD CONNECTOR
IC
USB INTERFACES TO MLB
SPI HOST TO Z2
2
3
4
5
48C5 48B5 48A6 7C3
8
48C5 48C2 48B5 7D1
WS_LEFT_SHIFT_KEY 48D8
4
U5725 Y
=PP3V42_G3H_TPAD
1
C5758
0.1UF
B
10%
16V
2 X7R-CERM
3
402
TP_P7_7
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
C5726
=PP3V42_G3H_TPAD
48C5 48C3 48C2 48B5 7D1
USB_TPAD_P
76B3 19D3
76B3
24
1
2
48D2 48C5 48B5 48A6 7C3
PP3V3_S3_PSOC
5%
B
TO MLB CONNECTOR
2
48A8 48D7
48C2 48B3 6A5
WS_LEFT_OPTION_KBD
CRITICAL
TC7SZ08AFEAPE
SOT665
A
5
WS_LEFT_OPTION_KEY
4
U5726 Y
1
20%
10V
CERM
402
48C2 48B5 6A5
48D8
B
48C2 48B5 6A5
48C2 48B5 6A5
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
1 A
3 B
6
CRITICAL
SN74LVC1G10
SC70
U5703 Y
4
41C7
SMC_TPAD_RST_L
C
3
B
2
R5702
USB_TPAD_N
76B3 19D3
=PP3V3_S3_TPAD
5
USB_TPAD_R_P
1/16W
MF-LF
402
1
APN 311S0406
DIFFERENTIAL_PAIR=USB2_TPAD
R5701
0.1UF
2
76B3
24
1
2
USB_TPAD_R_N
C5727
5%
1/16W
MF-LF
402
=PP3V42_G3H_TPAD
48C5 48C3 48C2 48B5 7D1
DIFFERENTIAL_PAIR=USB2_TPAD
48D2 48C5 48B5 48A6 7C3
48C2 48B3 6A5
=PP3V3_S3_TPAD
2
WS_CONTROL_KBD
1
5
CRITICAL
TC7SZ08AFEAPE
SOT665
A
U5727 Y
1
0.1UF
2
5%
20%
10V
CERM
402
2
WS_CONTROL_KEY
4
R5769
33K
1
1/16W
MF-LF
402
1
1
R5770
33K
R5771
33K
5%
1/16W
MF-LF
2 402
2
5%
1/16W
MF-LF
402
48D8
B
3
U5701 CHIP DECOUPLING
Alternate Parts
PLACE C5701, C5702 & C5703
CLOSE TO U5701 VDD PIN 22
PLACE C5704, C5705 & C5706
CLOSE TO U5701 VDD PIN 49
TABLE_ALT_HEAD
TPAD BUTTONS DISABLE
R5704
48B6
48D7
PP3V3_S3_PSOC
1
C5701
1
4.7UF
2
20%
6.3V
X5R
603
1
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
C5702
1
100PF
2
5%
50V
CERM
402
C5703
1
0.1UF
2
10%
16V
X7R-CERM
402
C5704
1
100PF
2
5%
50V
CERM
402
C5705
0.1UF
2
10%
16V
X7R-CERM
402
1
C5706
1.5
2
=PP3V3_S3_TPAD
48D8
BUTTON_DISABLE
7C3 48B5 48C5 48D2
5%
1/16W
MF-LF
402
4.7UF
PART NUMBER
ALTERNATE FOR
PART NUMBER
311S0406
311S0447
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
ALL
NXP PART AS ALTERNATE
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
Q5701
20%
6.3V
2 X5R
SSM3K15FV
603
WELLSPRING 1
D 3
SOD-VESM-HF
A
SYNC_MASTER=YUAN.MA
1
SMC_LID
58C1 41C2 40B5
IN
G
S 2
SYNC_DATE=04/22/2008
NOTICE OF PROPRIETARY PROPERTY
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
48
1
81
A
8
6
7
2
3
4
5
1
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
APN 152S0504
D
49B6 7C3
=PP5V_S3_TPAD
CRITICAL
D5802
2
0
5%
1/16W
MF-LF
402
R5806
SOD-323
INPUT_SW
BOOST_SW
VLF3010AT-SM-HF
0.50MM
0.20MM
MIN_NECK_WIDTH=0.20MM
2
39PF
APN 516S0689
CRITICAL
J5800
55560-0228
3
0.1UF
DO
20%
10V
CERM
402
2
5
CTRL
2
1
C5816
2.2UF
10%
16V
X7R-CERM
402
10%
16V
X5R
603
2
PAD
C5817
0.1UF
9
1
Z2_BOOST_EN
6C5 49C3
10%
25V
X5R
603-1
R5813
71.5K
1
48C8 6C5
4
3
48C8
6
5
8
7
10
9
12
11
14
13
48C8
48C8
1%
1
1/16W
R5811
49C5
MF-LF
2
100K
402
48D8
1%
1/16W
MF-LF
402
2
M-ST-SM
2
48C8
1
8
SW
6 GND
THRML
0.50MM
0.20MM
C5819
1UF
BOOST_FB
4
FB
CRITICAL
PLACEMENT_NOTE=NEAR J5800
7 PGND
2
1
TPS61045
QFN
IPD FLEX CONNECTOR
6C3 6C5 49C1
1%
1/16W
MF-LF
2 402
5%
50V
CERM
402
2
APN 353S1401
U5805
C5800
PP18V5_S3
R5812
1M
VIN
1
2
402
1
C5818
1
L
0
5%
1/16W
MF-LF
APN 371S0313
PP5V_S3_BOOSTER
1
1
B0520WSXG
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PP18V5_S3_SW
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
1
R5805
D
CRITICAL
L5801
3.3UH-870MA
Z2_CS_L
6C5 Z2_DEBUG3
6C5 Z2_MOSI
6C5 Z2_MISO
6C5 Z2_SCLK
6C5 Z2_BOOST_EN
6C5 Z2_HOST_INTN
48C6 6C5
49B4 6C5 6C3
16
15
NC 18
17
Z2_CLKIN
20
19
PP3V3_S3_LDO
22
21
0.50MM
0.20MM
0.50MM
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
PP18V5_S3
6C5 48C8
6C5 48C8
6C5 48C8
6C5 48D8
6C5 48C8
6C5 48C8
6C5 48C8
43D1
43D1
6C3 6C5 49D3
0.20MM
C
C
3V3 LDO FOR IPD
49D7 7C3
=PP5V_S3_TPAD
R5873
1
10
PP5V_S3_VR
2
1%
1/16W
MF-LF
402
49C3 6C5 6C3
PP3V3_S3_LDO
2.2UF
16V
2 X5R
1
CE
1%
1/6W
MF
402-HF
0.2
MM3243DRRE
MLF
10%
1
2
C5854
4.7UF
10%
GND
16V
X7R-CERM
402
2
20%
6.3V
X5R
603
B
4
B
C5838
0.1UF
PP3V3_S3_LDO_R
3
VOUT
603
1
1
VDD
VR5802
C5853
R5836
2
1
2
CRITICAL
APN 353S1364
KEYBOARD BACKLIGHT DRIVNG AND DETECTION
7C5
=PP3V3_S0_TPAD
7D5
KB_BL
CRITICAL
=PP5V_S0_KBDLED
APN 518S0691
L5850
10UH-0.58A-0.35OHM
R5853 1
470K
5%
1/16W
MF-LF
402
LOW = keyboard backlight present
2
A
1UF
10%
10V
X5R
402-1
SMC_SYS_KBDLED
KB_BL
4.7K
5%
1/16W
MF-LF
402 2
F-RT-SM
SMC_KDBLED_PRESENT_L
1
2
2
CTRL
NO STUFF
U5850
R5852 1
LT3491
SW
3
LED
5
3
1
KB_BL
SYNC_MASTER=YUAN.MA
1%
CAP
2
THRML
PAD
4
SYNC_DATE=05/09/2008
NOTICE OF PROPRIETARY PROPERTY
1/16W
2
2
WELLSPRING 2
R5855
MF-LF
GND
4
6A5 KBDLED_ANODE
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
10
DFN
10K
5%
1/16W
MF-LF
402
J5815 pin 1 is grounded
on keyboard backlight flex
FF18-4A-R11AD-B-3H
49A6 6A5
KB_BL
CRITICAL
R5854 1
R5853 ALWAYS PRESENT
J5815
VIN
6
40C8
BOM OPTION: KBDLED_YES
TURNED ON FOR BEST MLB CONFIG
1
KB_BL
CRITICAL
KBDLED_SW
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
1098AS-SM
KB_BL
C5850
HIGH= keyboard backlight not present
IN
2
KBD BACKLIGHT CONNECTOR
402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
KBDLED_CAP
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
7
tristate SMC_SYS_KBDLED:
1
1
To detect Keyboard backlight, SMC will
KB_BL
C5855
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1UF
2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10%
35V
X5R
603
SIZE
SMC_KDBLED_PRESENT_L
DRAWING NUMBER
D
49A4 6A5
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
49
1
81
A
8
6
7
2
3
4
5
1
D
D
C
C
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
7C3
=PP3V3_S3_SMS
14
1
R59211
B
40C8
IN
SMS_ONOFF_L
2
Desired orientation when
20%
4V
X5R
603
placed on board top-side:
AP344ALH
B
LGA
SMS_PWRDN
MAKE_BASE=TRUE
C5926
10UF
10%
2 16V
X5R
402
U5920
5%
1/16W
MF-LF
402 2
1
0.1UF
VDD
10K
C5922
SMS_SELFTEST
1 FS
VOUTX 12
5 PD CRITICAL
VOUTY 10
2 ST
VOUTZ 8
1
R5922
10K
NC
NC
NC
3 NC
6 NC
9 NC
OUT
40A8
SMS_Y_AXIS
OUT
40A8
SMS_Z_AXIS
OUT
40A8
+Y
Front of system
+X
+Z (up)
GND
NC 11 NC
NC 13 NC
NC 16 NC
1
C5923
0.01UF
10%
2 16V
CERM
402
7
2
5%
1/16W
MF-LF
402
NC
15 RES
4 RES
SMS_X_AXIS
1
C5924
0.01UF
10%
2 16V
CERM
402
1
C5925
0.01UF
Circle indicates pin 1 location when placed
in correct orientation
10%
2 16V
CERM
402
SMS
SYNC_MASTER=YUNWU
A
SYNC_DATE=06/26/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
50
1
81
A
8
6
7
2
3
4
5
1
D
D
=PP3V3_S5_ROM
NO STUFF
R61901 R61001
C
10K
R6150
42C5 42A8
IN
SPI_CLK_MUX
PLACEMENT_NOTE=PLACE CLOSE TO U6100
42B5
IN
0
1
SPI_MLB_CS_L
3.3K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
2
76A3
1
R6101
3.3K
C6100 1
8
42C7 42B5 7A3
20%
10V
CERM 2
402
SPI_CLK
5%
1/16W
MF-LF
402
U6100
32MBIT
6 SCLK
R6152
SOP
SI/SIO0 5
MX25L3205DM2I-12G
1 CE*
SPI_WP_L
SPI_HOLD_L
C
CRITICAL
VCC
0.1UF
5%
1/16W
MF-LF
2 402
SO/SIO1 2
SPI_MOSI
1
R6105
OMIT
3 WP*/ACC
7
76A3
76A3
HOLD*
SPI_MISO_R
NO STUFF
1
R6191
10K
GND
1
0
5%
1/16W
MF-LF
402
2
0
5%
1/16W
MF-LF
402
2
SPI_MOSI_MUX
IN
42A8 42C5
PLACEMENT_NOTE=PLACE CLOSE TO U6100
SPI_MISO_MUX
OUT
42A8 42B5
PLACEMENT_NOTE=PLACE CLOSE TO U6100
4
5%
1/16W
MF-LF
2 402
MCP79 SPI Frequency Select
Frequency
B
SPI_MOSI
SPI_CLK
31 MHz
0
0
42 MHz
0
1
25 MHz
1
0
1 MHz
1
1
B
25MHz is selected with R5190 and R5191
Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191
SPI ROM
A
SYNC_MASTER=CHANGZHANG
SYNC_DATE=05/02/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
51
1
81
A
8
6
7
2
3
4
5
1
AUDIO CODEC
APPLE P/N 353S2355
L6201
U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL
FERR-220-OHM
7B6
=PP1V8_S0_AUDIO
IN
1
=PP5V_S3_AUDIO
0402
C6210
D
1
1
4.7UF
20%
4V
X5R-1
402
=PP3V3_S0_AUDIO
C6211
0.1UF
PP4V5_AUDIO_ANALOG
10%
2 16V
X5R
402
2
C6216
C6218
10UF
1
1
10UF
20%
6.3V
X5R
603-1
R6210
1
2.67K
10UF
2
20%
6.3V
X5R
603-1
2
CRITICAL
1%
1/16W
MF-LF
2 402
VBIAS_DAC
CS4206_FP
CS4206_FN
14
15
13
SENSE_A
45
43
42
FLYP
FLYC
FLYN
29
56A7
OUT
2
54C5
OUT
12
57D8
IN
AUD_SENSE_A
CS4206_FLYP
CS4206_FLYC
C6222
1
20%
6.3V
CERM
402-LF
2
1
2.2UF
C6223
2.2UF
2
20%
6.3V
CERM
402-LF
CS4206_FLYN
C
76B3 20D2
IN
HDA_BIT_CLK
76B3 20D2
IN
HDA_SYNC
R6211
76A3 20D7
HDA_SDIN0
OUT
76A3 20D2
IN
76A3 20D2
IN
1
HDA_SDOUT
HDA_RST_L
TP_AUD_SPDIF_IN
NC
39
AUD_SDI_R
2
1
VL_IF
6
BITCLK
11
47
48
AUD_SPDIF_OUT_CHIP
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2CRITICAL
2
10UF
MIN_LINE_WIDTH=0.30MM
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM
39
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
AUD_CODEC_MICBIAS
VCOM
28
LINEIN_L+
LINEIN_CLINEIN_R+
22
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
VREF+_ADC
27
CS4206_VREF_ADC
NC
4
TP_AUD_DMIC_CLK
NC
SDI
SDO
RESET*
SPDIF_IN
SPDIF_OUT
IN
=PP3V3_S0_AUDIO
U6200
TPS71745
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
2
4V5_REG_IN
6 IN
4V5_REG_EN
4 EN
0402
R6200
57D3 57B8 56D8 52D2 7C5
2.21K2
C6200
NR/FB 3
2
1UF
10%
2 10V
X5R
402
1
C6201
54B7
IN
56D3
NC
NC
OUT
55B7
OUT
55B7
OUT
55B7
OUT
55A7
OUT
55C7
OUT
55C7
OUT
57C4
FR SPKR AMP. SIG. SOURCE
LFT. SPKR AMP. SIG. SOURCE
RT. SPKR AMP. SIG. SOURCE
AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R
IN
53C3
IN
53B3
IN
53B3
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
IN
57C3
IN
57C3
IN
57B4
IN
57B4
EXT MIC CODEC INPUT
BI MIC CODEC INPUT
1
C6225
NOSTUFF
10UF
R6213
1
20%
2 16V
TANT-POLY
2012-LLP
100K
5%
1/16W
MF-LF
2 402
B
NOTES ON CODEC I/O
OUT
DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
6C2 52D2 52D7
4V5_NR
NC 5
C6202
0.1UF
1UF
XW6200
SM
PP4V5_AUDIO_ANALOG
1
OUT
CRITICAL
GND
1
54C7
OUT
C
23
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V
SON
1
1%
1/16W
MF-LF
402
OUT
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GND_AUDIO_CODEC
1
52A5 52B7 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1
DGND THRM_PAD AGND
7
=PP5V_S3_AUDIO
52A5 52D7 54C4 54C7 56D2
CS4206_VCOM
21
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2456
IN
AUD_HP_PORT_REF
31
30
32
33
B
56B6 54D5 52D2 7C3
AUD_HP_PORT_L
AUD_HP_PORT_R
TP_AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_N_R
20%
16V 2
TANT
0603-SM
L6200
10UFCRITICAL
20%
6.3V
2 X5R
603-1
35
34
36
37
16
D
6C2 52A5 52D7
C6213
GND_AUDIO_HP_AMP
GND_AUDIO_CODEC
38
40
1UF
FERR-220-OHM
1
10%
16V
X5R 2
402
20%
2 16V
TANT-POLY
2012-LLP
C6224 1
57D1 57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52A5
1
0.1UF
10%
16V 2
X5R
402
MICBIAS
DMIC_SCL
5%
1/16W
MF-LF
402
10%
C6217 10V
X5R
402-1
IN
SYNC
39
AUD_SPDIF_OUT
OUT
VL_HD
8
5
R6212
56D3
3
10
5%
1/16W
MF-LF
402
U6201
1
C6215 1 C6214
0.1UF
7C5 52A8 56D8 57B8 57D3
26
GPIO1 = HP AMP CONTROL
VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206ACNZC HPREF
QFN
GPIO0/DMIC_SDA1 LINEOUT_L1+
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2
GPIO2
LINEOUT_R1+
GPIO3
LINEOUT_R1-
44
41
AUD_GPIO_0
AUD_GPIO_1
TP_AUD_GPIO_2
NC
GPIO3 = SPKR AMP SHDN CONTROL 55C7 OUT AUD_GPIO_3
GPIO0 = ANALOG SW CONTROL
10%
16V 2
X5R
402
25
C6220
46
C6221
24
IN
1
0.1UF
49
52D2 52A5 6C2
20%
16V 2
TANT-POLY
CRITICAL 2012-LLP
9
GND_AUDIO_HP_AMP
PP4V5_AUDIO_ANALOG
1
1UF
C6219 1
56D2 54C7 54C4 52D2 52A5
7C3 52A8 54D5 56B6
PP1V8_S0_AUDIO_DIG
2
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
1
10%
16V
X7R-CERM 2
402
10%
10V
2 X5R
402
1
C6203
1UF
10%
2 10V
X5R
402
GND_AUDIO_CODEC
AUDIO: CODEC/REGULATOR
52B7 52D2 53B6 56A7 57A8 57B4 57B8 57C3 57C8 57D1
NOSTUFF
A
R6201
0
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
XW6201
SM
1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
2
II NOT TO REPRODUCE OR COPY IT
GND_AUDIO_HP_AMP
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
52D2 52D7 54C4 54C7 56D2
SIZE
DRAWING NUMBER
D
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
A
NOTICE OF PROPRIETARY PROPERTY
5%
1/16W
MF-LF
402
4.7.0
OF
52
1
81
8
6
7
2
3
4
5
1
D
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)
FC_HP = 3.6 HZ
FC_LP = 43KHZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6301
R6301
56B7
AUD_LI_L
IN
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
C
7.87K
2.2UF
AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1%
1/16W
MF-LF
402
20%
10V
X5R-CERM
402
NOSTUFF
C6303
R6302
10%
50V
CERM
402
1%
1/16W
MF-LF
402
820PF
AUD_LI_P_L
52C2
OUT
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
C
21.5K
CRITICAL
C6302
2.2UF
20%
10V
X5R-CERM
402
56D2
IN
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
AUD_LI_GND
AUD_LI_REF
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
52C2
1
R6300
10
CRITICAL
1%
1/16W
MF-LF
2 402
57D1 57C8 57C3 57B8 57B4 57A8 56A7 52D2 52B7 52A5
IN
C6312
2.2UF
GND_AUDIO_CODEC
20%
10V
X5R-CERM
402
NOSTUFF
C6313
820PF
10%
50V
CERM
402
B
R6312
B
21.5K
1%
1/16W
MF-LF
402
CRITICAL
C6311
R6311
56A7
IN
AUD_LI_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
7.87K
1%
1/16W
MF-LF
402
AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
2.2UF
20%
10V
X5R-CERM
402
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
52C2
AUDIO: LINE INPUT FILTER
A
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
53
1
81
8
6
7
2
3
4
5
1
FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL
RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).
D
D
L6520
FERR-120-OHM-1.5A
=PP5V_S3_AUDIO
HP/LO AMP
APN: 353S1637
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
AUD_PP5V_F
56B6 52D2 52A8 7C3
0402-LF
C6520
C6521
NO STUFF
10%
16V
X7R-CERM
402
20%
6.3V
X5R
603
0
10UF
R6521
5%
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
12
0.1UF
AUD_LO_AMP_INL_M
AUD_HP_PORT_L
0
1
1
10%
16V
X7R-CERM
402
2
0.1UF
NC
C
AUD_HP_ZOBEL_L
OUT
AUD_GPIO_1_R
5 SHDN*
R6522
NO STUFF
CRITICAL
C6501
100K
R65001
56D2 54C4 52D7 52D2 52A5
IN
OUT
54B1 56B7
CRITICAL
C6524
1UF
MAX9724_C1N
C6522
1UF
10%
10V
X5R
402
GND_AUDIO_HP_AMP
56D2 54C7 52D7 52D2 52A5
2
54B1 56B7
MAX9724_C1P
C1P 1
C1N 3
CRITICAL
2
39
5%
1/16W
MF-LF
402
AUD_LO_AMP_OUTR
OUT
10%
10V
X5R
402
MAX9724_SVSS
5%
1/16W
MF-LF
402
1
0.0022UF
10%
50V
CERM
402
MAX9724A
TQFN
5%
1/16W
MF-LF
402
54B4
5%
1/16W
MF-LF
402
CRITICAL
C6500
AUD_HP_L
2
R6520
AUD_GPIO_1 1 0 2
OUTL 11
OUTR 10
4 PVSS
IN
IN
9 SVSS
52D2
52C7
U6500
2 PGND
R6501
AUD_LO_AMP_INR_M
7 SGND
54B3
VDD
CRITICAL
6 INL
8 INR
54B3
13 THRM
PAD
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
AUD_LO_AMP_OUTL
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
CRITICAL
C6523
C
1UF
10%
10V
X5R
402
GND_AUDIO_HP_AMP
R65101
39
5%
1/16W
MF-LF
402 2
NC
NO STUFF
CRITICAL
C6511
AUD_HP_ZOBEL_R
MAX9724 GAIN/FILTER COMPONENTS
1
AV_PB = -1V/V, FC_LPF = 35.2KHZ
0.0022UF
10%
50V
CERM
402
CRITICAL
C6510
1
10%
16V
X7R-CERM
402
2
CRITICAL
2
C6530
0.1UF
52D2
IN
AUD_HP_PORT_R
330PF
R6511
1
0
2
AUD_HP_R
OUT
5%
50V
COG
402
54B4
5%
1/16W
MF-LF
402
R6531
13.7K
1%
1/16W
MF-LF
402
B
AUD_HP_L
54C6
R6530
13.7K
AUD_LO_AMP_INL_M
B
AUD_LO_AMP_OUTL
54C4
IN
OUT
54D1 56B7
OUT
54C1 56B7
1%
1/16W
MF-LF
402
AUD_HP_R
54B6
R6532
13.7K
AUD_LO_AMP_INR_M
AUD_LO_AMP_OUTR
54C4
IN
1%
1/16W
MF-LF
402
R6533
13.7K
1%
1/16W
MF-LF
402
CRITICAL
C6531
330PF
5%
50V
COG
402
AUDIO: HEADPHONE FILTER
A
SYNC_MASTER=AUDIO
SYNC_DATE=02/03/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
54
1
81
A
8
6
7
SATELLITE
3
4
5
2
1
& SUB TWEETER AMPLIFIER
APN:353S2524
D
SATELLITE
169 HZ < FC < 282 HZ
SUB
GAIN
80 HZ < FC < 132 HZ
6DB
D
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
55C7 55B7 7C3
=PP5V_S3_AUDIO_AMP
CRITICAL
C6607 1
1UF
CRITICAL
L6610
52C2
AUD_LO2_P_R
IN
0402
AUD_LO2_N_R
55B7 55A7
2
0.047UF
2
SPKRAMP_INR_N
2
1
10
PVDD
C6601
47UF
20%
2 6.3V
TANT1
2012-LLP
U6610
TDFN
2 IN+
3 IN-
OUT+
8
OUT-
9
6
CRITICAL
SYNC
5 SHDN*
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT
6C7
56B2
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT
6C7
56A2
THRML
1
10%
16V
X7R
402
0
1
C
100K
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
SPKRAMP_SHDN
GND PGND PAD
4
7
11
R6611
R6610
AUD_GPIO_3
IN
MAX9705_R_P
MAX9705_R_N
10%
16V
X7R
402
C6611
0402
C
52C7
1
1
1
VDD
MAX9705A
0.047UF
CRITICAL
FERR-1000-OHM
IN
C6610
FERR-1000-OHM
1
2 SPKRAMP_INR_P
L6611
52C2
10%
10V
X5R 2
402
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
55D7 55B7 7C3
=PP5V_S3_AUDIO_AMP
CRITICAL
1
L6620
52C2
IN
1
AUD_LO1_P_R
2
0402
55C7 55A7
1
AUD_LO1_N_R
MAX9705_SUB_P
MAX9705_SUB_N
SPKRAMP_INSUB_P
2
CRITICAL
10%
16V
X5R
402
L6621
IN
10%
10V
X5R 2
402
0.1UF
FERR-1000-OHM
52C2
1UF
C6620
FERR-1000-OHM
C6621
1
SPKRAMP_INSUB_N
0402
VDD
PVDD
U6620
2
20%
2 6.3V
TANT
CASE-AL1
MAX9705A
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT
6C7
TDFN
IN+
IN-
CRITICAL
SHDN*
0.1UF
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT 6C7 56B2
100UF
C6608 1
CRITICAL
C6603
GND PGND
OUT+
OUT-
56B2
SYNC
THRML
PAD
10%
16V
X5R
402
SPKRAMP_SHDN
B
B
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
55D7 55C7 7C3
=PP5V_S3_AUDIO_AMP
CRITICAL
C6609 1
52C2
IN
AUD_LO2_P_L
1
2
SPKRAMP_INL_P
0402
55C7 55B7
AUD_LO2_N_L
1
2
0402
1
SPKRAMP_INL_N
MAX9705_L_P
MAX9705_L_N
2
10%
16V
X7R
402
FERR-1000-OHM
IN
10%
10V
X5R 2
402
C6630
0.047UF
L6631
52C2
1UF
CRITICAL
L6630
FERR-1000-OHM
1
CRITICAL
C6631
PVDD
U6630
MAX9705A
TDFN
IN+
IN-
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT
6D7
47UF
20%
2 6.3V
TANT1
2012-LLP
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT
OUT+
OUT-
56B2
6D7 56B2
CRITICAL SYNC
SHDN*
0.047UF
1
VDD
C6605
2
GND PGND
THRML
PAD
10%
16V
X7R
402
SPKRAMP_SHDN
AUDI0: SPEAKER AMP
A
SYNC_MASTER=AUDIO
SYNC_DATE=12/18/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
55
1
81
A
8
6
7
2
3
4
5
1
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX
AUD_SPDIF_OUT
IN
52B7
HS_MIC_HI
OUT
57C1
HS_MIC_LO
OUT
57C1
L6701
FERR-1000-OHM
57D3 57B8 52D2 52A8 7C5
1
=PP3V3_S0_AUDIO
2
0402
L6702
FERR-1000-OHM
1
D
2
0402
D
L6706
CRITICAL
FERR-220-OHM
AUD_HP_PORT_REF
APN:514-0671
J6700
0402
SPDIF-TXRX-K24
F-RT-TH
CRITICAL
MIC
DETECT
SWITCH
LEFT
RIGHT
GND
CRITICAL
AUD_CONNJ1_MIC
L6703
AUD_CONNJ1_SLEEVE
1
6
2
1
3
4
C
XW6701
SM
AUD_LI_GND
53B6
L6704
AUD_CONN_GND
FERR-220-OHM
1
56A7 56D2 56A7 56D2
AUD_CONN_L
2
0402
BI
56B3
BI
56A3
CRITICAL
L6705
7
FERR-220-OHM
8
9
1
AUD_CONN_R
2
0402
POF
SHIELD
PINS
52A5 52D2 52D7 54C4 54C7
AUD_CONN_GND
2
GND_AUDIO_HP_AMP
CRITICAL
OPERATING VOLTAGE 3.3
SHELL
XW6700
SM
0402-LF
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
5
AUDIO
A - VIN
B - VCC
C - GND
52D2
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
FERR-120-OHM-1.5A
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
OUT
1
10
11
R6700
C6700
CRITICAL
1UF
12
13
2
DZ6705
10%
2 6.3V
CERM
402
2
6.8V-100PF
CRITICAL
2
CRITICAL
2
402
1
402
1
CRITICAL
1
DZ6700
1
402
1
1
AUD_J1_SLEEVEDET_R
2
OUT
MIC CONNECTOR
57C6 57C8
APN:518S0520
R6701
2
6.8V-100PF
402
10K
5%
1/16W
MF-LF
402
402
6.8V-100PF
6.8V-100PF
DZ6703
6.8V-100PF
DZ6704
DZ6701
1
CRITICAL
1
C6701
100PF
4.7
78171-0003
OUT
57A7 57C8
5%
1/16W
MF-LF
402
57B1 6D7
57B1 6D7
57B1 6D7
BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI
1
2
3
5
CHASSIS GND STITCHES
NOSTUFF
XW6710
SM
R6723
0
NOSTUFF
R6722
XW6711
SM
0
R6725
0
0
=PP3V42_G3H_AUDIO
7D1
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SPEAKER CONNECTOR
5%
1/16W
MF-LF
402
NOSTUFF
R6760
R6724
=PP5V_S3_AUDIO
54D1 54B1
OUT
AUD_LO_AMP_OUTL
0
OUT
AUD_LO_AMP_OUTR
IN
IN
AUD_LI_L_SWITCH
0
C2 CB
IN
IN
55C2 6C7
IN
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
EN* B2
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
CRITICAL
B
J6703
78171-0004
M-RT-SM
5
C6761
5%
2 50V
CERM
402
1
2
3
1
4
C6762
33PF
5%
50V
2 CERM
402
AUD_CONN_R
BI
1
56C3
R6713
6
C6763
33PF
55C2 6C7
0.0033UF
C6760
IN
SPKRAMP_R_N_OUT
5%
50V
2 CERM
402
APN:518S0521
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
24K
10%
50V
CERM
402
5%
1/16W
MF-LF
402
R6720
0
AUD_GPIO_0
AUD_SWITCH_CTRL
5%
1/16W
MF-LF
402
A
AUDIO: JACK
R6721
100K
56D2
AUD_CONN_GND
GND STUFFING OPTIONS FOR CMOS SWITCH
57D1 57C8 57C3 57B8 57B4 57A8 53B6 52D2 52B7 52A5
R6715
0
5%
1/16W
MF-LF
402
GND_AUDIO_CODEC
5%
1/16W
MF-LF
402
R6714
0
SYNC_MASTER=AUDIO
ANALOG AUDIO IO SWITCH
GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED
GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
NOSTUFF
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R6727
SIZE
0
5
DRAWING NUMBER
D
5%
1/16W
MF-LF
402
6
SYNC_DATE=03/20/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
AUD_SWITCH_GND
5%
1/16W
MF-LF
402
7
5%
1/16W
MF-LF
402
55B2 6C7
GND
C6711
AUD_LI_R_SWITCH
2
33PF
24K
SWITCH_CP A2
NEG
5%
1/16W
MF-LF
402
52C7
1
COM2 B1
R6719
AUD_LI_R
1
SPKRAMP_SUB_P_OUT
56C3
R6712
COM1 B4
WLP
CRITICAL
A4 NO1
A1 NO2
5%
1/16W
MF-LF
402
53B6
IN
AUD_CONN_L
BI
MAX14504
B3
53C6
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
A3
C4 NC1
C1 NC2
R6718
0
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
APN: 353S2536
U6700
AUD_LO_AMP_OUTR_SWITCH
5%
1/16W
MF-LF
402
AUD_LI_L
IN
5%
50V
2 CERM
402
VCC
R6717
0
M-RT-SM
3
33PF
R6726
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
54C1 54B1
IN
55A2 6D7
NOSTUFF
0
10%
10V
X5R
402
AUD_LO_AMP_OUTL_SWITCH
55B2 6D7
1
C6710
1UF
R6716
55C2 6C7
PP_MAX14504_VCC
C3
B
J6702
4
0
5%
1/16W
MF-LF
402
CRITICAL
78171-0002
APN:518S0519
5%
1/16W
MF-LF
402
54D5 52D2 52A8 7C3
8
C
M-RT-SM
4
AUD_J1_TIPDET_R
2
5%
2 50V
CERM
402
GND_CHASSIS_AUDIO_JACK
CRITICAL
J6701
APPLE INC.
SCALE
SHT
NONE
4
3
2
REV.
051-7898
4.7.0
OF
56
1
81
A
8
6
7
2
3
4
5
1
CODEC OUTPUT SIGNAL PATHS
CONVERTER
0X02 (2)
0X05 (5)
0X04 (4)
0X03 (03)
0X08 (8)
PIN COMPLEX
0X09 (9,A)
0X0C (12)
0X0B (11)
0X0A (10)
0X10 (16)
MUTE CONTROL
GPIO_0 AND GPIO_1
GPIO_0 AND GPIO_1
GPIO_3
GPIO_3
N/A
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=8.82KHZ
DET ASSIGNMENT
0X09 (A)
0X09 (A)AND UI ELEMENT
N/A
N/A
0X0D (B)
MIKEY
L6880
57B8 56D8 52D2 52A8 7C5
=PP3V3_S0_AUDIO
1
2
CONVERTER
0X06 (6)
0X06 (6)
VREF
MIC_BIAS (80%)
MIKEY
PIN COMPLEX
0X0D (13,B,RIGHT)
0X0D (13,V22,B,LEFT)
APN:353S2256
CRITICAL
MIKEY
DET ASSIGNMENT
N/A
MIKEY
C6880
3
FUNCTION
BUILT-IN MIC
HEADSET MIC
1UF
10%
6.3V
CERM
402
AVDD
PORT A DETECT (HEADPHONES)
IN
43B6
BI
=I2C_MIKEY_SDA
18D7
PORT B DETECT(SPDIF DELEGATE)
DRC
43B6
=I2C_MIKEY_SCL
20C3 20A4
6
SCL
MICBIAS
1
HS_MIC_BIAS
5
SDA
DETECT
2
HS_SW_DET
OUT
AUD_I2C_INT_L
7
INT*
IN
AUD_IPHS_SWITCH_EN
8
ENABLE
GND
1
39.2K
APN:376S0613
300K
AUD_OUTJACK_INSERT_L
5%
1/16W
MF-LF
402
2
Q6801
47K
2
5
1
AUD_PORTB_DET_L
NC
Q6801
G
S
SSM6N15FEAPE
C6801
S
2
4
G
S
52C2
1
PP3V3_S0_AUDIO_F
1
220K
2
5%
1/16W
MF-LF
2 402
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
D
Q6800
6
57C8 56C3
1
R6883
1
100K
2
5%
1/16W
MF-LF
402
C6802
2
G
S
1
52C2
IN
AUD_CODEC_MICBIAS
100
1
10%
16V
CERM
402
2
1%
1/16W
MF-LF
402
R6882
2.2K
2
2
5%
1/16W
MF-LF
402
HS_MIC_HI
2
5%
1/16W
MF-LF
402
1
0.0082UF
2
10%
X7R
IN
56D3
IN
56D3
MIKEY
C6885
27PF
25V
402
5%
CERM
2
CRITICAL
50V
402
C
CRITICAL
SM
HS_MIC_LO
2
R6851
MIC_BIAS_FILT
1
1
2
1%
1/16W
MF
402-1
CRITICAL
C6852
2.2UF
GND_AUDIO_CODEC
2.4K
20%
6.3V
TANT
402
CRITICAL
L6850
FERR-1000-OHM
0.1UF
52C2
1
OUT AUD_MIC_INP_R
CRITICAL
C6851
0.1UF
52C2
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
57C8 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
1
OUT AUD_MIC_INN_R
B
GND_AUDIO_CODEC
1
2
2.4K
BI_MIC_HI_F
1
2
BI_MIC_HI
IN
6D7 56C2
BI_MIC_LO
IN
6D7 56C2
BI_MIC_SHIELD
IN
6D7 56C2
0402
10%
25V
X5R
402
1
R6852
CRITICAL
C6853
100K
R6853
1
SM
L6862
2
10%
25V
X5R
402
XW6851
EXTRACTION NOTIFICATION CKT
2
5%
1/16W
MF-LF
2 402
1
1
2
2
0.001UF
50V
402
BI_MIC_LO_F
10%
CERM
CRITICAL
C6854
27PF
5%
CERM
50V
402
L6851
B
FERR-1000-OHM
1
2
0402
1%
1/16W
MF
402-1
2
FERR-1000-OHM
1
2.2K
MIKEY
C6884
C6850
=PP3V3_S0_AUDIO
1%
1/16W
MF-LF
402
PORT B RIGHT(BUILT-IN MIC)
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
IN
1
R6884
1
MIKEY
R6850
2
57D3 56D8 52D2 52A8 7C5
R6881
1
AUD_J1_SLEEVEDET_R
AUD_J1_SLEEVEDET_R
GND_AUDIO_CODEC
52A5 52B7 52D2 53B6 56A7 57A8
57B4 57B8 57C3 57C8
MIKEY
AUD_J1_SLEEVEDET_INV
0.01UF
57C3 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1 57C8
2
MIKEY
10%
25V
X5R
402
1
SOT563
2
MIKEY
XW6880
GND_AUDIO_CODEC
SSM6N15FEAPE
1
10%
CERM
HS_MIC_HI_RC
2
2
10%
25V
X5R
402
10V
402
5%
1/16W
MF-LF
402
R6804
220K
IN
1
OUT AUD_MIC_INN_L
0.1UF
20%
CERM
2
1
SOT563
GND_AUDIO_CODEC
1
57C6 56C3
OUT AUD_MIC_INP_L
0.1UF
G
0.01UF
MIKEY
CRITICAL
MIKEY
CRITICAL
4
5
GND_AUDIO_CODEC
1
C6881
C6883
52C2
R6803
57C8 57B8
MIKEY
16V
402
1K
NC
6
20%
6.3V
TANT
402
THM
0.1UF
D
2.2UF
2
GND_AUDIO_CODEC
57C8 57C3 57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1
C6886
AUD_J1_DET_RC
2
57B8 57B4 57A8 56A7 53B6 52D2 52B7 52A5
57D1 57C3
3
SOT563
5%
1/16W
MF-LF
402
C
D
SSM6N15FEAPE
R6802
1
2
1%
1/16W
MF-LF
402
3
SOT563
AUD_J1_TIPDET_R
R6805
C6882
HS_RX_BP
20.0K
1%
1/16W
MF-LF
402
AUD_PORTA_DET_L
D
Q6800
SSM6N15FEAPE
IN
1
R6806
5%
1/16W
MF-LF
402
MIKEY
CRITICAL
1
10
BYPASS
100K
PP3V3_S0_AUDIO_F
R6801
57A7 56C3
4
MIKEY
R6880 1
OUT AUD_SENSE_A
57C8 57B8
D
MIKEY
U6880
CD3275
PULLUPS ON MCP PAGE
52C7
DRC MIKEY
0402
CODEC INPUT SIGNAL PATHS
D
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
PP3V3_S0_HS_RX
FERR-1000-OHM
11
VOLUME
0X02 (2)
0X05 (5)
0X04 (4)
0X03 (3)
N/A
9
FUNCTION
HP/LINE OUT
LINE IN
SATELLITES
SUB
SPDIF OUT
HP=80HZ
2
0402
R6864
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA
C6861
220K
1
5%
1/16W
MF-LF
402
0.1UF
10V
402
20%
CERM
2
R6865
100K
Q6802
5%
1/16W
MF-LF
402
D 6
SSM6N15FEAPE
2
R6860
57C8 56C3
15K
AUD_J1_TIPDET_R
5%
1/16W
MF-LF
402
A
G
S 1
Q6802
0
AUD_IP_PERIPHERAL_DET OUT
16B6
5%
1/16W
MF-LF
402
D 3
SSM6N15FEAPE
SOT563
TIPDET_FILT
5
C6860
0.1UF
G
AUDIO: JACK TRANSLATORS
S 4
SYNC_MASTER=AUDIO
AUD_J1_TIPDET_INV
20%
10V
CERM
402
57D1 57C8 57C3 57B8 57B4 56A7 53B6 52D2 52B7 52A5
R6861
AUD_PERPH_DET_R
SOT563
SYNC_DATE=03/20/2009
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
GND_AUDIO_CODEC
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
57
1
81
A
8
6
7
2
3
4
5
1
MagSafe DC Power Jack
CRITICAL
J6900
CRITICAL
F6905
78048-0573
M-RT-SM
6AMP-24V
1
6C3
3
ADAPTER_SENSE
0
1
1
2
5%
1/16W
MF-LF
402
518S0656
=PP3V42_G3H_ONEWIRE
C6905
0.01UF
2
1
20%
50V
CERM
603
SMC_BC_ACOK_VCC
R6929
2.0K
402
MF-LF
1/16W
5%
7D2 58C8
U6900
1
SC70-5
4 INT
2
NEAR U6901
1
SMC_BC_ACOK
40C5 41B2 41D5
NC
3
2
GND
U6901
3
EXT 5
20% PLACEMENT_NOTE=PLACE
2 10V
CERM
402
Y
B
MAX9940
SYS_ONEWIRE
BI
4
D
7D1
C6908
0.1UF
SOT665
TC7SZ08AFEAPE
A
VCC
ONEWIRE_PU
40B8
5
1
6B3
=PP18V5_DCIN_CONN
2
5
2
1206-1
R6928
4
D
1
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
2
NC
1-Wire OverVoltage Protection
ADAPTER_SENSE_R
BIL CONNECTOR
C
=PP3V42_G3H_BATT
2
58C2 7D1
J6955
1
10K
CPB6312-0101F
1/16W
402
MF-LF
5%
F-ST-SM
14
2
CRITICAL
D6905
R6905
47
2
5%
1/8W
MF-LF
805
5
1
C6954
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=12.6V
NC
2
10%
50V
CERM
402
PPVIN_G3H_P3V42G3H
NC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
C6990
10%
25V
X5R
805
VIN
2
NC
7 NC
SW 4
DFN
CRITICAL
5
GND
BIAS 2
C6994
1
20%
6.3V
X5R
402
2
0.22uF
LT3470A
8 SHDN*
B
BOOST
U6990
33UH
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE DIDT=TRUE
C6953
2
=PP3V42_G3H_REG
2
5
8
7
10
9
12
11
58C4 7D1
1
47PF
5%
50V
CERM
402
5%
50V
CERM
402
100
1
2
1/16W
SMC_LID
402
40B5 41C2 48A5
5%
MF-LF
1
NC
C6951
16
R6961
=PP3V42_G3H_BATT
SMC_LID_R
6A7
2
0.1UF
15
10%
25V
X5R
402
2
C6955
0.001UF
1
10%
50V
CERM
402
2
2
7D2
Vout = 3.425V
CDPH4D19FHF-SM
250MA MAX OUTPUT
C6995
22pF
2
NC
3
6
L6995
1
1
1
4
CRITICAL
P3V42G3H_SW
FB 1
THRM
PAD
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
13
1
47PF
DIDT=TRUE
10UF
BI
1
P3V42G3H_BOOST
1
BI
58A6 43C3
SMC_BIL_BUTTON_L
0.001UF
4
BATT_POS_F
58A6 43C3
C6952
Supply needs to guarantee 3.31V delivered to SMC VRef generator
3
59A3 58A7 6A7
TO SMC
3.425V "G3Hot" Supply
SOT665
PPDCIN_S5_P3V42G3H
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
3
1
9
=PP18V5_DCIN_CONN
6
58D1 7D2
HN2D01JEAPE
C
516S0523
CRITICAL
R6960
5%
50V
CERM
402
<Ra>
R6995 1
B
(Switcher limit)
348K
1%
1/16W
MF-LF
402 2
CRITICAL
1
C6999
22UF
P3V42G3H_FB
<Rb>
R6996 1
2
20%
6.3V
CERM
805
200K
1%
1/16W
MF-LF
402 2
Vout = 1.25V * (1 + Ra / Rb)
518-0359
BATTERY CONNECTOR
CRITICAL
J6950
BAT-K24
M-RT-TH
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
1
2
59A3 58B8 6A7
6
7
8
9
6A7
=SMBUS_BATT_SCL
SYS_DETECT_L
=SMBUS_BATT_SDA
43C3 58C3
DC-In & Battery Connectors
43C3 58C3
CRITICAL
D6950
RCLAMP2402B
SC-75
2
5
1
3
4
BATT_POS_F
R6950 1
10K
5%
1/16W
MF-LF
402
10
11
SYNC_MASTER=YUNWU
C6950
12
13
SYNC_DATE=12/11/2008
NOTICE OF PROPRIETARY PROPERTY
1
0.1UF
10%
25V
X5R
402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
2
2
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
3
A
P1
P2
P3
P4
P5
P6
P7
P8
P9
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
58
1
81
A
8
6
7
2
3
4
5
1
PBUS SUPPLY / BATTERY CHARGER
CRITICAL
Q7001
CRITICAL
HAT1127H
MIN_NECK_WIDTH=0.3 MM
PPVDCIN_G3H_PRE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
R7098 1
1
100K
5%
0.1UF
1/16W
MF-LF
402 2
10%
25V 2
X5R
402
CRITICAL
R7010
1%
1/16W
MF-LF
402
59C5
G
R7060
R7001
62K
1
CHGR_SGATE
57.6K
5%
1/16W
MF-LF
402
2
59C5
45B3
59B8
R7061 1
CHGR_AMON
1
VCC
1UF
9.31K
1%
10%
10V 2
X5R
402-1
VDD
2
C
43B3
43B3
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
NC
CHGR_ACIN
1
10%
16V
X5R
402
2
0.033UF
1
R7045
1
56.2K
1%
1/16W
MF-LF
402 2
C7044
0.01UF
10%
16V
2 CERM
402
59C4 59B6
CHGR_ICOMP 5
CHGR_VCOMP 7
CHGR_VNEG 8
CHGR_CSOP 18
CHGR_CSON 17
CHGR_VCOMP_R
C7045 1
C7043
0.1UF
1
2
10%
16V
X5R
402
ICOMP
VCOMP
VNEG
CSOP
CSON
5%
1/16W
MF-LF
402
1
2
C7040
10%
2 10V
X5R
402-1
QFN
2
1
CHGR_AGATE
CHGR_CSIP
CHGR_CSIN
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
LGATE 21
CHGR_LGATE
5%
1/16W
MF-LF
402
2
1
2
2
1
2
0.1UF
MIN_NECK_WIDTH=0.3 MM
0.5%
1W
MF
2 0612-1
MIN_LINE_WIDTH=0.6 MM
PP18V5_S5_CHGR_SW_R
CRITICAL
CRITICAL
10%
25V
X5R
402
2
10%
25V
X5R
402
GND_CHGR_SGND 59B6
C7020
2
20%
25V
POLY-TANT
CASE-D2-SM
5
1
C7021
2
20%
25V
2
POLY-TANT
CASE-D2-SM
2
1 2 3
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
PPVBAT_G3H_CHGR_REG
2
4.7UH-9.5A
IHLP4040DZ-SM
5
1
CHGR_VNEG_R
DIDT=TRUE
2
1
2
4
PPVBAT_G3H_CHGR_OUT
1
RJK0305DPB
LFPAK-HF
10%
2 50V
X7R
402
GND_CHGR_SGND
C7011 1
1UF
C7008
10%
25V
2 X5R
20%
16V
POLY-TANT
CASED2E-SM
603-1
CRITICAL
2
59A5
C7028
0.001UF
20%
50V
CERM
402
PWM FREQ. = 400 kHz
MAX CURRENT = 7A
1 2 3
(??? limited)
R7031
10
5%
1/16W
MF-LF
402
470PF
10%
50V
CERM 2
402
1
3
1206
Q7021
C7026
0.001UF
(CHGR_CSOP)
C7046 1
CRITICAL
0.5%
1W
MF
0612-1
33UF
3.01K
59C4 59B8
7AMP
0.01
L7000
TO SYSTEM
7C2
F7000
R7008
CRITICAL
=PPBUS_G3H
2
CRITICAL
DIDT=TRUE
C
20%
50V
CERM
402
1
C7025 1
10%
25V
X5R
402
XW7000
SM
1%
1/16W
MF-LF
402 2
2
C7027
0.001UF
CRITICAL
4
R7046
1
1UF
LFPAK-HF
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
1
2
C7023
10%
25V
X5R
603-1
RJK0305DPB
0.1UF
CHGR_AMON 59D4
45B3
59B8
CHGR_BMON 45A6
=CHGR_ACOK 41D4
C7022 1
1UF
10%
25V
X5R
603-1
Q7020
2
1
1
22UF
CRITICAL
59B8
4
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
1
22UF
0.1UF
DIDT=TRUE
10%
50V
CERM 2
402
B
R7020
0.02
XW7021
SM
0.001UF
GND_CHGR_SGND
1CRITICAL
C7061 1 C7062
TRKL* 13 NC
AMON 9
BMON 15
ACOK 14
1
CHGR_CSIN_XW7021
CHGR_BGATE
CHGR_DCIN 59D8
BOOT 25
UGATE 24
PHASE 23
TL331
XW7020
SM
R7021
10
0.047UF
10%
10V
CERM
402
16
59A3
BGATE
DCIN 2
U7060
CHGR_CSIP_XW7020
C7024 1
VDDP
U7000
4 VREF
3 ACIN
R7023
10
1UF
12 VHST
AGATE 1
11 SCL
CSIP 28
10 SDA CRITICALCSIN 27
29 THRM_PAD
C7042
1
CHGR_LOWCURRENT_GATE
SOT23-5
CHGR_VDDP
5%
1/16W
MF-LF
402
1UF
10%
ISL6258A
R7011
C7041
10V
X5R
402-1
C7047 1
1
1/16W
MF-LF
402
=PP3V42_G3H_CHGR
2
R7040
4.7
26
6 AGND
59D5 59A8 7D1
2 CHGR_VDD 1
19
10%
25V 2
X5R
402
1
20
59A8
22 PGND
(CHGR_ACIN)
62K
CRITICAL
2
1%
1/16W
MF-LF
402
2
2
5%
1/16W
MF-LF
402
2
4
GND
3
CHGR_LOWCURRENT_REF
100K
5%
1/16W
MF-LF
402
R7062 1
10%
25V
X5R
402
5
1.82K
0.1UF
0.1UF
2
1%
1/16W
MF-LF
402 2
2
CHGR_LOWCURRENT_GATE_R 1
C7060
1
1
1
C7010 1
R7099
59C6 59A8 7D1
30.1K
CHGR_DCIN
D
5
=PP3V42_G3H_CHGR
4
C7063
G
2
SOD-723-HF
4
1SS418
1
D
1
D7010
S
D
2
1
3
D
5
MIN_LINE_WIDTH=0.6 MM
LFPAK-SM
2 3
LFPAK-SM
PPVDCIN_G3H_PRE2
HAT1127H
=PP18V5_G3H_CHGR
S
Q7000
7C1
(CHGR_CSON)
80D3 45A8
B
CHGR_CSO_R_P
R7047
10
80D3 45A8
CHGR_CSO_R_N
5%
1/16W
MF-LF
402
(CHGR_CSO_R_N)
AMON PULLDOWN LOGIC
=PP3V42_G3H_CHGR
R70751
1M
Q7050
SI7137DP
59C1
1
CHGR_VDD_L
C7050
0.01uF
Q7070
10%
2 16V
CERM
402
D 3
SSM6N15FEAPE
SOT563
A
59C6
1
CRITICAL
SO-8
PPVBAT_G3H_CHGR_OUT
C7051
0.1UF
D
S 1
5%
1/16W
MF-LF
402
2
S
5%
1/16W
MF-LF
402 2
2 G
BATTERY CHARGE LIMITING FETS
NOSTUFF
5
D 6
2 3
1M
Q7070
SSM6N15FEAPE
SOT563
BATT_POS_F
6A7 58A7 58B8
1
R70741
10%
2 16V
X5R
402
PBUS Supply/Battery Charger
G
59D5 59C6 7D1
CHGR_AMON
4
59D4 59C5 45B3
SYNC_MASTER=RAYMOND
R70731
5 G
CHGR_BGATE
S 4
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
59C5
1K
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5%
1/16W
MF-LF
402 2
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
CHGR_VDD_R
APPLE INC.
7
6
5
4
3
2
REV.
051-7898
SCALE
SHT
NONE
8
SYNC_DATE=01/31/2008
NOTICE OF PROPRIETARY PROPERTY
CHGR_VDD
4.7.0
OF
59
1
81
A
8
6
7
2
3
4
5
1
5V_S3/3.3V_S5 POWER SUPPLY
D
VOUT = (2 * RA / RB) + 2
ROUTING NOTE:
Place XW7203 by Pin1 OF L7260.
SM
2
1%
1/16W
MF-LF
402
5V_S3_VFB_XW7203
1
VOUT = (2 * RC / RD) + 2
<RA>
<RB>
<RD>
<RC>
R7267
R7268
R7269
15.0K
10K
10K
XW7203
2
1
R7270
6.49K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1
D
2
1
1%
1/16W
MF-LF
402
2
1
Place XW7204 by Pin 2 of L7220.
SM
3V3S5_VFB_R7270
2
ROUTING NOTE:
XW7204
2
1
60B5
GND_5V3V3S5_SGND
XW7205
66D8 40D5 6C3
C
60C7 7C1
ROUTING NOTE:
2
1
R7273
C7272
1UF
100K
5%
1/16W
MF-LF
402
10%
2 25V
X5R
603-1
1
1
=PPVIN_S3_5VS3
2
5V3V3S5_REG3
5VS3_3V3S5_VREF
C7260
0.1UF
10%
5
CRITICAL
16V
X5R
402
D
Q7260
2
SI7110DN
PWRPK-1212-8-HF
B
1
3 2 1
DIDT=TRUE
DIDT=TRUE
5V_S3_DRVH
21 DRVH1
5V_S3_LL
20 LL1
5
VOLTAGE=5V
5V_S3_ENTRIP
D
50V
CERM
402
2 6.3V
X5R
0.001UF
20%
2
C7290
10UF
C7293
1
20%
603
CRITICAL
1
Q7261
C7291
G
SI7108DN
220UF
20%
2 6.3V
ELEC
D1A-SM
QFN
2 VFB1
DIDT=TRUE
1
3 2 1
CRITICAL
2
1/16W
MF-LF
402
9 4 3 2
1
VO2 7 3V3S5VO2
ENTRIP2 6
0.001UF
1
PWM FREQ. = 375 KHZ
MAX CURRENT = 4A
2
CRITICAL
4.7UH-5.5A
=PP3V3_S5_REG
IHLP2525CZ
3V3S5_ENTRIP
EN0 13 5V3V3_REG_EN
GND THRM_PAD
1
C7273
10UF
20%
2 6.3V
X5R
603
GND_5V3V3S5_SGND
1
1
R7272
2
1/16W
MF-LF
402
1
C7250
10UF
1
20%
20%
2 6.3V
POLY
B1A-SM
7 6 5
1
C7251
150UF
75K
1%
B
7B4
VOLTAGE=3.3V
CRITICAL
Q2
NC
PGOOD 23
C7242
20%
2 50V
CERM
402
Q7220
10
SW
8
VFB2 5 3V3S5_VFB
2
20%
16V
POLY
B1A-SM
L7220
Q1
DIDT=TRUE
1
39UF-0.027OHM
FDMS9600S
MLP
CRITICAL
1
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
1 C7240
10%
2 25V
X5R
603-1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDT=0.2 DIDT=TRUE
DRVL2 12 3V3S5DRVL
1 ENTRIP1
60C4
D 6
DRVH2 10 3V3S5_DRVH
CRITICAL
C7241
1UF
C7220
2
DIDT=TRUE
LL2 11 3V3S5_LL
R7271
86.6K
1%
1
16V
X5R
402
VBST2 9 3V3S5_VBST
VCLK 18
4
S
PWRPK-1212-8-HF
U7200
=PPVIN_S5_3V3S5
0.1UF
10%
VREG3 8
VREG5 17 5V3V3S5_REG5
24 VO1
5V_S3_VFB
PCMB104E4R7-SM
VREF
CRITICAL
19 DRVL1
5V_S3_DRVL
7C4
1
22 VBST1
5V_S3_VO1
CRITICAL
4.7UH-13A-15MOHM
=PP5V_S3_REG
5V_S3_VBST
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
603
4 TONSEL
7C1
10UF
20%
2 6.3V
X5R
VIN
14 SKIPSEL
10%
2 10V
CERM
402
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2
C7271
0.22UF
MIN_LINE_WIDTH=0.6 MM
DIDT=TRUE
S
L7260
MAX CURRENT = 8A
PWM FREQ. = 300 KHZ
4
G
1
1
C7270
3
2
C7281
1UF
10%
2 25V
X5R
603-1
20%
16V
POLY
B1A-SM
25
39UF-0.027OHM
1
16
20%
50V
2 CERM
402
1
TPS51125
C7282
0.001UF
CRITICAL
1 C7280
15
1
1
C
SM
2
60C6 7C1
SMC_PM_G2_EN
ROUTING NOTE:
Place XW7205 by C7252.
=PPVIN_S3_5VS3
XW7202
Place XW7202 by C7292.
SM
2 6.3V
X5R
603
2
C7253
0.001UF
20%
50V
CERM
402
2
XW7201
SM
Q7221
SSM6N15FEAPE
P5V3V3_PGOOD
66A5
SOT563
ROUTING NOTE:
=P5VS3_EN_L
66C6
IN
2
G
S 1
D 3
Q7221
Place XW7201 between Pin 15 and Pin 25 of U7200.
SSM6N15FEAPE
5V/3.3V SUPPLY
SOT563
A
=P3V3S5_EN_L 5
66D6
IN
SYNC_MASTER=RAYMOND
G
S 4
SYNC_DATE=02/08/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
60
1
81
A
8
6
7
2
3
4
5
1
1.5V/0.75V(DDR3) POWER SUPPLY
D
402
25D3 7C4 =PPVTT_S3_DDR_BUF
1
1
50V
CERM
402
0.1%
1/16W
MF
402
2
2
C7340
0.033UF
1
10%
16V
X5R
402
1
1V5S3_V5FILT
2
10%
10V
X5R
402-1
C7301
10UF
20%
2 6.3V
X5R
603
1
C7300
1UF
=PP5V_S3_1V5S30V75S0
2
R7307
4.7
5%
1/16W
MF-LF
402
7C3
C7302
1
10UF
20%
6.3V
X5R
603
2
1V5S3_VDDQSNS
=PP0V75_S0_REG
ROUTING NOTE:
XW7301
SM
1V5S3_VTTSNS
1
Place XW7301 by L7320.
2
C
7C8
1
R7310
10.7K
VDDQSET VTTREF VLDOIN VTT V5FILT
0
PGOOD
CRITICAL
QFN
CS
ROUTING NOTE:
ROUTING NOTE:
Place XW7303 by C7308.
C7308
22UF
20%
6.3V
2 X5R-CERM-1
603
19 1V5S3_DRVL
MODE
4
NC0
NC1
C7309
0.1uF
10%
16V
X5R
402
D
4
CS_GND
B
GND
PGND
VTTGND
GND_1V5S3_SGND
S
1 2 3
DIDT=TRUE
GND_1V5S3_CSGND
PWRPK-1212-8-HF
2
C7330
1
CRITICAL
20%
16V
POLY
B1A-SM
1
20%
16V
POLY
B1A-SM
10%
2 25V
X5R
603-1
39UF-0.027OHM
2
C7332
C7331
1
1UF
C7333
0.001UF
2
20%
50V
CERM
402
MAX CURRENT = 12A
PWM FREQ. = 400 KHZ
PUT ONE BULK CAP NEXT TO THE LOAD
=PP1V5_S3_REG
VOLTAGE=1.5V
MIN_LINE_WIDTH=1.5 mm
MIN_NECK_WIDTH=0.25 mm
2
7D4
CRITICAL
5
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
1
CRITICAL
DIDT=TRUE
7 NC
12 NC
CRITICAL
39UF-0.027OHM
SM-IHLP-1
1
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
D
4
G
CRITICAL
1
SI7108DN
20%
2 2.5V
TANT
CASE-B2-SM
Q7321
PWRPK-1212-8-HF
1
C7342
330UF
C7343
1
330UF
C7341
10UF
20%
2 2.5V
TANT
CASE-B2-SM
20%
2 6.3V
X5R
603
C7344
0.001UF
2
20%
50V
CERM
402
1 2 3
1
1
DDRREG_PGOOD
2
XW7300
SM
ROUTING NOTE:
PUT 6 VIAS UNDER THE THERMAL PAD
1
7C1
CRITICAL
L7320
1.0UH-13A-5.6M-OHM
G
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
CRITICAL
Q7320
SI7110DN
S
THRM_PAD
1
CRITICAL
DIDT=TRUE
2
21 1V5S3_DRVH
20 1V5S3_LL
DRVL
CONNECT CS_GND TO
Q7321 PIN1,2.3
USING KEVIN CONNECTION.
25
C7307
22UF
20%
6.3V
2 X5R-CERM-1
603
1
13
5
1V8S3_VBST_RC
DIDT=TRUE
18
16
COMP
3
1V5S3_CS
DRVH
LL
TPS51116
17
SM
2
6
CRITICAL
1
S3
S5
U7300
SYM (1 OF 2)
1
=DDRREG_EN
=PPVIN_S5_1V5S30V75S0
1
10
11
XW7303
66C6
=DDRVTT_EN
2
5%
1/16W
MF-LF
402
VBST V5IN VDDQSNS VTTSNS
1%
1/16W
MF-LF
2 402
67A3 24C1
1
R7300
2
8
15
22
14
24
5
23
1V5S3_VBST
DIDT=TRUE
9
C
D
VOUT = 0.75V * (1 + RA / RB)
NO STUFF
<RB>
1
2
1
2
1V5S3_VDDQSET
R7322
<RA> C7303
20K
0.1%
100PF
R7321 5%
1/16W
MF
20K
R7399
100K
ROUTING NOTE:
Place XW7300 between
Pin 3 and Pin 25
of U7300.
1
2
XW7302
SM
B
66A2
5%
1/16W
MF-LF
402
2
=PP3V3_S3_PDCISENS
7D3
ROUTING NOTE:
Place XW7302 by Q7321.
STATE
PM_SLP_S4_L
PM_SLP_S3_L
PP1V5_S3
PP0V75_S0
S0
HIGH
HIGH
1.5V
0.75V
S3
HIGH
LOW
1.5V
0.0V
S5/G3HOT
LOW
LOW
0.0V
0.0V
1.5V/0.75V DDR3 SUPPLY
A
SYNC_MASTER=RAYMOND
SYNC_DATE=01/31/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
61
1
81
A
8
62D8 62C3 7B1
1
R7412
1
10
5%
1/16W
MF-LF
402
1UF
10%
6.3V
CERM
402
1
R7420
10
2
C7430
R7421
0.1uF
GND_IMVP6_SGND
NO STUFF
R7427
1
73A3
1
2
73A3
2
R7445
1
NO STUFF
C7410
0.01uF
1
1%
1/16W
MF-LF
2 402
IMVP6_NTC_R
10%
16V
CERM
402
C
499
ERT-J0EV474J
73A3
73A3
R7447
2
NO STUFF
R7406
45B3
0
5%
2 402
CPU_VID<6>
10B6 CPU_VID<5>
10B6 CPU_VID<4>
10B6 CPU_VID<3>
73A3
10B6 CPU_VID<2>
73A3
10B6 CPU_VID<1>
10B6 CPU_VID<0>
1
1
FROM SMC
24A8
2
OUT
147K
1%
0.015uF
1
QFN
2 PSI*
3 IMON
48 3V3
47 CLK_EN*
DIDT=TRUE
IMVP6_UGATE1
62A8
34
IMVP6_PHASE1
62A8
32
33
IMVP6_LGATE1
(GND)
24
IMVP6_ISEN1
62A8
UGATE2 27
IMVP6_UGATE2
62A6
PHASE2 28
IMVP6_PHASE2
62A6
30
IMVP6_LGATE2
(GND)
PHASE1
LGATE1
PGND1
ISEN1
LGATE2
PGND2
29
IMVP6_ISEN2
IMVP6_SOFT
7 SOFT
VSUM
OCSET 8
19
62A4
IMVP6_RBIAS
4 RBIAS
IMVP6_VSUM
IMVP6_OCSET
IMVP6_VO
IMVP6_DROOP
62A4
IMVP6_VDIFF
13 VDIFF
VO
18
DROOP 16
1
R7409
1%
1/16W
MF-LF
2 402
1
0.001UF
10%
50V
CERM
402
2
1K
DFB
C7406
1
62A4
62A4
R7413
1K
IMVP6_VDIFF_RC
1
IMVP6_FB2
IMVP6_FB
62A4 IMVP6_COMP
62A4 IMVP6_VW
2
NO STUFF
R7411
1%
1/16W
MF-LF
402
12 FB2
11 FB
VSEN
10 COMP
9 VW
RTN
GND
1%
1/16W
MF-LF
2 402
62A4
62C8
1
IMVP6_COMP_RC
2
1
R7414
C7413
220PF
1
5%
25V
CERM
402
2
C7407
1
1%
1/16W
MF-LF
2 402
0.001UF
R7410
DIDT=TRUE
2
62A4
1
2
C7427
1
0.1UF
C7431
0.068UF
10%
10V
CERM
402
62A4
0.1UF
62C6
62C6
62C6
62C6
62C6
NO STUFF
62A4
C7416
1
R7418 R7417
1%
1/16W
MF-LF
2 402
10%
50V
CERM
402
2
5.36K
1%
1/16W
MF-LF
402
1
C7429
180pF
5%
2 50V
CERM
402
1
2
1
2
R7404
1
0.22uF
5%
1/16W
MF-LF
10%
6.3V
CERM-X5R
402
402
=PPVIN_S5_CPU_IMVP
CRITICAL
CRITICAL
C7401
33UF
20%
16V
POLY-TANT
CASED2E-SM
1
402
1
2
C7408
33UF
C
C7411
1
10%
25V
X5R
603-1
2
1
20%
16V
POLY-TANT 2
CASED2E-SM
1UF
C7422
0.001UF
20%
50V
CERM
402
RJK0305DPB
LFPAK-HF
(IMVP6_PHASE2)
1
R7401
3.65K
1%
1/16W
MF-LF
2 402
1
5
L7401
CRITICAL
DIDT=TRUE
MPC1055-SM
MPC1055LR36
DCR=0.8MOHM
RJK0328DPB
4
1%
1/16W
MF-LF
402
1 2 3
R7430
3.92K
C7428
10%
16V
CERM
402
2
10%
10.0V
CERM-X5R 2
402
10%
6.3V
CERM-X5R
402
0.12UF
1
2
R7405
10K
C7434 1
1
0.22UF
R7415
11K
1%
1/16W
MF-LF
2 402
2
1
1
2
CRITICAL
R7431
1
C7404
20%
50V
CERM
402
2
1
0.22uF
5%
1/16W
MF-LF
402
B
NO STUFF
2
1
C7402
1
0.0022UF
R7452
10K
R7443
3.65K
10%
50V
CERM
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
10KOHM-5%
(IMVP6_ISEN2)
2
(IMVP6_VSUM)
ERT-J1VR103J
(IMVP6_VO)
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
2
C7421
1
10%
6.3V
CERM-X5R
402
5%
1/16W
MF-LF
2 402
0.22uF
IMVP6_PHASE2
IMVP6_BOOT2
IMVP6_UGATE2
IMVP6_LGATE2
IMVP6_ISEN2
R7423
0
1
R7422
0
5%
1/16W
MF-LF
2 402
CPU_VCCSENSE_P
CPU_VCCSENSE_N
10B5 73A3
10A5 73A3
62C6
62C8 62B7
62C6
62C6
62B6
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
62B7
62B7
62B7
62B7
62B7
IMVP6_OCSET
IMVP6_VSUM
GND_IMVP6_SGND
IMVP6_VO
IMVP6_DROOP
IMVP6_DFB
IMVP6_SOFT
IMVP6_RBIAS
IMVP6_VDIFF
IMVP6_FB2
IMVP6_FB
IMVP6_COMP
IMVP6_VW
IMVP6_RTN
IMVP6_VSEN
MIN_LINE_WIDTH
0.25 MM
0.25 MM
0.50 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
MIN_NECK_WIDTH
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.20 MM
0.25 MM
IMVP6 CPU VCore Regulator
SYNC_MASTER=RAYMOND
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
0.25 MM
0.25 MM
0.25 MM
0.25 MM
5
4
3
SYNC_DATE=01/31/2008
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
D
APPLE INC.
2
REV.
051-7898
SCALE
SHT
NONE
6
C7423
0.001UF
R7407
10%
6.3V
CERM-X5R
402
NO STUFF
IMVP6_VO_R
2
2
LFPAK-HF
1
1%
1/16W
MF-LF
2 402
1
0.36UH-30A-0.80MOHM
Q7403
1%
1/16W
MF-LF
2 402
1
2
CRITICAL
2
13.7K
(IMVP6_VO)
1 2 3
DIDT=TRUE
R7416
62B5
7
20%
50V
CERM
402
2
Q7402
62A4
62B6
8
C7420
0.001UF
2
C7403
10K
1%
1/16W
MF-LF
10%
50V
CERM
402
CRITICAL
62C7
62C6
C7400
0.0022UF
62A4
62C7
MIN_NECK_WIDTH
0.25 MM
0.25 MM
0.25 MM
0.25 MM
0.25 MM
1
2
R7400
NO STUFF
4
1
1
2
1
1
1/16W
MF-LF
402
DIDT=TRUE
IMVP6 CPU VCORE REGULATOR
62C6
MPC1055-SM
1
62C6
62C6
0.36UH-30A-0.80MOHM
RJK0328DPB
5
1K
2
7D8
MPC1055LR36
DCR=0.8MOHM
1 2 3
1
D
=PPVCORE_S0_CPU_REG
2
(IMVP6_ISEN1)
0.018UF
1
IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
4
C7415
0.001UF
1
PWM FREQ. = 300 KHZ
MAX CURRENT = 44A
1
Q7401
62A4
1
20%
50V
CERM
402
L7400
10%
16V
X7R
402
XW7400
SM
62C6
(IMVP6_PHASE1)
0603-LF
OMIT
62C6
2
NO STUFF
R7451
10K
1%
10%
16V
2 X5R
402
10%
16V
X5R
402
C7433
(IMVP6_COMP)
MIN_LINE_WIDTH
1.5 MM
0.25 MM
1.5 MM
1.5 MM
0.25 MM
20%
16V
POLY-TANT 2
CASED2E-SM
C7419
0.001UF
LFPAK-HF
C7432
1
6.81K
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
A
1
1UF
CRITICAL
62A6
0.01UF
10%
50V
CERM
402
97.6K
1%
1/16W
MF-LF
2 402
C7418
10%
25V
X5R
603-1
CRITICAL
62D8 62D4 7B1
VOLTAGE=0V
(IMVP6_VW)
10%
50V
CERM
402
2
1
1-PHASE DCM
62A6
NO STUFF
470PF
1 2 3
DIDT=TRUE
2
62A4
15
49
1
GND_IMVP6_SGND
C7414
1
2
C7417
33UF
62A8
IMVP6_DFB
14
TPAD
21
(IMVP6_FB)
B
17
25 NC
255
5%
1/16W
MF-LF
402
35
UGATE1
ISEN2 23
62A4
2
26
0
IMVP6_BOOT162A8
IMVP6_BOOT2 62A6
5 VR_TT*
6 NTC
IMVP6_VR_TT
IMVP6_NTC
1/16W
MF-LF
402
10%
16V
X7R
402
CRITICAL
LOAD LINE SLOPE = -2.1 MV/A
2 IMVP6_BOOT2_RC
R7425
DIDT=TRUE
U7400BOOT2
44 VR_ON
IMVP_VR_ON
VR_PWRGOOD_DELAY 1 PGOOD
IN
R7408
C7405
20%
16V
POLY-TANT
CASED2E-SM
1
LFPAK-HF
1-PHASE DCM
DIDT=TRUE
PVCC
BOOT1 36
46 DPRSTP*
45 DPRSLPVR
IMVP6_IMON
40D8
VDD
39 VID2
38 VID1
37 VID0
(NC)
2
2
C7409
33UF
1-PHASE CCM
IMVP6_BOOT1_RC
2
402
1
31
CRITICAL
41 VID4
40 VID3
1/16W
MF-LF
CPU_PROCHOT_L 402
73C3 41D4 13B6 9C5
22
20
43 VID6
42 VID5
IN
OUT
CRITICAL
RJK0305DPB
5%
1/16W
MF-LF
5%
1/16W
MF-LF
2
CPU_DPRSTP_L
73B3 IMVP_DPRSLPVR
9B2
IN CPU_PSI_L
73B3 13A3 9B2
2-PHASE CCM
R7424
2.0K
73A3 10B6
CRITICAL
1
0
1
0
Q7400
4
DIDT=TRUE
0
VIN
R7426
470K
402
OPERATION MODE
DIDT=TRUE
NO STUFF
4.02K
1%
1/16W
MF-LF
402
1
1
1
10%
16V
X5R
402
10
5%
1/16W
MF-LF
402
1
CRITICAL
1
5
PP3V3_S0_IMVP6_3V3
2
PSI*
1
1
0
0
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
=PP3V3_S0_IMVP1
62B7 62A4
0.01UF
10%
16V
CERM
402
IMVP6_VSEN
7C5
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
C7496
1
DPRSTP*
0
0
1
1
20%
6.3V
X5R
603
PPVIN_S5_IMVP6_VIN
2
5%
1/16W
MF-LF
402
PM_DPRSLPVR
DPRSLPVR
10UF
2
=PPVIN_S5_CPU_IMVP
IN
C7435
1
IMVP6_RTN
62D4 62C3 7B1
5
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
C7426
ISL9504BCRZ
D
2
=PPVIN_S5_CPU_IMVP
PP5V_S0_IMVP6_VDD
2
2
3
4
5
=PP5V_S0_CPU_IMVP
7D5
73B3 20C7
6
7
4.7.0
OF
62
1
81
A
8
6
7
2
3
4
5
1
MCP VCORE POWER SUPPLY
7C1
D
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
5V_S0_MCPREG_VIN
R7593
C7550 1
2
1K
20C3 20A3
IN
IN
MCP_VID<0>
1
2
5%
1/16W
MF-LF
402
MCP_VID<1>
R7591
R7592
20C3 20A3
IN
MCP_VID<2>
1
0
0
1
MCPCORES0_SOFT
MCPCORES0_IMON_R
66A5
OUT
5%
1/16W
MF-LF
402
1NOSTUFF 1NOSTUFF
R7580 R7581
20.0K
PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE
PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE
1%
1/16W
MF-LF
2 402
20.0K
66C1
1%
1/16W
MF-LF
2 402
IN
MCPCORES0_PGOOD
MCP_VID0_R
MCP_VID1_R
MCP_VID2_R
MCPCORES0_OS0
MCPCORES0_OS1
=MCPCORES0_EN
MCPCORES0_FDE
MCPCORES0_VW
20.0K
1%
1/16W
MF-LF
2 402
MCPCORES0_COMP
2
1 2 3
MCPCORES0_PHASE
PPMCPCORE_S0_R
1NO
SPM6550T-COMBO
MCPCORES0_LGATE
4
GATE_NODE=TRUE
DIDT=TRUE
2
4
(Q7560 Limit)
=PPMCPCORE_S0_REG
1
3
10UF
20%
4V
X5R 2
603
MCPCORE_SNUBBER
MICROFET3X3
1
S
1
1
NO STUFF
2
C7567
10UF
C7589
2 3
f = 300 kHz
CRITICAL
1
FDMC8678S
G
20%
2 4V
X5R
603
0.001UF
50V 10%
X7R 402
C7565
R7566
20
1
MCPCORES0_RSEN_P
2
1%
1/16W
MF-LF
402
1
R7568
20
1
MCPCORES0_RSEN_N
1%
1/16W
MF-LF
402
2
C7576 1
1%
1/16W
MF-LF
2 402
(MCPCORES0_VSEN)
0.1UF
10%
16V
X7R-CERM 2
402
C7570
ICOMP 10
MCPCORES0_ICOMP
7 VDIFF
20
VSS
1
0.001UF
10%
2 50V
X7R
402
1
R7573
10K C7573 1
1%
1/16W
MF-LF
2 402
47PF
5%
50V
CERM 2
402
R7500
100
1
2
MCPCORES0_ISP_R
1%
1/16W
MF-LF
402
XW7561
SM
2
(MCPCORES0_ISN)
1
R7575
47.0K
1%
1/16W
MF-LF
2 402
1
R7571
100
1
C7575
47PF
5%
2 50V
CERM
402
(MCPCORES0_ICOMP)
1%
1/16W
MF-LF
2 402
B
1%
1/16W
MF-LF
402
150K
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
10%
50V
2 X7R
402
(MCPCORES0_RTN)
C
C7569
0.001UF
11.3K2
THRM_PAD
GND_MCPCORES0_AGND1
20%
2 2V
TANT
CASE-B4-SM
1
R7572
1%
1/16W
MF-LF
2 402
CRITICAL
C7568
270UF
20%
2 2V
TANT
CASE-B4-SM
(MCPCORES0_VO)
MCPCORES0_OCSET
MCPCORES0_ISP
MCPCORES0_ISN
1
270UF
R7569
ISP 13
ISN 11
6 FB
PGND
MCPCORES0_VO
OCSET 3
7C8 63B8 63C7
C7566 1
5%
1/10W
MF-LF
2 603
CRITICAL
Q7565
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
1%
1W
MF-1
0612
1
5
LGATE 21
STUFF
MAX CURRENT: 13A
0.001
L7560
0.82UH-16A
R7589
(MCPCORES0_LGATE)
R7525
CRITICAL
CERM-X7R
10V
603
5%
(MCPCORES0_PHASE)
SWITCHNODE
DIDT=TRUE
D
5 COMP
=PPMCPCORE_S0_REG
OMIT
CRITICAL
S
SWITCH_NODE=TRUE
DIDT=TRUE
VO 12
1%
1/16W
MF-LF
2 402
100
1
0.25 MM
0.2 MM
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
20.0K
R7563
XW7563
SM
1
2
MCPCORES0_BOOT_R
2
10%
2 25V
X5R
603-1
1
1
1
2
=PPMCPCORE_S0_REG
OMIT
PHASE 19
0
5%
1/10W
0.2 MM MF-LF
0.25 MM 603
MCPCORES0_BOOT
1UF
FDMC8676
C7564
0.22UF
R7565
MCPCORES0_UGATE 1
20%
2 16V
POLY-TANT
CASE-D2E-SM
C7561
POWER33-SM
GATE_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
20%
2 16V
POLY-TANT
CASE-D2E-SM
1
Q7560
G
4 VW
MCPCORES0_VDIFF
63C7 63C1 7C8
BOOT 17
68UF
R7582 1R7583
MCPCORES0_FB
PLACE XW NEAR THE MCP,
CONNECT SENSE LINES TO CLOSEST
MCPCORE AND GND BALL
OF MCP
PGOOD
VID0
VID1
VID2
OFFSET0
OFFSET1
VR_ON
AF_EN
FDE
VSEN
RTN
UGATE 18
C7571
1
PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE
PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE
XW7562
SM
28 IMON
4
(MCPCORES0_UGATE)
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VIN 14
QFN
2 SOFT
31
25
26
27
23
24
29
30
32
8
9
MCPCORES0_VSEN
MCPCORES0_RTN
C
63C1 63B8 7C8
1 RBIAS
U7500
2
5%
1/16W
MF-LF
402
2
MCPCORES0_RBIAS
D
PVCC
33
20C3 20A3
VDD
ISL6263D
5%
1/16W
MF-LF
2 402
1
68UF
5
1UF
D
CRITICAL
C7560
1
10%
50V 2
X7R
402
C7562
10%
2 16V
X5R
402
22
R7561
R7590
0
1
10%
16V 2
X5R
402
1
C7563 1
7D5
0.001UF
1UF
5%
1/16W
MF-LF
402
CRITICAL
=PP5V_S0_MCPREG
2
5%
1/10W
MF-LF
603
16
MCPCORES0_IMON
0
2.2
1
15
45D8
1
=PPVIN_S0_MCPCORE
R7560
B
(MCPCORES0_VW)
C7580
68PF
1
2
5%
50V
CERM
402-1
C7579 1
0.001UF
10%
50V 2
X7R
402
C7581
R7577
560PF
133K 2 MCPCORES0_COMP_C
1
2
1
1%
1/16W
MF-LF
402
10%
50V
CERM
402
R7578
1
100
1%
1/16W
MF-LF
402
A
2
1
R7576
VID<2:0>
MCP TARGET
6.98K
1%
1/16W
MF-LF
2 402
(MCPCORES0_COMP)
(MCPCORES0_FB)
C7582
560PF
1
2
MCPCORES0_VDIF_C
10%
50V
CERM
2.21K2
402
1
(MCPCORES0_VDIFF)
1%
1/16W
MF-LF
402
R7579
000
+1.05V
001
+1.00V
010
+0.95V
011
+0.90V
100
+0.85V
101
+0.80V
110
+0.75V
111
+0.70V
MCP CORE REGULATOR
SYNC_MASTER=K19_MLB
SYNC_DATE=12/10/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
63
1
81
A
8
6
7
2
3
4
5
1
CPUVTT POWER SUPPLY
D
7C1
D
=PPVIN_S0_CPUVTTS0
CRITICAL
C7630
1
1
20%
16V
POLY-TANT
CASED2E-SM
C7695
1
1UF
33UF
2
2
10%
25V
X5R
603-1
C7696
0.001UF
20%
50V
CERM
402
2
C
C
Q7620
FDMS9600S
9 4 3 2
MLP
CRITICAL1
7D5
L7620
=PP5V_S0_CPUVTTS0
R7601
Q1
PP5V_S0_CPUVTTS0_V5FILT
R7603 1
C7601
1
10%
10V
X5R
402-1
2
1UF
66C1
66A5
10
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
V5FILT
2
U7600
10%
6.3V
X5R-CERM
603
=CPUVTTS0_EN
1
2
CPUVTTS0_TON
CPUVTTS0_PGOOD
6
PGOOD
VBST
14
CPUVTTS0_VBST
3
VOUT
DRVH
13
5
VFB
LL
12
11
TRIP
DRVL
THRM_PAD
7
1
2
XW7665
Q2
CPUVTTS0_DRVH
GATE_NODE=TRUE
CPUVTTS0_LL
SWITCH_NODE=TRUE
9
CPUVTTS0_DRVL
GATE_NODE=TRUE
PGND
C7603
1
1
7 6 5
0.1UF
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
10%
50V
X7R
603-1
2
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
CPUVTTS0_VSNS
MIN_LINE_WIDTH=0.6MM DIDT=TRUE
MIN_NECK_WIDTH=0.2MM
R7670
8.45K
R7604
1%
1/16W
MF-LF
2 402
8.87K
1%
1/16W
MF-LF
2 402
XW7600
<Ra>
SM
1
PCMB065T-SM
2
1
15
GND
10
SW
SM
IN
CPUVTTS0_TRIP
1%
1/16W
MF-LF
402
4.7UF
V5DRV
CRITICAL
OUT
CPUVTTS0_VFB
200K
C7604
TPS51117RGY_QFN14
SYM QFN
(2 OF 2)
EN_PSV
TON
(=PPCPUVTT_S0_REG)
B
1
8
8
2
4
301
1%
1/16W
MF-LF
402
2
NO STUFF
C7670
1
100PF
5%
50V
CERM
402
2
(GND)
ROUTING NOTE:
7D8
R7671
1
VOUT = 1.062V
8A max output
F = 320 KHZ
C7665
10UF
2
20%
6.3V
X5R
603
CRITICAL
C7660
330UF
20%
2.5V
TANT
CASE-B2-SM
2
20%
50V
CERM
402
0.001UF
1
2
2
XW7601
1
1%
1/16W
MF-LF
2 402
ROUTING NOTE:
<Rb>
GND_CPUVTTS0_SGND
C7661
B
20.0K
Place XW7600 between Pin 7 and Pin 15 of U7600.
1
SM
1
PLACEMENT_NOTE=Place XW7665 next to L7620
1
=PPCPUVTT_S0_REG
2.2UH-8.0A
1
2 CRITICAL
Place XW7601 by C7660.
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)
(CPUVTTS0_VFB)
CPUVTTS0_VOUT
(=PPCPUVTT_S0_REG)
CPU VTT(1.05V) SUPPLY
A
SYNC_MASTER=RAYMOND
SYNC_DATE=02/08/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
64
1
81
A
8
6
7
2
3
4
5
1
1.8V S0 SWITCHER
D
7B5
D
=PP3V3_S0_P1V8S0
CRITICAL
1
C7760
10uF
20%
6.3V
X5R
603
CRITICAL
VI
L7760
U7760
1
10UH-0.55A-330MOHM
TPS62202
4
2
66C1
=P1V8S0_EN
3
FB
EN
SW 5
MAX CURRENT = 200MA
PCAA031B-SM
SOT23-5
P1V8S0_SW
1
=PP1V8_S0_REG
2
DIDT=TRUE
GND
2
C7762
1
20%
6.3V
X5R
603
2
7B8
10uF
C
C
1.05V S0 PLL LDO
LDO_YES
7B5
=PP3V3_S0_MCP_PLL_VLDO
R7743
1
100
2
PP3V3_S0_MCP_PLL_VLDO_BIAS
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
LDO_NO
C7740 1
=PP1V05_S0_MCP_PLL_UF_R
7C7
1UF
10%
LDO_YES 6.3V
4
CERM 2
402
BIAS
1
0.0022UF
10%
50V
CERM 2
402
CRITICAL
7
FB
U7740
SS
PG
8
3
P1V05S0_LDO_FB
GND THRML_PAD
TP_P1V05S0_LDO_PGOOD
C7750
2
1%
1/16W
MF-LF
402
SON
22UF
=PP3V3_S5_P1V05S5
7A3
<Ra>
LDO_YES
1.37K
P1V05S0_LDO_SS
NOSTUFF
C7743
1
EN
PP1V05_S0_MCP_PLL_UF_LDO
9
10
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
R7746
<Rb>
1%
1/16W
MF-LF
402
MCP 1.05V S5 (AUXC) SUPPLY
5
11
1UF
B
IN0
OUT0
IN1 LDO_YES
OUT1
TPS74701
C7741 1
10%
LDO_YES 6.3V
CERM 2
402
1
2
4.42K
=PP1V5_S0_MCP_PLL_VLDO
6
7B6
0
1
2
5%
1/16W
MF-LF
402
Vout = 1.05V
MAX CURRENT = 0.5A
CRITICAL
R7745
C7742
4.7UF
=PP1V05_S0_MCP_PLL_UF
7B8 22C4
R7744
1
0
2
5%
1/16W
MF-LF
402
LDO_YES
20%
2 4V
X5R
402
B
LDO_YES
LDO_YES
R7747
20%
6.3V
CERM
805
VOUT = 0.8V * (1 + RA / RB)
1
VIN
CRITICAL
L7770
U7750
2.2UH-3.25A
ISL8009B
DFN
66D6
66B1
IN
=P1V05_S5_EN
P1V05_S5_PGOOD
2 EN
IHLP1616BZ-SM
CRITICAL
3 POR
LX 8
VFB 6
4 SKIP
RSI 5
GND
7
THRM_PAD
9
1
1V05S5_SW
DIDT=TRUE
1V05S5_FB
2
1
C7776 1
47PF
=PP1V05_S5_REG
<Ra>
R7780
255K
5%
50V
CERM 2
402
2
1
1%
1/16W
MF-LF
402
<Rb>
R7781
806K
2
A
7B4
Vout = 1.05V
CRITICAL
MAX CURRENT = 0.8A
1
C7771
FREQ = 1.6MHZ
2
20%
6.3V
CERM-X5R
0805
47UF
MISC POWER SUPPLIES
1%
1/16W
MF-LF
402
SYNC_MASTER=RAYMOND
SYNC_DATE=01/23/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
VOUT = 0.8V * (1 + RA / RB)
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
65
1
81
A
8
6
7
3.3V 1.05V S5 ENABLE
100K
2
=PP3V42_G3H_PWRCTL
1
PM_G2_P3V3S5_EN_L
5%
1/16W
MF-LF
402
1
D 3
1
100K
5%
1/16W
MF-LF
402
G
PM_SLP_S3_L
Run (S0)
1
1
1
1
1
0
Soft-Off (S5)
1
0
0
Battery Off (G3Hot)
0
0
0
CERM
1
R7800
PM_SLP_S4_L
Sleep (S3)
10%
10V
SMC_PM_G2_EN
IN
SMC_PM_G2_ENABLE
D
402
SOD-VESM-HF
60C5 40D5 6C3
State
NO STUFF
0.068UF
2
3.3V_S0, 1.8V_S0 ENABLE
MCPDDR, CPUVTT,MCPCORES0 ENABLE
1.5V S0 AND 1.05V S0 ENABLE
60A5
OUT
C7802
Q7800
D
=P3V3S5_EN_L
MAKE_BASE=TRUE
SSM3K15FV
1
Power Control Signals
R7802
66C8 66B3 7D1
2
3
4
5
S 2
R7801
2
2
5.1K
1 PM_G2_P1V05S5_EN
=P1V05_S5_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
1
OUT
65A8
C7801
0.47UF
2
10%
6.3V
CERM-X5R
402
(PM_SLP_S3_L)
70D8 40C5 35A5 32B7 20C3 6C3
IN
PM_SLP_S3_L
R7859
2
100
1
PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R7813
=PP3V42_G3H_PWRCTL
2
68K
5%
41A2 40C5 20C3 6C3
IN
5%
1/16W
MF-LF
402
22K
1
5%
1/16W
MF-LF
402
1
D 3
Q7813
PM_SLP_S3_L_INVERT
SSM3K15FV
=P5VS3_EN_L
MAKE_BASE=TRUE
SOD-VESM-HF
1
PM_SLP_S4_L
MAKE_BASE=TRUE
33K
5%
1/16W
MF-LF
402
1
1
0
=P5VS0_EN
OUT
67A8
=PBUSVSENS_EN
OUT
44B7
R7884
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
10K
1
OUT
5.1K
P3V3S0_EN
60A7
G
P1V8S0_EN
C7813
2
S 2
=P3V3S0_EN
OUT
=P1V8S0_EN
OUT
65C7
=MCPDDR_EN
OUT
67C4
=CPUVTTS0_EN
OUT
64B7
=MCPCORES0_EN
OUT
63C6
MAKE_BASE=TRUE
NO STUFF
MAKE_BASE=TRUE
MCPDDR_EN
10%
10V
MAKE_BASE=TRUE
67B8
C
CERM
CPUVTTS0_EN
402
MAKE_BASE=TRUE
(PM_S4_STATE_L)
100K
5%
1/16W
MF-LF
402
1
R7883
2
2
0.068UF
R7810
R7882
2
2
R7881
2
1
1/16W
MF-LF
402
C
R7880
2
100K
S3 ENABLE
66D8 66B3 7D1
1
1
R7879
MCPCORES0_EN
MAKE_BASE=TRUE
2
1
0.47UF
5.1K
1
NO STUFF
C7810
R7811
1
2
2
2
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
C7880
1
MAKE_BASE=TRUE
=DDRREG_EN
OUT
61C8
=USB_PWR_EN
OUT
38B7
1
C7882
0.47UF
0.47UF
10%
6.3V
10%
6.3V
10%
6.3V
CERM-X5R
2
402
DDRREG_EN
C7881
0.47UF
CERM-X5R
402
2
1
C7883
1
0.47UF
CERM-X5R
2
CERM-X5R
402
C7884
0.47UF
10%
6.3V
2
402
10%
6.3V
CERM-X5R
402
NO STUFF
C7812
R7812
0.47UF
0
1
1
VOLTAGE MONITOR
2
2
5%
1/16W
MF-LF
402
10%
6.3V
CERM-X5R
402
66D8 66C8 7D1 =PP3V42_G3H_PWRCTL
P3V3S3_EN
=P3V3S3_EN
MAKE_BASE=TRUE
OUT
67C8
7A3
=PP3V3_S5_PWRCTL
C7840
B
1
1
0.1uF
20%
10V
CERM
402
100K
6
VDD
5 SENSE
U7840
B
R7840
2
2
RESET* 1
5%
1/16W
MF-LF
402
RSMRST_PWRGD
40D8
P1V05_S5_PGOOD
65A8
TPS3808G33DBVRG4
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
=PP5V_S0_VMON
CT
7D5
4 CT
SOT23-6
MR* 3
GND
10K
1%
1/16W
MF-LF
402
C7841
2
7
C7870
VDD
2
20%
50V
CERM
402
OTHER S0 RAILS PGOOD
U7870
20%
10V
CERM
402
TDFN
7D7
=PP1V5_S0_VMON
=PP1V05_S0_VMON
4
GND
MR*
RST*
1
2
1%
1/16W
MF-LF
402
1
7C5 =PP3V3_S0_PWRCTL
2
R7820
NC
1
10K
5%
1/16W
MF-LF
402
S0PGOOD_PWROK
8
2
THRM_PAD
9
7B6
3 V2MON
5 V3MON
6 V4MON
R7871
2
20.0K
0.1uF
ISL88042IRTEZ
7C5 =PP3V3_S0_VMON
1
1
0.001UF
PP3V3_VMON_VDD
353S2310
TPS3808 MR* HAS INTERNAL PULLUP
2
R7870
1
POWER SEQUENCING
Unused PGOOD signal
60A2
A
P5V3V3_PGOOD
IN
TP_DDRREG_PGOOD
DDRREG_PGOOD
61B3
SYNC_MASTER=YUAN.MA
SYNC_DATE=12/11/2008
MAKE_BASE=TRUE
63C6
V2MON THRESHOLD IS 2.866V
V3MON THRESHOLD IS 0.6V
V4MON THRESHOLD IS 0.6V
64B7
MCPCORES0_PGOOD
IN
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
CPUVTTS0_PGOOD
IN
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
ALL_SYS_PWRGD
OUT
MAKE_BASE=TRUE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
24B8 40D8
SIZE
(S0PGOOD_PWROK)
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
66
1
81
A
8
6
7
5
2
3
4
1
1.5V S0 FET
3.3V S3 FET
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
CRITICAL
Q7910
=PP3V3_S3_FET
=PP3V3_S5_P3V3S3FET
D
3.3V S3 FET
7D4
9
5
MOSFET
FDC638P
CHANNEL
P-TYPE
CRITICAL
Q7901
6
DFN
X5R
2
402
402
3
R7910
2
P3V3S3_EN_L
1
47K
48 mOhm @4.5V
LOADING
C7910
0.182 A (EDP)
7C3
1
P3V3S3_SS
2
R7903 1
10%
Q7903
MF-LF
16V
402
CERM
Q7971
5%
1/16W
MF-LF
402
SOD-VESM-HF
66B6
1
S 2
=P3V3S3_EN
IN
Q7971
1
2
3
D
47K
2
5
S
1
1
C7903
10%
10V
CERM
402
MCPDDR_EN_L_RC
7C8
1.5V S0 FET
0.068UF
2
SSM6N15FEAPE
OUT
P1V5_S0_SENSE
2
5%
1/16W
MF-LF
402
3
G
OUT
P1V5_S0_KELVIN
=PP1V5_S0_FET
2
R7971
G
7
6
SOT563
MCPDDR_EN_L
1
D
KELVIN 6
S
SSM6N15FEAPE
100K
402
D 3
4 G
2
MCPDDR_SS
2
5%
1/16W
MF-LF
402
2
5%
SSM3K15FV
10K
1
0.01UF
1/16W
20%
10V
CERM
402
R7901
=PP5V_S3_MCPDDRFET
45D8
RDS(ON)
10%
16V
5%
1/16W
MF-LF
NC 8
0.1UF
1
0.033UF
10K
C7902
GND
1
1
SENSE
R7912
C7911
1
2
D
ROME
D
4
45C8
SM
7A3
=PP1V5_S3_P1V5S0FET
7D3
FDC638P_G
MOSFET
Rome SenseFET
CHANNEL
N-TYPE
RDS(ON)
SOT563
6.3 mOHM @4.5V VGS
LOADING
5
3.3V S0 FET
66C1
IN
G
S
5A (EDP)
4
=MCPDDR_EN
CRITICAL
Q7930
C
C
FDC606P_G
10%
16V
5%
1/16W
X5R
MF-LF
402
P3V3S0_EN_L
1
2
1
D
FDC606P
CHANNEL
P-TYPE
RDS(ON)
26 MOHM @4.5V
LOADING
C7930
R7930
47K
MOSFET
G
2
402
2
3.3V S0 FET
7D6
1
0.033UF
100K
=PP3V3_S0_FET
3
R7932
C7931
1
S
=PP3V3_S5_P3V3S0FET
4
7A3
5 6
SOT-6
1.431 A (EDP)
0.01UF
1
P3V3S0_SS
2
2
5%
10%
1/16W
Q7905
SSM3K15FV
16V
MF-LF
CERM
402
402
D 3
SOD-VESM-HF
MCP79 DDRVTT FET
1
66C1
G
=P3V3S0_EN
IN
S 2
B
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
LOW THROUGH VTT TERMINATION RESISTORS.
5.0V S0 FET
B
CRITICAL
Q7940
10%
16V
5%
1/16W
X5R
MF-LF
402
1
47K
2
5
D
CHANNEL
P-TYPE
7C7
6
TPCP8102
LOADING
C7940
R7940
P5V0S0_EN_L
R7975
MOSFET
RDS(ON)
2
402
2
5.0V S0 FET
7D6
=PPVTT_S0_VTTCLAMP
2
13.5 MOHM @4.5V
7C3
1.7 A (EDP)
1
Q7945
SSM3K15FV
16V
CERM
CKT FROM T18
5%
1/16W
MF-LF
402
D
6
S
1
SOT563
100K
10%
402
90mA max load @ 0.9V
81mW max power
SSM6N15FEAPE
R7976 1
2
MF-LF
VTTCLAMP_L
Q7975
5%
1/16W
1
=PP5V_S3_VTTCLAMP
0.01UF
P5V0S0_SS
10
5%
1/10W
MF-LF
603
G
1
0.033UF
47K
=PP5V_S0_FET
4
R7942
C7941
1
S
3
=PP5V_S3_P5VS0FET
1 2
7C3
7 8
TPCP8102
376S0778
23V1K-SM
2
2
G
402
D 3
VTTCLAMP_EN
SOD-VESM-HF
Q7975
D
3
SSM6N15FEAPE
1
66C1
IN
=P5VS0_EN
G
S 2
A
5
61C8 24C1
IN
G
NO STUFF
C7976
1
0.001UF
SOT563
20%
50V
CERM
402
S
POWER FETS
2
SYNC_MASTER=YUAN.MA
4
SYNC_DATE=12/11/2008
NOTICE OF PROPRIETARY PROPERTY
=DDRVTT_EN
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
.
.
REV.
051-7898
4.7.0
OF
67
1
81
A
8
6
7
2
3
4
5
1
D
D
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP
17B6
LCD
LVDS_IG_PANEL_PWR
LVDS CONNECTOR:518S0650
R9014
1K
1
CRITICAL
J9000
5%
1/16W
MF-LF
2402
20474-030E-11
C9015
CRITICAL
FPF1009
1 ON
=PP3V3_S5_LCD
C
1
C9009
0.1UF
10%
50V
X7R
402
L9004
MFET-2X2
FERR-120-OHM-1.5A
2 VIN_1
VOUT_1 4
PP3V3_LCDVDD_SW
3 VIN_2
VOUT_2 5
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
GND
6
C9010
1
0.001UF
U9000
7A3
CONNECTOR
THRM
PAD
7
1
C9011
0.1UF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
1
C9012
1
1
=PP3V3_S0_LCD
1
R9008
100K
5%
1/16W
MF-LF
2 402
17B3 6C7
17A3 6C7
PP3V3_LCDVDD_SW_F
3
MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
CRITICAL
6B7
2
0402-LF
7C5
1
2
6C7 6C3
L9008
32
2
120-OHM-0.3A-EMI
10UF
20%
2 6.3V
X5R
603
10%
50V
X7R
402
2
2
0402-LF
F-RT-SM
31
1
0.001UF
6C7
4
TP_BKL_SYNC
5
PP3V3_S0_LCD_F
C
6
MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V
7
MIN_NECK_WIDTH=0.20 MM
17B3 6C7
75B3
(LVDS DDC POWER)
17B3 6C7
75B3
1
R9009
17B3 6C7
75B3
75B3 17B3 6C7
100K
5%
1/16W
MF-LF
2 402
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
8
9
10
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
11
12
13
75B3 17B3 6C7
75B3 17B3 6C7
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
14
15
16
CRITICAL
L9080
90-OHM-200MA
AMC2012-SM
SYM_VER-1
75B3 17B3
LVDS_IG_A_CLK_N
4
LVDS_IG_A_CLK_F_N
6C7 LVDS_IG_A_CLK_F_P
75B3 6C7
17
75B3
18
1
20
NC
75B3 17B3
LVDS_IG_A_CLK_P
3
2
71B1 6C7
71B1 6C7
71B1 6C7
71B1 6B7
71B1 6B7
71A1 6B7
LVDS I/F
19
71C1 6C7 6C3
21
PPVOUT_S0_LCDBKLT
22
23
NC
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
LED BKLT I/F
24
25
26
27
28
29
30
NC
B
B
33
34
LVDS CONNECTOR
SYNC_MASTER=NMARTIN
SYNC_DATE=04/04/2008
A
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
68
1
81
A
8
6
7
3
4
5
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
17B6
D
17A3
17A3
DP_AUX_CH_C_N
69D1
BI
1
BI
DP_IG_DDC_CLK
0.1UF
1
2
5%
1/16W
MF-LF
402
Display Port Interoperability spec says that sources
or sinks which do both DP and DVI must depend on the
external adapter for pull ups on DDC lines (since DP
AUX CH has 100K pull up/down on the MLB)..
69D1
33
1
33
5%
1/16W
MF-LF
402
C
2
75B3
2
0.1UF
1
2
75B3
4
BI
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
70C1 75C3
MAKE_BASE=TRUE
D
70A8
MAKE_BASE=TRUE
DP_IG_DDC_CLK
DP_IG_DDC_DATA
69C8
MAKE_BASE=TRUE
69C8
MAKE_BASE=TRUE
70C8 75B3
DP_AUX_CH_C_P
BI
70C8 75B3
DP_AUX_CH_SW_P
Q9300
D
SOT563
75B3 17B6
70C8 75C3
MAKE_BASE=TRUE
10%
16V
X5R
402
SSM6N15FEAPE
BI
70C8 75C3
MAKE_BASE=TRUE
C9301
3
75B3 17B6
DP_ML_P<3>
DP_ML_N<3>
DP_ML_P<2>
DP_ML_N<2>
DP_ML_P<1>
DP_ML_N<1>
DP_ML_P<0>
DP_ML_N<0>
DP_HPD
DP_AUX_CH_SW_N
10%
16V
X5R
402
R9301
1
C9300
R9300
DP_IG_DDC_DATA
BI
=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>
=MCP_HDMI_HPD
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
2
S
Q9300
C
D 6
SSM6N15FEAPE
SOT563
G 5
2
G
S 1
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
=PP5V_S0_DP_AUX_MUX
7D5
R9302
1
100K
5%
1/16W
MF-LF
2 402
R9306
1
1K
5%
1/16W
MF-LF
402 2
DDC_CA_DET_LS5V_L
B
B
Q9301
3
D
SSM3K15FV
SOD-VESM-HF
2
70B8
IN
S
G 1
DP_CA_DET
DP_IG_CA_DET
OUT
17B6
DISPLAYPORT SUPPORT
A
SYNC_MASTER=AMASON
SYNC_DATE=04/18/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
69
1
81
A
8
6
7
2
3
4
5
1
Port Power Switch
DP_ESD
CRITICAL
CRITICAL
L9400
7A3
66D5 40C5 35A5 32B7 20C3 6C3
5 IN
=PP3V3_S5_DP_PORT_PWR
IN
4 EN
PM_SLP_S3_L
FERR-120-OHM-3A
TPS2051B
SOT23
OUT 1
PP3V3_S0_DPILIM
OC* 3
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
TP_DPPWR_OC_L
2
0603
1
GND
2
C9400
D9410
RCLAMP0524P
SLP2510P8
SLP2510P8
PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
5 IO
IO
NC
6 NC
4.7UF
2
D
D9410
RCLAMP0524P
20%
6.3V
X5R-CERM
402
4
2 IO
7
9 NC
IO
NC
GND
U9480
GND
D
DP_ESD
CRITICAL
3
3
1
10
CRITICAL
C9480
1
1
22UF
20%
6.3V
X5R-CERM-1
603
C9481
4.7UF
2
2
1
20%
6.3V
X5R-CERM-1
603
2
20%
2 6.3V
X5R-CERM-1
603
22UF
22UF
20%
6.3V
X5R-CERM
402
C9486
C9485
1
R9420
1
100K
5%
1/16W
MF-LF
402
2
CRITICAL
J9400
HDMI_CEC
DSPLYPRT-M97-1
FL9400
F-RT-THSM
1
C
R9425
1M
FL9403
12-OHM-100MA
DP_ML_P<3>
C9414
75C3 69D1
IN
DP_ML_N<3>
C9415
75B3 69C4
BI
DP_AUX_CH_C_P
BI
DP_AUX_CH_C_N
1
2 75C3 DP_ML_C_P<3>
10%
16V
X5R
402
1
2 75C3 DP_ML_C_N<3>
10%
16V
X5R
402
0.1uF
0.1uF
TCM1210-4SM
SYM_VER-2
TOP ROW
TH PINS
SM PINS
2
6
8
2
75B3
DP_ML_CONN_P<3>
DP_ML_CONN_N<3>
10
12
ML_LANE3N
GND
AUX_CHP
AUX_CHN
DP_PWR
14
16
18
75B3 69D4
70B8 7C5
20
DP_ESD
CRITICAL
=PP3V3_S0_DPCONN
R9443 1
5%
1/16W
MF-LF
402
69B7
OUT
DP_CA_DET
100K
5%
1/16W
MF-LF
402
2
R9421
5%
1/16W
MF-LF
402
2
2 IO
2
IO
NC
9 NC
G
2
DP_CA_DET_L_Q
3
SOT-363
DP_ML_CONN_P<2>
75B3
DP_ML_CONN_N<2>
75C3
DP_ML_C_N<0>
19
C9411
1
TCM1210-4SM
SYM_VER-2
DP_ML_C_P<1>
C9412
75C3
DP_ML_C_N<1>
C9413
75C3
DP_ML_C_P<2>
C9416
16V
1
2
10%
DP_ML_N<1>
1
2
DP_ML_P<2>
3
75C3
DP_ML_C_N<2>
C9417
1
0.1uF
16V
16V
X5R
X5R
X5R
X5R
402
402
402
10%
16V
2
DP_ML_N<2>
10%
16V
X5R
C
402
DP_ML_P<1>
0.1uF
2
DP_ML_N<0>
X5R
2
10%
0.1uF
4
2
16V
10%
0.1uF
FL9402
12-OHM-100MA
1
75C3
DP_ML_P<0>
1
0.1uF
3
75B3
3
2
10%
402
402
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
IN
69D1 75C3
21
514-0637
DP_ESD
CRITICAL
D9411
RCLAMP0524P
SLP2510P8
RCLAMP0504F
SC70-6-1
S
G
DP_CA_DET_Q
5
4
R9422
1
DP to DVI/HDMI
Cable Adapter
(CA) has 100k
pull-up to DP_PWR.
1
1M
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
5%
1/16W
MF-LF
402
2
5 IO
6
IO
NC
6 NC
B
4
7
5
3
3
4
2
=PP3V3_S0_DPCONN
R9445 1
R9444 1
10K
5%
1/16W
MF-LF
402
69D1
2
4
17
D9400
2N7002DW-X-G
70C8 7C5
15
DP_ESD
CRITICAL
D
Q9440
B
2
1
0.1uF
13
10
3
1
DP_ML_CONN_P<1>
DP_ML_CONN_N<1>
C9410
1
GND
D
S
75B3
11
SYM_VER-2
DP_ML_C_P<0>
100K
2N7002DW-X-G
SOT-363
9
12-OHM-100MA
TCM1210-4SM
4
SLP2510P8
6
Q9440
7
ML_LANE1N
GND
ML_LANE2P
ML_LANE2N
RETURN
22
RCLAMP0524P
1
1
SYM_VER-2
75C3
FL9401
5
12-OHM-100MA
TCM1210-4SM
SHIELD PINS
D9411
R9442 1
100K
75B3
3
75B3
1
DP_ML_CONN_P<0>
DP_ML_CONN_N<0>
75B3
1
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
4
1
75B3
3
BOT ROW
GND
IN
75C3 69D1
4
2
5%
1/16W
MF-LF
402
OUT
DP_HPD
10K
5%
1/16W
MF-LF
402
2
2
6
R9446 1
100K
5%
1/16W
MF-LF
402
2
MCP79 requires pull
Q9441
down HPD input with
2N7002DW-X-G
SOT-363
100K if DP_HPD is used.
D
S
G
2
DP_HPD_L_Q
3
1
A
DisplayPort Connector
D
Q9441
2N7002DW-X-G
SYNC_MASTER=AMASON
SOT-363
S
G
5
DP_HPD_Q
SYNC_DATE=06/30/2008
NOTICE OF PROPRIETARY PROPERTY
4
R9423
1
100K
5%
1/16W
MF-LF
402
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
70
1
81
A
8
6
7
2
3
4
5
1
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
BKLT_VLDO_EN_L
NO STUFF
Q9701
NTUD3127CXXG
SOT-963
N-CHANNEL
6
D
NO STUFF
R9701
G
D
BKLT_EN_R
2
0
1
S
BKLT_EN
2
D
71B6
5%
1/16W
MF-LF
402
1
3
D
NO STUFF
R9735
G
5
1
S
100K
2
1%
1/16W
MF-LF
402
4
P-CHANNEL
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
=PP5V_S0_BKL
7D5
NO STUFF
VOLTAGE=5V
1
R9702
0
5%
1/16W
MF-LF
CRITICAL
2 402
C
PPVIN_BKL
2
CRITICAL
0
C9712
1
5%
1/16W
MF-LF
402
1
10UF
2
71B5 71C2
1
C9710
1
1UF
C9711
0.1UF
10%
2 25V
X5R
603-1
10%
2 16V
X5R
402
VDDIO
NC
5%
1/16W
MF-LF
402
20 ADR
2
5%
R9757
0
1
1/16W
BKL_SDA
11 SDA
402
2
5%
MF-LF
402
R9731
PPBUS_S0_LCDBKLT_PWR
71D3
C9723
10%
25V
X5R
402
BKL_ISEN2
OUT3 14
BKL_ISEN3
OUT4 16
BKL_ISEN4
TP_BKL_FAULT
7 FAULT
OUT6 18
4 EN
OUT7 19
BKL_SWGND HIGH CURRENT
NEED 2 VIAS
1%
1/16W
MF-LF
402
1
LVDS_IG_BKL_PWM
1
0
BKL_ISEN5
BKL_ISEN6
R9704 SHOULD BE 47K IF RC FILTER IS USED
10%
2 100V
X7R
1210
1
C9797
C
2.2UF
10%
100V
2 X7R
1210
71B5 71C5
2
1
THRM
PAD
33PF
BKL_SGND
5%
50V
LED_RETURN_2
2
0
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
6C7 68B3
OUT
6C7 68B3
B
LED_RETURN_3
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
0
LED_RETURN_4
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
5%
1/16W
MF-LF
402
OUT
6C7 68B3
OUT
6B7 68B3
OUT
6B7 68B3
OUT
6B7 68B3
R9721
1
XW9710
SM
C9704
OUT
R9720
1
BKL_SWGND
NO STUFF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
1
0
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
71C5
71C2
LED_RETURN_1
2
BKLT_PROD
R9719
NC
2
5%
1/16W
MF-LF
402
2.2UF
R9718
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACEMENT_NOTE=SW9700 PLACE NEAR C9712 C9713
R9704
0
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
XW9700
SM
NO STUFF
IN
OMIT
BKL_ISEN1
OUT2 13
BKLT_EN
R9715
100K
0.1UF
2
72B7 17B6
OUT1 12
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
1
C9799
R9717
FB 21
2
1%
1/16W
MF-LF
402
1
BKL_SWGND
SW 24
OUT5 17
1 GND_SW
301K
2
1
1
72C3 71C7
5%
2 100V
CERM
1206
CRITICAL
2 PWM
LVDS_IG_BKL_PWM_RC
B
200PF
25
=I2C_BKL_1_SDA
MF-LF
10 SCLK
15 GND_L
43B6
1/16W
VIN
3 IF_SEL
BKL_SCL
9 GND_S
1
6 ALSO
5 ALSI
IF_SEL=1 FOR SMBUS
IF_SEL=0 FOR I2C
BKL_IF_SEL
0
VLDO
LP8543SQX
100K
R9753
C9796
LLP
R9714
=I2C_BKL_1_SCL
1
VOLTAGE=50V
U9701
NO STUFF
43B6
23
10%
2 16V
CERM
402
6C3 6C7 68B2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
5%
1/16W
MF-LF
402
22
0.01UF
8
C9714
PPVOUT_S0_LCDBKLT
2
RB160M-40
VOLTAGE=50V
SWITCH_NODE=TRUE
PPVIN_BKL_R
1
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
0
=PP3V3_S0_BKL_VDDIO
5%
1/16W
MF-LF
402
PPBUS_S0_LCDBKLT_PWR_SW
R9703
BKL_VLDO
100K
2
IHLP2525CZ-SM
1
10%
25V
X5R
402
2
R9716
1
VOLTAGE=6V
0.1UF
10%
25V
X5R
805
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
C9713
BKL_SWGND
7B5
D9701
SOD-123
22UH-2.5A
R9700
PPBUS_S0_LCDBKLT_PWR
1
72C3 71B7
CRITICAL
L9701
BKLT_PROD
1
0
LED_RETURN_5
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
5%
1/16W
MF-LF
402
R9722
2
1
2 CERM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
402
0
5%
1/16W
MF-LF
402
LED_RETURN_6
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT_PROD
LCD BACKLIGHT DRIVER
A
SYNC_MASTER=KIRAN
SYNC_DATE=12/05/2008
NOTICE OF PROPRIETARY PROPERTY
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
103S0198
6
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
R9717,R9718,R9719,R9720,R9721,R9722
BKLT_ENG
116S0005
1
RES,1/16W,0.1 OHM,1%,0402,SM
R9700
BKLT_ENG
PART NUMBER
353S2670
QTY
1
DESCRIPTION
REFERENCE DES
IC,LP8543,WHT LED BKLT CTRLR,QFN24,PROD
U9701
CRITICAL
BOM OPTION
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
CRITICAL
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
71
1
81
A
8
6
7
4
5
2
3
1
CRITICAL
Q9806
FDC638APZ_SBMS001
PPBUS S0 LCDBkLT FET
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
0402-HF
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
R9808
1
301K
FDC638APZ
CHANNEL
P-TYPE
LOADING
0.1UF
10%
16V
X5R
402
1/16W
2
MF-LF
RDS(ON)
D
43 mOhm @4.5V
C9802
1%
2
MOSFET
1
IN
2
402
0.4 A (EDP)
3
D
1
=PPBUS_S0_LCDBKLT
4
2AMP-32V
7C1
6
F9800
2 5
SSOT6-HF
PPBUS_S0_LCDBKLT_EN_DIV
1
R9809
147K
1%
1/16W
MF-LF
2
402
PPBUS_S0_LCDBKLT_EN_L
Q9807
D
3
S
4
SSM6N15FEAPE
SOT563
72B7 17B6
5
LVDS_IG_BKL_ON
IN
G
PPBUS_S0_LCDBKLT_PWR
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
BKLT_EN_L
Q9807
D
6
S
1
OUT
71B7 71C7
SSM6N15FEAPE
SOT563
C
24C1
2
BKLT_PLT_RST_L
IN
G
C
B
B
LVDS_IG_BKL_ON
LVDS_IG_BKL_PWM
1
R9840
1K
2
5%
1/16W
MF-LF
402
17B6 72C8
17B6 71A7
1
R9841
1K
5%
1/16W
MF-LF
2 402
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS
LCD Backlight Support
A
SYNC_MASTER=YITE
SYNC_DATE=06/30/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
.
REV.
051-7898
4.7.0
OF
72
1
81
A
8
6
7
FSB (Front-Side Bus) Constraints
2
3
4
5
1
CPU / FSB Net Properties
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FSB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DATA_GROUP0
FSB_50S
FSB_DATA
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB0
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DATA_GROUP1
FSB_50S
FSB_DATA
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB1
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DATA_GROUP2
FSB_50S
FSB_DATA
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB2
FSB_DSTB_50S
FSB_DSTB
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DATA_GROUP3
FSB_50S
FSB_DATA
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_DSTB3
FSB_DSTB_50S
FSB_DSTB
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADDR_GROUP0
FSB_50S
FSB_ADDR
FSB_ADSTB0
FSB_50S
FSB_ADSTB
FSB_ADDR_GROUP1
FSB_50S
FSB_ADDR
FSB_ADSTB1
FSB_50S
FSB_ADSTB
FSB_1X
FSB_50S
FSB_1X
FSB_BREQ0_L
FSB_50S
FSB_1X
FSB_BREQ1_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
FSB_1X
FSB_50S
FSB_1X
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_BSEL
CPU_50S
CPU_AGTL
CPU_FERR_L
CPU_50S
CPU_8MIL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_INIT_L
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_ASYNC_R
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
FSB_CPUSLP_L
CPU_50S
CPU_AGTL
CPU_FROM_SB
CPU_50S
CPU_AGTL
CPU_DPRSTP_L
CPU_50S
CPU_AGTL
CPU_ASYNC
CPU_50S
CPU_AGTL
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
MCP_CPU_COMP
MCP_50S
MCP_FSB_COMP
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_CPU
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
FSB_CLK_MCP
CLK_FSB_100D
CLK_FSB
CPU_IERR_L
CPU_50S
PM_DPRSLPVR
CPU_50S
CPU_AGTL
(See above)
CPU_50S
CPU_AGTL
CPU_GTLREF
CPU_50S
CPU_GTLREF
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
CPU_COMP
CPU_50S
CPU_COMP
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO
CPU_50S
CPU_ITP
XDP_TMS
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
XDP_TRST_L
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_L5
CPU_50S
CPU_ITP
(FSB_CPURST_L)
CPU_50S
CPU_ITP
CPU_50S
CPU_8MIL
TABLE_PHYSICAL_RULE_ITEM
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
FSB_DATA
*
=2x_DIELECTRIC
?
FSB_DSTB
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_DATA
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
FSB_ADDR
*
=STANDARD
TABLE_SPACING_RULE_ITEM
?
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_ADSTB
*
=2x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
FSB_1X
*
=STANDARD
FSB 4X Signal Groups
FSB_DSTB_50S
TABLE_SPACING_RULE_ITEM
?
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
?
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 2X
Signals
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.
FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.
FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
FSB 1X Signals
Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
C
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_AGTL
*
=STANDARD
TABLE_SPACING_RULE_ITEM
?
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
CPU_8MIL
*
8 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_COMP
*
25 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_GTLREF
*
25 MIL
SR DG recommends at least 25 mils, >50 mils preferred
?
TABLE_SPACING_RULE_ITEM
CPU_ITP
*
=2:1_SPACING
?
CPU_VCCSENSE
*
25 MIL
?
TABLE_SPACING_RULE_ITEM
Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MCP_50S
*
=50_OHM_SE
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
B
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MCP_FSB_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
FSB Clock Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
CLK_FSB_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
CLK_FSB
*
=3x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
?
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
A
FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<35..17>
FSB_ADSTB_L<1>
FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L
CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N
CPU_IERR_L
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
CPU_50S
CPU_8MIL
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
(CPU_VCCSENSE)
(CPU_VCCSENSE)
CPU_27P4S
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
9C4 13D3
9C4 13D6
9C4 13D6
9C4 13D6
9B4 9C4 13C3 13D3
9B4 13D6
9B4 13D6
D
9B4 13D6
9C2 13B3 13C3
9C2 13D6
9C2 13D6
9C2 13D6
9B2 9C2 13B3
9B2 13D6
9B2 13D6
9B2 13D6
9D8 13C6 13D6
9D8 13B6
9D8 13B6
9C8 9D8 13C6
9C8 13B6
9D6 13B6
9D6 13B6
13B6
9D6 13B6
9D6 13B3
9D6 13B6
9D6 13B3
9D6 13B6
9D6 13B6
9D6 13B6
C
9D6 13B6
9D6 12C2 13A3
9D6 13A6
9D6 13B6
9C8 13A3
8B2 9B4
9C8 13B7
9C8 13A3
9D6 13A3
9C8 13A3
9B8 13A3
9C5 13B6 41D4 62C8
9B2 12C7 13A3
9B8 13A3
9C8 13A3
9C6 13B7 41C4
9B2 13A3
9B2 13A3
9B2 13A3 62C7
9B2 13A3
13A6
13A6
13A6
13A6
9B6 13B3
B
9B6 13B3
12C3 13B3
12C3 13B3
13A4
13A4
9D6
PM_DPRSLPVR
IMVP_DPRSLPVR
CPU_GTLREF
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
20C7 62D8
62C7
9B4 25B1
9B3
9B3
9B3
9B3
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L<4..0>
XDP_BPM_L<5>
XDP_CPURST_L
CPU_VID<6..0>
IMVP6_VID<6..0>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
IMVP6_VSEN_P
IMVP6_VSEN_N
9B6 9C6 12B3
9B6 9C6 12B3
9B6 9C6 12B3
9A6 9C6 12B6
9A6 9C6 12B3
9C6 12C6
9C5 12C6
12C4
10B6 62C7
CPU/FSB Constraints
10B5 62A5
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
10A5 62A5
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
73
1
81
A
8
6
7
Memory Bus Constraints
2
3
4
5
1
Memory Net Properties
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CLK
MEM_70D_VDD
MEM_CLK
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_CMD
TABLE_PHYSICAL_RULE_ITEM
MEM_40S_VDD
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
14B5 26C5 26C7
14B5 26C5 26C7
TABLE_PHYSICAL_RULE_ITEM
MEM_70D
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_70D_VDD
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
D
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=2:1_SPACING
?
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
14A5 26D5 26D7
14B5 26C5 26C7
14B5 26C5
14B5 14C5 26C5 26C7
D
14C5 26C5 26C7
14C5 26C5
14C5 26C7
14C5 26C7
TABLE_SPACING_RULE_ITEM
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
MEM_CMD2CMD
*
=1.5:1_SPACING
?
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS0
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS1
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS2
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS3
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS4
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS5
MEM_70D
MEM_DQS
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS6
MEM_70D
MEM_DQS
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_A_DQS7
MEM_70D
MEM_DQS
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CLK
MEM_70D_VDD
MEM_CLK
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CNTL
MEM_40S_VDD
MEM_CTRL
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_CMD
MEM_40S_VDD
MEM_CMD
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE0
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_40S
MEM_DATA
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MEM_B_DQ_BYTE6
MEM_40S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_40S
MEM_DATA
MCP MEM COMP Signal Constraints
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS0
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS1
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS2
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS3
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS4
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS5
MEM_70D
MEM_DQS
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS6
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MEM_B_DQS7
MEM_70D
MEM_DQS
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
MCP_MEM_COMP
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DATA2DATA
*
=1.5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DATA2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
14B7 26C2 26C4 26D2 26D4
14B7 26C2 26C4
14B7 14C7 26B2 26B4 26C2 26C4
14C7 26C2 26C4
14C7 26B5 26B7 26C5 26C7
14C7 14D7 26B5 26B7
14D7 26B5 26B7
14D7 26A5 26A7 26B5 26B7
TABLE_SPACING_RULE_ITEM
MEM_2OTHER
*
25 MIL
?
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CLK
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CTRL
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CMD
*
MEM_CLK2MEM
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
MEM_CLK
MEM_DQS
*
MEM_CLK2MEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
MEM_CMD
MEM_DATA
*
MEM_CMD2MEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
C
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_CLK
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CTRL
*
MEM_CTRL2CTRL
MEM_CTRL
MEM_CMD
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_CTRL
*
MEM_DATA2MEM
MEM_DATA
MEM_CMD
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DATA
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DATA
*
MEM_DATA2DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_DQS
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DQS
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_CLK
*
MEM_DQS2MEM
MEM_DQS
MEM_CTRL
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
*
*
MEM_2OTHER
MEM_CTRL
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DATA
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DQS
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
*
*
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR2:
B
DQ signals should be matched within 20 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DDR3:
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
MCP_MEM_COMP
*
Y
7 MIL
7 MIL
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MCP_MEM_COMP
*
8 MIL
14A7 26C2
14B7 26B4
14B7 26C2
14B7 26B5
14B7 26B7
14B7 26B5
14B7 26A7
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
14D5 26C2
14D5 26D2
14D5 26C4
14D5 26C4
14D5 26B2
14D5 26C2
C
14D5 26C4
14D5 26C4
14D5 26B7
14D5 26B7
14D5 26B5
14D5 26B5
14D5 26B7
14D5 26B7
14D5 26A5
14D5 26A5
14B1 27C5 27C7
14B1 27C5 27C7
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
14A7 26C4
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
A
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
14A1 27D5 27D7
14B1 27C5 27C7
14B1 27C5
14B1 14C1 27C5 27C7
14C1 27C5 27C7
14C1 27C5
14C1 27C7
14C1 27C7
14B3 27C2 27C4 27D2 27D4
14B3 27C2 27C4
14B3 14C3 27C2 27C4
14C3 27B2 27B4 27C2 27C4
B
14C3 27B5 27B7 27C5 27C7
14C3 14D3 27B5 27B7
14D3 27B5 27B7
14D3 27A5 27A7 27B5 27B7
14A3 27C4
14A3 27C2
14B3 27C2
14B3 27B4
14B3 27B5
14B3 27B7
14B3 27B5
14B3 27A7
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND
14D1 27C2
14D1 27D2
14D1 27C4
14D1 27C4
14D1 27C4
14D1 27C4
14D1 27B2
14D1 27C2
14D1 27B7
14D1 27B7
14D1 27B5
Memory Constraints
14D1 27B5
14D1 27B7
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
14D1 27B7
NOTICE OF PROPRIETARY PROPERTY
14D1 27A5
14D1 27A5
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
15C6
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
15C6
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
74
1
81
A
8
6
7
2
3
4
5
1
NET_TYPE
PCI-Express
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
PCIE_MINI_R2D
TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
PCIE_MINI_D2R
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
PCIE_90D
PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE_100D
CLK_PCIE
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
MCP_PEX_COMP
MCP_PEX_CLK_COMP
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE
*
=3X_DIELECTRIC
?
CLK_PCIE
*
20 MIL
?
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
D
PCIE_FW_R2D
TABLE_SPACING_RULE_ITEM
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
PCIE_FW_D2R
MCP_PE1_REFCLK
MCP_PE4_REFCLK
MCP_PEX_CLK_COMP
C
6D5 29C7
6D5 29C7
16B3 29C5
16B3 29C5
6D5 16B6 29C7
6D5 16B6 29C7
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MCP_PEX_COMP
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_90D
TABLE_PHYSICAL_RULE_ITEM
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N
34C3
34C3
D
16B3 34C1
16B3 34C1
16B6 34C1
16B6 34C1
34C3
34C3
16C3 29C5
16C3 29C5
6D5 29C7
6D5 29C7
16A6
C
Digital Video Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
DP_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
LVDS_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
MCP_DV_COMP
*
Y
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
*
=3x_DIELECTRIC
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
*
?
=3x_DIELECTRIC
DISPLAYPORT
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
TMDS_IG_TXD
DP_100D
DISPLAYPORT
DP_ML
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
TABLE_SPACING_RULE_ITEM
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
LVDS
DP_100D
TMDS_IG_TXC
DP_ML
TABLE_SPACING_RULE_ITEM
?
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
DP_AUX_CH
SATA Interface Constraints
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
DP_ML_P<3..0>
DP_ML_C_P<3..0>
DP_ML_N<3..0>
DP_ML_C_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
DP_AUX_CH_SW_P
DP_AUX_CH_SW_N
DP_AUX_CH_C_P
DP_AUX_CH_C_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE
MCP_HDMI_RSET
MCP_DV_COMP
MCP_HDMI_VPROBE
MCP_DV_COMP
LVDS_IG_A_CLK
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
LVDS_IG_A_DATA
LVDS_100D
LVDS
DP_ML
DP_100D
DISPLAYPORT
DP_100D
DISPLAYPORT
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD_N<2..0>
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
DISPLAYPORT
TMDS_IG_TXC
69D1 70C1 70C8
70C2 70C7
69D1 70C1 70C8
70C2 70C7
17B6 69C7
17B6 69C7
69C6
69C5
69C4 70C8
69D4 70C8
17A6 23C7
17A6 23C7
TABLE_PHYSICAL_RULE_ITEM
SATA_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SATA_90D_HDD
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
LVDS_IG_A_CLK
B
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA
*
TABLE_SPACING_RULE_ITEM
SATA
TOP,BOTTOM
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_F_P
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_F_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
17B3 68B3
6C7 68C2
17B3 68B3
6C7 68C2
B
6C7 17B3 68C2
6C7 17B3 68C2
TABLE_SPACING_RULE_ITEM
SATA_TERMP
*
8 MIL
?
I183
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
I182
MCP_IFPAB_RSET
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MCP_DV_COMP
MCP_IFPAB_VPROBE
SATA_HDD_R2D
SATA_HDD_D2R
SATA_ODD_R2D
A
SATA_ODD_D2R
MCP_SATA_TERMP
8
7
6
5
4
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_90D_HDD
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_100D
SATA
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_R2D_UF_P
SATA_HDD_R2D_UF_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_TERMP
MCP_SATA_TERMP
3
70C3 70C4 70C5
70C3 70C4 70C5
17A3 23C6
17A3 23C6
19D6 37A2
19D6 37A2
6B7 37A5
6B7 37A5
37A4
37A4
19D6 37B2
19D6 37B2
6B7 37B5
6B7 37B5
37B4
MCP Constraints 1
37B4
19D6 37C3
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
19D6 37C3
NOTICE OF PROPRIETARY PROPERTY
6B7 37C6
6A7 6B7 37C6
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
37C4
37C4
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
19D6 37C3
II NOT TO REPRODUCE OR COPY IT
19D6 37C3
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
6B7 37C6
SIZE
6B7 37C6
37C4
DRAWING NUMBER
D
37C4
APPLE INC.
19A6
SCALE
SHT
NONE
2
REV.
051-7898
4.7.0
OF
75
1
81
A
8
6
7
2
3
4
5
1
PCI Bus Constraints
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_DEBUG
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD24
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_AD
PCI_55S
PCI
PCI_C_BE_L
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_CNTL
PCI_55S
PCI
PCI_REQ0_L
PCI_55S
PCI
PCI_GNT0_L
PCI_55S
PCI
PCI_REQ1_L
PCI_55S
PCI
PCI_GNT1_L
PCI_55S
PCI
PCI_INTW_L
PCI_55S
PCI
PCI_INTX_L
PCI_55S
PCI
PCI_INTY_L
PCI_55S
PCI
PCI_INTZ_L
PCI_55S
PCI
MCP_PCI_CLK2
CLK_PCI_55S
CLK_PCI
CLK_PCI_55S
CLK_PCI
LPC_AD
LPC_55S
LPC
LPC_FRAME_L
LPC_55S
LPC
LPC_RESET_L
LPC_55S
LPC
MCP_LPC_CLK0
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
CLK_LPC_55S
CLK_LPC
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
USB_90D
USB
TABLE_PHYSICAL_RULE_ITEM
CLK_PCI_55S
*
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCI
*
=STANDARD
?
TABLE_SPACING_RULE_ITEM
CLK_PCI
D
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
6 MIL
?
TABLE_SPACING_RULE_ITEM
LPC
*
TABLE_SPACING_RULE_ITEM
CLK_LPC
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.
USB 2.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MCP_DEBUG<7..0>
PCI_AD<23..8>
PCI_AD<24>
PCI_AD<31..25>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
12C3 18D7
D
18D2 18D7
18D2 18D7
18C5
18C5
18B3 40C8 42D3 42D5
18C3 40C8 42D5
18C3 24D4
TABLE_PHYSICAL_RULE_ITEM
MCP_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB
C
*
USB_EXTA
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.
SMBus Interface Constraints
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
CONN_USB_EXTA_P
CONN_USB_EXTA_N
18B3 24B4
24B1 40C8
24B1 42D3
19D3 38A8
19D3 38A8
38C4
C
38C4
38C3
38C3
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SMB_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
USB_CAMERA
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SMB
*
=2x_DIELECTRIC
?
USB_BT
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.
HD Audio Interface Constraints
USB_TPAD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
HDA_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
USB_IR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
HDA
*
=2x_DIELECTRIC
?
USB_EXTB
TABLE_SPACING_RULE_ITEM
MCP_HDA_COMP
*
8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
B
USB_SD
SIO Signal Constraints
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
CONN_USB2_BT_P
CONN_USB2_BT_N
USB_TPAD_P
USB_TPAD_N
USB_TPAD_R_P
USB_TPAD_R_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
CONN_USB_EXTB_P
CONN_USB_EXTB_N
USB_CARDREADER_P
USB_CARDREADER_N
19D3 29B5
19D3 29B5
6D5 29B7
6D5 29B7
19D3 29B5
19C3 29B5
6D5 29B7
6D5 29B7
19D3 48B8
19D3 48B8
48B7
48B7
19D3 39D7
19D3 39D7
19C3 38A4
19C3 38B4
38B3
38B3
19C3 30C7
B
19C3 30C7
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
CLK_SLOW_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_USB_RBIAS_GND
MCP_USB_RBIAS
MCP_USB_RBIAS
SMBUS_MCP_0_CLK
SMB_55S
SMB
SMBUS_MCP_0_DATA
SMB_55S
SMB
SMBUS_MCP_1_CLK
SMB_55S
SMB
SMBUS_MCP_1_DATA
SMB_55S
SMB
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.
HDA_BIT_CLK
HDA_55S
HDA
SPI Interface Constraints
HDA_55S
HDA
HDA_SYNC
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_55S
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R
MCP_HDA_COMP
MCP_HDA_PULLDN_COMP
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
8 MIL
?
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
HDA_RST_L
TABLE_PHYSICAL_RULE_ITEM
HDA_SDIN0
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
8 MIL
?
HDA_SDOUT
TABLE_SPACING_RULE_ITEM
SPI
*
MCP_HDA_PULLDN_COMP
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.
MCP_SUS_CLK
SPI_CLK
A
SPI_MOSI
SPI_MISO
SPI_CS0
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
SPI_CLK_R
SPI_CLK
SPI_ALT_CLK
SPI_MOSI_R
SPI_MOSI
SPI_ALT_MOSI
SPI_MISO
SPI_MISO_R
SPI_ALT_MISO
SPI_CS0_R_L
SPI_CS0_L
SPI_CS1_R_L
SPI_CS1_R_L_USE_MLB
19C4
12B6 20C3 43D8
12B6 20C3 43D8
20C3 43B8
20C3 43B8
20D2 52C7
20A7 20D4
20D2 52C7
20A7 20D4
20A7 20D4
20D2 52C7
20D7 52C7
20D2 52C7
20A7 20D4
20C7
20B3 24B4
24B1 40C5
MCP Constraints 2
20B3 42A5 42C8
51C5
SYNC_MASTER=T18_MLB
42C5 42D3
20B3 42A5 42C7
SYNC_DATE=12/14/2007
NOTICE OF PROPRIETARY PROPERTY
51C4
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
42C5 42D5
20B3 42A5 42B7
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
51C4
II NOT TO REPRODUCE OR COPY IT
42B5 42D5
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20B3 42B7
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
76
1
81
A
8
6
7
2
3
4
5
1
MCP RGMII (Ethernet) Constraints
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MCP_MII_COMP
*
=STANDARD
7.5 MIL
7.5 MIL
=STANDARD
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MCP_MII_COMP_VDD
MCP_MII_COMP_GND
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S
MCP_BUF0_CLK
ENET_MII_55S
MCP_BUF0_CLK
ENET_INTR_L
ENET_MII_55S
ENET_MII
ENET_MDIO
ENET_MII_55S
ENET_MII
ENET_MDC
ENET_MII_55S
ENET_MII
ENET_PWRDWN_L
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_RXD_STRAP
ENET_MII_55S
ENET_MII
ENET_RXD
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_MII_55S
ENET_MII
ENET_TXCLK
ENET_MII_55S
ENET_MII
ENET_TXD0
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_TXD
ENET_MII_55S
ENET_MII
ENET_CLK125M_TXCLK_R
ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MII_55S
ENET_MII
ENET_RESET_L
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
ENET_MDI_100D
ENET_MDI
TABLE_PHYSICAL_RULE_ITEM
ENET_MII_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1
17C6
17C6
17C3 32A5
31B6 32A3
TABLE_SPACING_RULE_ITEM
MCP_BUF0_CLK
*
=3:1_SPACING
?
ENET_MII
*
12 MIL
?
TABLE_SPACING_RULE_ITEM
D
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
88E1116R (Ethernet PHY) Constraints
ENET_RXCLK
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_MDI_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
25 MIL
?
TABLE_SPACING_RULE_ITEM
ENET_MDI
*
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
ENET_MDI
ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L
ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R<3..0>
ENET_RXD<0>
ENET_RXD<3..1>
ENET_RX_CTRL
ENET_RXCTL_R
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
ENET_MDI_TRAN_P<3..0>
ENET_MDI_TRAN_N<3..0>
17C3 31B6
D
17D3 31B6
31C4
17D6 31C1
31C4
17D6 31C1
17D6 31C1
17D6 31B1
31B4
31C6
17D3 31C8
17D3 31C6
17D3 31C6
17D3 31B6
17C3 31B7
31B3 33B8 33C8
31B3 33B8 33C8
33B4 33C4 33C5
33B4 33C4 33C5
C
C
B
B
Ethernet Constraints
A
SYNC_MASTER=T18_MLB
SYNC_DATE=03/19/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
77
1
81
A
8
6
7
FireWire Interface Constraints
2
3
4
5
1
FireWire Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FW_110D
*
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB
FW_110D
FW_TP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
FW_TP
*
=3:1_SPACING
?
D
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
34B6 36C4
34C6 36C4
34B6 36C4
34B6 36C4
34B6 36B8
34B6 36B8
34B6 36B8
D
34B6 36B8
Port 2 Not Used
SD CARD NET PROPERTIES
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SD CARD INTERFACE CONSTRAINTS
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I23
SD_DATA
I24
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SD_INTERFACE
*
=3X_DIELECTRIC
?
SPACING
SD_55S
SD_INTERFACE
SD_DATA
SD_55S
SD_INTERFACE
I25
SD_DATA
SD_55S
SD_INTERFACE
I26
SD_DATA
SD_55S
SD_INTERFACE
I27
SD_DATA
SD_55S
SD_INTERFACE
I28
SD_DATA
SD_55S
SD_INTERFACE
I29
SD_DATA
SD_55S
SD_INTERFACE
I30
SD_DATA
SD_55S
SD_INTERFACE
I32
SD_CLK
SD_55S
SD_INTERFACE
I31
SD_CMD
SD_55S
SD_INTERFACE
TABLE_PHYSICAL_RULE_ITEM
SD_55S
PHYSICAL
SD_D<0>
SD_D<1>
SD_D<2>
SD_D<3>
SD_D<4>
SD_D<5>
SD_D<6>
SD_D<7>
30C2
30C2
30C2
30C2
30C2
30C2
30C2
30C2
SD_CLK
SD_CMD
30C2
30C2
C
C
B
B
FireWire Constraints
A
SYNC_MASTER=K19_MLB
SYNC_DATE=12/01/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
78
1
81
A
8
6
7
2
3
4
5
1
SMC SMBus Net Properties
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
D
SMBUS_SMC_A_S3_SCL
SMB_55S
SMB
SMBUS_SMC_A_S3_SDA
SMB_55S
SMB
SMBUS_SMC_B_S0_SCL
SMB_55S
SMB
SMBUS_SMC_B_S0_SDA
SMB_55S
SMB
SMBUS_SMC_0_S0_SCL
SMB_55S
SMB
SMBUS_SMC_0_S0_SDA
SMB_55S
SMB
SMBUS_SMC_BSA_SCL
SMB_55S
SMB
SMBUS_SMC_BSA_SDA
SMB_55S
SMB
SMBUS_SMC_MGMT_SCL
SMB_55S
SMB
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
6C5 6D5 43D2
6C5 6D5 43D2
43C2
43C2
43D5
43D5
6A7 43C5
D
6A7 43C5
43B5
43B5
SMBus Charger Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSO_P
CHGR_CSO_N
C
C
B
B
SMC Constraints
A
SYNC_MASTER=T18_MLB
SYNC_DATE=01/04/2008
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
79
1
81
A
8
6
7
2
3
4
5
1
K24 SENSOR NET PROPERTIES
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
D
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
CHGR_CSO_R_P
CHGR_CSO_R_N
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
ISNS_CPUVTT_P
ISNS_CPUVTT_N
ISNS_P1V5S0MCP_P
ISNS_P1V5S0MCP_N
ISNS_PVCORES0MCP_P
ISNS_PVCORES0MCP_N
MCPTHMSNS_D2_P
MCPTHMSNS_D2_N
MCP_THMDIODE_P
MCP_THMDIODE_N
45A8 59B3
45A8 59B3
46C5
46C5
9C6 46D5
9C6 46D5
45B7
D
45B7
6C7 46B5
6C7 46B5
20C3 46B5
20C3 46B5
C
C
B
B
K24 SPECIAL CONSTRAINTS
A
A
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
80
1
81
8
6
7
2
3
4
5
1
K24 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA_P1MM
MM
15.5.1
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_RULE_ITEM
DEFAULT
*
0.1 MM
?
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
*
*
BGA_P1MM
STANDARD
*
=DEFAULT
?
BGA_P1MM
*
=DEFAULT
?
DEFAULT
*
Y
=50_OHM_SE
0.100MM
30 MM
0 MM
0 MM
STANDARD
*
Y
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT
BGA_P2MM
*
=DEFAULT
?
*
BGA_P1MM
BGA_P2MM
CLK_FSB
*
BGA_P1MM
BGA_P2MM
*
=DEFAULT
?
CLK_LPC
*
BGA_P1MM
BGA_P2MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
LINE-TO-LINE SPACING
WEIGHT
TOP,BOTTOM
Y
STANDARD
MEM_40S_VDD
BGA_P1MM
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CLK_PCI
*
BGA_P1MM
BGA_P2MM
CLK_PCIE
*
BGA_P1MM
BGA_P2MM
CLK_SLOW
*
BGA_P1MM
BGA_P2MM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
D
TABLE_SPACING_ASSIGNMENT_ITEM
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
BGA_P1MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD
D
MEM_40S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
BGA_P3MM
PHYSICAL_RULE_SET
BGA_P1MM
MEM_CLK
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
SPACING_RULE_SET
0.090 MM
0.090 MM
LAYER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
1.5:1_SPACING
*
0.15 MM
?
2:1_SPACING
*
0.2 MM
?
TABLE_SPACING_ASSIGNMENT_ITEM
FSB_DSTB
FSB_DSTB
BGA_P1MM
BGA_P3MM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
50_OHM_SE
TOP,BOTTOM
Y
0.115 MM
0.115 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAP
2.5:1_SPACING
*
0.25 MM
?
3:1_SPACING
*
0.3 MM
?
4:1_SPACING
*
0.4 MM
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
TABLE_SPACING_RULE_ITEM
0.100 MM
2X_DIELECTRIC
TOP,BOTTOM
0.140 MM
?
3X_DIELECTRIC
TOP,BOTTOM
0.210 MM
?
4X_DIELECTRIC
TOP,BOTTOM
0.280 MM
?
5X_DIELECTRIC
TOP,BOTTOM
0.350 MM
?
2X_DIELECTRIC
*
0.126 MM
?
3X_DIELECTRIC
*
0.189 MM
?
4X_DIELECTRIC
*
0.252 MM
?
5X_DIELECTRIC
*
0.315 MM
?
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
*
Y
0.126 MM
0.100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.310 MM
27P4_OHM_SE
*
Y
0.222 MM
0.222 MM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
70_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.151 MM
0.100 MM
=STANDARD
0.224 MM
0.224 MM
70_OHM_DIFF
TOP,BOTTOM
Y
0.185 MM
0.100 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.095 MM
0.095 MM
0.234 MM
0.234 MM
90_OHM_DIFF
TOP,BOTTOM
Y
0.112 MM
0.112 MM
0.220 MM
0.220 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.244 MM
0.244 MM
100_OHM_DIFF
TOP,BOTTOM
Y
0.091 MM
0.091 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.075 MM
0.075 MM
0.330 MM
0.330 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
C
C
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
B
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
110_OHM_DIFF
TOP,BOTTOM
Y
0.077 MM
0.077 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
0.330 MM
0.330 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
K24 RULE DEFINITIONS
A
A
SYNC_MASTER=M97_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE INC.
SCALE
SHT
NONE
8
7
6
5
4
3
2
REV.
051-7898
4.7.0
OF
81
1
81
