Spa
Content
KEY FEATURES OF TMS320C6713
D Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6 !3 " #ight 32-$it %nstr&ctions'C(cle " 32'6)-$it Data *or+ " 22,-MH- (.DP)/ !,0-MH- (P0P) Cloc1 2ates " )3)-/ 63 -ns %nstr&ction C(cle Time " !400 M%PS'!3,0 MF56PS/ !200 M%PS '700 MF56PS " 2ich Peri8heral Set/ 68timi-e+ for 9&+io " Highl( 68timi-e+ C'C:: Com8iler D ;elociT%™9+<ance+ ;er( 5ong %nstr&ction *or+ (;5%*) TMS320C6 =™DSP Core " #ight %n+e8en+ent F&nctional >nits: " T?o 95>s (Fi=e+-Point) " Fo&r 95>s (Floating- an+ Fi=e+-Point) " T?o M<i8liers (Floating- an+ Fi=e+-Point) " 5oa+-Store 9rchitect&re *ith 32 32-$it .eneral-P&r8ose 2egisters " %nstr&ction Pac1ing 2e+&ces Co+e Si-e " 9ll %nstr&ctions Con+itional D %nstr&ction Set Feat&res " @ati<e %nstr&ctions for %### ,) " Single- an+ Do&Ale-Precision " $(te-9++ressaAle (4-/ !6-/ 32-$it Data) " 4-$it 6<erflo? Protection " Sat&rationB $it-Fiel+ #=tract/ Set/ ClearB $it-Co&ntingB @ormali-ation D 5!'52 Memor( 9rchitect&re " )C-$(te 5!P Program Cache (Direct-Ma88e+) " )C-$(te 5!D Data Cache (2-*a() " 2,6C-$(te 52 Memor( Total: 6)C-$(te 52 >nifie+ Cache'Ma88e+ 29M/ an+ !72C-$(te 9++itional 52 Ma88e+ 29M D De<ice Config&ration " $oot Mo+e: HP%/ 4-/ !6-/ 32-$it 26M $oot " #n+ianness: 5ittle #n+ian/ $ig #n+ian D 32-$it #=ternal Memor( %nterface (#M%F) " .l&eless %nterface to S29M/ #P26M/ Flash/ S$S29M/ an+ SD29M " ,!2M-$(te Total 9++ressaAle #=ternal Memor( S8ace D #nhance+ Direct-Memor(-9ccess (#DM9) Controller (!6 %n+e8en+ent Channels)
D D
D D
D D D D D
D D D
SPRS186B – DECEMBER 2001 – REVISED NOVEMBER 2002 !6-$it Host-Port %nterface (HP%) T?o M<ichannel 9&+io Serial Ports (Mc9SPs) " T?o %n+e8en+ent Cloc1 Dones #ach (! TE an+ ! 2E) " #ight Serial Data Pins Per Port: %n+i<i+&all( 9ssignaAle to an( of the Cloc1 Dones " #ach Cloc1 Done %ncl&+es: " ProgrammaAle Cloc1 .enerator " ProgrammaAle Frame S(nc .enerator " TDM Streams From 2-32 Time Slots " S&88ort for Slot Si-e: 4/ !2/ !6/ 20/ 2)/ 24/ 32 $its " Data Formatter for $it Mani8&lation " *i+e ;ariet( of %2S an+ Similar $it Stream Formats " %ntegrate+ Digital 9&+io %nterface Transmitter (D%T) S&88orts: " S'PD%F/ %#C607,4-!/ 9#S-3/ CP-)30 Formats " >8 to !6 transmit 8ins " #nhance+ Channel Stat&s'>ser Data " #=tensi<e #rror Chec1ing an+ 2eco<er( T?o %nter-%ntegrate+ Circ&it $&s (%2C $&s™ ) M<i-Master an+ Sla<e %nterfaces T?o M<ichannel $&ffere+ Serial Ports: " Serial-Peri8heral-%nterface (SP%) " High-S8ee+ TDM %nterface " 9C7 %nterface T?o 32-$it .eneral-P&r8ose Timers De+icate+ .P%6 Mo+&le *ith !6 8ins (#=ternal %nterr&8t Ca8aAle) Fle=iAle Phase-5oc1e+-5oo8 (P55) $ase+ Cloc1 .enerator Mo+&le %###-!!)73! (FT9.G) $o&n+ar(-Scan-Com8atiAle Pac1age 68tions: " 204-Pin Po?erP9D™Plastic (5o?-Profile) H&a+ Flat8ac1 (P0P) " 2 2-$all/ $all .ri+ 9rra( Pac1age (.DP) 03!3-∝m'6-5e<el Co88er Metal Process " CM6S Technolog( 333-; %'6s/ !32-; %nternal (P0P) 333-; %'6s/ !326-; %nternal (.DP)
Functional Overview of the TMS320C6713 DSK: 32-bit wide EMIF (External Memory InterFace). The SDRAM, Flash and CPLD are all connected to the bus. EMIF signals are also connected daughter card expansion connectors which are used for third party add-in boards. The DSP interfaces to analog audio signals through an on-board AIC23 codec and four 3.5 mm audio jacks (microphone input, line input, line output, and headphone output). The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP0 is used to send commands to the codec control interface while McBSP1 is used for digital audio data. McBSP0 and McBSP1 can be re-routed to the expansion connectors in software. A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to its registers. The DSK includes 4 LEDs and a 4 position DIP switch as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. An included 5V external power supply is used to power the board. Onboard switching voltage regulators provide the +1.26V DSP core voltage and +3.3V I/O supplies. The board is held in reset until these supplies are within operating specifications. Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulate through the external JTAG connector
Texas Instruments DSP’s can be grouped into the following three categories: • Low Cost !ixed"Point #$"%it &ord Length 'otor control dis( head positioning control T'S)*+C#s ’C*x ’C*,x • Power -fficient !ixed"Point #$%it &ords &ireless phones modems .oIP ’C/x ’C/,x ’C//x • 0igh Performance DSP’s Communications infrastructure xDSL imaging 1ideo ’C$*x 2#$"bit fixed"point3 ’C)x ’C,x ’C$,x ’C$4x 2)*"bit floating"point3 Key features: • A Texas Instruments TMS320C6713 DSP operating at 225 MHz. • An AIC23 stereo codec • 16 Mbytes of synchronous DRAM • 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default configuration) • 4 user accessible LEDs and DIP switches • Software board configuration through registers implemented in CPLD • Configurable boot options • Standard expansion connectors for daughter card use • JTAG emulation through on-board JTAG emulator with USB host
interface or external emulator • Single voltage power supply (+5V) Ba ic O!eration:
The DSK is designed to work with TI’s Code Composer Studio development environment and ships with a version specifically tailored to work with the board. Code Composer communicates with the board through the on-board JTAG emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. After the install is complete, follow these steps to run Code Composer. The DSK must be fully connected to launch the DSK version of Code Composer. 1) Connect the included power supply to the DSK. 2)Connect the DSK to your PC with a standard USB cable (also included). 3) Launch Code Composer from its icon on your desktop.
Functional block diagram of 6713(dsk) started kit:
The ma5or DS6 hardware features are:
• 7 T'S)*+C$4#) DSP operating at **/ '089 • 7n 7IC*) stereo codec with Line In Line :ut 'IC and headphone stereo 5ac(s • #$ 'b;tes of s;nchronous D<7' 2SD<7'3 • /#* 6b;tes of non"1olatile !lash memor; 2*/$ 6b;tes usable in default configuration3 • 9!our user accessible L-Ds and DIP switches • Software board configuration through registers implemented in complex logic de1ice2CPLD3 • Configurable boot options
• -xpansion connectors for daughter cards • =T7> emulation through on"board =T7> emulator with "SB host interface or external emulator Me#or$ Ma!:
The C$4xx famil; of DSPs has a large b;te addressable address space9 Program code and data can be placed an;where in the unified address space9 7ddresses are alwa;s )*"bits wide9 The memory map shows the address space of a generic 6713 processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of the internal memory be reconfigured in software as L2 cache rather than fixed RAM. The EMIF has 4 separate addressable regions called chip enable spaces (CE0-CE3). The SDRAM occupies CE0 while the Flash and CPLD share CE1. CE2 and CE3 are generally reserved for daughtercards.
Confi%uration Switch Settin% : The DSK has 4 configuration switches that allows users to control the operational state of the DSP when it is released from reset. The configuration switch block is labelled SW3 on the DSK board, next to the reset switch. Configuration switch 1 controls the endianness of the DSP while switches 2 and 3 configure the boot mode that will be used when the DSP starts executing. Configuration switch 4 controls the on-chip multiplexing of HPI and McASP signals brought out to the HPI expansion connector. By default all switches are off which corresponds to EMIF boot (out of 8-bit Flash) in little endian mode and HPI signals on the HPI expansion connector.
&ower Su!!l$: The DSK operates from a single +5V external power supply connected to the main power input (J5). Internally, the +5V input is converted into +1.26V and +3.3V using separate voltage regulators. The +1.26V supply is used for the DSP core while the+3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The power connector is a 2.5mm barrel-type plug. There are three power test points on the DSK at JP1, JP2 and JP4. All I/O current passes through JP2 while all core current passes through JP1. All system current passes through JP4. Normally these jumpers are closed. To measure the current passing through remove the jumpers and connect the pins with a current measuring device such as a multimeter or current probe. It is possible to provide the daughter card with +12V and -12V when the external power connector (J6) is used.
Dau%hter Car' (nterface: The DSK provides three expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their DSK platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for memory, peripherals, and the Host Port Interface (HPI). The memory connector provides access to the DSP’s asynchronous EMIF signals to interface with memories and memory mapped devices. It supports byte addressing on 32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals like McBSPs, timers, and clocks. Both connectors provide power and ground to the daughter card. The HPI is a high speed interface that can be used to allow multiple DSPs to communicate and cooperate on a given task. The HPI connector brings out the HPI specific control signals. Most of the expansion connector signals are buffered so that the daughter card cannot directly influence the operation of the DSK board. The use of TI low voltage, 5V tolerant buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be used on the daughter card. Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET and DC_DET exist and are accessible through the CPLD DC_REG register. The DSK also multiplexes the McBSP0 and McBSP1 of on-board or external use. This function is controlled through the CPLD MISC register.
The TMS320C6713 Floatin%)&oint DS&:
The TMS320C6713 Floatin%)&oint DS&: The experiments in this boo( are explained for the Texas Instruments T'S)*+C$4#) DS6 floating"point DSP boards9 !loating"point DSP’s with )*"bit words were chosen for this lab to simplif; the programming tas(s especiall; in a high"le1el language li(e C9 'ost integer DSP’s ha1e #$"bit words so underflow o1erflow and d;namic range must be ta(en into account when programming them9 In addition emulating )*"bit floating"point arithmetic on a #$"bit integer DSP generates inefficient machine code9 In practice integer arithmetic can be used for most applications without 1er; much difficult;9
Therefore high 1olume commercial products almost alwa;s use #$"bit integer DSP’s because the; are faster use less power and are cheaper9 !loating"point DSP’s are used for high"end low 1olume applications9
1*2*1 The +C6000 Central &roce
in% "nit ,C&"-:
'embers of the T'S)*+C$4x famil; of DSP’s all ha1e essentiall; the same central processing unit 2CP?3 which is also called the DSP core9 The CP? has a 1er; long instruction word 2.LI&3 architecture that TI calls .elociTi9 The CP? alwa;s fetches eight )*"bit instructions at once and there is a */$"bit bus to the internal program memor;9 -ach group of eight instructions is called a fetch pac(et9 The CP? has eight functional units that can operate in parallel and are e@uall; split into two hal1es called the 7 or # and % or * sides9 7ll eight units do not ha1e to be gi1en instruction words if the; are not read;9 Therefore instructions are dispatched to the functional units as execute pac(ets with a 1ariable number of )*"bit instruction words9 This 1ariable length feature distinguishes the ’C$+++ CP? from other .LI& architectures9 The eight functional units include: • !our arithmetic and logic units 27L?’s3 that can perform fixed and floating"point operations 29L# 9L* 9S# 9S*3 • Two 7L?’s that perform onl; fixed"point operations 29D# 9D*3 • Two multipliers that can perform fixed or floating"point multiplications 29'# 9'*3
The Multi!lier: The T'S)*+C$4x DSP’s ha1e two multipliers 9'# and 9'*9 -ach multiplier can perform a 1ariet; of #$"bit integer A #$"bit integer products resulting in a )*"bit integer product that is stored in one register9 The; can perform the integer product of the lower #$ bits of one register and the lower #$ bits of another the product of the lower #$ bits of one register and the upper #$ bits of another register etc9 The; can also perform the product of two )*"bit integers resulting in a )*"bit product which is stored in one register and is the lower )* bits of the product or a $,"bit product which is stored in two ad5acent registers with the lower )* bits in the e1en register and upper )* bits in the odd register9 The multipliers can also perform the product of two single" precision floating"point numbers resulting in a single"precision floating"point product9 In addition the; can perform the product of two double"precision floating"point numbers resulting in a double"precision product9 The .eneral &ur!o e /e%i ter File: The CP? has thirt;"two )*"bit general purpose registers split e@uall; between the 7 and % sides9 The CP? has a loadBstore architecture in which all instructions operate on registers9 The data"addressing units 9D# and 9D* are in charge of all data transfers between the register files and memor;9 The four functional units on a side can freel; share the #$ registers on that side9 -ach side has a single data bus connected to all the registers on the other side so the functional units on one side can
access data in the registers on the other side9 7ccess to a register on the same side uses one cloc( c;cle while access to a register on the other side re@uires a read and write c;cle9
0nhance' Direct Me#or$ 1cce
Controller ,0DM1-:
The T'S)*+C$4#) has an enhanced direct memor; access controller 2-D'73 that can transfer data between an; locations in the DSP’s )*"bit address space independentl; of the CP?9 The -D'7 handles all data transfers between the L* cacheBmemor; controller and the peripherals9 These include cache ser1icing non"cacheable memor; access user" programmed data transfers and host access9 It can mo1e data to and from an; addressable memor; spaces including internal memor; 2L* S<7'3 peripherals and external memor;9 The -D'7includes e1ent and interrupt processing registers an e1ent encoder a parameter <7' and address generation hardware9 It has #$ independent channels and the; can be assigned priorities9 Data transfers can be initiated b; the CP? or e1ents from the peripherals and some external pins9 The user can select how e1ents are mapped to the channels9 The -D'7 can transfer elements that are C"bit b;tes #$"bit halfwords or )*"bit words9 .er; sophisticated bloc( transfers can be programmed including transfers of #"dimensional and *" dimensional data bloc(s consisting of multiple frames9
D(/0CT M0MO/2 1CC0SS: Direct memor; access 2D'73 allows for the transfer of data to and from internal memor; or external de1ices without inter1ention from the CP? D4E9 Sixteen enhanced D'7 channels 2-D'73 can be configured independentl; for data transfer9 D'7 can access on"chip memor; and the -'I! as well as the 0PI9 Data of different si8es can be transferred: C"bit b;tes #$" bit half"words and )*"bit words9 7 number of D'7 registers are used to configure the D'7: address 2source and destination3 index count reload D'7 global data and control registers9 Thesource and destination addresses can be from internal program memor; internal data memor; an external memor; interface and an internal peripheral bus9 D'7 transfers can be triggered b; interrupts from internal peripherals as well as from external pins9 !or each resource
each D'7 channel can be programmed for priorities with the CP? with channel + ha1ing the highest priorit;9 -ach D'7 channel can be made to start initiating bloc( transfer of data independentl;97 bloc( can contain a number of frames9&ithin each frame can be man; elements9 -ach element is a single data 1alue9 The D'7 count reload register contains the 1alue to specif; the frame count 2#$ 'S%s3 and the element count 2#$ LS%s39
Data 1li%n#ent: The C$x alwa;s accesses aligned data that allow it to address b;tes half"words and words 2)* bits39 The data format consists of four b;te boundaries two half"word boundaries and one word boundar;9 !or example to assign a )*"bit load with LDW the address must be aligned with a word boundar; so that the lower * bits of the address are 8ero9 :therwise incorrect data can be loaded9 7 double"word 2$, bits3 also can be accessed9 %oth .S1 and .S2 can be used to execute the double"word instruction LDDW to load two $,"bit double words for a total of #*C bits per c;cle9
C&3D ,&ro%ra##a4le 3o%ic-: The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic Device (CPLD) device to implement: • 4 Memory-mapped control/status registers that allow software control of various board features. • Control of the daughter card interface and signals. • Assorted "glue" logic that ties the board components together.
C&3D Overview: The CPLD logic is used to implement functionality specific to the DSK. Your own hardware designs will likely implement a completely different set of functions or take advantage of the DSPs high level of integration for system design and avoid the use of external logic completely. The CPLD implements simple random logic functions that eliminate the need for additional discrete devices. In particular, the CPLD aggregates the various reset signals coming from the reset button and power supervisors and generates a global reset. The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industry standard VHDL (Hardware Design Language) and included with the DSK. C&3D /e%i ter : The 4 CPLD memory-mapped registers allows users to control CPLD functions in software. On the 6713 DSK the registers are primarily used to access the LEDs and DIP switches and control the daughter card interface. The registers are mapped into EMIF CE1 data space at address 0x90080000. They appear as 8-bit registers with a simple asynchronous memory interface. The following table gives a high level overview of the CPLD registers and their bit fields: The table below shows the bit definitions for the 4 registers in CPLD.
"S0/5/0. /e%i ter: USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or off to allow the user to interact with the DSK.
The DIP switches are read by reading thetop 4 bits of the register and the LEDs are set by writing to the low 4 bits.
DC5/0. /e%i ter: DC_REG is used to monitor and control the daughter card interface. DC_DET detects the presence of a daughter card. DC_STAT and DC_CNTL provide simple communications with the daughter cardthrough readable status lines and writable control lines.
The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset.
60/S(O7 /e%i ter: The VERSION register contains two read only fields that indicate the BOARD and CPLD versions. This register will allow your software to differentiate between production releases of the DSK and account for any variances. This register is not expected to change often, if at all.
M(SC /e%i ter: The MISC register is used to provide software control for miscellaneous board functions. On the 6713 DSK, the MISC register controls how auxiliary signals are brought out to the daughter-card connectors. McBSP0 and McBSP1 are usually used as the control and data ports of the on-board AIC23 codec. The power-on state of these bits (both 0s) represents that situation. Set the corresponding McBSP select bit to use the McBSP with a daughter card instead. The Flash and CPLD share CE1 which means that the highest DSP address bit (A21) is used to differentiate between the two. The FLASH_PAGE bit is driven to the Flash as a replacement for that address line which is connected to A19 of the Flash. On a standard DSK, the on-board Flash is not large enough for this bit to be significant. FLASH_PAGE is only useful if the board is re-populated with a larger pin-compatible Flash chip. The scratch bits are unused. They can be set to any value.
S$nchronou D/1M:
The DSK uses a 128 megabit synchronous DRAM (SDRAM) on the 32bit EMIF. The SDRAM is mapped at the beginning of CE0 (address 0x80000000) Total availablememory is 16 megabytes. The integrated SDRAM controller is part of the EMIF and must be configured in software for proper operation. The EMIF clock is derived from the PLL settings and should be configured in software at 90MHz. This number is based on an internal PLL clock of 450MHz required to achieve 225 MHz operation with a divisorof 2 and a 90MHz EMIF clock with a divisor of 5. When using SDRAM, the controller must be set up to refresh one row of the memory array every 15.6 microseconds to maintain data integrity. With a 90MHz EMIF clock, this period is 1400 bus cycles. Fla h Me#or$: Flash is a type of memory which does not lose its contents when the power is turned off. When read it looks like a simple asynchronous readonly memory (ROM).
Flash can be erased in large blocks commonly referred to as sectors or pages. Once a block has been erased each word can be programmed once through a special command sequence. After than the entire block must be erased again to change the contents. The DSK uses a 512Kbyte external Flash as a boot option. It is visible at the beginning of CE1 (address 0x90000000). The Flash is wired as a 256K by 16 bit device to support the DSK's 16-bit boot option. However, the software that ships with the DSK treats the Flash as an 8-bit device (ignoring the top 8 bits) to match the 6713's default 8-bit boot mode. In this configuration, only 256Kbytes are readily usable without software changes.
30D an' D(& Switche :
The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) that provide the user a simple form of input/output. Both are accessed through the CPLD USER_REG register.
/e et Switch: There are three resets on the TMS320C6713 DSK. The first reset is the power on reset. This circuit waits until power is within the specified range before releasing the power on reset pin to the TMS320C6713. External sources which control the reset are push button SW2, and the on board embedded USB JTAG emulator.
Co'e Co#!o er Stu'io:
Fou will constantl; use Texas Instruments’ multi"function program Code Composer Studio 2CCS3 on the PC to generate programs for the T'S)*+C$4#) DSP load them into the DSP memor; run them and monitor program execution9 &ro8ect File an' Buil'in% &ro%ra# : Fou can build a pro5ect in CCS to easil; manage an application in1ol1ing multiple source files libraries memor; maps and special command files9 The file containing all the pro5ect information is gi1en the extension p5t9 %; clic(ing on the <ebuild 7ll or Incremental build tas( bar buttons or b; menu selections ;ou can create an executable module in C:!! 2common ob5ect format file3 that can be loaded into the DSP’s memor;9 The default beha1ior is to use the extension out for executable modules9 To build a program CCS in1o(es the program cl$x9exe with the appropriate command line options input source file names and output file names9 The program cl$x9exe is a shell program that:
#9 compiles C source files using the TI optimi8ing C compiler outputting assembl; modules with the extension asm *9 assembles assembl; and linear assembl; source files including those generated b; the compiler using asm$x9exe creating relocatable ob5ect modules with the extension ob5
)9 lin(s the ob5ect modules and re@uired librar; modules using ln($x9exe according to information in a lin(er command file into an executable C:!! file9 Lin(er command files normall; ha1e the extension cmd9 The Incremental build option onl; compiles and assembles source files that ha1e been modified since the last build speeding up the building process9 !igure #94 illustrates the process of building an executable module9 CCS includes a full featured editor with s;ntax highlighting for entering and modif;ing source code9 &hen a file is compiled or assembled and errors are detected CCS can 5ump from the error message window to the location of the error in the source file displa;ed in the editing window9
The O!ti#i9in% Co#!iler an' 1
e#4ler:
Code Composer Studio includes a CBCGG optimi8ing compiler that con1erts standard 7HSI C source programs into C$+++ assembl; language source9 7n interlist facilit; can be in1o(ed that creates an output file showing each C source statement followed b; the assembl; code generated to implement the statement9 Se1eral le1els of optimi8ation can be used9 The compiler automaticall; schedules parallel use of the ’C$x execution units and inserts H:P’s where necessar; to account for dela; slots9 7t the higher optimi8ation le1els the compiler performs software pipelining which is a techni@ue to ma(e loops execute as efficientl; as possible b; ma(ing maximum parallel use of the execution units and pipeline stages9
This would be extremel; difficult and time consuming b; hand9 7 smart compiler is a necessit; to ma(e the complicated hardware architecture of the ’C$+++ famil; eas; and producti1e to use9 The compiler has se1eral extensions to 7HSI C9 7ssembl; statements can be included inline with the C source code9 This is useful for manipulating registers in the DSP and using special hardware features that are not efficientl; accessible thorough C9 There are also a number of intrinsics that can be used li(e C functions and perform assembl; instructions9 7n interrupt (e;word has been added that can be used to declare a C function to be an interrupt handler9 The compiler then generates the code necessar; to sa1e and restore the machine state on entr; and exit9 7 1olatile (e;word can be used to t;pe a 1ariable so that the optimi8er does not optimi8e it out of existence9 !or example a status register in a serial port ma; change when a word is recei1ed but the compiler will not recogni8e this can happen and assume a reference to the register ne1er changes9 Program efficienc; can be impro1ed significantl; b; using the compiler’s optimi8ation features appropriate compiler directi1es and good memor; assignments9 7nother 5ump in efficienc; can be made b; using the intrinsics9 The; are somewhat similar to inline assembl; instructions and ma(e the compiler use the DSP’s hardware efficientl;9 The trend in industr; these da;s is to write almost an entire application in C because of the speed in writing the program ease of reading b; others and its portabilit; to new DSP t;pes9 Small portions of the program that are time intensi1e ma; be hand programmed and optimi8ed9
The TI code generation tools can profile running programs and produce statistics about the execution time of program segments9 TI has created a language called linear assembl; that is part wa; between pure assembl; language and C9 Linear assembl; source files ha1e the extension sa9 In linear assembl; ;ou do not ha1e to be concerned with assigning registers or pipeline issues9 S;mbolic names can be used for registers9 The assembl; optimi8er assigns registers and optimi8es loops to generate highl; parallel assembl; code9 The assembl; source code files generated b; the compiler and optimi8ing assembler must then be passed through the assembler to generate relocatable ob5ect modules9
!ig: building programs The 3in:er: The final step in building a program is to lin( all the relocatable modules together9 The lin(er ln($x9exe combines relocatable ob5ect modules to form an executable output program9 The default extension for executable programs is out9 In addition the lin(er can generate a map file showing the absolute memor; addresses of all global 1ariables9 7 1er; important input to the lin(er is a lin(er command file which has the extension cmd9 The command file can contain names of additional ob5ect modules to lin( paths to libraries names for the map and out files a memor; map for the target hardware s;stem and commands describing where to put specific program sections in memor;9 Buil'in% &ro%ra# fro# Co##an' 3ine &ro#!t : The programs cl$x9exe asm$x9exe and ln($x9exe can all be executed from a command line prompt9 The general format for in1o(ing the cl$x9exe shell is cl$x D"compiler optionsE DfilenamesE D"8 Dlin( optionsEE Items in rectangular brac(ets are optional9 The entr; DfilenamesE is a list of source files9 !ilenames that ha1e no extension are automaticall; considered to ha1e the extension c and to be C source code9 !ilenames with the extension asm are considered to be assembl; language source code and are assembled and files with the extension sa are treated as linear assembl; source and operated on b; the optimi8ing assembler9 -1er;thing to the right of the "8 option applies onl; to the lin(er9 The assembler and lin(er can be executed in a similar manner9
The 1rchiver: CCS includes an archi1er program ar$x9exe that can be used to build libraries of relocatable ob5ect modules or source files9 It can displa; a table of contents for an archi1e9 The archi1er can also insert modules into or extract modules from an archi1e 9 1''itional Co'e Co#!o er Stu'io Feature : CCS has man; additional features and some are described in the following list9 • Code Composer Studio has extensi1e capabilities for loading running and monitoring program execution9 It is the tool ;ou will almost alwa;s use to load program into the target board memor; and start the program running9 It can single step through C or assembl; instructions stop at brea( points displa; or change the contents of memor; ranges and registers watch selected C 1ariables and profile running programs9 • CCS can send data to the target board from a PC file or read data from probe points in the DSP program to a PC file9 • CCS can capture data from the target board and graph the results as a function of time perform an !!T or displa; a constellation diagram e;e diagram or image9 • CCS has an interpreti1e general extension language 2>-L3 similar to C that allows ;ou to extend CCS’s capabilities9 Through >-L functions CCS can access and change target memor; locations including DSP registers and add options to the CCS menus9 • CCS facilitates building programs including a real"time operating s;stem DSPB%I:S9 &hen CCS does normal file IB: it halts the DSP during the data transfers so the program will not run in real"time9 DSPB%I:S allows real"time data exchange 2<TDI39 DSPB%I:S can run multiple threads with different priorities9 &e will not use this facilit; in our experiments because it adds another le1el of complication and hides the basic DSP software
and hardware issues9 0owe1er it certainl; could be used in further independent pro5ects9 S:'- I'P:<T7HT P:IHTS: CCS pro1ides an ID- to incorporate the software tools9 CCS includes tools for code generation such as a C compiler an assembler and a lin(er9 It has graphical capabilities and supports real"time debugging9 It pro1ides an eas;"to"use software tool to build and debug programs9 The C compiler compiles a C source program with extension .c to produce an assembl; source file with extension .asm9The assembler assembles an.asm source file to produce a machine language ob5ect file with extension.obj9The lin(er combines ob5ect files and ob5ect libraries as input to produce an executable file withextension.out9 This executable file represents a lin(ed common ob5ect file format 2C:!!3 popular in ?nix"based s;stems and adopted b; se1eral ma(ers of digital signal processors D*/E9 This executable file can be loaded and run directl; on the C$4#) processor9 Chapter ) introduces the linear assembl; source file with extension .sa which is a cross between C and assembl; code9 7 linear optimi8er optimi8es this source file to create an assembl; file with extension .asm 2similar to the tas( of the C compiler39 To create an application pro5ect one can JaddK the appropriate files to the pro5ect9 CompilerBlin(er options can readil; be specified9 7 number of debugging features are a1ailable including setting brea(points and watching 1ariablesL 1iewing memor; registers and mixed C and assembl; codeL graphing resultsL and monitoring execution time9 :ne can step through a program in different wa;s 2step into o1er or out39 <eal"time anal;sis can be performed using real"time data exchange 2<TDI3 <TDI allows for data exchange between the
host PC and the target DS6 as well as anal;sis in real time without stopping the target9 6e; statistics andperformance can be monitored in real time9 Through the 5oint team action group 2=T7>3 communication with on"chip emulation support occurs to control and monitor program execution9 The C$4#) DS6 board includes a =T7> interface through the ?S% port9
CCS (n tallation an' Su!!ort: ?se the ?S% cable to connect the DS6 board to the ?S% port on the PC9 ?se the /". power suppl; included with the DS6 pac(age to connect to the G/". power connector on the DS6 to turn it on9 Install CCS with the CD"<:' included with the DS6 preferabl; using the c:\C6713 structure 2in lieu of c:\ti as the default39 The CCS icon should be on the des(top as JC$4#)DS6 CCSK and is used to launch CCS9The code generation tools 2C compiler assembler lin(er3 are used with CCS 1ersion *9x9 CCS pro1ides useful documentations included with the DS6 pac(age on the following 2see the 0elp icon3: 1* Code generation tools 2compiler assembler lin(er etc93 2* Tutorials on CCS compiler <TDI 3* DSP instructions and registers ;* Tools on <TDI DSPBbasic inputBoutput s;stem 2DSPB%I:S3 and so on9 7n extensi1e amount of support material 2pdf files3 is included with CCS9There are also examples included with CCS within the folder c:\C6713\examples9 The; illustrate the board and chip support librar; files DSPB%I:S and so on9 CCS .ersion *9x was used to build and test the examples included in this boo(97 number of files included in the following subfoldersBdirectories within c:\C6713
2suggested structure during CCS installation3 can be 1er; useful: 1. myprojects: a folder supplied onl; for ;our pro5ects9 7ll the folders in the accompan;ing boo( CD should be placed within this subdirector;9 2* bin: contains man; utilities9 3* docs: contains documentation and manuals9 ;* c6000\cgtools: contains code generation tools9 <* c6000\R !": contains support files for real"time data transfer9 6* c6000\bios: contains support files for DSPB%I:S9 7* examples: contains examples included with CCS9 =* tutorial: contains additional examples supplied with CCS9
" eful T$!e of File : Fou will be wor(ing with a number of files with different extensions9 The; include: 1* file.pjt: to create and build a pro5ect named file 2* file.c: C source program 3* file.asm: assembl; source program created b; the user b; the C compiler or b; the linear optimi8er ;* file.sa: linear assembl; source program9The linear optimi8er uses file.sa as input to produce an assembl; program file.asm <* file.h: header support file 6* file.lib: librar; file such as the run"time support librar; file rts6700.lib 7* file.cmd: lin(er command file that maps sections to memor; =* file.obj: ob5ect file created b; the assembler >* file.out: executable file created b; the lin(er to be loaded and run on the C$4#) processor 10* file.cdb: configuration file when using DSPB%I:S9
D Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6 !3 " #ight 32-$it %nstr&ctions'C(cle " 32'6)-$it Data *or+ " 22,-MH- (.DP)/ !,0-MH- (P0P) Cloc1 2ates " )3)-/ 63 -ns %nstr&ction C(cle Time " !400 M%PS'!3,0 MF56PS/ !200 M%PS '700 MF56PS " 2ich Peri8heral Set/ 68timi-e+ for 9&+io " Highl( 68timi-e+ C'C:: Com8iler D ;elociT%™9+<ance+ ;er( 5ong %nstr&ction *or+ (;5%*) TMS320C6 =™DSP Core " #ight %n+e8en+ent F&nctional >nits: " T?o 95>s (Fi=e+-Point) " Fo&r 95>s (Floating- an+ Fi=e+-Point) " T?o M<i8liers (Floating- an+ Fi=e+-Point) " 5oa+-Store 9rchitect&re *ith 32 32-$it .eneral-P&r8ose 2egisters " %nstr&ction Pac1ing 2e+&ces Co+e Si-e " 9ll %nstr&ctions Con+itional D %nstr&ction Set Feat&res " @ati<e %nstr&ctions for %### ,) " Single- an+ Do&Ale-Precision " $(te-9++ressaAle (4-/ !6-/ 32-$it Data) " 4-$it 6<erflo? Protection " Sat&rationB $it-Fiel+ #=tract/ Set/ ClearB $it-Co&ntingB @ormali-ation D 5!'52 Memor( 9rchitect&re " )C-$(te 5!P Program Cache (Direct-Ma88e+) " )C-$(te 5!D Data Cache (2-*a() " 2,6C-$(te 52 Memor( Total: 6)C-$(te 52 >nifie+ Cache'Ma88e+ 29M/ an+ !72C-$(te 9++itional 52 Ma88e+ 29M D De<ice Config&ration " $oot Mo+e: HP%/ 4-/ !6-/ 32-$it 26M $oot " #n+ianness: 5ittle #n+ian/ $ig #n+ian D 32-$it #=ternal Memor( %nterface (#M%F) " .l&eless %nterface to S29M/ #P26M/ Flash/ S$S29M/ an+ SD29M " ,!2M-$(te Total 9++ressaAle #=ternal Memor( S8ace D #nhance+ Direct-Memor(-9ccess (#DM9) Controller (!6 %n+e8en+ent Channels)
D D
D D
D D D D D
D D D
SPRS186B – DECEMBER 2001 – REVISED NOVEMBER 2002 !6-$it Host-Port %nterface (HP%) T?o M<ichannel 9&+io Serial Ports (Mc9SPs) " T?o %n+e8en+ent Cloc1 Dones #ach (! TE an+ ! 2E) " #ight Serial Data Pins Per Port: %n+i<i+&all( 9ssignaAle to an( of the Cloc1 Dones " #ach Cloc1 Done %ncl&+es: " ProgrammaAle Cloc1 .enerator " ProgrammaAle Frame S(nc .enerator " TDM Streams From 2-32 Time Slots " S&88ort for Slot Si-e: 4/ !2/ !6/ 20/ 2)/ 24/ 32 $its " Data Formatter for $it Mani8&lation " *i+e ;ariet( of %2S an+ Similar $it Stream Formats " %ntegrate+ Digital 9&+io %nterface Transmitter (D%T) S&88orts: " S'PD%F/ %#C607,4-!/ 9#S-3/ CP-)30 Formats " >8 to !6 transmit 8ins " #nhance+ Channel Stat&s'>ser Data " #=tensi<e #rror Chec1ing an+ 2eco<er( T?o %nter-%ntegrate+ Circ&it $&s (%2C $&s™ ) M<i-Master an+ Sla<e %nterfaces T?o M<ichannel $&ffere+ Serial Ports: " Serial-Peri8heral-%nterface (SP%) " High-S8ee+ TDM %nterface " 9C7 %nterface T?o 32-$it .eneral-P&r8ose Timers De+icate+ .P%6 Mo+&le *ith !6 8ins (#=ternal %nterr&8t Ca8aAle) Fle=iAle Phase-5oc1e+-5oo8 (P55) $ase+ Cloc1 .enerator Mo+&le %###-!!)73! (FT9.G) $o&n+ar(-Scan-Com8atiAle Pac1age 68tions: " 204-Pin Po?erP9D™Plastic (5o?-Profile) H&a+ Flat8ac1 (P0P) " 2 2-$all/ $all .ri+ 9rra( Pac1age (.DP) 03!3-∝m'6-5e<el Co88er Metal Process " CM6S Technolog( 333-; %'6s/ !32-; %nternal (P0P) 333-; %'6s/ !326-; %nternal (.DP)
Functional Overview of the TMS320C6713 DSK: 32-bit wide EMIF (External Memory InterFace). The SDRAM, Flash and CPLD are all connected to the bus. EMIF signals are also connected daughter card expansion connectors which are used for third party add-in boards. The DSP interfaces to analog audio signals through an on-board AIC23 codec and four 3.5 mm audio jacks (microphone input, line input, line output, and headphone output). The codec can select the microphone or the line input as the active input. The analog output is driven to both the line out (fixed gain) and headphone (adjustable gain) connectors. McBSP0 is used to send commands to the codec control interface while McBSP1 is used for digital audio data. McBSP0 and McBSP1 can be re-routed to the expansion connectors in software. A programmable logic device called a CPLD is used to implement glue logic that ties the board components together. The CPLD has a register based user interface that lets the user configure the board by reading and writing to its registers. The DSK includes 4 LEDs and a 4 position DIP switch as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers. An included 5V external power supply is used to power the board. Onboard switching voltage regulators provide the +1.26V DSP core voltage and +3.3V I/O supplies. The board is held in reset until these supplies are within operating specifications. Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulate through the external JTAG connector
Texas Instruments DSP’s can be grouped into the following three categories: • Low Cost !ixed"Point #$"%it &ord Length 'otor control dis( head positioning control T'S)*+C#s ’C*x ’C*,x • Power -fficient !ixed"Point #$%it &ords &ireless phones modems .oIP ’C/x ’C/,x ’C//x • 0igh Performance DSP’s Communications infrastructure xDSL imaging 1ideo ’C$*x 2#$"bit fixed"point3 ’C)x ’C,x ’C$,x ’C$4x 2)*"bit floating"point3 Key features: • A Texas Instruments TMS320C6713 DSP operating at 225 MHz. • An AIC23 stereo codec • 16 Mbytes of synchronous DRAM • 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default configuration) • 4 user accessible LEDs and DIP switches • Software board configuration through registers implemented in CPLD • Configurable boot options • Standard expansion connectors for daughter card use • JTAG emulation through on-board JTAG emulator with USB host
interface or external emulator • Single voltage power supply (+5V) Ba ic O!eration:
The DSK is designed to work with TI’s Code Composer Studio development environment and ships with a version specifically tailored to work with the board. Code Composer communicates with the board through the on-board JTAG emulator. To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation and drivers. After the install is complete, follow these steps to run Code Composer. The DSK must be fully connected to launch the DSK version of Code Composer. 1) Connect the included power supply to the DSK. 2)Connect the DSK to your PC with a standard USB cable (also included). 3) Launch Code Composer from its icon on your desktop.
Functional block diagram of 6713(dsk) started kit:
The ma5or DS6 hardware features are:
• 7 T'S)*+C$4#) DSP operating at **/ '089 • 7n 7IC*) stereo codec with Line In Line :ut 'IC and headphone stereo 5ac(s • #$ 'b;tes of s;nchronous D<7' 2SD<7'3 • /#* 6b;tes of non"1olatile !lash memor; 2*/$ 6b;tes usable in default configuration3 • 9!our user accessible L-Ds and DIP switches • Software board configuration through registers implemented in complex logic de1ice2CPLD3 • Configurable boot options
• -xpansion connectors for daughter cards • =T7> emulation through on"board =T7> emulator with "SB host interface or external emulator Me#or$ Ma!:
The C$4xx famil; of DSPs has a large b;te addressable address space9 Program code and data can be placed an;where in the unified address space9 7ddresses are alwa;s )*"bits wide9 The memory map shows the address space of a generic 6713 processor on the left with specific details of how each region is used on the right. By default, the internal memory sits at the beginning of the address space. Portions of the internal memory be reconfigured in software as L2 cache rather than fixed RAM. The EMIF has 4 separate addressable regions called chip enable spaces (CE0-CE3). The SDRAM occupies CE0 while the Flash and CPLD share CE1. CE2 and CE3 are generally reserved for daughtercards.
Confi%uration Switch Settin% : The DSK has 4 configuration switches that allows users to control the operational state of the DSP when it is released from reset. The configuration switch block is labelled SW3 on the DSK board, next to the reset switch. Configuration switch 1 controls the endianness of the DSP while switches 2 and 3 configure the boot mode that will be used when the DSP starts executing. Configuration switch 4 controls the on-chip multiplexing of HPI and McASP signals brought out to the HPI expansion connector. By default all switches are off which corresponds to EMIF boot (out of 8-bit Flash) in little endian mode and HPI signals on the HPI expansion connector.
&ower Su!!l$: The DSK operates from a single +5V external power supply connected to the main power input (J5). Internally, the +5V input is converted into +1.26V and +3.3V using separate voltage regulators. The +1.26V supply is used for the DSP core while the+3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The power connector is a 2.5mm barrel-type plug. There are three power test points on the DSK at JP1, JP2 and JP4. All I/O current passes through JP2 while all core current passes through JP1. All system current passes through JP4. Normally these jumpers are closed. To measure the current passing through remove the jumpers and connect the pins with a current measuring device such as a multimeter or current probe. It is possible to provide the daughter card with +12V and -12V when the external power connector (J6) is used.
Dau%hter Car' (nterface: The DSK provides three expansion connectors that can be used to accept plug-in daughter cards. The daughter card allows users to build on their DSK platform to extend its capabilities and provide customer and application specific I/O. The expansion connectors are for memory, peripherals, and the Host Port Interface (HPI). The memory connector provides access to the DSP’s asynchronous EMIF signals to interface with memories and memory mapped devices. It supports byte addressing on 32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals like McBSPs, timers, and clocks. Both connectors provide power and ground to the daughter card. The HPI is a high speed interface that can be used to allow multiple DSPs to communicate and cooperate on a given task. The HPI connector brings out the HPI specific control signals. Most of the expansion connector signals are buffered so that the daughter card cannot directly influence the operation of the DSK board. The use of TI low voltage, 5V tolerant buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be used on the daughter card. Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET and DC_DET exist and are accessible through the CPLD DC_REG register. The DSK also multiplexes the McBSP0 and McBSP1 of on-board or external use. This function is controlled through the CPLD MISC register.
The TMS320C6713 Floatin%)&oint DS&:
The TMS320C6713 Floatin%)&oint DS&: The experiments in this boo( are explained for the Texas Instruments T'S)*+C$4#) DS6 floating"point DSP boards9 !loating"point DSP’s with )*"bit words were chosen for this lab to simplif; the programming tas(s especiall; in a high"le1el language li(e C9 'ost integer DSP’s ha1e #$"bit words so underflow o1erflow and d;namic range must be ta(en into account when programming them9 In addition emulating )*"bit floating"point arithmetic on a #$"bit integer DSP generates inefficient machine code9 In practice integer arithmetic can be used for most applications without 1er; much difficult;9
Therefore high 1olume commercial products almost alwa;s use #$"bit integer DSP’s because the; are faster use less power and are cheaper9 !loating"point DSP’s are used for high"end low 1olume applications9
1*2*1 The +C6000 Central &roce
in% "nit ,C&"-:
'embers of the T'S)*+C$4x famil; of DSP’s all ha1e essentiall; the same central processing unit 2CP?3 which is also called the DSP core9 The CP? has a 1er; long instruction word 2.LI&3 architecture that TI calls .elociTi9 The CP? alwa;s fetches eight )*"bit instructions at once and there is a */$"bit bus to the internal program memor;9 -ach group of eight instructions is called a fetch pac(et9 The CP? has eight functional units that can operate in parallel and are e@uall; split into two hal1es called the 7 or # and % or * sides9 7ll eight units do not ha1e to be gi1en instruction words if the; are not read;9 Therefore instructions are dispatched to the functional units as execute pac(ets with a 1ariable number of )*"bit instruction words9 This 1ariable length feature distinguishes the ’C$+++ CP? from other .LI& architectures9 The eight functional units include: • !our arithmetic and logic units 27L?’s3 that can perform fixed and floating"point operations 29L# 9L* 9S# 9S*3 • Two 7L?’s that perform onl; fixed"point operations 29D# 9D*3 • Two multipliers that can perform fixed or floating"point multiplications 29'# 9'*3
The Multi!lier: The T'S)*+C$4x DSP’s ha1e two multipliers 9'# and 9'*9 -ach multiplier can perform a 1ariet; of #$"bit integer A #$"bit integer products resulting in a )*"bit integer product that is stored in one register9 The; can perform the integer product of the lower #$ bits of one register and the lower #$ bits of another the product of the lower #$ bits of one register and the upper #$ bits of another register etc9 The; can also perform the product of two )*"bit integers resulting in a )*"bit product which is stored in one register and is the lower )* bits of the product or a $,"bit product which is stored in two ad5acent registers with the lower )* bits in the e1en register and upper )* bits in the odd register9 The multipliers can also perform the product of two single" precision floating"point numbers resulting in a single"precision floating"point product9 In addition the; can perform the product of two double"precision floating"point numbers resulting in a double"precision product9 The .eneral &ur!o e /e%i ter File: The CP? has thirt;"two )*"bit general purpose registers split e@uall; between the 7 and % sides9 The CP? has a loadBstore architecture in which all instructions operate on registers9 The data"addressing units 9D# and 9D* are in charge of all data transfers between the register files and memor;9 The four functional units on a side can freel; share the #$ registers on that side9 -ach side has a single data bus connected to all the registers on the other side so the functional units on one side can
access data in the registers on the other side9 7ccess to a register on the same side uses one cloc( c;cle while access to a register on the other side re@uires a read and write c;cle9
0nhance' Direct Me#or$ 1cce
Controller ,0DM1-:
The T'S)*+C$4#) has an enhanced direct memor; access controller 2-D'73 that can transfer data between an; locations in the DSP’s )*"bit address space independentl; of the CP?9 The -D'7 handles all data transfers between the L* cacheBmemor; controller and the peripherals9 These include cache ser1icing non"cacheable memor; access user" programmed data transfers and host access9 It can mo1e data to and from an; addressable memor; spaces including internal memor; 2L* S<7'3 peripherals and external memor;9 The -D'7includes e1ent and interrupt processing registers an e1ent encoder a parameter <7' and address generation hardware9 It has #$ independent channels and the; can be assigned priorities9 Data transfers can be initiated b; the CP? or e1ents from the peripherals and some external pins9 The user can select how e1ents are mapped to the channels9 The -D'7 can transfer elements that are C"bit b;tes #$"bit halfwords or )*"bit words9 .er; sophisticated bloc( transfers can be programmed including transfers of #"dimensional and *" dimensional data bloc(s consisting of multiple frames9
D(/0CT M0MO/2 1CC0SS: Direct memor; access 2D'73 allows for the transfer of data to and from internal memor; or external de1ices without inter1ention from the CP? D4E9 Sixteen enhanced D'7 channels 2-D'73 can be configured independentl; for data transfer9 D'7 can access on"chip memor; and the -'I! as well as the 0PI9 Data of different si8es can be transferred: C"bit b;tes #$" bit half"words and )*"bit words9 7 number of D'7 registers are used to configure the D'7: address 2source and destination3 index count reload D'7 global data and control registers9 Thesource and destination addresses can be from internal program memor; internal data memor; an external memor; interface and an internal peripheral bus9 D'7 transfers can be triggered b; interrupts from internal peripherals as well as from external pins9 !or each resource
each D'7 channel can be programmed for priorities with the CP? with channel + ha1ing the highest priorit;9 -ach D'7 channel can be made to start initiating bloc( transfer of data independentl;97 bloc( can contain a number of frames9&ithin each frame can be man; elements9 -ach element is a single data 1alue9 The D'7 count reload register contains the 1alue to specif; the frame count 2#$ 'S%s3 and the element count 2#$ LS%s39
Data 1li%n#ent: The C$x alwa;s accesses aligned data that allow it to address b;tes half"words and words 2)* bits39 The data format consists of four b;te boundaries two half"word boundaries and one word boundar;9 !or example to assign a )*"bit load with LDW the address must be aligned with a word boundar; so that the lower * bits of the address are 8ero9 :therwise incorrect data can be loaded9 7 double"word 2$, bits3 also can be accessed9 %oth .S1 and .S2 can be used to execute the double"word instruction LDDW to load two $,"bit double words for a total of #*C bits per c;cle9
C&3D ,&ro%ra##a4le 3o%ic-: The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic Device (CPLD) device to implement: • 4 Memory-mapped control/status registers that allow software control of various board features. • Control of the daughter card interface and signals. • Assorted "glue" logic that ties the board components together.
C&3D Overview: The CPLD logic is used to implement functionality specific to the DSK. Your own hardware designs will likely implement a completely different set of functions or take advantage of the DSPs high level of integration for system design and avoid the use of external logic completely. The CPLD implements simple random logic functions that eliminate the need for additional discrete devices. In particular, the CPLD aggregates the various reset signals coming from the reset button and power supervisors and generates a global reset. The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industry standard VHDL (Hardware Design Language) and included with the DSK. C&3D /e%i ter : The 4 CPLD memory-mapped registers allows users to control CPLD functions in software. On the 6713 DSK the registers are primarily used to access the LEDs and DIP switches and control the daughter card interface. The registers are mapped into EMIF CE1 data space at address 0x90080000. They appear as 8-bit registers with a simple asynchronous memory interface. The following table gives a high level overview of the CPLD registers and their bit fields: The table below shows the bit definitions for the 4 registers in CPLD.
"S0/5/0. /e%i ter: USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or off to allow the user to interact with the DSK.
The DIP switches are read by reading thetop 4 bits of the register and the LEDs are set by writing to the low 4 bits.
DC5/0. /e%i ter: DC_REG is used to monitor and control the daughter card interface. DC_DET detects the presence of a daughter card. DC_STAT and DC_CNTL provide simple communications with the daughter cardthrough readable status lines and writable control lines.
The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset.
60/S(O7 /e%i ter: The VERSION register contains two read only fields that indicate the BOARD and CPLD versions. This register will allow your software to differentiate between production releases of the DSK and account for any variances. This register is not expected to change often, if at all.
M(SC /e%i ter: The MISC register is used to provide software control for miscellaneous board functions. On the 6713 DSK, the MISC register controls how auxiliary signals are brought out to the daughter-card connectors. McBSP0 and McBSP1 are usually used as the control and data ports of the on-board AIC23 codec. The power-on state of these bits (both 0s) represents that situation. Set the corresponding McBSP select bit to use the McBSP with a daughter card instead. The Flash and CPLD share CE1 which means that the highest DSP address bit (A21) is used to differentiate between the two. The FLASH_PAGE bit is driven to the Flash as a replacement for that address line which is connected to A19 of the Flash. On a standard DSK, the on-board Flash is not large enough for this bit to be significant. FLASH_PAGE is only useful if the board is re-populated with a larger pin-compatible Flash chip. The scratch bits are unused. They can be set to any value.
S$nchronou D/1M:
The DSK uses a 128 megabit synchronous DRAM (SDRAM) on the 32bit EMIF. The SDRAM is mapped at the beginning of CE0 (address 0x80000000) Total availablememory is 16 megabytes. The integrated SDRAM controller is part of the EMIF and must be configured in software for proper operation. The EMIF clock is derived from the PLL settings and should be configured in software at 90MHz. This number is based on an internal PLL clock of 450MHz required to achieve 225 MHz operation with a divisorof 2 and a 90MHz EMIF clock with a divisor of 5. When using SDRAM, the controller must be set up to refresh one row of the memory array every 15.6 microseconds to maintain data integrity. With a 90MHz EMIF clock, this period is 1400 bus cycles. Fla h Me#or$: Flash is a type of memory which does not lose its contents when the power is turned off. When read it looks like a simple asynchronous readonly memory (ROM).
Flash can be erased in large blocks commonly referred to as sectors or pages. Once a block has been erased each word can be programmed once through a special command sequence. After than the entire block must be erased again to change the contents. The DSK uses a 512Kbyte external Flash as a boot option. It is visible at the beginning of CE1 (address 0x90000000). The Flash is wired as a 256K by 16 bit device to support the DSK's 16-bit boot option. However, the software that ships with the DSK treats the Flash as an 8-bit device (ignoring the top 8 bits) to match the 6713's default 8-bit boot mode. In this configuration, only 256Kbytes are readily usable without software changes.
30D an' D(& Switche :
The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) that provide the user a simple form of input/output. Both are accessed through the CPLD USER_REG register.
/e et Switch: There are three resets on the TMS320C6713 DSK. The first reset is the power on reset. This circuit waits until power is within the specified range before releasing the power on reset pin to the TMS320C6713. External sources which control the reset are push button SW2, and the on board embedded USB JTAG emulator.
Co'e Co#!o er Stu'io:
Fou will constantl; use Texas Instruments’ multi"function program Code Composer Studio 2CCS3 on the PC to generate programs for the T'S)*+C$4#) DSP load them into the DSP memor; run them and monitor program execution9 &ro8ect File an' Buil'in% &ro%ra# : Fou can build a pro5ect in CCS to easil; manage an application in1ol1ing multiple source files libraries memor; maps and special command files9 The file containing all the pro5ect information is gi1en the extension p5t9 %; clic(ing on the <ebuild 7ll or Incremental build tas( bar buttons or b; menu selections ;ou can create an executable module in C:!! 2common ob5ect format file3 that can be loaded into the DSP’s memor;9 The default beha1ior is to use the extension out for executable modules9 To build a program CCS in1o(es the program cl$x9exe with the appropriate command line options input source file names and output file names9 The program cl$x9exe is a shell program that:
#9 compiles C source files using the TI optimi8ing C compiler outputting assembl; modules with the extension asm *9 assembles assembl; and linear assembl; source files including those generated b; the compiler using asm$x9exe creating relocatable ob5ect modules with the extension ob5
)9 lin(s the ob5ect modules and re@uired librar; modules using ln($x9exe according to information in a lin(er command file into an executable C:!! file9 Lin(er command files normall; ha1e the extension cmd9 The Incremental build option onl; compiles and assembles source files that ha1e been modified since the last build speeding up the building process9 !igure #94 illustrates the process of building an executable module9 CCS includes a full featured editor with s;ntax highlighting for entering and modif;ing source code9 &hen a file is compiled or assembled and errors are detected CCS can 5ump from the error message window to the location of the error in the source file displa;ed in the editing window9
The O!ti#i9in% Co#!iler an' 1
e#4ler:
Code Composer Studio includes a CBCGG optimi8ing compiler that con1erts standard 7HSI C source programs into C$+++ assembl; language source9 7n interlist facilit; can be in1o(ed that creates an output file showing each C source statement followed b; the assembl; code generated to implement the statement9 Se1eral le1els of optimi8ation can be used9 The compiler automaticall; schedules parallel use of the ’C$x execution units and inserts H:P’s where necessar; to account for dela; slots9 7t the higher optimi8ation le1els the compiler performs software pipelining which is a techni@ue to ma(e loops execute as efficientl; as possible b; ma(ing maximum parallel use of the execution units and pipeline stages9
This would be extremel; difficult and time consuming b; hand9 7 smart compiler is a necessit; to ma(e the complicated hardware architecture of the ’C$+++ famil; eas; and producti1e to use9 The compiler has se1eral extensions to 7HSI C9 7ssembl; statements can be included inline with the C source code9 This is useful for manipulating registers in the DSP and using special hardware features that are not efficientl; accessible thorough C9 There are also a number of intrinsics that can be used li(e C functions and perform assembl; instructions9 7n interrupt (e;word has been added that can be used to declare a C function to be an interrupt handler9 The compiler then generates the code necessar; to sa1e and restore the machine state on entr; and exit9 7 1olatile (e;word can be used to t;pe a 1ariable so that the optimi8er does not optimi8e it out of existence9 !or example a status register in a serial port ma; change when a word is recei1ed but the compiler will not recogni8e this can happen and assume a reference to the register ne1er changes9 Program efficienc; can be impro1ed significantl; b; using the compiler’s optimi8ation features appropriate compiler directi1es and good memor; assignments9 7nother 5ump in efficienc; can be made b; using the intrinsics9 The; are somewhat similar to inline assembl; instructions and ma(e the compiler use the DSP’s hardware efficientl;9 The trend in industr; these da;s is to write almost an entire application in C because of the speed in writing the program ease of reading b; others and its portabilit; to new DSP t;pes9 Small portions of the program that are time intensi1e ma; be hand programmed and optimi8ed9
The TI code generation tools can profile running programs and produce statistics about the execution time of program segments9 TI has created a language called linear assembl; that is part wa; between pure assembl; language and C9 Linear assembl; source files ha1e the extension sa9 In linear assembl; ;ou do not ha1e to be concerned with assigning registers or pipeline issues9 S;mbolic names can be used for registers9 The assembl; optimi8er assigns registers and optimi8es loops to generate highl; parallel assembl; code9 The assembl; source code files generated b; the compiler and optimi8ing assembler must then be passed through the assembler to generate relocatable ob5ect modules9
!ig: building programs The 3in:er: The final step in building a program is to lin( all the relocatable modules together9 The lin(er ln($x9exe combines relocatable ob5ect modules to form an executable output program9 The default extension for executable programs is out9 In addition the lin(er can generate a map file showing the absolute memor; addresses of all global 1ariables9 7 1er; important input to the lin(er is a lin(er command file which has the extension cmd9 The command file can contain names of additional ob5ect modules to lin( paths to libraries names for the map and out files a memor; map for the target hardware s;stem and commands describing where to put specific program sections in memor;9 Buil'in% &ro%ra# fro# Co##an' 3ine &ro#!t : The programs cl$x9exe asm$x9exe and ln($x9exe can all be executed from a command line prompt9 The general format for in1o(ing the cl$x9exe shell is cl$x D"compiler optionsE DfilenamesE D"8 Dlin( optionsEE Items in rectangular brac(ets are optional9 The entr; DfilenamesE is a list of source files9 !ilenames that ha1e no extension are automaticall; considered to ha1e the extension c and to be C source code9 !ilenames with the extension asm are considered to be assembl; language source code and are assembled and files with the extension sa are treated as linear assembl; source and operated on b; the optimi8ing assembler9 -1er;thing to the right of the "8 option applies onl; to the lin(er9 The assembler and lin(er can be executed in a similar manner9
The 1rchiver: CCS includes an archi1er program ar$x9exe that can be used to build libraries of relocatable ob5ect modules or source files9 It can displa; a table of contents for an archi1e9 The archi1er can also insert modules into or extract modules from an archi1e 9 1''itional Co'e Co#!o er Stu'io Feature : CCS has man; additional features and some are described in the following list9 • Code Composer Studio has extensi1e capabilities for loading running and monitoring program execution9 It is the tool ;ou will almost alwa;s use to load program into the target board memor; and start the program running9 It can single step through C or assembl; instructions stop at brea( points displa; or change the contents of memor; ranges and registers watch selected C 1ariables and profile running programs9 • CCS can send data to the target board from a PC file or read data from probe points in the DSP program to a PC file9 • CCS can capture data from the target board and graph the results as a function of time perform an !!T or displa; a constellation diagram e;e diagram or image9 • CCS has an interpreti1e general extension language 2>-L3 similar to C that allows ;ou to extend CCS’s capabilities9 Through >-L functions CCS can access and change target memor; locations including DSP registers and add options to the CCS menus9 • CCS facilitates building programs including a real"time operating s;stem DSPB%I:S9 &hen CCS does normal file IB: it halts the DSP during the data transfers so the program will not run in real"time9 DSPB%I:S allows real"time data exchange 2<TDI39 DSPB%I:S can run multiple threads with different priorities9 &e will not use this facilit; in our experiments because it adds another le1el of complication and hides the basic DSP software
and hardware issues9 0owe1er it certainl; could be used in further independent pro5ects9 S:'- I'P:<T7HT P:IHTS: CCS pro1ides an ID- to incorporate the software tools9 CCS includes tools for code generation such as a C compiler an assembler and a lin(er9 It has graphical capabilities and supports real"time debugging9 It pro1ides an eas;"to"use software tool to build and debug programs9 The C compiler compiles a C source program with extension .c to produce an assembl; source file with extension .asm9The assembler assembles an.asm source file to produce a machine language ob5ect file with extension.obj9The lin(er combines ob5ect files and ob5ect libraries as input to produce an executable file withextension.out9 This executable file represents a lin(ed common ob5ect file format 2C:!!3 popular in ?nix"based s;stems and adopted b; se1eral ma(ers of digital signal processors D*/E9 This executable file can be loaded and run directl; on the C$4#) processor9 Chapter ) introduces the linear assembl; source file with extension .sa which is a cross between C and assembl; code9 7 linear optimi8er optimi8es this source file to create an assembl; file with extension .asm 2similar to the tas( of the C compiler39 To create an application pro5ect one can JaddK the appropriate files to the pro5ect9 CompilerBlin(er options can readil; be specified9 7 number of debugging features are a1ailable including setting brea(points and watching 1ariablesL 1iewing memor; registers and mixed C and assembl; codeL graphing resultsL and monitoring execution time9 :ne can step through a program in different wa;s 2step into o1er or out39 <eal"time anal;sis can be performed using real"time data exchange 2<TDI3 <TDI allows for data exchange between the
host PC and the target DS6 as well as anal;sis in real time without stopping the target9 6e; statistics andperformance can be monitored in real time9 Through the 5oint team action group 2=T7>3 communication with on"chip emulation support occurs to control and monitor program execution9 The C$4#) DS6 board includes a =T7> interface through the ?S% port9
CCS (n tallation an' Su!!ort: ?se the ?S% cable to connect the DS6 board to the ?S% port on the PC9 ?se the /". power suppl; included with the DS6 pac(age to connect to the G/". power connector on the DS6 to turn it on9 Install CCS with the CD"<:' included with the DS6 preferabl; using the c:\C6713 structure 2in lieu of c:\ti as the default39 The CCS icon should be on the des(top as JC$4#)DS6 CCSK and is used to launch CCS9The code generation tools 2C compiler assembler lin(er3 are used with CCS 1ersion *9x9 CCS pro1ides useful documentations included with the DS6 pac(age on the following 2see the 0elp icon3: 1* Code generation tools 2compiler assembler lin(er etc93 2* Tutorials on CCS compiler <TDI 3* DSP instructions and registers ;* Tools on <TDI DSPBbasic inputBoutput s;stem 2DSPB%I:S3 and so on9 7n extensi1e amount of support material 2pdf files3 is included with CCS9There are also examples included with CCS within the folder c:\C6713\examples9 The; illustrate the board and chip support librar; files DSPB%I:S and so on9 CCS .ersion *9x was used to build and test the examples included in this boo(97 number of files included in the following subfoldersBdirectories within c:\C6713
2suggested structure during CCS installation3 can be 1er; useful: 1. myprojects: a folder supplied onl; for ;our pro5ects9 7ll the folders in the accompan;ing boo( CD should be placed within this subdirector;9 2* bin: contains man; utilities9 3* docs: contains documentation and manuals9 ;* c6000\cgtools: contains code generation tools9 <* c6000\R !": contains support files for real"time data transfer9 6* c6000\bios: contains support files for DSPB%I:S9 7* examples: contains examples included with CCS9 =* tutorial: contains additional examples supplied with CCS9
" eful T$!e of File : Fou will be wor(ing with a number of files with different extensions9 The; include: 1* file.pjt: to create and build a pro5ect named file 2* file.c: C source program 3* file.asm: assembl; source program created b; the user b; the C compiler or b; the linear optimi8er ;* file.sa: linear assembl; source program9The linear optimi8er uses file.sa as input to produce an assembl; program file.asm <* file.h: header support file 6* file.lib: librar; file such as the run"time support librar; file rts6700.lib 7* file.cmd: lin(er command file that maps sections to memor; =* file.obj: ob5ect file created b; the assembler >* file.out: executable file created b; the lin(er to be loaded and run on the C$4#) processor 10* file.cdb: configuration file when using DSPB%I:S9
