VHDL Programs

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[Type text]

EXPERIMENT NUMBER 1
One Bit AND Gate,OR Gate and NOT Gate
AND GATE
File 1:
entity myand is
port(x,y:in bit;
z:out bit);
end entity;
architecture myand_arch of myand is
begin
z<=x and y;
end myand_arch;

File 2:
entity testbench is
end entity;
architecture test_arch of testbench is
component myand is
port(x,y:in bit;
z:out bit);
end component;
signal xt,yt,zt:bit;
begin
west: myand port map(xt,yt,zt);
process
begin
xt<='0';
yt<='0';
wait for 10 ns;
xt<='0';
yt<='1';
wait for 10 ns;
xt<='1';
yt<='1';
wait for 10 ns;
end process;
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end test_arch;

NOT GATE
File 1:
entity mynot is
port(x:in bit;
z:out bit);
end entity;
architecture mynot_arch of mynot is
begin
z<=not x;
end mynot_arch;

OR GATE
File 1:
entity myor is
port(x,y:in bit;
z:out bit);
end entity;
architecture myor_arch of myor is
begin
z>=x or y;
end myor_arch;

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EXPERIMENT NUMBER 2
One Bit Half Adder

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One Bit Full Adder

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EXPERIMENT NUMBER 3
FULLADDER
entity fulladder is
port(x,y,z:in bit; s,c:out bit);
end fulladder;
architecture fulladder_arch of fulladder is
begin
c <= ((x and y) or (y and z) or (z and x));
s <= (x xor y xor z);
end fulladder_arch;

FULL4BIT_ADDER
entity full4bit is
port(in1,in2:in bit_vector(3 downto 0); cin:in bit; output:out bit_vector(3 downto 0); cout:out bit);
end full4bit;
architecture full4bit_arch of full4bit is
component fulladder is
port(x,y,z:in bit; s,c:out bit);
end component;
signal c1:bit;
signal c2:bit;
signal c3:bit;
signal c4:bit;
begin
inst0: fulladder port map(in1(0), in2(0), cin, output(0), c1);
inst1: fulladder port map(in1(1), in2(1), c1, output(1), c2);
inst2: fulladder port map(in1(2), in2(2), c2, output(2), c3);
inst3: fulladder port map(in1(3), in2(3), c3, output(3), cout);
end full4bit_arch;

[Type text]

BCD ADDER
entity bcd_adder is
port(in1,in2: bit_vector(3 downto 0); cin:in bit; output:out bit_vector(3 downto 0); carry_out:out
bit);
end bcd_adder;
architecture bcd_adder_arch of bcd_adder is
component full4bit is
port(in1,in2:in bit_vector(3 downto 0); cin:in bit; output:out bit_vector(3 downto 0); cout:out bit);
end component;
signal temp, new_sum:bit_vector(3 downto 0);
signal c:bit;
signal d:bit;
signal z:bit;
begin
inst0: full4bit port map(in1,in2,cin,temp,c);
z <= c or (temp(3) and temp(2)) or (temp(3) and temp(1));
new_sum(0) <= z and '0';
new_sum(1) <= z and '1';
new_sum(2) <= z and '1';
new_sum(3) <= z and '0';
inst1: full4bit port map(temp, new_sum, '0', output, d);
carry_out <= z;
end bcd_adder_arch;

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EXPERIMENT NUMBER 4
PROGRAM 8 : 4 bit by 3 bit array multiplier
File 1:
entity fa1bitnew is
port( x,y,cin:in bit;
s,cout:out bit);
end entity;
architecture fa1bitnew_arch of fa1bitnew is
begin
s<=(x xor y)xor cin;
cout<=(x and y)or(x and cin)or(y and cin);
end fa1bitnew_arch;

File 2:
entity fa4for is
port(x1,y1:in bit_vector(3 downto 0);
z1:out bit_vector(4 downto 0));
end entity;
architecture fa4for of fa4for is
component fa1bitnew is
port( x,y,cin:in bit;
s,cout:out bit);
end component;
signal tc: bit_vector(4 downto 0);
begin
tc(0)<='0';
inst0: for i in 0 to 3 generate
inst1:fa1bitnew port map(x1(i),y1(i),tc(i),z1(i),tc(i+1));
end generate;
z1(4)<=tc(4);
end fa4for;

File 3:
entity arraymult is
port(a:in bit_vector(2 downto 0);
b:in bit_vector(3 downto 0);
c:out bit_vector(6 downto 0));
end entity;
architecture arraymult of arraymult is
component fa4for is
port(x1,y1:in bit_vector(3 downto 0);
z1:out bit_vector(4 downto 0));

[Type text]

end component;
signal x11,x12,y11:bit_vector(3 downto 0);
signal y12:bit_vector(4 downto 0);
begin
c(0)<=b(0)and a(0);
inst0:for i in 0 to 3 generate
x11(i)<=a(1) and b(i);
end generate;
inst1:for i in 0 to 2 generate
y11(i)<=a(0) and b(i+1);
end generate;
y11(3)<='0';
inst2: fa4for port map(x11,y11,y12);
c(1)<=y12(0);
inst3:for i in 0 to 3 generate
x12(i)<=a(2) and b(i);
end generate;
inst4: fa4for port map(x12,y12(4 downto 1),c(6 downto 2));
end arraymult;

File 4:
entity test_arraymult is
end entity;
architecture test_arraymult of test_arraymult is
component arraymult is
port(a:in bit_vector(2 downto 0);
b:in bit_vector(3 downto 0);
c:out bit_vector(6 downto 0));
end component;
signal at:bit_vector(2 downto 0);
signal bt:bit_vector(3 downto 0);
signal ct:bit_vector(6 downto 0);
begin
inst:arraymult port map(at,bt,ct);
process
begin
at<="000";
bt<="0101";
wait for 10 ns;
at<="001";
bt<="0101";
wait for 10 ns;
at<="111";
bt<="0111";
wait for 10 ns;
end process;
end test_arraymult;

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EXPERIMENT NUMBER 5
3X8 Decoder

16

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EXPERIMENT NUMBER 6
Design a 4X1 Multiplexer

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EXPERIMENT NUMBER 7
JK Flip Flop

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EXPERIMENT NUMBER 8
T Flip Flop

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EXPERIMENT NUMBER 9
D Flip Flop

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EXPERIMENT NUMBER 10
4 Bit Comparator
4BIT COMPARATOR
Comparator

entity comparator is
port( a,b : in bit_vector(3 downto 0);
g,l,e : out bit);
end comparator;
architecture arch_comparator of comparator is
begin
process (a,b)
begin
IF (a(3)='0' AND b(3)='1') THEN
l <= '1';e <= '0';g <= '0';
ELSE IF (a(3)='1' AND b(3)='0') THEN l <= '0';e <= '0';g <= '1';
ELSE IF (a(2)='0' AND b(2)='1') THEN l <= '1';e <= '0';g <= '0';
ELSE IF (a(2)='1' AND b(2)='0') THEN l <= '0';e <= '0';g <= '1';
ELSE IF (a(1)='0' AND b(1)='1') THEN l <= '1';e <= '0';g <= '0';
ELSE IF (a(1)='1' AND b(1)='0') THEN l <= '0';e <= '0';g <= '1';
ELSE IF (a(0)='0' AND b(0)='1') THEN l <= '1';e <= '0';g <=
'0';
ELSE IF (a(0)='1' AND b(0)='0') THEN l <= '0';e <= '0';g
<= '1';
ELSE
l <= '0';e <= '1';g <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
end process;
end arch_comparator;
entity testbench_comparator is
end testbench_comparator;

Comparator Test Bench

architecture arch_testbench_comparator of testbench_comparator is
component comparator is
18

[Type text]

port( a,b : in bit_vector(3 downto 0);
g,l,e : out bit);
end component;
signal a,b:bit_vector(3 downto 0);
signal g,l,e : bit;
begin
inst1 : comparator port map (a,b,g,l,e);
process
begin
a<="0000";
b<="0000";
wait for 20 ns;
a<="1111";
b<="1111";
wait for 20 ns;
a<="1100";
b<="0011";
wait for 20 ns;
a<="1010";
b<="1111";
wait for 20 ns;
end process;
end arch_testbench_comparator;

19

[Type text]

EXPERIMENT NUMBER 11
8 bit shifter
SHIFTER

entity shifter is
port (si,clk,clr:in bit;s1,s2,s3,s4,s5,s6,s7,s8:inout bit);
end shifter;
architecture arc of shifter is
component dff is
port (d,clk,clr:in bit;q :out bit);
end component;
begin
d1: dff port map(si,clk,clr,s1);
d2:dff port map(s1,clk,clr,s2);
d3:dff port map(s2,clk,clr,s3);
d4:dff port map(s3,clk,clr,s4);
d5:dff port map(s4,clk,clr,s5);
d6:dff port map(s5,clk,clr,s6);
d7:dff port map(s6,clk,clr,s7);
d8:dff port map(s7,clk,clr,s8);
end architecture;
TEST BENCH SHIFTER

entity tb is
end tb;
architecture test of tb is

20

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component shifter is
port (si,clk,clr:in bit;s1,s2,s3,s4,s5,s6,s7,s8:inout bit);
end component;
signal si1,clk1,clr1:bit;
signal s:bit_vector(7 downto 0);
begin
shift1: shifter port map(si1,clk1,clr1,s(0),s(1),s(2),s(3),s(4),s(5),s(6),s(7));
process
begin
si1<=not si1 after 30 ns;
clk1<=not clk1;
wait for 10 ns;
end process;
end architecture;

21

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E X P E R I M E N T N U M B E R 12
Arithmetic Logic Unit

ALU

entity alu is
port (L,M:in bit_vector(3 downto 0);
CIN,SEL1,SEL2,SEL3: in bit;
FOUT: out bit_vector(3 downto 0));
end entity;
architecture alu_arch of alu is
component arthm_comp is
port (x,y: in bit_vector(3 downto 0);
cin,op1,op2: in bit;
f1: out bit_vector(3 downto 0));
end component;
component logical is
port(x: in bit_vector(3 downto 0);
y: in bit_vector(3 downto 0);
op1,op2: in bit;
f2: out bit_vector(3 downto 0));
end component;
component mux2x1 is
port (i1,i2: in bit;
s1: in bit;
e: out bit);
end component;
signal val1,val2: bit_vector(3 downto 0);
begin
AC: arthm_comp port map(L,M,CIN,SEL1,SEL2,val1);
LC: logical port map(L,M,SEL1,SEL2,val2);
MUX1: mux2x1 port map(val1(0),val2(0),SEL3,FOUT(0));
MUX2: mux2x1 port map(val1(1),val2(1),SEL3,FOUT(1));
MUX3: mux2x1 port map(val1(2),val2(2),SEL3,FOUT(2));
MUX4: mux2x1 port map(val1(3),val2(3),SEL3,FOUT(3));
end alu_arch;

2X 1 MUX

entity mux2x1 is

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port (i1,i2: in bit;
s1: in bit;
e: out bit);
end entity;
architecture mux2x1_arch of mux2x1 is
begin
e <= i1 when s1='0' else
i2;
end mux2x1_arch;

4X 1 MUX

entity mux4x1 is
port (i: in bit;
s1,s2: in bit;
e: out bit);
end entity;
architecture mux4x1_arch of mux4x1 is
begin
e <= i when s1='0' and s2='0' else
not i when s1='0' and s2='1' else
'0' when s1='1' and s2='0' else
'1' ;
end mux4x1_arch;

1 BIT FULL ADDER
entity fa_1bit is
port ( a , b, cin : in bit ;
f, cout : out bit);
end entity;

architecture fa_1bit_arch of fa_1bit is
begin
f <= a xor (b xor cin) ;
cout <= (a and b ) or ( a and cin) or (b and cin) ;
end fa_1bit_arch ;

4 BIT FULL ADDER
entity fa_4bit is
port ( x , y : in bit_vector( 3 downto 0);
carryin,op1,op2 : in bit;
z : out bit_vector( 3 downto 0);
carryout : out bit);

23

[Type text]

end entity ;
architecture fa_4bit_arch of fa_4bit is
component fa_1bit is
port ( a , b, cin : in bit ;
f, cout : out bit);
end component ;
component mux4x1 is
port (i: in bit;
s1,s2: in bit;
e: out bit);
end component;
signal tmp_carry : bit_vector ( 2 downto 0);
signal muxop:bit_vector(3 downto 0);
begin
inst1: mux4x1 port map(y(0),op1,op2,muxop(0));
inst2: mux4x1 port map(y(1),op1,op2,muxop(1));
inst3: mux4x1 port map(y(2),op1,op2,muxop(2));
inst4: mux4x1 port map(y(3),op1,op2,muxop(3));
inst5: fa_1bit port map(x(0), muxop(0), carryin, z(0), tmp_carry(0) );
inst6: fa_1bit port map(x(1), muxop(1), tmp_carry(0), z(1), tmp_carry(1) );
inst7: fa_1bit port map(x(2), muxop(2), tmp_carry(1), z(2), tmp_carry(2) );
inst8: fa_1bit port map(x(3), muxop(3), tmp_carry(2), z(3), carryout );
end fa_4bit_arch ;

ARITHMETIC COMPONENT
entity arthm_comp is
port (x,y: in bit_vector(3 downto 0);
cin,op1,op2: in bit;
f1: out bit_vector(3 downto 0));
end entity;
architecture arthm_comp_arch of arthm_comp is
component fa_4bit is
port ( x , y : in bit_vector( 3 downto 0);
carryin,op1,op2 : in bit;
z : out bit_vector( 3 downto 0);
carryout : out bit);
end component;

24

[Type text]

begin
adder_4bit: fa_4bit port map(x,y,cin,op1,op2,f1);
end arthm_comp_arch;

LOGICAL COMPONENT
entity logical is
port(x: in bit_vector(3 downto 0);
y: in bit_vector(3 downto 0);
op1,op2: in bit;
f2: out bit_vector(3 downto 0));
end entity;
architecture logical_arch of logical is
begin
f2 <= x and y when op1='0' and op2='0' else
x or y when op1='0' and op2='1' else
x xor y when op1='1' and op2='0' else
not x;
end logical_arch;

A L U TEST BENCH

entity alu_testbench is
end entity;
architecture alu_test_arch of alu_testbench is
component alu is
port (L,M:in bit_vector(3 downto 0);
CIN,SEL1,SEL2,SEL3: in bit;
FOUT: out bit_vector(3 downto 0));
end component;
signal in1,in2,out1:bit_vector(3 downto 0);
signal cin,s1,s2,s3 :bit;

begin
inst1: alu port map(in1,in2,cin,s1,s2,s3,out1);
process
begin
in1 <= "0001";
in2 <= "0101";
cin <='0';
s1 <= '0';
s2 <= '0';

25

[Type text]

s3 <= '0';
wait for 20 ns;
s1 <= '0';
s2 <= '1';
wait for 20 ns;
s1 <= '1';
s2 <= '0';
wait for 20 ns;
s1 <= '1';
s2 <= '1';
wait for 20 ns;
s1 <= '0';
s2 <= '0';
s3 <= '1';
wait for 20 ns;
end process;
end alu_test_arch;

LOGICAL UNIT TEST BENCH

entity logic_test is
end entity;
architecture logic_test_arch of logic_test is
component logical is
port(x: in bit_vector(3 downto 0);
y: in bit_vector(3 downto 0);
op1,op2: in bit;
f2: out bit_vector(3 downto 0));
end component;
signal in1,in2,op :bit_vector(3 downto 0);
signal sel1,sel2: bit;
begin
inst1: logical port map(in1,in2,sel1,sel2,op);
process
begin
in1 <= "0000";
in2 <= "1111";
sel1 <= '0';
sel2 <= '0';
wait for 20 ns;
sel1 <= '0';
sel2 <= '1';
wait for 20 ns;
sel1 <= '1';
sel2 <= '0';
wait for 20 ns;
sel1 <= '1';

26

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sel2 <= '1';
wait for 20 ns;
end process;
end logic_test_arch;

27

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E X P E R I M E N T N U M B E R 13
Implementation of Shift Operations

LEFT SHIFTER

entity leftshifter is
port(a:in bit_vector;al:out bit_vector);
end leftshifter;
architecture leftsh_arch of leftshifter is
begin
al(1)<=a(0);
al(2)<=a(1);
al(3)<=a(2);
al(0)<='0';
end leftsh_arch;

LOGICAL

entity logical is
port(a,b,s1,s0:in bit;z:out bit);
end logical;
architecture logical_arch of logical is
component mux4x1
port(a,b,c,d,s1,s0:in bit;z:out bit);
end component;
signal y0,y1,y2,y3:bit;
begin
y0<=a and b;

28

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y1<=a or b;
y2<=not a;
y3<=a nand b;
inst:mux4x1 port map(y0,y1,y2,y3,s1,s0,z);
end logical_arch;

RIGHT SHIFTER

entity rightshifter is
port(a:in bit_vector;ar:out bit_vector);
end rightshifter;
architecture rightsh_arch of rightshifter is
begin
ar(0)<=a(1);
ar(1)<=a(2);
ar(2)<=a(3);
ar(3)<='0';
end rightsh_arch;
TEST ALU
entity tb is
end tb;
architecture tb_arch of tb is
component alu
port(s,a,b:in bit_vector;f:out bit_vector);
end component;
signal s,a,b,f:bit_vector(3 downto 0);
begin
inst:alu port map(s,a,b,f);
process
29

[Type text]

begin
s<="0011";wait for 20 ns;
a<="1100";wait for 20 ns;
b<="0011";wait for 20 ns;
s<="1100";wait for 20 ns;
a<="1001";wait for 20 ns;
b<="0000";wait for 20 ns;
end process;
end tb_arch;

30

[Type text]

EXPERIMENT NUMBER 14
8 Up Down Counter
UP DOWN COUNTER

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port ( src1: in std_logic_vector(7 downto 0);
inc,clk,up: in std_logic;
dest: out std_logic_vector(7 downto 0));
end entity;
architecture counter_arch of counter is
signal count: std_logic_vector(7 downto 0);
begin
process(clk)
begin
if(clk = '1') then
if(up = '1') then
count <= src1 + inc;
else
count <= src1 - inc;
end if;
end if;
end process;
process(count)
--the code was needed to be entered in process so that it executes
--only when count value is computed. Otherwise both the if condition and
--the count assignment will take place simultaneously.
begin
dest <= count;
end process;
end counter_arch;
Counter Test Bench

library IEEE;

31

[Type text]

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter_test is
end entity;
architecture counter_test_arch of counter_test is
component counter is
port ( src1: in std_logic_vector(7 downto 0);
inc,clk,up: in std_logic;
dest: out std_logic_vector(7 downto 0));
end component;
signal in_count: std_logic_vector(7 downto 0):="00000000";
signal out_count: std_logic_vector(7 downto 0);
signal inc,clk,sel: std_logic;
begin
inst2: counter port map(in_count,inc,clk,sel,out_count);
process
begin
inc <= '1';
clk <= '1';
wait for 10 ns;
clk <= '0';
in_count <= out_count;
wait for 10 ns;
end process;
process
begin
sel <= '1';
wait for 400 ns;
sel <= '0';
wait for 400 ns;
end process;
end counter_test_arch;

32

[Type text]

EXPERIMENT NUMBER 15
Ring Counter

D- Flip Flop
entity dflipflop is
port (d,clk:in bit;
q:buffer bit);
end entity;
architecture dflipflop_arch of dflipflop is
begin
process (clk)
begin
if (clk='1')and (clk'event) then
q<=d;
end if;
end process;
end dflipflop_arch;

Ring Counter
entity ringcounter is
port (clk:in bit;
input:in bit_vector(3 downto 0);
output:buffer bit_vector(3 downto 0));
end entity;
architecture arch of ringcounter is
component dflipflop is
port (d,clk:in bit;
q:buffer bit);
end component;
begin
inst3:dflipflop port map(input(0),clk,output(3));
inst2:dflipflop port map(input(3),clk,output(2));
inst1:dflipflop port map(input(2),clk,output(1));
inst0:dflipflop port map(input(1),clk,output(0));
end arch;

Test Bench
entity testbench is
end entity;
architecture test of testbench is
component ringcounter is

33

[Type text]

port (clk:in bit;
input:in bit_vector(3 downto 0);
output:buffer bit_vector(3 downto
0));
end component;
signal clk,init:bit;
signal input,output:bit_vector(3 downto 0);
begin
inst:ringcounter port
map(clk,input,output); clk<=not clk
after 10 ns;
process
begin
init<='
1';
wait for 20 ns;
init<='0';
wait for 400
ns; end
process;
process(clk,ini
t) begin
if clk='1' and clk'event
then if (init='1')
then
input<="0
001"; else if
init='0' then
input<=outp
ut;
end if;
end
if;
end
if;
end
process;
end test

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