Wireless Gesture Controlled Tank Toy

WIRELESS GESTURE CONTROLLED TANK

ABBREVIATIONS
ISP: In-System Programmable UART: Universal Asynchronous Receiver Transmitter TTL: Transistor Transistor Logic RST: Reset ALE: Address Latch Enable PSEN: Program Store Enable EA: External Access Enable WDT: Watch-Dog Timer WDTRST: Watch-Dog Timer Reset LED: Light Emitting Diode PCB: Printed Circuit Board COM: Common NC: Noramally Closed NO: Normally Open IR: Infrared

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CHAPTER 1 INTRODUCTION

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INTRODUCTION

1. WIRELESS GESTURE CONTROLLED TANK TOY

1.1 PROJECT OVERVIEW
Most of controllers of existing remote toys, as shown in figure 1.1, require users to interface with joysticks and push buttons.Comparing to these conventional controllers,we built a wireless gesture controller which enables toys to mock hand motions in all three dimensions as shown in figure 1.2.To demonstrate this wireless gesture controller, a remote tank is also implemented, as shown in figure 1.3.

Fig.1.1 Conventional Wireless Controller

Fig.1.2 Gesture Wireless Controller
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Fig.1.3 Remote Controlled Tank

1.2. SYSTEM BLOCK DIAGRAM
The below overall block diagram illustrates the structure of the system, the modules and the communication protocols between them. The whole is divided into four main parts: Remote tank and Gesture controller as described below. A pair of wireless-serial module communicates between these two parts As shown in figure 1.4, the microcontroller, MCU collects angular acceleration data from the metallic ball and translates these motion data into corresponded commands which control the motors on the remote tank before sending these commands to the wireless Zigbee protocol. The remote tank reads the commands sent by the gesture controller via wireless Zigbee protocol and performed the required motor controls. On the other hand, feedback from the IR-sensor and encoder are sent from the remote tank back to the gesture controller wirelessly as the way the gesture controller sends commands.

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VIBRATION MOTOR

I/O

MCU
UART IC BUS

IC BUS

METALLIC BALL SENSOR

XBEE

XBEE
UART IC BUS

917 Mhz WIRELESS

Encoder

I/O
H-Bridge

MCU
I/O

I/O
H-Bridge

H-Bridge

INFRA-RED SENSOR
Figure 1.4. System Block Diagram

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CHAPTER 2 LITERATURE REVIEW

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2.1. LITERATURE REVIEW
The idea of “Gesture Controlled Tank” is taken from website of „CORNELL UNIVERSITY‟. The project was intended to ease the spying and investigating activities. The „GESTURE CONTROL‟ provides facility to easily control the movement of tank. The tank is also provided with sensors to retain information about the track on which it is moving. Gyroscope was used by the „CORNELL UNIVERSITY‟ for sensing the gesture of hand. Due to high cost of gyroscope, „Metallic Ball Sensor‟ is used here for gesture sensing. Use of metallic ball sensor not only reduce the cost of the project but also reduce the bulkiness of the circuit. Also the RF sensors used for sensing the obstacles in the path are replaced by IR sensor which improves the sensitivity of tank. The additional feature of „Analog Camera‟ provides facility to visualize the geographical features of the area in which the tank is moving. So this project is very useful for defence purposes. With improvement in communicating technology in this project the tank can be used to access the remote areas.

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CHAPTER 3 MICROCONTROLLER

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MICROCONTROLLER (89S52) 3.1. Features
 Compatible with MCS®-51 Product  8K Bytes of In-System Programmable (ISP) Flash Memory -Endurance: 1000 Write/Erase Cycles  4.0V to 5.5V Operating Range  Fully Static Operation: 0 Hz to 33 MH  Three-level Program Memory Lock  256 x 8-bit Internal RAM  32 Programmable I/O Lines  Three 16-bit Timer/Counters  Eight Interrupt Sources  Full Duplex UART Serial Channel  Low-power Idle and Power-down Modes  Interrupt Recovery from Power-down Mode  Watchdog Timer  Dual Data Pointer  Power-off Flag  Fast Programming Time  Flexible ISP Programming (Byte and Page Mode)  Green (Pb/Halide-free) Packaging Option.

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3.2. DESCRIPTION
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel‟s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con- tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

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3.3. PIN DIAGRAM

Figure 3.1 Pin Diagram of 89S52

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3.4. Block Diagram

Figure 3.2. Block Diagram of 89S52

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3.5. PIN DESCRIPTION 3.5.1. VCC
Supply Voltage

3.5.2. GND
Ground 3.5.3. PORT 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port,each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

3.5.4. PORT 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups.The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

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Port Pin P1.0 P1.1 P1.5 P1.6 P1.7

Alternate Functions T2 (external count input to Timer/Counter 2), clock-out T2EX (Timer/Counter 2 capture/reload trigger and direction control) MOSI (used for In-System Programming) MISO (used for In-System Programming) SCK (used for In-System Programming)

Table 3.1. Alternate Function of Port 1

3.5.5. PORT 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

3.5.6. PORT 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52.

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Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) Table 3.2. Alternate Function of PORT 3

3.5.7. RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

3.5.8. ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

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3.5.9. PSEN
Programmable Store Enable(PSEN) is the read stobe to external program memory. When the AT89S52 is executing code fron external program memory. PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory.

3.5.10. EA/VPP
External Access Enable (EA) must be strapped to GND in order to enable the device to fetch code from external program memory locations starting from 0000H up to FFFFH.Note, however that if lock bit 1 is programmed. EA will be internally latched on reset EA should be strapped to Vcc for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

3.5.11. XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

3.5.12. XTAL2
Output from the inverting oscillator amplifier.

3.6. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR). Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in registers T2CON and
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T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.

3.7. Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

3.7.1. Program Memory
If the EA pin is connected to gnd,all program fetches are directed to external memory.On the AT89S52,if EA is connected to Vcc ,program fetches to addresses 0000H through 1FFFFH are direced to internal memory and fetches to addresses 2000H through FFFFH are to exernal memory.

3.7.2. Data Memory
AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address0A0H, rather than P2 (whose address is 0A0H).

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MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data. RAM are available as stack space.

3.8. Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over- flows, it will drive an output RESET HIGH pulse at the RST pin.

3.8.1. Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

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3.8.2. WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power- down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

3.8.3. UART
It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates.

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It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. (However, if the first byte still hasn‟t been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically second receive register.

The serial port can operate in 4 modes:

Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator frequency.

Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit(0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable.

Mode 2: 11 bits are transmitted (through TXD) or received (through RXD): a start bit(0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency.

Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit(0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated in Mode 0 by the condition RI = 0 and REN =1. Reception is initiated in Mde 0 by the condition RI = 0 and REN = 1. Reception is initiated. In the other modes by the incoming start bit if REN = 1.
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Serial I/O port includes the following enhancements:  Framing error detection  Automatic address recognition

3.9. Timer 0 and Timer 1
Timer 0 functions as either a timer or event counter in four modes of operation.  Timer 0 is controlled by the four lower bits of the TMOD register and bits 0, 1, 4 and 5 of the TCON register. TMOD register selects the method of timer gating (GATE0), timer or counter operation (T/C0#) and mode of operation (M10 and M00). The TCON register provides timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation.  Timer 0 overflow(count rolls over from all 1s to all 0s) sets TF0 flag, generating an interrupt request.  It is important to stop timer/counter before changing mode.

Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode. The following comments help to understand the differences:  Timer 1 functions as either a timer or event counter in three modes of operation. Timer1‟s mode 3 is a hold-count mode.  Timer 1 is controlled by the four high-order bits of the TMOD register and bits 2, 3, 6 and 7 of the TCON register. The TMOD register selects the method of timer gating (GATE1), timer or counter operation (C/T1#) and mode of operation (M11 and M01). The TCON register provides timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1).
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 Timer 1 can serve as the baud rate generator for the serial port. Mode 2 is best suited for this purpose.  For normal timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control timer operation.  Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request.  When timer 0 is in mode 3, it uses timer 1‟s overflow flag (TF1) and run control bit(TR1). For this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on.  It is important to stop timer/counter before changing modes.

3.10. TIMER 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON . Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

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RCLK ,TCLK 0 0 1 X

CP/RL2 0 1 X X

TR2 1 1 1 0

MODE 16-bit Auto-reload 16-bit capture Baud Rate Generator (Off)

Table3.3. Timer 2 Operating Modes

3.10.1. CAPTURE MODE
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.

3.10.2. AUTO-RELOAD (UP OR DOWN COUNTER)
Timer 2 can be programmed to count up or down when configured in its 16-bit autoreload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 3.4) Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.

Table 3.4. T2MOD-Timer 2 Mode Control Register 7 6 = 5 = 4 3 2 T2OE 1 DCEN 0

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Symbol T2OE DCEN

Function Not implemented,reserved for future Timer 2 Output Enable bit When set,this bit allows Timer 2 to be configured as up/down counter

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CHAPTER 4 IR SENSOR

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4.1. THE IR LIGHT EMITTER

4.1.1. Principle of Operation
Because they emit at wavelengths which provide a close match to the peak spectral response of silicon photodetectors, both GaAs and GaAlAs. In general, there are four characteristics of IR emitters that designers have to take care of:  Rise and Fall Time  Emitter Wavelength  Emitter Power  Emitter Half-angle

Fig 4.1 Wavelength vs. Radiant Power

4.1.2. Description
In this system IR LED used is QED233 / QED234 which is a 940 nm GaAs / AlGaAs LED encapsulated in a clear untinted, plastic T-1 3/4 package.

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Figure 4.2. IR Led & Led Schematic

4.1.3. QED 234 Features
 Wavelength=940nm  Chip material =GaAs with AlGaAs window.  Medium Emission Angle, 40°  High Output Power  Package material and color: Clear, untinted, plastic  Ideal for remote control applications.

4.2. IR LIGHT DETECTOR
The most common device used for detecting light energy in the standard data stream is a photodiode. Photo transistors are not typically used in IrDA standard-compatible systems because of their slow speed. Photo transistors typically have ton/toff of 2 µs or more. A photo

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transistor may be used, however, if the data rate is limited to 9.6 kb with a pulse width of 19.5 µs. A photodiode is packed in such a way so as to allow light to strike the PN junction.

Fig 4.3 Characteristic Curve of a Reverse Biased Photodiode

In infrared applications, it is common practice to apply a reverse bias to the device. There will be a reverse current that will vary with the light level. Like all diodes, there is an intrinsic capacitance that varies with the reverse bias voltage. This capacitance is an important factor in speed.

4.2.1. Description
The QSE973 is a silicon PIN photodiode encapsulated in an infrared transparent, black, plastic T092 package.

Cathode

1

_

2

+

Fig 4.4. IR Photodiode & Reverse Bias Photodiode

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4.2.2. QSE 973 Features
 Daylight filter  T092 package  PIN photodiode  Recepting angle 90°  Chip size = .1072 sq. inches (2.712 sq. mm)

4.3. Link Distance
To select an appropriate IR photo-detect diode, the designer must keep in mind the distance of communication, the amount of light that may be expected at that distance and the current that will be generated by the photodiode given a certain amount of light energy. The amount of light energy, or irradiance that is present at the active-input interface is typically given in µW/cm2.

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CHAPTER 5 L293D IC

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5.1. PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES

Fig 5.1. IC 7293D

5.1.1. Features
 600mA OUTPUT CURRENT CAPABILITY PER CHANNEL  1.2A PEAK OUTPUT CURRENT (non repetitive) PER CHANNEL  ENABLE FACILITY OVERTEMPERATURE PROTECTION  LOGICAL º0º INPUT VOLTAGE UP TO 1.5 V (HIGH NOISE IMMUNITY)  INTERNAL CLAMP DIODES

5.1.2. DESCRIPTION
The Device is a monolithic integrated high volt-age, high current four channel driver designed to accept standard DTL or TTL logic levels and drive inductive loads (such as relays solenoides, DC and stepping motors) and switching power transistors. To simplify use as two bridges each pair of channels is equipped with an enable input. A separate supply input is provided for the logic, allowing operation at a lower voltage and internal clamp diodes are included.

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This device is suitable for use in switching applications at frequencies up to 5 kHz. The L293D is assembled in a 16 lead plastic package which has 4 center pins connected together and used for heat sinking.

The L293DD is assembled in a 20 lead surface mount which has 8 center pins connected together and used for heat sinking.

5.2. BLOCK DIAGRAM

Fig 5.2. Block Diagram of L293d

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5.3. PIN CONNECTIONS (Top view)

Fig 5.3 PIN Diagram of IC l293d

5.4. TRUTH TABLE (ONE CHANNEL)
INPUT H L H L ENABLE H H L L OUTPUT H L Z Z

Z= HIGH IMPEDENCE H=HIGH LEVEL (1) L=LOW LEVEL (0)

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Fig 5.4. Switching Times

Fig 5.5. Junction to ambient thermal resistance vs. area on board heat sink (SO12+4+4 package)

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CHAPTER 6 GEARED MOTORS

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6.1. What is a Motor?
 Something, such as a machine, that produces rotation.  It is an arrangement of coils and magnets that converts electric current(ac or dc) into mechanical rotation.  In a motor, practically all of the electromechanical energy conversion takes place in the air gap, using magnetic fields as the energy link between the electrical input and the mechanical output.  The air-gap magnetic field is set up by current-carrying windings located on the stator.  The magnetic field exerts force on the rotor to produce the mechanical torque, on the shaft connected to the rotor.  Now, anything placed on the shaft (suppose wheel) will tend to rotate.

Fig 6.1. Motor View

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Fig 6.2. Motor View

6.2. Types of Motors
 AC motors

Fig 6.3. AC Motor  DC motors

Fig 6.4. DC Motor

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 DC geared motors

Fig 6.5. DC Geared Motor  Stepper motors

Fig 6.6. Stepper Motor  Servo motors

Fig 6.7. Servo Motors
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6.3. DC geared motor
 Motors having external gear arrangement attached with motor.  It has a gearbox that increases torque and decreases speed.  Most commonly used in robotics as they are having considerable torque.

Fig 6.8. Geared motors

The toothed and interlocking wheels which make up a typical gear movement.

Fig 6.9. Toothed and interlocking wheels

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\ Gear ratio is calculated by dividing the number of teeth on the driver gear by the number of teeth on the driven gear (gear ratio = driver/driven); the idler gears are ignored. Idler gears change the direction of rotation but do not affect speed. A high driven to driver ratio (middle) is a speed-reducing ratio.

Fig 4.3 Different Gears Different gears are used to perform different engineering functions depending on the change in direction of motion that is needed. Rack and pinion gears are the commonest gears and are used in car steering mechanisms. Toothed wheel that transmits the turning movement of one shaft to another shaft. Gear wheels may be used in pairs, or in threes if both shafts are to turn in the same direction. The gear ratio – the ratio of the number of teeth on the two wheels – determines the torque ratio, the turning force on the output shaft compared with the turning force on the input shaft. The ratio of the angular velocities of the shafts is the inverse of the gear ratio. The common type of gear for parallel shafts is the spur gear, with straight teeth parallel to the shaft axis. The helical gear has teeth cut along sections of a helix or corkscrew shape; the double form of the helix gear is the most efficient for energy transfer. Bevel gears, with tapering teeth set on the base of a cone, are used to connect intersecting shafts.

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CHAPTER 7 XBEE

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7.1. XBee RF Modules
The XBee RF Modules were engineered to meet IEEE 802.15.4 standards and support the unique needs of low-cost, low-power wireless sensor networks. The modules require minimal power and provide reliable delivery of data between devices. The modules operate within the ISM 2.4 GHz frequency band and are pin-for-pin compatible with each other

Fig 7.1. XBee

7.1.1. Features 7.1.1.1. Long Range Data Integrity
XBee  Indoor/Urban: up to 100‟ (30 m)  Outdoor line-of-sight: up to 300‟ (90 m)  Transmit Power: 1 mW (0 dBm)  Receiver Sensitivity: -92 dBm XBee-PRO  Indoor/Urban: up to 300‟ (90 m), 200' (60 m) for International variant  Outdoor line-of-sight: up to 1 mile (1600 m), 2500' (750 m) for International variant  Transmit Power: 63mW (18dBm), 10mW (10dBm) for International variant  Receiver Sensitivity: -100 dBm
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 RF Data Rate: 250,000 bps.

7.1.1.2. Advanced Networking & Security
 Retries and Acknowledgements DSSS (Direct Sequence Spread Spectrum)  Each direct sequence channels has over 65,000 unique network addresses available Source/Destination Addressing  Unicast & Broadcast Communications  Point-to-point, point-to-multipoint and peer-to-peer topologies supported

7.1.1.3. Low Power
XBee  TX Peak Current: 45 mA (@3.3 V)  RX Current: 50 mA (@3.3 V)  Power-down Current: < 10 μA XBee-PRO  TX Peak Current: 250mA (150mA for international variant)  TX Peak Current (RPSMA module only): 340mA (180mA for international variant  RX Current: 55 mA (@3.3 V)  Power-down Current: < 10 μA

7.1.2. ADC and I/O line support
Analog-to-digital conversion, Digital I/O I/O Line Passing

7.1.3. Easy-to-Use
 No configuration necessary for out-of box RF communications.  Free X-CTU Software (Testing and configuration software)  AT and API Command Modes for configuring module parameters
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 Extensive command set  Small form factor.

7.2. RF Module Operation 7.2.1. Serial Communications
The XBee®/XBee-PRO® RF Modules interface to a host device through a logic level asynchronous serial port. Through its serial port, the module can communicate with any logic and voltage com- patible UART; or through a level translator to any serial device (For example: Through a Digi proprietary RS-232 or USB interface board).

7.2.2. UART Data Flow
Devices that have a UART interface can connect directly to the pins of the RF module as shown in the figure below.

Figure 7.1. System Data Flow Diagram in a UART‐interfaced environment (Low‐asserted signals distinguished with horizontal line over signal name.)

7.2.3. SERIAL DATA
Data enters the module UART through the DI pin (pin 3) as an asynchronous serial signal. The signal should idle high when no data is being transmitted. Each data byte consists of a start bit (low), 8 data bits (least significant bit first) and a stop bit(high). The following figure illustrates the serial bit pattern of data passing through the module. Example:- Data Format is 8‐N‐1 (bits ‐ parity ‐ # of stop bits).
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Figure 7.2. UART data packet 0x1F (decimal number ʺ31ʺ) as transmitted through the RF module. Serial communications depend on the two UARTs (the microcontroller's and the RF module's) to be configured with compatible settings (baud rate, parity, start bits, stop bits, data bits). The UART baud rate and parity settings on the XBee module can be configured with the BD and SB commands, respectively.

7.3. Transparent Operation
By default, XBee®/XBee-PRO® RF Modules operate in Transparent Mode. When operating in this mode, the modules act as a serial line replacement - all UART data received through the DI pin is queued up for RF transmission. When RF data is received, the data is sent out the DO pin.

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7.4. Serial-to-RF Packetization
Data is buffered in the DI buffer until one of the following causes the data to be packetized and transmitted: 1. No serial characters are received for the amount of time determined by the RO (Packetization Timeout) parameter. If RO = 0, packetization begins when a character is received. 2. The maximum number of characters that will fit in an RF packet (100) is received. 3. The Command Mode Sequence (GT + CC + GT) is received. Any character buffered in the DI buffer before the sequence is transmitted.

If the module cannot immediately transmit (for instance, if it is already receiving RF data), the serial data is stored in the DI Buffer. The data is packetized and sent at any RO timeout or when 100 bytes (maximum packet size) are received. If the DI buffer becomes full, hardware or software flow control must be implemented in order to prevent overflow (loss of data between the host and module).

7.5. FLOW DIAGRAM

Figure 7.3. Internal Data Flow Diagram
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7.6. MODES OF OPERATION
It operates in 5 Modes.

Fig 7.4. MODES OF OPERATION

7.6.1. IDLE OPERATION
When not receiving or transmitting data, the RF module is in Idle Mode. The module shifts into the other modes of operation under the following conditions:  Transmit Mode (Serial data is received in the DI Buffer)  Receive Mode (Valid RF data is received through the antenna)  Sleep Mode (Sleep Mode condition is met)  Command Mode (Command Mode Sequence is issued)

7.6.2. Transmit/Receive Modes
7.6.2.1. RF Data Packets Each transmitted data packet contains a Source Address and Destination Address field. The Source Address matches the address of the transmitting module as specified by the MY (Source Address) parameter (if MY >= 0xFFFE), the SH
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(Serial Number High) parameter or the SL (Serial Number Low) parameter. The <Destination Address> field is created from the DH (Destination Address High) and DL (Destination Address Low) parameter values. The Source Address and/or Destination Address fields will either contain a 16-bit short or long 64-bit long address.

7.6.2.2. Direct and Indirect Transmission
There are two methods to transmit data:  Direct Transmission - data is transmitted immediately to the Destination Address  Indirect Transmission - A packet is retained for a period of time and is only transmitted after the destination module (Source Address = Destination Address) requests the data.Indirect Transmissions can only occur on a Coordinator. Thus, if all nodes in a network are End Devices, only Direct Transmissions will occur. Indirect Transmissions are useful to ensure packet delivery to a sleeping node. The Coordinator currently is able to retain up to 2 indirect messages. Direct Transmission A Coordinator can be configured to use only Direct Transmission by setting the SP (Cyclic Sleep Period) parameter to "0". Also, a Coordinator using indirect transmissions will revert to direct transmission if it knows the destination module is awake. To enable this behavior, the ST (Time before Sleep) value of the Coordinator must be set to match the ST value of the End Device. Once the End Device either transmits data to the Coordinator or polls the Coordinator for data, the Coordinator will use direct transmission for all subsequent data transmissions to that module address until ST time occurs with no activity (at which point it will revert to using indirect transmissions for that module address). "No activity" means no transmis- sion or reception of messages with a specific address. Global messages will not reset the ST timer.

Indirect Transmission
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To configure Indirect Transmissions in a PAN (Personal Area Network), the SP (Cyclic Sleep Period) parameter value on the Coordinator must be set to match the longest sleep value of any End Device. The sleep period value on the Coordinator determines how long (time or number of beacons) the Coordinator will retain an indirect message before discarding it. An End Device must poll the Coordinator once it wakes from Sleep to determine If the Coordinator has an indirect message for it. For Cyclic Sleep Modes, this is done automatically every time the module wakes (after SP time). For Pin Sleep Modes, the A1 (End Device Association) parameter value must be set to enable Coordinator polling on pin wake-up. Alternatively, an End Device can use the FP (Force Poll) command to poll the Coordinator as needed.

7.6.3. CCA (Clear Channel Assessment)
Prior to transmitting a packet, a CCA (Clear Channel Assessment) is performed on the channel to determine if the channel is available for transmission. The detected energy on the channel is com- pared with the CA (Clear Channel Assessment) parameter value. If the detected energy exceeds the CA parameter value, the packet is not transmitted. Also, a delay is inserted before a transmission takes place. This delay is settable using the RN (Back off Exponent) parameter. If RN is set to “0”, then there is no delay before the first CCA is per- formed. The RN parameter value is the equivalent of the “minBE” parameter in the 802.15.4 spec- ification. The transmit sequence follows the 802.15.4 specification. By default, the MM (MAC Mode) parameter = 0. On a CCA failure, the module will attempt to re- send the packet up to two additional times. When in Unicast packets with RR (Retries) = 0, the module will execute two CCA retries. Broadcast packets always get two CCA retries.

7.6.4. Acknowledgement
If the transmission is not a broadcast message, the module will expect to receive an acknowledgement from the destination node. If an acknowledgement is not received, the packet will be resent up to 3 more times. If the acknowledgement is not received after all transmissions, an ACK failure is recorded.
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7.6.5.Sleep Mode
Sleep Modes enable the RF module to enter states of low-power consumption when not in use. In order to enter Sleep Mode, one of the following conditions must be met (in addition to the module having a non-zero SM parameter value):  Sleep_RQ (pin 9) is asserted and the module is in a pin sleep mode (SM = 1, 2, or 5)  The module is idle (no data transmission or reception) for the amount of time defined by the ST (Time before Sleep) parameter. [NOTE: ST is only active when SM = 4-5.]

7.6.6. Command Mode
To modify or read RF Module parameters, the module must first enter into Command Mode - a state in which incoming characters are interpreted as commands. Two Command Mode options are supported: AT Command Mode [refer to section below] and API Command Mode [p57].

7.6.6.1. AT Command Mode
To Enter AT Command Mode: Send the 3-character command sequence “+++” and observe guard times before and after the command characters. [Refer to the “Default AT Command Mode Sequence” below.] Default AT Command Mode Sequence (for transition to Command Mode):  No characters sent for one second [GT (Guard Times) parameter = 0x3E8]  Input three plus characters (“+++”) within one second [CC (Command Sequence Character) parameter = 0x2B.]  No characters sent for one second [GT (Guard Times) parameter = 0x3E8]  All of the parameter values in the sequence can be modified to reflect user preferences.

NOTE: Failure to enter AT Command Mode is most commonly due to baud rate mismatch. Ensure the „Baud‟ setting on the “PC Settings” tab matches the interface data rate of the RF module. By default, the BD parameter = 3 (9600 bps).

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To Send AT Commands: Send AT commands and parameters using the syntax shown below.

Figure 2‐08. Syntax for sending AT Commands

To read a parameter value stored in the RF module‟s register, omit the parameter field.

The preceding example would change the RF module Destination Address (Low) to “0x1F”. To store the new value to non-volatile (long term) memory, subsequently send the WR (Write) command. For modified parameter values to persist in the module‟s registry after a reset, changes must be saved to non-volatile memory using the WR (Write) Command. Otherwise, parameters are restored to previously saved values after the module is reset.

System Response. When a command is sent to the module, the module will parse and execute the command. Upon successful execution of a command, the module returns an “OK” message. If execution of a command results in an error, the module returns an “ERROR” message. To Exit AT Command Mode: 1. Send the ATCN (Exit Command Mode) command (followed by a carriage return). [OR] 2. If no valid AT Commands are received within the time specified by CT (Command Mode Timeout) Command, the RF module automatically returns to Idle Mode.
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CHAPTER 8 POWER SUPPLY

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8.1. POWER SUPPLY
A power supply is a device that supplies electrical energy to one or more electrical loads. The term is most commonly applied to devices that convert one form of electrical energy to another, though it may also refer to devices that convert another form of energy( e.g mechanical, chemical ,solar) to electrical energy. A regulated power supply is one that controls the output voltage or current to a specific value; the controlled value is held nearly constant despite variation in either load current or the voltage supplied by the power supply‟s energy source. Every power supply must obtain the energy it supplies to its load ,as well as energy it consumes while performing that task, from an energy source. Depending on its design, a power supply may obtain energy from:  Electrical energy transmission system. Common examples of this include power supplies that converts AC line voltage to DC voltage  Energy storage devices such as batteries and fuel cells.  Electromechanical systems such as generators and alternators  Solar power A power supply may be implemented as a discrete ,stand-alone device or as an integral device that is hardwired to its load. In the latter case, for example, low voltage DC power supplies are commonly integrated with their loads in devices such as computers and household devices. Constraints that commonly affect power supplies include:  The amount of voltage and current they can supply.  How long they can supply energy without needing some kind of refuelling or recharging (applies to power supplies that employ portable energy sources).  How stable their output or current is under varying load condition.  Whether they provide continuous or pulsed energy.

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8.1.1. REGULATOR
Voltage regulator ICs are available with fixed (typically 5,12 and 15V) or output voltages. They are also rated by maximum current they can pass. Negative voltage regulators are available, mainly for use in dual supplies. Most regulators include some automatic protection from excessive current („overload protection‟) and overheating („thermal protection‟). Many of the fixed voltage regulator ICs has 3 leads and look like power transistors, such as the 7805 +5V 1A regulator shown in the figure. They include hole for attaching a heat sink if necessary.

Fig 8.1. Voltage Regulator

8.1.2. BATTERY
A battery is an alternative to a line operated power supply;it is independent of the availability of mains electricity, suitable for portable equipments use in locations without main power. A battery consist of several electrochemical cells connected in series to provide the
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voltage desired. Batteries may be primary(able to supply current when constructed, discarded when drained) or secondary (rechargeable; can be charged, used, and recharged many times). The primary cell first used was carbon-zinc dry cell. It had a voltage of 1.5 volts; later battery types have been manufactured, when possible, to give same voltage per cell. Carbon-zinc and related cells are still used, but the alkaline battery delivers more energy per unit weight and is widely used. The most commonly used battery voltages are 1.5(1 cell) and 9V (6 cells). Various technologies of rechargeable battery are used. Types most commonly used are NiMH ,and lithium ions and variants.

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CONCLUSION
While making the major project we learnt many things. The important thing we learnt is the art of cooperation among the group members. It is like team work where everyone has to work for it, without any team member work could not be completed. It has increased our interest in practical work and our moral was also boosted. This project increased our professionalism to higher extent. The field of our major project “embedded system” made us more knowledgeable which seems to be very difficult. It was a great experience for us to commence our project in embedded systems field. the project gave us a real look into the basic of this field. It was quite a fascinating when the model was working completely.

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BIBLIOGRAPHY
1) www.google.com 2) www.atmel.com 3) www.wikipedia.org 4) www.datasheetcatalog.com

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APPENDIX-A PROGRAM

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Program for tank :$include(mod51) org ljmp org ljmp ljmp org 0000h main 23h sendtx main 00ffh

main: see_switch:

lcall jb lcall p2.3, led p2.0, delays p2.0, work p2.1, delays p2.1, a, sbuf,

inzdata see switch

main1:

jnb lcall jnb ljmp

checkup

checkup

checkup:

jnb lcall jnb

main1

main1 #01h a

work:

mov mov nop

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mov lcall lcall lcall mov hang: jb jb send2: mov mov nop ljmp dowork: cjne lcall ret check1: cjne lcall ret check2: cjne lcall ret check3: cjne

ie, mstop delayb delayb

#0001000b

ie,#1001000b p2.0, p2.1, a, #02h sbuf, a hang hang

main1 a, #001h, check1

movelef;..........................forward

a, #02h,

check2

move f;..............................rewind

a, #03h,

check3

move ri;-.............................left

a, #04h,

stop
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lcall lcall ret stop: cjne lcall goback : delayb: back321: back331: back341: ret mov mov mov djnz djnz djnz ret delay: l2: l1: mov mov djnz djnz ret delays: va: mov djnz ret

move rew;...............................right delayb

a, mstop

#05h, goback

r2, r0, r1, r1, r0, r2,

#06h #0ffh #0ffh back341 back331 back321

r0, r1, r1, r0,

#0ffh #0ffh l1 l2

r0, r0,

#0ffh va

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movef:

lcall clr setb clr setb clr ret

led_off p3.7 p1.0 p1.1 p1.2 p1.3

moverew:

lcall clr clr setb clr setb ret

led_off p3.6 p1.0 p1.1 p1.2 p1.3

movelef:

lcall clr setb clr clr setb ret

led_off p3.5 p1.0 p1.1 p1.2 p1.3

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moveri:

lcall clr clr setb setb clr ret

led_off p3.4 p1.0 p1.1 p1.2 p1.3

mstop:

lcall clr clr clr clr ret

led_off p1.0 p1.1 p1.2 p1.3

led_off:

setb setb setb setb ret

p3.7 p3.6 p3.5 p3.4

;------------------------------------------------------------sendtx: push push 0 1
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push push jb clr mov lcall lcall

acc psw ti, ri a, led dowork sbuf sendrx

;--------------------------------------------------------pop pop pop pop reti sendrx: clr pop pop pop pop reti ;--------------------------------------------------------led: clr p2.0
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psw acc 1 0

ti psw acc 1 0

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lcall setb ret inzdata: mov mov mov mov setb ret end

delay p2.2

tmod, th1, scon, ie, tr1 #1001000b

#20h #0fdh #50h

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Program for gestures :$ include (mod51) flags equ stopbit org ljmp org ljmp org main: lcall setb 0000h main 23h sendtx 30h inzdata stopbit 20h bit 0

;-----------------------------------------------------------checkswitch: jb nop nop jb mov mov setb nop see2a: jnb p2.0, see2a
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p2.0,

see2

p2.0, a, sbuf, stopbit

see2 #01h a

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see2:

jb nop nop jb mov mov setb nop

p2.1,

see3

p2.1, a, sbuf, stopbit

see3 #02h a

see2b: see3:

jnb jb nop nop jb mov mov setb nop

p2.1, p2.2,

see2b see4

p2.2, a, sbuf, stopbit

see4 #03h a

see2c: see4:

jnb jb nop nop

p2.2, p2.3,

see2c see5

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jb mov mov setb nop see2d: see5: jnb jnb mov mov nop clr ljmp

p2.3, a, sbuf, stopbit

see5 #04h a

p2.3,

see2d

stopbit,checkswitch a, sbuf, #05h a

stopbit checkswitch

;------------------------------------------------------------------org sendtx: jb mov cjne setb clr reti check6: cjne a, #02h, go
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100h ti, a, a, p1.0 ri sendrx sbuf #01h, check6

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clr clr go: sendrx: reti clr lcall reti

p1.0 ri

ti led

;--------------------------------------------------------led: clr lcall setb ret inzdata: mov mov mov mov setb clr ret delay: l2: l1: mov mov djnz r0, r1, r1, #0fh #0fh l1
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p3.7 delay p3.7

tmod, th1, scon, ie, tr1 p1.0 #1001000b

#20h #0fdh #50h

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djnz ret end

r0,

l2

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